diff options
Diffstat (limited to 'manufacturer/altera')
65 files changed, 31571 insertions, 0 deletions
diff --git a/manufacturer/altera/cyclone10_lp/.gitignore b/manufacturer/altera/cyclone10_lp/.gitignore new file mode 100644 index 0000000..2e58f2c --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/.gitignore @@ -0,0 +1,12 @@ +betsy_top.txt +db +greybox_tmp +incremental_db +simulation +output_* +*.bak +*.map +*.rpd +*.rpt +*.rpd +*.qws diff --git a/manufacturer/altera/cyclone10_lp/betsy.cof b/manufacturer/altera/cyclone10_lp/betsy.cof new file mode 100644 index 0000000..82b7d02 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/betsy.cof @@ -0,0 +1,32 @@ +<?xml version="1.0" encoding="US-ASCII" standalone="yes"?> +<cof> + <eprom_name>MT25QL128</eprom_name> + <flash_loader_device>10CL025Y</flash_loader_device> + <output_filename>output_file.jic</output_filename> + <n_pages>1</n_pages> + <width>1</width> + <mode>7</mode> + <sof_data> + <user_name>Page_0</user_name> + <page_flags>1</page_flags> + <bit0> + <sof_filename>C:/Projects/PrivateIsland/pi-betsy/manufacturer/intel/cyclone10_lp/output_betsy/betsy.sof</sof_filename> + </bit0> + </sof_data> + <version>10</version> + <create_cvp_file>0</create_cvp_file> + <create_hps_iocsr>0</create_hps_iocsr> + <auto_create_rpd>0</auto_create_rpd> + <rpd_little_endian>1</rpd_little_endian> + <options> + <map_file>1</map_file> + </options> + <advanced_options> + <ignore_epcs_id_check>1</ignore_epcs_id_check> + <ignore_condone_check>2</ignore_condone_check> + <plc_adjustment>0</plc_adjustment> + <post_chain_bitstream_pad_bytes>-1</post_chain_bitstream_pad_bytes> + <post_device_bitstream_pad_bytes>-1</post_device_bitstream_pad_bytes> + <bitslice_pre_padding>1</bitslice_pre_padding> + </advanced_options> +</cof>
\ No newline at end of file diff --git a/manufacturer/altera/cyclone10_lp/betsy.jic b/manufacturer/altera/cyclone10_lp/betsy.jic Binary files differnew file mode 100644 index 0000000..501f0f1 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/betsy.jic diff --git a/manufacturer/altera/cyclone10_lp/betsy.qpf b/manufacturer/altera/cyclone10_lp/betsy.qpf new file mode 100644 index 0000000..c6aaaba --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/betsy.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2023 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details, at +# https://fpgasoftware.intel.com/eula. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 23.1std.0 Build 991 11/28/2023 Patches 0.02std SC Lite Edition +# Date created = 13:02:56 May 09, 2024 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "23.1" +DATE = "13:02:56 May 09, 2024" + +# Revisions + +PROJECT_REVISION = "betsy" diff --git a/manufacturer/altera/cyclone10_lp/betsy.qsf b/manufacturer/altera/cyclone10_lp/betsy.qsf new file mode 100644 index 0000000..2d4da4c --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/betsy.qsf @@ -0,0 +1,742 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2020 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details, at +# https://fpgasoftware.intel.com/eula. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition +# Date created = 00:31:06 February 23, 2021 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# betsy_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone 10 LP" +set_global_assignment -name DEVICE 10CL025YU256I7G +set_global_assignment -name TOP_LEVEL_ENTITY betsy +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:31:06 FEBRUARY 23, 2021" +set_global_assignment -name LAST_QUARTUS_VERSION "25.1std.0 Standard Edition" +set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40" +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 +set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 256 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V +set_global_assignment -name EDA_SIMULATION_TOOL "Questa Altera FPGA (Verilog)" +set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name ENABLE_OCT_DONE OFF +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall +set_global_assignment -name ENABLE_SIGNALTAP ON +set_global_assignment -name USE_SIGNALTAP_FILE brds/betsy/betsy.stp +set_global_assignment -name USE_CONFIGURATION_DEVICE ON +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE MT25QL128 +set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" + +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_betsy + + + +# Bank 1 Configuration, Sheet 6 +set_location_assignment PIN_E1 -to flash_dqs +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to flash_dqs +#set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to flash_dqs + +set_location_assignment PIN_B1 -to flash_d[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to flash_d[4] + +set_location_assignment PIN_C1 -to flash_d[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to flash_d[0] + +set_location_assignment PIN_D2 -to flash_seln +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to flash_seln + +set_location_assignment PIN_G1 -to rstn +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to rstn + +set_location_assignment PIN_H1 -to flash_clk +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to flash_clk + +set_location_assignment PIN_H2 -to flash_d[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to flash_d[1] + +# JTAG is defined in bank 1. Can this be supported in user mode? + + +# Bank 2 RGMII 0, Sheet 3 +set_location_assignment PIN_M1 -to phy0_rx_clk +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy0_rx_clk + +set_location_assignment PIN_J2 -to phy0_tx_ctl +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy0_tx_ctl + +set_location_assignment PIN_J1 -to phy0_rx_ctl +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy0_rx_ctl + +set_location_assignment PIN_K2 -to phy0_rx_d[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy0_rx_d[2] + +set_location_assignment PIN_K1 -to phy0_rx_d[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy0_rx_d[3] + +set_location_assignment PIN_L2 -to phy0_rx_d[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy0_rx_d[0] + +set_location_assignment PIN_L1 -to phy0_rx_d[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy0_rx_d[1] + +# L3 + +set_location_assignment PIN_N2 -to phy0_intn +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy0_intn + +set_location_assignment PIN_N1 -to phy0_rstn +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy0_rstn + +# K5 +# L4 + +set_location_assignment PIN_R1 -to phy0_gpio[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy0_gpio[0] + +# P2 + +set_location_assignment PIN_P1 -to phy0_gpio[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy0_gpio[1] + + +# Bank 3 RGMII 0, Sheet 3 +set_location_assignment PIN_T8 -to phy0_clk +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy0_clk + +# N3 +# P3 + +set_location_assignment PIN_R3 -to phy0_tx_d[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy0_tx_d[1] + +set_location_assignment PIN_T3 -to phy0_tx_d[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy0_tx_d[0] + +set_location_assignment PIN_T2 -to phy0_tx_clk +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy0_tx_clk + +set_location_assignment PIN_R4 -to phy0_tx_d[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy0_tx_d[3] + +set_location_assignment PIN_T4 -to phy0_tx_d[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy0_tx_d[2] + +# N5 +# N6 +# M6 +# P6 +# M7 +# R5 +# T5 +# R6 + +set_location_assignment PIN_T6 -to phy0_mdio +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy0_mdio + +# L7 +# R7 + +set_location_assignment PIN_T7 -to phy0_mdc +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy0_mdc + +# L8 +# M8 +# N8 +# P8 + +# Bank 4, RGMII 1, Sheet 4 +set_location_assignment PIN_T9 -to phy1_rx_clk +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy1_rx_clk + +set_location_assignment PIN_T10 -to phy1_rx_d[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy1_rx_d[3] + +set_location_assignment PIN_T11 -to phy1_rx_d[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy1_rx_d[2] + +set_location_assignment PIN_T12 -to phy1_rx_d[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy1_rx_d[1] + +set_location_assignment PIN_P9 -to phy1_gpio[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy1_gpio[0] + +set_location_assignment PIN_R13 -to phy1_rx_ctl +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy1_rx_ctl + +set_location_assignment PIN_T13 -to phy1_rx_d[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy1_rx_d[0] + +set_location_assignment PIN_T14 -to phy1_tx_ctl +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy1_tx_ctl + +set_location_assignment PIN_T15 -to phy1_tx_clk +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy1_tx_clk + +set_location_assignment PIN_P14 -to phy1_rstn +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy1_rstn + + +# Bank 5, RGMII 1, Sheet 4 +set_location_assignment PIN_P15 -to phy1_clk +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy1_clk + +set_location_assignment PIN_P16 -to phy1_tx_d[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy1_tx_d[1] + +set_location_assignment PIN_R16 -to phy1_tx_d[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy1_tx_d[0] + +set_location_assignment PIN_N16 -to phy1_tx_d[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy1_tx_d[3] + +set_location_assignment PIN_N15 -to phy1_tx_d[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy1_tx_d[2] + +set_location_assignment PIN_L16 -to phy1_mdio +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy1_mdio + +set_location_assignment PIN_L15 -to phy1_intn +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy1_intn + +set_location_assignment PIN_K16 -to phy1_mdc +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy1_mdc + +set_location_assignment PIN_K15 -to phy1_gpio[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy1_gpio[1] + +set_location_assignment PIN_J16 -to phy2_mdio +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy2_mdio + +set_location_assignment PIN_J15 -to phy2_mdc +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy2_mdc + + +# Bank 6, RGMII 2, Sheet 5 +set_location_assignment PIN_E16 -to phy2_rx_clk +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy2_rx_clk + +set_location_assignment PIN_G16 -to phy2_rx_d[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy2_rx_d[2] + +set_location_assignment PIN_G15 -to phy2_rx_d[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy2_rx_d[3] + +set_location_assignment PIN_F16 -to phy2_rx_ctl +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy2_rx_ctl + +set_location_assignment PIN_F15 -to phy2_rx_d[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy2_rx_d[1] + +set_location_assignment PIN_B16 -to phy2_gpio[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy2_gpio[1] + +set_location_assignment PIN_D16 -to phy2_rx_d[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy2_rx_d[0] + +set_location_assignment PIN_D15 -to phy2_intn +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy2_intn + +set_location_assignment PIN_C16 -to phy2_gpio +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy2_gpio + +# Bank 7, RGMII 2, Sheet 5 +set_location_assignment PIN_A13 -to phy2_tx_d[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy2_tx_d[1] + +set_location_assignment PIN_A14 -to phy2_tx_ctl +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy2_tx_ctl + +set_location_assignment PIN_B14 -to phy2_rstn +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy2_rstn + +set_location_assignment PIN_A12 -to phy2_tx_d[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy2_tx_d[0] + +set_location_assignment PIN_A11 -to phy2_tx_d[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy2_tx_d[2] + +set_location_assignment PIN_A15 -to phy2_tx_clk +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy2_tx_clk + +set_location_assignment PIN_A10 -to phy2_tx_d[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy2_tx_d[3] + +# Bank 8 + +set_location_assignment PIN_A7 -to fpga_led[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to fpga_led[2] + +set_location_assignment PIN_A6 -to fpga_led[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to fpga_led[1] + +set_location_assignment PIN_A5 -to fpga_led[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to fpga_led[0] + +set_location_assignment PIN_A4 -to flash_d[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to flash_d[7] + +set_location_assignment PIN_B4 -to flash_d[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to flash_d[5] + +set_location_assignment PIN_A2 -to flash_d[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to flash_d[2] + +set_location_assignment PIN_A3 -to flash_d[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to flash_d[6] + +set_location_assignment PIN_B3 -to flash_d[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to flash_d[3] + + + + + + +set_location_assignment PIN_A8 -to clk_i +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to clk_i +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name SDC_FILE betsy.sdc +set_global_assignment -name SIGNALTAP_FILE brds/betsy/betsy.stp +set_global_assignment -name VERILOG_FILE src/betsy.v +set_global_assignment -name VERILOG_FILE ../../../src/cam.v +set_global_assignment -name VERILOG_FILE ../../../src/controller.v +set_global_assignment -name VERILOG_FILE ../../../src/cont_params.v +set_global_assignment -name VERILOG_FILE ../../../src/dpram_inf.v +set_global_assignment -name VERILOG_FILE ../../../src/drop_fifo.v +set_global_assignment -name VERILOG_FILE ../../../src/ethernet_params.v +set_global_assignment -name VERILOG_FILE ../../../src/fcs.v +set_global_assignment -name VERILOG_FILE ../../../src/half_fifo.v +set_global_assignment -name VERILOG_FILE ../../../src/ipv4_rx.v +set_global_assignment -name VERILOG_FILE ../../../src/ipv4_rx_c.v +set_global_assignment -name VERILOG_FILE ../../../src/ipv4_tx_c.v +set_global_assignment -name VERILOG_FILE ../../../src/ipv4_tx_mle.v +set_global_assignment -name VERILOG_FILE ../../../src/mac_rgmii.v +set_global_assignment -name VERILOG_FILE ../../../src/ml_engine.v +set_global_assignment -name VERILOG_FILE ../../../src/mdio.v +set_global_assignment -name VERILOG_FILE ../../../src/mdio_cont.v +set_global_assignment -name VERILOG_FILE ../../../src/mdio_data_ti.v +set_global_assignment -name VERILOG_FILE ../../../src/pkt_filter.v +set_global_assignment -name VERILOG_FILE ../../../src/rgmii_params.v +set_global_assignment -name VERILOG_FILE ../../../src/rm.v +set_global_assignment -name VERILOG_FILE ../../../src/switch.v +set_global_assignment -name VERILOG_FILE ../../../src/sync_fifo.v +set_global_assignment -name VERILOG_FILE ../../../src/udp_rx.v +set_global_assignment -name VERILOG_FILE ../../../src/udp_rx_c.v +set_global_assignment -name QIP_FILE ip/ddrio/ddrio.qip +set_global_assignment -name QIP_FILE ip/rgmii_rxd/ddri.qip +set_global_assignment -name QIP_FILE ip/pll/pll.qip +set_global_assignment -name QIP_FILE ip/rgmii_txd/ddro.qip +set_global_assignment -name VERILOG_TEST_BENCH_FILE sim/src/tb.sv + +set_global_assignment -name SLD_NODE_CREATOR_ID 110 -section_id tst_controller +set_global_assignment -name SLD_NODE_ENTITY_NAME sld_signaltap -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_clk -to "pll:pll_0|c0" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[0] -to "controller:controller_0|msg_addr[0]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[1] -to "controller:controller_0|msg_addr[10]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[2] -to "controller:controller_0|msg_addr[11]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[3] -to "controller:controller_0|msg_addr[12]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[4] -to "controller:controller_0|msg_addr[13]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[5] -to "controller:controller_0|msg_addr[14]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[6] -to "controller:controller_0|msg_addr[15]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[7] -to "controller:controller_0|msg_addr[1]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[8] -to "controller:controller_0|msg_addr[2]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[9] -to "controller:controller_0|msg_addr[3]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[10] -to "controller:controller_0|msg_addr[4]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[11] -to "controller:controller_0|msg_addr[5]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[12] -to "controller:controller_0|msg_addr[6]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[13] -to "controller:controller_0|msg_addr[7]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[14] -to "controller:controller_0|msg_addr[8]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[15] -to "controller:controller_0|msg_addr[9]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[16] -to "controller:controller_0|msg_addr_ro" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[17] -to "controller:controller_0|msg_addr_valid" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[18] -to "controller:controller_0|msg_data[0]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[19] -to "controller:controller_0|msg_data[10]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[20] -to "controller:controller_0|msg_data[11]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[21] -to "controller:controller_0|msg_data[12]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[22] -to "controller:controller_0|msg_data[13]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[23] -to "controller:controller_0|msg_data[14]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[24] -to "controller:controller_0|msg_data[15]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[25] -to "controller:controller_0|msg_data[16]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[26] -to "controller:controller_0|msg_data[17]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[27] -to "controller:controller_0|msg_data[18]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[28] -to "controller:controller_0|msg_data[19]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[29] -to "controller:controller_0|msg_data[1]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[30] -to "controller:controller_0|msg_data[20]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[31] -to "controller:controller_0|msg_data[21]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[32] -to "controller:controller_0|msg_data[22]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[33] -to "controller:controller_0|msg_data[23]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[34] -to "controller:controller_0|msg_data[24]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[35] -to "controller:controller_0|msg_data[25]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[36] -to "controller:controller_0|msg_data[26]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[37] -to "controller:controller_0|msg_data[27]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[38] -to "controller:controller_0|msg_data[28]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[39] -to "controller:controller_0|msg_data[29]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[40] -to "controller:controller_0|msg_data[2]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[41] -to "controller:controller_0|msg_data[30]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[42] -to "controller:controller_0|msg_data[31]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[43] -to "controller:controller_0|msg_data[3]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[44] -to "controller:controller_0|msg_data[4]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[45] -to "controller:controller_0|msg_data[5]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[46] -to "controller:controller_0|msg_data[6]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[47] -to "controller:controller_0|msg_data[7]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[48] -to "controller:controller_0|msg_data[8]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[49] -to "controller:controller_0|msg_data[9]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[50] -to "controller:controller_0|msg_error" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[51] -to "controller:controller_0|msg_response[0]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[52] -to "controller:controller_0|msg_response[10]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[53] -to "controller:controller_0|msg_response[11]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[54] -to "controller:controller_0|msg_response[12]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[55] -to "controller:controller_0|msg_response[13]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[56] -to "controller:controller_0|msg_response[14]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[57] -to "controller:controller_0|msg_response[15]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[58] -to "controller:controller_0|msg_response[16]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[59] -to "controller:controller_0|msg_response[17]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[60] -to "controller:controller_0|msg_response[18]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[61] -to "controller:controller_0|msg_response[19]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[62] -to "controller:controller_0|msg_response[1]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[63] -to "controller:controller_0|msg_response[20]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[64] -to "controller:controller_0|msg_response[21]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[65] -to "controller:controller_0|msg_response[22]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[66] -to "controller:controller_0|msg_response[23]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[67] -to "controller:controller_0|msg_response[24]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[68] -to "controller:controller_0|msg_response[25]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[69] -to "controller:controller_0|msg_response[26]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[70] -to "controller:controller_0|msg_response[27]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[71] -to "controller:controller_0|msg_response[28]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[72] -to "controller:controller_0|msg_response[29]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[73] -to "controller:controller_0|msg_response[2]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[74] -to "controller:controller_0|msg_response[30]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[75] -to "controller:controller_0|msg_response[31]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[76] -to "controller:controller_0|msg_response[3]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[77] -to "controller:controller_0|msg_response[4]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[78] -to "controller:controller_0|msg_response[5]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[79] -to "controller:controller_0|msg_response[6]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[80] -to "controller:controller_0|msg_response[7]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[81] -to "controller:controller_0|msg_response[8]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[82] -to "controller:controller_0|msg_response[9]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[83] -to "controller:controller_0|msg_token[0]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[84] -to "controller:controller_0|msg_token[1]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[85] -to "controller:controller_0|msg_token[2]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[86] -to "controller:controller_0|msg_token[3]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[87] -to "controller:controller_0|msg_token[4]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[88] -to "controller:controller_0|msg_token[5]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[89] -to "controller:controller_0|msg_token[6]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[90] -to "controller:controller_0|msg_token[7]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[91] -to "controller:controller_0|msg_type[0]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[92] -to "controller:controller_0|msg_type[1]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[93] -to "controller:controller_0|msg_type[2]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[94] -to "controller:controller_0|msg_type[3]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[95] -to "controller:controller_0|msg_type[4]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[96] -to "controller:controller_0|msg_type[5]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[97] -to "controller:controller_0|msg_type[6]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[98] -to "controller:controller_0|msg_type[7]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[99] -to "controller:controller_0|rx_cnt[0]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[100] -to "controller:controller_0|rx_cnt[1]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[101] -to "controller:controller_0|rx_cnt[2]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[102] -to "controller:controller_0|rx_cnt[3]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[103] -to "controller:controller_0|rx_cnt[4]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[104] -to "controller:controller_0|rx_fifo_int" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[105] -to "controller:controller_0|rx_fifo_int_acked" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[106] -to "controller:controller_0|rx_fifo_int_m1" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[107] -to "controller:controller_0|rx_fifo_int_m2" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[108] -to "controller:controller_0|rx_msg_captured" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[109] -to "controller:controller_0|rx_msg_cnt[0]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[110] -to "controller:controller_0|rx_msg_cnt[10]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[111] -to "controller:controller_0|rx_msg_cnt[11]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[112] -to "controller:controller_0|rx_msg_cnt[12]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[113] -to "controller:controller_0|rx_msg_cnt[13]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[114] -to "controller:controller_0|rx_msg_cnt[14]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[115] -to "controller:controller_0|rx_msg_cnt[15]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[116] -to "controller:controller_0|rx_msg_cnt[1]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[117] -to "controller:controller_0|rx_msg_cnt[2]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[118] -to "controller:controller_0|rx_msg_cnt[3]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[119] -to "controller:controller_0|rx_msg_cnt[4]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[120] -to "controller:controller_0|rx_msg_cnt[5]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[121] -to "controller:controller_0|rx_msg_cnt[6]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[122] -to "controller:controller_0|rx_msg_cnt[7]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[123] -to "controller:controller_0|rx_msg_cnt[8]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[124] -to "controller:controller_0|rx_msg_cnt[9]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[125] -to "controller:controller_0|rx_rd_active" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[126] -to "controller:controller_0|rx_rd_ptr[0]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[127] -to "controller:controller_0|rx_rd_ptr[10]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[128] -to "controller:controller_0|rx_rd_ptr[1]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[129] -to "controller:controller_0|rx_rd_ptr[2]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[130] -to "controller:controller_0|rx_rd_ptr[3]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[131] -to "controller:controller_0|rx_rd_ptr[4]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[132] -to "controller:controller_0|rx_rd_ptr[5]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[133] -to "controller:controller_0|rx_rd_ptr[6]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[134] -to "controller:controller_0|rx_rd_ptr[7]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[135] -to "controller:controller_0|rx_rd_ptr[8]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[136] -to "controller:controller_0|rx_rd_ptr[9]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[137] -to "controller:controller_0|rx_wr_ptr[0]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[138] -to "controller:controller_0|rx_wr_ptr[10]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[139] -to "controller:controller_0|rx_wr_ptr[1]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[140] -to "controller:controller_0|rx_wr_ptr[2]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[141] -to "controller:controller_0|rx_wr_ptr[3]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[142] -to "controller:controller_0|rx_wr_ptr[4]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[143] -to "controller:controller_0|rx_wr_ptr[5]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[144] -to "controller:controller_0|rx_wr_ptr[6]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[145] -to "controller:controller_0|rx_wr_ptr[7]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[146] -to "controller:controller_0|rx_wr_ptr[8]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[147] -to "controller:controller_0|rx_wr_ptr[9]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[0] -to "controller:controller_0|msg_addr[0]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[1] -to "controller:controller_0|msg_addr[10]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[2] -to "controller:controller_0|msg_addr[11]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[3] -to "controller:controller_0|msg_addr[12]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[4] -to "controller:controller_0|msg_addr[13]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[5] -to "controller:controller_0|msg_addr[14]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[6] -to "controller:controller_0|msg_addr[15]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[7] -to "controller:controller_0|msg_addr[1]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[8] -to "controller:controller_0|msg_addr[2]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[9] -to "controller:controller_0|msg_addr[3]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[10] -to "controller:controller_0|msg_addr[4]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[11] -to "controller:controller_0|msg_addr[5]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[12] -to "controller:controller_0|msg_addr[6]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[13] -to "controller:controller_0|msg_addr[7]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[14] -to "controller:controller_0|msg_addr[8]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[15] -to "controller:controller_0|msg_addr[9]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[16] -to "controller:controller_0|msg_addr_ro" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[17] -to "controller:controller_0|msg_addr_valid" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[18] -to "controller:controller_0|msg_data[0]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[19] -to "controller:controller_0|msg_data[10]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[20] -to "controller:controller_0|msg_data[11]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[21] -to "controller:controller_0|msg_data[12]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[22] -to "controller:controller_0|msg_data[13]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[23] -to "controller:controller_0|msg_data[14]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[24] -to "controller:controller_0|msg_data[15]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[25] -to "controller:controller_0|msg_data[16]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[26] -to "controller:controller_0|msg_data[17]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[27] -to "controller:controller_0|msg_data[18]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[28] -to "controller:controller_0|msg_data[19]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[29] -to "controller:controller_0|msg_data[1]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[30] -to "controller:controller_0|msg_data[20]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[31] -to "controller:controller_0|msg_data[21]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[32] -to "controller:controller_0|msg_data[22]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[33] -to "controller:controller_0|msg_data[23]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[34] -to "controller:controller_0|msg_data[24]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[35] -to "controller:controller_0|msg_data[25]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[36] -to "controller:controller_0|msg_data[26]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[37] -to "controller:controller_0|msg_data[27]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[38] -to "controller:controller_0|msg_data[28]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[39] -to "controller:controller_0|msg_data[29]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[40] -to "controller:controller_0|msg_data[2]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[41] -to "controller:controller_0|msg_data[30]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[42] -to "controller:controller_0|msg_data[31]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[43] -to "controller:controller_0|msg_data[3]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[44] -to "controller:controller_0|msg_data[4]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[45] -to "controller:controller_0|msg_data[5]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[46] -to "controller:controller_0|msg_data[6]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[47] -to "controller:controller_0|msg_data[7]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[48] -to "controller:controller_0|msg_data[8]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[49] -to "controller:controller_0|msg_data[9]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[50] -to "controller:controller_0|msg_error" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[51] -to "controller:controller_0|msg_response[0]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[52] -to "controller:controller_0|msg_response[10]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[53] -to "controller:controller_0|msg_response[11]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[54] -to "controller:controller_0|msg_response[12]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[55] -to "controller:controller_0|msg_response[13]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[56] -to "controller:controller_0|msg_response[14]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[57] -to "controller:controller_0|msg_response[15]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[58] -to "controller:controller_0|msg_response[16]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[59] -to "controller:controller_0|msg_response[17]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[60] -to "controller:controller_0|msg_response[18]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[61] -to "controller:controller_0|msg_response[19]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[62] -to "controller:controller_0|msg_response[1]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[63] -to "controller:controller_0|msg_response[20]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[64] -to "controller:controller_0|msg_response[21]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[65] -to "controller:controller_0|msg_response[22]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[66] -to "controller:controller_0|msg_response[23]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[67] -to "controller:controller_0|msg_response[24]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[68] -to "controller:controller_0|msg_response[25]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[69] -to "controller:controller_0|msg_response[26]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[70] -to "controller:controller_0|msg_response[27]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[71] -to "controller:controller_0|msg_response[28]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[72] -to "controller:controller_0|msg_response[29]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[73] -to "controller:controller_0|msg_response[2]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[74] -to "controller:controller_0|msg_response[30]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[75] -to "controller:controller_0|msg_response[31]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[76] -to "controller:controller_0|msg_response[3]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[77] -to "controller:controller_0|msg_response[4]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[78] -to "controller:controller_0|msg_response[5]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[79] -to "controller:controller_0|msg_response[6]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[80] -to "controller:controller_0|msg_response[7]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[81] -to "controller:controller_0|msg_response[8]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[82] -to "controller:controller_0|msg_response[9]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[83] -to "controller:controller_0|msg_token[0]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[84] -to "controller:controller_0|msg_token[1]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[85] -to "controller:controller_0|msg_token[2]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[86] -to "controller:controller_0|msg_token[3]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[87] -to "controller:controller_0|msg_token[4]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[88] -to "controller:controller_0|msg_token[5]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[89] -to "controller:controller_0|msg_token[6]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[90] -to "controller:controller_0|msg_token[7]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[91] -to "controller:controller_0|msg_type[0]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[92] -to "controller:controller_0|msg_type[1]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[93] -to "controller:controller_0|msg_type[2]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[94] -to "controller:controller_0|msg_type[3]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[95] -to "controller:controller_0|msg_type[4]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[96] -to "controller:controller_0|msg_type[5]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[97] -to "controller:controller_0|msg_type[6]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[98] -to "controller:controller_0|msg_type[7]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[99] -to "controller:controller_0|rx_cnt[0]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[100] -to "controller:controller_0|rx_cnt[1]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[101] -to "controller:controller_0|rx_cnt[2]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[102] -to "controller:controller_0|rx_cnt[3]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[103] -to "controller:controller_0|rx_cnt[4]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[104] -to "controller:controller_0|rx_fifo_int" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[105] -to "controller:controller_0|rx_fifo_int_acked" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[106] -to "controller:controller_0|rx_fifo_int_m1" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[107] -to "controller:controller_0|rx_fifo_int_m2" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[108] -to "controller:controller_0|rx_msg_captured" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[109] -to "controller:controller_0|rx_msg_cnt[0]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[110] -to "controller:controller_0|rx_msg_cnt[10]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[111] -to "controller:controller_0|rx_msg_cnt[11]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[112] -to "controller:controller_0|rx_msg_cnt[12]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[113] -to "controller:controller_0|rx_msg_cnt[13]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[114] -to "controller:controller_0|rx_msg_cnt[14]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[115] -to "controller:controller_0|rx_msg_cnt[15]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[116] -to "controller:controller_0|rx_msg_cnt[1]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[117] -to "controller:controller_0|rx_msg_cnt[2]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[118] -to "controller:controller_0|rx_msg_cnt[3]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[119] -to "controller:controller_0|rx_msg_cnt[4]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[120] -to "controller:controller_0|rx_msg_cnt[5]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[121] -to "controller:controller_0|rx_msg_cnt[6]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[122] -to "controller:controller_0|rx_msg_cnt[7]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[123] -to "controller:controller_0|rx_msg_cnt[8]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[124] -to "controller:controller_0|rx_msg_cnt[9]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[125] -to "controller:controller_0|rx_rd_active" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[126] -to "controller:controller_0|rx_rd_ptr[0]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[127] -to "controller:controller_0|rx_rd_ptr[10]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[128] -to "controller:controller_0|rx_rd_ptr[1]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[129] -to "controller:controller_0|rx_rd_ptr[2]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[130] -to "controller:controller_0|rx_rd_ptr[3]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[131] -to "controller:controller_0|rx_rd_ptr[4]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[132] -to "controller:controller_0|rx_rd_ptr[5]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[133] -to "controller:controller_0|rx_rd_ptr[6]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[134] -to "controller:controller_0|rx_rd_ptr[7]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[135] -to "controller:controller_0|rx_rd_ptr[8]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[136] -to "controller:controller_0|rx_rd_ptr[9]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[137] -to "controller:controller_0|rx_wr_ptr[0]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[138] -to "controller:controller_0|rx_wr_ptr[10]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[139] -to "controller:controller_0|rx_wr_ptr[1]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[140] -to "controller:controller_0|rx_wr_ptr[2]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[141] -to "controller:controller_0|rx_wr_ptr[3]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[142] -to "controller:controller_0|rx_wr_ptr[4]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[143] -to "controller:controller_0|rx_wr_ptr[5]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[144] -to "controller:controller_0|rx_wr_ptr[6]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[145] -to "controller:controller_0|rx_wr_ptr[7]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[146] -to "controller:controller_0|rx_wr_ptr[8]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[147] -to "controller:controller_0|rx_wr_ptr[9]" -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_RAM_BLOCK_TYPE=AUTO" -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_DATA_BITS=148" -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_BITS=148" -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_BITS=148" -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_INFO=805334538" -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_POWER_UP_TRIGGER=0" -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK=0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK_LENGTH=466" -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH=0" -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SEGMENT_SIZE=256" -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ATTRIBUTE_MEM_MODE=OFF" -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_FLOW_USE_GENERATED=0" -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_BITS=11" -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_BUFFER_FULL_STOP=1" -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_CURRENT_RESOURCE_WIDTH=1" -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INCREMENTAL_ROUTING=1" -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[0] -to tst_controller|gnd -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[1] -to tst_controller|gnd -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[2] -to tst_controller|vcc -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[3] -to tst_controller|gnd -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[4] -to tst_controller|gnd -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[5] -to tst_controller|gnd -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[6] -to tst_controller|gnd -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[7] -to tst_controller|vcc -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[8] -to tst_controller|gnd -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[9] -to tst_controller|gnd -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[10] -to tst_controller|gnd -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[11] -to tst_controller|gnd -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[12] -to tst_controller|vcc -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[13] -to tst_controller|gnd -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[14] -to tst_controller|vcc -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[15] -to tst_controller|gnd -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[16] -to tst_controller|gnd -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[17] -to tst_controller|gnd -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[18] -to tst_controller|gnd -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[19] -to tst_controller|vcc -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[20] -to tst_controller|gnd -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[21] -to tst_controller|gnd -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[22] -to tst_controller|vcc -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[23] -to tst_controller|gnd -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[24] -to tst_controller|gnd -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[25] -to tst_controller|vcc -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[26] -to tst_controller|vcc -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[27] -to tst_controller|gnd -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[28] -to tst_controller|gnd -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[29] -to tst_controller|gnd -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[30] -to tst_controller|gnd -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[31] -to tst_controller|vcc -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL=1" -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SAMPLE_DEPTH=256" -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_IN_ENABLED=0" -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_PIPELINE=0" -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_RAM_PIPELINE=0" -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_COUNTER_PIPELINE=0" -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=basic,1," -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=0" -section_id tst_controller +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_global_assignment -name SLD_FILE db/betsy_auto_stripped.stp
\ No newline at end of file diff --git a/manufacturer/altera/cyclone10_lp/betsy.sdc b/manufacturer/altera/cyclone10_lp/betsy.sdc new file mode 100644 index 0000000..9d58e0c --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/betsy.sdc @@ -0,0 +1,84 @@ +create_clock -name clk -period 40.0 [get_ports clk_i]; + +create_clock -name phy0_rx_clk_v -period 8.0; # virtual clock for input constraint timing +create_clock -name phy0_rx_clk -period 8.0 -waveform { 2 6 } [get_ports phy0_rx_clk]; + +create_clock -name phy1_rx_clk_v -period 8.0; # virtual clock for input constraint timing +create_clock -name phy1_rx_clk -period 8.0 -waveform { 2 6 } [get_ports phy1_rx_clk]; + +create_clock -name phy2_rx_clk_v -period 8.0; # virtual clock for input constraint timi +create_clock -name phy2_rx_clk -period 8.0 -waveform { 2 6 } [get_ports phy2_rx_clk]; + + +create_clock -name phy0_tx_clk -period 8.0 [get_ports phy0_tx_clk]; +create_clock -name phy0_tx_clk_v -period 8.0; # virtual clock for input constraint timing + +create_clock -name phy1_tx_clk -period 8.0 [get_ports phy1_tx_clk]; +create_clock -name phy1_tx_clk_v -period 8.0; # virtual clock for input constraint timing + +create_clock -name phy2_tx_clk -period 8.0 [get_ports phy2_tx_clk]; +create_clock -name phy2_tx_clk_v -period 8.0; # virtual clock for input constraint timing + + +create_clock -name phy0_clk -period 8.0 [get_ports phy0_clk]; + +derive_pll_clocks -create_base_clocks -use_net_name + +create_clock -name flash_dqs -period 10.0 [get_ports flash_dqs]; + +# PHY0 Input Clock +set_input_delay -min -0.8 -clock { phy0_rx_clk_v } [get_ports {phy0_rx_d[0] phy0_rx_d[1] phy0_rx_d[2] phy0_rx_d[3] phy0_rx_ctl}] -add_delay +set_input_delay -min -0.8 -clock { phy0_rx_clk_v } -clock_fall [get_ports {phy0_rx_d[0] phy0_rx_d[1] phy0_rx_d[2] phy0_rx_d[3] phy0_rx_ctl}] -add_delay + +set_input_delay -max 0.8 -clock { phy0_rx_clk_v } [get_ports {phy0_rx_d[0] phy0_rx_d[1] phy0_rx_d[2] phy0_rx_d[3] phy0_rx_ctl}] -add_delay +set_input_delay -max 0.8 -clock { phy0_rx_clk_v } -clock_fall [get_ports {phy0_rx_d[0] phy0_rx_d[1] phy0_rx_d[2] phy0_rx_d[3] phy0_rx_ctl}] -add_delay + +# PHY1 Input Clock +set_input_delay -min -0.8 -clock { phy1_rx_clk_v } [get_ports {phy1_rx_d[0] phy1_rx_d[1] phy1_rx_d[2] phy1_rx_d[3] phy1_rx_ctl}] -add_delay +set_input_delay -min -0.8 -clock { phy1_rx_clk_v } -clock_fall [get_ports {phy1_rx_d[0] phy1_rx_d[1] phy1_rx_d[2] phy1_rx_d[3] phy1_rx_ctl}] -add_delay; + +set_input_delay -max 0.8 -clock { phy1_rx_clk_v } [get_ports {phy1_rx_d[0] phy1_rx_d[1] phy1_rx_d[2] phy1_rx_d[3] phy1_rx_ctl}] -add_delay +set_input_delay -max 0.8 -clock { phy1_rx_clk_v } -clock_fall [get_ports {phy1_rx_d[0] phy1_rx_d[1] phy1_rx_d[2] phy1_rx_d[3] phy1_rx_ctl}] -add_delay; + +# phy2 Input Clock +set_input_delay -min -0.8 -clock { phy2_rx_clk_v } [get_ports {phy2_rx_d[0] phy2_rx_d[1] phy2_rx_d[2] phy2_rx_d[3] phy2_rx_ctl}] -add_delay +set_input_delay -min -0.8 -clock { phy2_rx_clk_v } -clock_fall [get_ports {phy2_rx_d[0] phy2_rx_d[1] phy2_rx_d[2] phy2_rx_d[3] phy2_rx_ctl}] -add_delay; + +set_input_delay -max 0.8 -clock { phy2_rx_clk_v } [get_ports {phy2_rx_d[0] phy2_rx_d[1] phy2_rx_d[2] phy2_rx_d[3] phy2_rx_ctl}] -add_delay +set_input_delay -max 0.8 -clock { phy2_rx_clk_v } -clock_fall [get_ports {phy2_rx_d[0] phy2_rx_d[1] phy2_rx_d[2] phy2_rx_d[3] phy2_rx_ctl}] -add_delay; + + +# Set false paths to remove irrelevant setup and hold analysis +set_false_path -fall_from [get_clocks phy0_rx_clk_v] -rise_to [get_clocks {phy0_rx_clk}] -setup +set_false_path -rise_from [get_clocks phy0_rx_clk_v] -fall_to [get_clocks {phy0_rx_clk}] -setup +set_false_path -fall_from [get_clocks phy0_rx_clk_v] -fall_to [get_clocks {phy0_rx_clk}] -hold +set_false_path -rise_from [get_clocks phy0_rx_clk_v] -rise_to [get_clocks {phy0_rx_clk}] -hold + +set_false_path -fall_from [get_clocks phy1_rx_clk_v] -rise_to [get_clocks {phy1_rx_clk}] -setup +set_false_path -rise_from [get_clocks phy1_rx_clk_v] -fall_to [get_clocks {phy1_rx_clk}] -setup +set_false_path -fall_from [get_clocks phy1_rx_clk_v] -fall_to [get_clocks {phy1_rx_clk}] -hold +set_false_path -rise_from [get_clocks phy1_rx_clk_v] -rise_to [get_clocks {phy1_rx_clk}] -hold + + +set_false_path -fall_from [get_clocks phy2_rx_clk_v] -rise_to [get_clocks {phy2_rx_clk}] -setup +set_false_path -rise_from [get_clocks phy2_rx_clk_v] -fall_to [get_clocks {phy2_rx_clk}] -setup +set_false_path -fall_from [get_clocks phy2_rx_clk_v] -fall_to [get_clocks {phy2_rx_clk}] -hold +set_false_path -rise_from [get_clocks phy2_rx_clk_v] -rise_to [get_clocks {phy2_rx_clk}] -hold + +set_output_delay -max 0.5 -clock { phy0_tx_clk } [get_ports {phy0_tx_d[0] phy0_tx_d[1] phy0_tx_d[2] phy0_tx_d[3] phy0_tx_ctl}] -add_delay +set_output_delay -max 0.5 -clock { phy0_tx_clk } -clock_fall [get_ports {phy0_tx_d[0] phy0_tx_d[1] phy0_tx_d[2] phy0_tx_d[3] phy0_tx_ctl}] -add_delay + +set_output_delay -min -0.5 -clock { phy0_tx_clk } [get_ports {phy0_tx_d[0] phy0_tx_d[1] phy0_tx_d[2] phy0_tx_d[3] phy0_tx_ctl}] -add_delay +set_output_delay -min -0.5 -clock { phy0_tx_clk } -clock_fall [get_ports {phy0_tx_d[0] phy0_tx_d[1] phy0_tx_d[2] phy0_tx_d[3] phy0_tx_ctl}] -add_delay + +set_output_delay -max 0.5 -clock { phy1_tx_clk } [get_ports {phy1_tx_d[0] phy1_tx_d[1] phy1_tx_d[2] phy1_tx_d[3] phy1_tx_ctl}] +set_output_delay -max 0.5 -clock { phy1_tx_clk } -clock_fall [get_ports {phy1_tx_d[0] phy1_tx_d[1] phy1_tx_d[2] phy1_tx_d[3] phy1_tx_ctl}] -add_delay + +set_output_delay -min -0.5 -clock { phy1_tx_clk } [get_ports {phy1_tx_d[0] phy1_tx_d[1] phy1_tx_d[2] phy1_tx_d[3] phy1_tx_ctl}] -add_delay +set_output_delay -min -0.5 -clock { phy1_tx_clk } -clock_fall [get_ports {phy1_tx_d[0] phy1_tx_d[1] phy1_tx_d[2] phy1_tx_d[3] phy1_tx_ctl}] -add_delay + +set_output_delay -max 0.5 -clock { phy2_tx_clk } [get_ports {phy2_tx_d[0] phy2_tx_d[2] phy2_tx_d[2] phy2_tx_d[3] phy2_tx_ctl}] +set_output_delay -max 0.5 -clock { phy2_tx_clk } -clock_fall [get_ports {phy2_tx_d[0] phy2_tx_d[2] phy2_tx_d[2] phy2_tx_d[3] phy2_tx_ctl}] -add_delay + +set_output_delay -min -0.5 -clock { phy2_tx_clk } [get_ports {phy2_tx_d[0] phy2_tx_d[2] phy2_tx_d[2] phy2_tx_d[3] phy2_tx_ctl}] -add_delay +set_output_delay -min -0.5 -clock { phy2_tx_clk } -clock_fall [get_ports {phy2_tx_d[0] phy2_tx_d[2] phy2_tx_d[2] phy2_tx_d[3] phy2_tx_ctl}] -add_delay
\ No newline at end of file diff --git a/manufacturer/altera/cyclone10_lp/betsy_assignment_defaults.qdf b/manufacturer/altera/cyclone10_lp/betsy_assignment_defaults.qdf new file mode 100644 index 0000000..b0bacd2 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/betsy_assignment_defaults.qdf @@ -0,0 +1,806 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2022 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details, at +# https://fpgasoftware.intel.com/eula. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition +# Date created = 12:01:56 May 07, 2023 +# +# -------------------------------------------------------------------------- # +# +# Note: +# +# 1) Do not modify this file. This file was generated +# automatically by the Quartus Prime software and is used +# to preserve global assignments across Quartus Prime versions. +# +# -------------------------------------------------------------------------- # + +set_global_assignment -name IP_COMPONENT_REPORT_HIERARCHY Off +set_global_assignment -name IP_COMPONENT_INTERNAL Off +set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On +set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off +set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off +set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db +set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off +set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off +set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off +set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off +set_global_assignment -name HC_OUTPUT_DIR hc_output +set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off +set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off +set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On +set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off +set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings" +set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On +set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On +set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off +set_global_assignment -name REVISION_TYPE Base -family "Arria V" +set_global_assignment -name REVISION_TYPE Base -family "Stratix V" +set_global_assignment -name REVISION_TYPE Base -family "Arria V GZ" +set_global_assignment -name REVISION_TYPE Base -family "Cyclone V" +set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle" +set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On +set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On +set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On +set_global_assignment -name DO_COMBINED_ANALYSIS Off +set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT Off +set_global_assignment -name ENABLE_HPS_INTERNAL_TIMING Off +set_global_assignment -name EMIF_SOC_PHYCLK_ADVANCE_MODELING Off +set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN Off +set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On +set_global_assignment -name TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria V" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone 10 LP" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "MAX 10" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix IV" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone IV E" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria 10" 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+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V" +set_global_assignment -name TIMING_ANALYZER_REPORT_NUM_WORST_CASE_TIMING_PATHS 100 +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria V" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone 10 LP" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "MAX 10" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone IV E" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix IV" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria 10" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL Off -family "MAX V" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix V" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria V GZ" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL Off -family "MAX II" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GX" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GZ" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone IV GX" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone V" +set_global_assignment -name OPTIMIZATION_MODE Balanced +set_global_assignment -name ALLOW_REGISTER_MERGING On +set_global_assignment -name ALLOW_REGISTER_DUPLICATION On +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria V" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON -family "Cyclone 10 LP" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX 10" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Stratix IV" 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Off +set_global_assignment -name ENABLE_IP_DEBUG Off +set_global_assignment -name SAVE_DISK_SPACE On +set_global_assignment -name OCP_HW_EVAL Enable +set_global_assignment -name DEVICE_FILTER_PACKAGE Any +set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any +set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>" +set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001 +set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993 +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name TRUE_WYSIWYG_FLOW Off +set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off +set_global_assignment -name STATE_MACHINE_PROCESSING Auto +set_global_assignment -name SAFE_STATE_MACHINE Off +set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On +set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On +set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off 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MERCURY_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name ALLOW_XOR_GATE_USAGE On +set_global_assignment -name AUTO_LCELL_INSERTION On +set_global_assignment -name CARRY_CHAIN_LENGTH 48 +set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32 +set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32 +set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48 +set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70 +set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70 +set_global_assignment -name CASCADE_CHAIN_LENGTH 2 +set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16 +set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4 +set_global_assignment -name AUTO_CARRY_CHAINS On +set_global_assignment -name AUTO_CASCADE_CHAINS On +set_global_assignment -name AUTO_PARALLEL_EXPANDERS On +set_global_assignment -name AUTO_OPEN_DRAIN_PINS On +set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off +set_global_assignment -name AUTO_ROM_RECOGNITION On +set_global_assignment -name AUTO_RAM_RECOGNITION On +set_global_assignment -name AUTO_DSP_RECOGNITION On +set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto +set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto +set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On +set_global_assignment -name STRICT_RAM_RECOGNITION Off +set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On +set_global_assignment -name FORCE_SYNCH_CLEAR Off +set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On +set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off +set_global_assignment -name AUTO_RESOURCE_SHARING Off +set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off +set_global_assignment -name MAX7000_FANIN_PER_CELL 100 +set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On +set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)" +set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)" +set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)" +set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off +set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone 10 LP" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "MAX 10" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria 10" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX" +set_global_assignment -name REPORT_PARAMETER_SETTINGS On +set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On +set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On +set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone 10 LP" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX 10" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria 10" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V" +set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation" +set_global_assignment -name HDL_MESSAGE_LEVEL Level2 +set_global_assignment -name USE_HIGH_SPEED_ADDER Auto +set_global_assignment -name NUMBER_OF_PROTECTED_REGISTERS_REPORTED 100 +set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000 +set_global_assignment -name NUMBER_OF_SYNTHESIS_MIGRATION_ROWS 5000 +set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS Off +set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000 +set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100 +set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On +set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off +set_global_assignment -name BLOCK_DESIGN_NAMING Auto +set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off +set_global_assignment -name SYNTHESIS_EFFORT Auto +set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On +set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off +set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium +set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone 10 LP" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "MAX 10" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria 10" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX" +set_global_assignment -name MAX_LABS "-1 (Unlimited)" +set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On +set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)" +set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On +set_global_assignment -name PRPOF_ID Off +set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING Off +set_global_assignment -name REPORT_PARAMETER_SETTINGS_PRO On +set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS_PRO On +set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE Off +set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off +set_global_assignment -name AUTO_MERGE_PLLS On +set_global_assignment -name IGNORE_MODE_FOR_MERGE Off +set_global_assignment -name TXPMA_SLEW_RATE Low +set_global_assignment -name ADCE_ENABLED Auto +set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal +set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off +set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0 +set_global_assignment -name PHYSICAL_SYNTHESIS Off +set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off +set_global_assignment -name DEVICE AUTO +set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off +set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off +set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On +set_global_assignment -name ENABLE_NCEO_OUTPUT Off +set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name STRATIXIII_UPDATE_MODE Standard +set_global_assignment -name STRATIX_UPDATE_MODE Standard +set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image" +set_global_assignment -name CVP_MODE Off +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria 10" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Stratix V" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V GZ" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Cyclone V" +set_global_assignment -name VID_OPERATION_MODE "PMBus Slave" +set_global_assignment -name USE_CONF_DONE AUTO +set_global_assignment -name USE_PWRMGT_SCL AUTO +set_global_assignment -name USE_PWRMGT_SDA AUTO +set_global_assignment -name USE_PWRMGT_ALERT AUTO +set_global_assignment -name USE_INIT_DONE AUTO +set_global_assignment -name USE_CVP_CONFDONE AUTO +set_global_assignment -name USE_SEU_ERROR AUTO +set_global_assignment -name RESERVE_AVST_CLK_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_VALID_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration" +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name USER_START_UP_CLOCK Off +set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND Off +set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off +set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS On +set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION On +set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC +set_global_assignment -name ENABLE_VREFA_PIN Off +set_global_assignment -name ENABLE_VREFB_PIN Off +set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off +set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off +set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off +set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground" +set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off +set_global_assignment -name INIT_DONE_OPEN_DRAIN On +set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name ENABLE_CONFIGURATION_PINS On +set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off +set_global_assignment -name ENABLE_NCE_PIN Off +set_global_assignment -name ENABLE_BOOT_SEL_PIN On +set_global_assignment -name CRC_ERROR_CHECKING Off +set_global_assignment -name INTERNAL_SCRUBBING Off +set_global_assignment -name PR_ERROR_OPEN_DRAIN On +set_global_assignment -name PR_READY_OPEN_DRAIN On +set_global_assignment -name ENABLE_CVP_CONFDONE Off +set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On +set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone 10 LP" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "MAX 10" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone 10 LP" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "MAX 10" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V" +set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix IV" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix V" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria V GZ" +set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0 +set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation" +set_global_assignment -name OPTIMIZE_SSN Off +set_global_assignment -name OPTIMIZE_TIMING "Normal compilation" +set_global_assignment -name ECO_OPTIMIZE_TIMING Off +set_global_assignment -name ECO_REGENERATE_REPORT Off +set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal +set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically +set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically +set_global_assignment -name SEED 1 +set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION OFF +set_global_assignment -name RESERVE_ROUTING_OUTPUT_FLEXIBILITY Off +set_global_assignment -name SLOW_SLEW_RATE Off +set_global_assignment -name PCI_IO Off +set_global_assignment -name TURBO_BIT On +set_global_assignment -name WEAK_PULL_UP_RESISTOR Off +set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off +set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off +set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On +set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto +set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto +set_global_assignment -name NORMAL_LCELL_INSERT On +set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone 10 LP" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX 10" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix IV" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV E" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria 10" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX II" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V GZ" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GX" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GZ" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV GX" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone V" +set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF +set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off +set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off +set_global_assignment -name AUTO_TURBO_BIT ON +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off +set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off +set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On +set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off +set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off +set_global_assignment -name FITTER_EFFORT "Auto Fit" +set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal +set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto +set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto +set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off +set_global_assignment -name AUTO_GLOBAL_CLOCK On +set_global_assignment -name AUTO_GLOBAL_OE On +set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On +set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic +set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off +set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up" +set_global_assignment -name ENABLE_HOLD_BACK_OFF On +set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto +set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off +set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Auto +set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On +set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone 10 LP" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "MAX 10" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V" +set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX" +set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off +set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On +set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off +set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off +set_global_assignment -name PR_DONE_OPEN_DRAIN On +set_global_assignment -name NCEO_OPEN_DRAIN On +set_global_assignment -name ENABLE_CRC_ERROR_PIN Off +set_global_assignment -name ENABLE_PR_PINS Off +set_global_assignment -name RESERVE_PR_PINS Off +set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS Off +set_global_assignment -name PR_PINS_OPEN_DRAIN Off +set_global_assignment -name CLAMPING_DIODE Off +set_global_assignment -name TRI_STATE_SPI_PINS Off +set_global_assignment -name UNUSED_TSD_PINS_GND Off +set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off +set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off +set_global_assignment -name ALM_REGISTER_PACKING_EFFORT Medium +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION Off -family "Stratix IV" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria 10" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix V" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V GZ" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Cyclone V" +set_global_assignment -name RELATIVE_NEUTRON_FLUX 1.0 +set_global_assignment -name SEU_FIT_REPORT Off +set_global_assignment -name HYPER_RETIMER Off -family "Arria 10" +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX "-1" +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR Auto +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION Auto +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS On +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS On +set_global_assignment -name EDA_SIMULATION_TOOL "<None>" +set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<None>" +set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "<None>" +set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "<None>" +set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "<None>" +set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "<None>" +set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<None>" +set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>" +set_global_assignment -name EDA_RESYNTHESIS_TOOL "<None>" +set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On +set_global_assignment -name COMPRESSION_MODE Off +set_global_assignment -name CLOCK_SOURCE Internal +set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz" +set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1 +set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off +set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF +set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F +set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name USE_CHECKSUM_AS_USERCODE On +set_global_assignment -name SECURITY_BIT Off +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone 10 LP" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX 10" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX" +set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto +set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE "PV3102 or EM1130" +set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 0000000 +set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "Auto discovery" +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 0 +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_B 0 +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 0 +set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto +set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto +set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto +set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On +set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off +set_global_assignment -name GENERATE_TTF_FILE Off +set_global_assignment -name GENERATE_RBF_FILE Off +set_global_assignment -name GENERATE_HEX_FILE Off +set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0 +set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal" +set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off +set_global_assignment -name AUTO_RESTART_CONFIGURATION On +set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off +set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off +set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone 10 LP" +set_global_assignment -name ENABLE_OCT_DONE On -family "MAX 10" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV E" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria 10" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Stratix V" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V GZ" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria II GX" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV GX" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone V" +set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF +set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off +set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off +set_global_assignment -name ENABLE_ADV_SEU_DETECTION Off +set_global_assignment -name POR_SCHEME "Instant ON" +set_global_assignment -name EN_USER_IO_WEAK_PULLUP On +set_global_assignment -name EN_SPI_IO_WEAK_PULLUP On +set_global_assignment -name POF_VERIFY_PROTECT Off +set_global_assignment -name ENABLE_SPI_MODE_CHECK Off +set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK On +set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off +set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0 +set_global_assignment -name GENERATE_PMSF_FILES On +set_global_assignment -name START_TIME 0ns +set_global_assignment -name SIMULATION_MODE TIMING +set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off +set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On +set_global_assignment -name SETUP_HOLD_DETECTION Off +set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off +set_global_assignment -name CHECK_OUTPUTS Off +set_global_assignment -name SIMULATION_COVERAGE On +set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name GLITCH_DETECTION Off +set_global_assignment -name GLITCH_INTERVAL 1ns +set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off +set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On +set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off +set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On +set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE +set_global_assignment -name SIMULATION_NETLIST_VIEWER Off +set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT +set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT +set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off +set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO +set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO +set_global_assignment -name DRC_TOP_FANOUT 50 +set_global_assignment -name DRC_FANOUT_EXCEEDING 30 +set_global_assignment -name DRC_GATED_CLOCK_FEED 30 +set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY +set_global_assignment -name ENABLE_DRC_SETTINGS Off +set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25 +set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10 +set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30 +set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2 +set_global_assignment -name MERGE_HEX_FILE Off +set_global_assignment -name GENERATE_SVF_FILE Off +set_global_assignment -name GENERATE_ISC_FILE Off +set_global_assignment -name GENERATE_JAM_FILE Off +set_global_assignment -name GENERATE_JBC_FILE Off +set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On +set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off +set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off +set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off +set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off +set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On +set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off +set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state" +set_global_assignment -name HPS_EARLY_IO_RELEASE Off +set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off +set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off +set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_USE_PVA On +set_global_assignment -name POWER_USE_INPUT_FILE "No File" +set_global_assignment -name POWER_USE_INPUT_FILES Off +set_global_assignment -name POWER_VCD_FILTER_GLITCHES On +set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off +set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off +set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL +set_global_assignment -name POWER_AUTO_COMPUTE_TJ On +set_global_assignment -name POWER_TJ_VALUE 25 +set_global_assignment -name POWER_USE_TA_VALUE 25 +set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off +set_global_assignment -name POWER_BOARD_TEMPERATURE 25 +set_global_assignment -name POWER_HPS_ENABLE Off +set_global_assignment -name POWER_HPS_PROC_FREQ 0.0 +set_global_assignment -name ENABLE_SMART_VOLTAGE_ID Off +set_global_assignment -name IGNORE_PARTITIONS Off +set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off +set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On +set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End" +set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On +set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On +set_global_assignment -name RTLV_GROUP_RELATED_NODES On +set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off +set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off +set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On +set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On +set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On +set_global_assignment -name EQC_BBOX_MERGE On +set_global_assignment -name EQC_LVDS_MERGE On +set_global_assignment -name EQC_RAM_UNMERGING On +set_global_assignment -name EQC_DFF_SS_EMULATION On +set_global_assignment -name EQC_RAM_REGISTER_UNPACK On +set_global_assignment -name EQC_MAC_REGISTER_UNPACK On +set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On +set_global_assignment -name EQC_STRUCTURE_MATCHING On +set_global_assignment -name EQC_AUTO_BREAK_CONE On +set_global_assignment -name EQC_POWER_UP_COMPARE Off +set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On +set_global_assignment -name EQC_AUTO_INVERSION On +set_global_assignment -name EQC_AUTO_TERMINATE On +set_global_assignment -name EQC_SUB_CONE_REPORT Off +set_global_assignment -name EQC_RENAMING_RULES On +set_global_assignment -name EQC_PARAMETER_CHECK On +set_global_assignment -name EQC_AUTO_PORTSWAP On +set_global_assignment -name EQC_DETECT_DONT_CARES On +set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off +set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ? +set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ? +set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ? +set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ? +set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ? +set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ? +set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ? +set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ? +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ? +set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ? +set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "<None>" -section_id ? +set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ? +set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ? +set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ? +set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ? +set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ? +set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ? +set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ? +set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ? +set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ? +set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ? +set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ? +set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ? +set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ? +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST On -section_id ? +set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ? +set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ? +set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ? +set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ? +set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ? +set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ? +set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ? +set_global_assignment -name EDA_IBIS_EXTENDED_MODEL_SELECTOR Off -section_id ? +set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ? +set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ? +set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ? +set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ? +set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ? +set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p2 -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ? +set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ? +set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ? +set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ? +set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ? +set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ? +set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ? +set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ? +set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ? +set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ? +set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ? +set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ? +set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ? +set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ? diff --git a/manufacturer/altera/cyclone10_lp/brds/betsy/betsy.stp b/manufacturer/altera/cyclone10_lp/brds/betsy/betsy.stp new file mode 100644 index 0000000..f87d148 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/brds/betsy/betsy.stp @@ -0,0 +1,6345 @@ +<session jtag_chain="USB-BlasterII [1-3]" jtag_device="@1: 10CL025(Y|Z)/EP3C25/EP4CE22 (0x020F30DD)" sof_file="../../output_betsy/betsy.sof"> + <display_tree gui_logging_enabled="0"> + <display_branch instance="rgmii_0" signal_set="USE_GLOBAL_TEMP" trigger="USE_GLOBAL_TEMP"/> + <display_branch instance="rgmii_1" log="USE_GLOBAL_TEMP" signal_set="USE_GLOBAL_TEMP" trigger="USE_GLOBAL_TEMP"/> + <display_branch instance="top" log="USE_GLOBAL_TEMP" signal_set="USE_GLOBAL_TEMP" trigger="USE_GLOBAL_TEMP"/> + <display_branch instance="controller_mdio" signal_set="USE_GLOBAL_TEMP" trigger="USE_GLOBAL_TEMP"/> + <display_branch instance="tst_mac0" log="USE_GLOBAL_TEMP" signal_set="USE_GLOBAL_TEMP" trigger="USE_GLOBAL_TEMP"/> + <display_branch instance="tst_mac2_rx" signal_set="USE_GLOBAL_TEMP" trigger="USE_GLOBAL_TEMP"/> + <display_branch instance="tst_switch" signal_set="USE_GLOBAL_TEMP" trigger="USE_GLOBAL_TEMP"/> + <display_branch instance="tst_controller" log="USE_GLOBAL_TEMP" signal_set="USE_GLOBAL_TEMP" trigger="USE_GLOBAL_TEMP"/> + </display_tree> + <instance enabled="false" entity_name="sld_signaltap" is_auto_node="yes" is_expanded="true" name="rgmii_0" source_file="sld_signaltap.vhd"> + <node_ip_info instance_id="0" mfg_id="110" node_id="0" version="6"/> + <signal_set global_temp="1" is_expanded="true" name="signal_set: 2025/07/02 01:41:08 #0"> + <clock name="phy0_rx_clk" polarity="posedge" tap_mode="classic"/> + <config pipeline_level="0" ram_type="AUTO" reserved_data_nodes="0" reserved_storage_qualifier_nodes="0" reserved_trigger_nodes="0" sample_depth="512" trigger_in_enable="no" trigger_out_enable="no"/> + <top_entity/> + <signal_vec> + <trigger_input_vec> + <wire name="fcs:fcs_rx_0|addr[0]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|addr[1]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[0]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[10]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[11]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[12]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[13]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[14]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[15]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[16]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[17]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[18]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[19]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[1]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[20]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[21]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[22]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[23]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[24]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[25]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[26]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[27]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[28]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[29]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[2]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[30]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[31]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[3]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[4]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[5]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[6]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[7]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[8]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[9]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|din[0]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|din[1]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|din[2]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|din[3]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|din[4]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|din[5]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|din[6]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|din[7]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|dout[0]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|dout[1]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|dout[2]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|dout[3]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|dout[4]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|dout[5]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|dout[6]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|dout[7]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|enable" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|init" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|fcs_rx_addr[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|fcs_rx_addr[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|fcs_rx_addr_e" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|fcs_rx_din[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|fcs_rx_din[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|fcs_rx_din[2]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|fcs_rx_din[3]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|fcs_rx_din[4]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|fcs_rx_din[5]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|fcs_rx_din[6]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|fcs_rx_din[7]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|fcs_rx_dout[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|fcs_rx_dout[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|fcs_rx_dout[2]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|fcs_rx_dout[3]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|fcs_rx_dout[4]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|fcs_rx_dout[5]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|fcs_rx_dout[6]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|fcs_rx_dout[7]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|fcs_rx_enable" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|fcs_rx_error" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|fcs_rx_init" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_byte_cnt[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_byte_cnt[10]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_byte_cnt[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_byte_cnt[2]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_byte_cnt[3]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_byte_cnt[4]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_byte_cnt[5]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_byte_cnt[6]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_byte_cnt[7]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_byte_cnt[8]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_byte_cnt[9]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_ctl[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_ctl[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_ctl_m1[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_ctl_m1[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_ctl_m2[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_ctl_m2[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d[2]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d[3]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d[4]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d[5]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d[6]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d[7]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m1[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m1[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m1[2]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m1[3]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m1[4]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m1[5]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m1[6]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m1[7]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m2[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m2[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m2[2]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m2[3]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m2[4]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m2[5]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m2[6]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m2[7]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_eop" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_fifo_d[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_fifo_d[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_fifo_d[2]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_fifo_d[3]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_fifo_d[4]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_fifo_d[5]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_fifo_d[6]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_fifo_d[7]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_fifo_d[8]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_l3_proto[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_l3_proto[10]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_l3_proto[11]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_l3_proto[12]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_l3_proto[13]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_l3_proto[14]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_l3_proto[15]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_l3_proto[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_l3_proto[2]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_l3_proto[3]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_l3_proto[4]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_l3_proto[5]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_l3_proto[6]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_l3_proto[7]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_l3_proto[8]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_l3_proto[9]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_packet_complete" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[10]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[11]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[2]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[3]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[4]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[5]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[6]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[7]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[8]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[9]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_sample" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_sop" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_state[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_state[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_state[2]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_state[3]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_wr_done" tap_mode="classic"/> + </trigger_input_vec> + <data_input_vec> + <wire name="fcs:fcs_rx_0|addr[0]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|addr[1]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[0]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[10]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[11]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[12]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[13]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[14]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[15]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[16]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[17]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[18]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[19]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[1]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[20]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[21]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[22]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[23]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[24]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[25]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[26]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[27]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[28]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[29]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[2]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[30]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[31]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[3]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[4]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[5]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[6]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[7]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[8]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[9]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|din[0]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|din[1]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|din[2]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|din[3]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|din[4]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|din[5]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|din[6]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|din[7]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|dout[0]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|dout[1]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|dout[2]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|dout[3]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|dout[4]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|dout[5]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|dout[6]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|dout[7]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|enable" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|init" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|fcs_rx_addr[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|fcs_rx_addr[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|fcs_rx_addr_e" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|fcs_rx_din[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|fcs_rx_din[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|fcs_rx_din[2]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|fcs_rx_din[3]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|fcs_rx_din[4]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|fcs_rx_din[5]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|fcs_rx_din[6]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|fcs_rx_din[7]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|fcs_rx_dout[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|fcs_rx_dout[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|fcs_rx_dout[2]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|fcs_rx_dout[3]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|fcs_rx_dout[4]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|fcs_rx_dout[5]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|fcs_rx_dout[6]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|fcs_rx_dout[7]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|fcs_rx_enable" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|fcs_rx_error" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|fcs_rx_init" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_byte_cnt[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_byte_cnt[10]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_byte_cnt[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_byte_cnt[2]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_byte_cnt[3]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_byte_cnt[4]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_byte_cnt[5]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_byte_cnt[6]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_byte_cnt[7]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_byte_cnt[8]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_byte_cnt[9]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_ctl[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_ctl[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_ctl_m1[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_ctl_m1[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_ctl_m2[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_ctl_m2[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d[2]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d[3]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d[4]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d[5]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d[6]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d[7]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m1[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m1[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m1[2]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m1[3]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m1[4]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m1[5]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m1[6]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m1[7]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m2[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m2[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m2[2]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m2[3]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m2[4]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m2[5]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m2[6]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m2[7]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_eop" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_fifo_d[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_fifo_d[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_fifo_d[2]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_fifo_d[3]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_fifo_d[4]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_fifo_d[5]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_fifo_d[6]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_fifo_d[7]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_fifo_d[8]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_l3_proto[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_l3_proto[10]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_l3_proto[11]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_l3_proto[12]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_l3_proto[13]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_l3_proto[14]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_l3_proto[15]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_l3_proto[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_l3_proto[2]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_l3_proto[3]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_l3_proto[4]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_l3_proto[5]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_l3_proto[6]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_l3_proto[7]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_l3_proto[8]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_l3_proto[9]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_packet_complete" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[10]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[11]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[2]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[3]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[4]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[5]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[6]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[7]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[8]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[9]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_sample" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_sop" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_state[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_state[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_state[2]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_state[3]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_wr_done" tap_mode="classic"/> + </data_input_vec> + <storage_qualifier_input_vec> + <wire name="fcs:fcs_rx_0|addr[0]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|addr[1]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[0]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[10]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[11]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[12]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[13]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[14]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[15]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[16]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[17]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[18]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[19]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[1]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[20]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[21]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[22]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[23]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[24]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[25]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[26]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[27]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[28]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[29]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[2]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[30]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[31]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[3]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[4]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[5]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[6]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[7]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[8]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|crc[9]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|din[0]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|din[1]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|din[2]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|din[3]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|din[4]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|din[5]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|din[6]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|din[7]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|dout[0]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|dout[1]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|dout[2]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|dout[3]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|dout[4]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|dout[5]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|dout[6]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|dout[7]" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|enable" tap_mode="classic"/> + <wire name="fcs:fcs_rx_0|init" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|fcs_rx_addr[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|fcs_rx_addr[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|fcs_rx_addr_e" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|fcs_rx_din[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|fcs_rx_din[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|fcs_rx_din[2]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|fcs_rx_din[3]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|fcs_rx_din[4]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|fcs_rx_din[5]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|fcs_rx_din[6]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|fcs_rx_din[7]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|fcs_rx_dout[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|fcs_rx_dout[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|fcs_rx_dout[2]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|fcs_rx_dout[3]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|fcs_rx_dout[4]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|fcs_rx_dout[5]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|fcs_rx_dout[6]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|fcs_rx_dout[7]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|fcs_rx_enable" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|fcs_rx_error" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|fcs_rx_init" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_byte_cnt[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_byte_cnt[10]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_byte_cnt[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_byte_cnt[2]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_byte_cnt[3]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_byte_cnt[4]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_byte_cnt[5]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_byte_cnt[6]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_byte_cnt[7]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_byte_cnt[8]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_byte_cnt[9]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_ctl[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_ctl[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_ctl_m1[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_ctl_m1[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_ctl_m2[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_ctl_m2[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d[2]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d[3]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d[4]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d[5]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d[6]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d[7]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m1[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m1[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m1[2]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m1[3]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m1[4]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m1[5]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m1[6]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m1[7]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m2[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m2[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m2[2]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m2[3]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m2[4]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m2[5]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m2[6]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m2[7]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_eop" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_fifo_d[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_fifo_d[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_fifo_d[2]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_fifo_d[3]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_fifo_d[4]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_fifo_d[5]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_fifo_d[6]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_fifo_d[7]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_fifo_d[8]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_l3_proto[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_l3_proto[10]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_l3_proto[11]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_l3_proto[12]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_l3_proto[13]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_l3_proto[14]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_l3_proto[15]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_l3_proto[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_l3_proto[2]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_l3_proto[3]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_l3_proto[4]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_l3_proto[5]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_l3_proto[6]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_l3_proto[7]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_l3_proto[8]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_l3_proto[9]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_packet_complete" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[10]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[11]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[2]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[3]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[4]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[5]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[6]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[7]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[8]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[9]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_sample" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_sop" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_state[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_state[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_state[2]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_state[3]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_wr_done" tap_mode="classic"/> + </storage_qualifier_input_vec> + </signal_vec> + <presentation> + <unified_setup_data_view> + <node is_selected="false" level-0="alt_or" name="mac_rgmii:mac_0|rx_ctl[1..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <node data_index="86" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_ctl[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="86" tap_mode="classic" trigger_index="86" type="unknown"/> + <node data_index="85" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_ctl[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="85" tap_mode="classic" trigger_index="85" type="unknown"/> + </node> + <node is_selected="false" level-0="alt_or" name="mac_rgmii:mac_0|rx_d[7..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <node data_index="98" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="98" tap_mode="classic" trigger_index="98" type="unknown"/> + <node data_index="97" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="97" tap_mode="classic" trigger_index="97" type="unknown"/> + <node data_index="96" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="96" tap_mode="classic" trigger_index="96" type="unknown"/> + <node data_index="95" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="95" tap_mode="classic" trigger_index="95" type="unknown"/> + <node data_index="94" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="94" tap_mode="classic" trigger_index="94" type="unknown"/> + <node data_index="93" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="93" tap_mode="classic" trigger_index="93" type="unknown"/> + <node data_index="92" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="92" tap_mode="classic" trigger_index="92" type="unknown"/> + <node data_index="91" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="91" tap_mode="classic" trigger_index="91" type="unknown"/> + </node> + <node is_selected="false" level-0="alt_or" name="mac_rgmii:mac_0|rx_ctl_m1[1..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <node data_index="88" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_ctl_m1[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="88" tap_mode="classic" trigger_index="88" type="unknown"/> + <node data_index="87" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_ctl_m1[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="87" tap_mode="classic" trigger_index="87" type="unknown"/> + </node> + <node is_selected="false" level-0="alt_or" name="mac_rgmii:mac_0|rx_d_m1[7..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <node data_index="106" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d_m1[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="106" tap_mode="classic" trigger_index="106" type="unknown"/> + <node data_index="105" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d_m1[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="105" tap_mode="classic" trigger_index="105" type="unknown"/> + <node data_index="104" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d_m1[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="104" tap_mode="classic" trigger_index="104" type="unknown"/> + <node data_index="103" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d_m1[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="103" tap_mode="classic" trigger_index="103" type="unknown"/> + <node data_index="102" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d_m1[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="102" tap_mode="classic" trigger_index="102" type="unknown"/> + <node data_index="101" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d_m1[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="101" tap_mode="classic" trigger_index="101" type="unknown"/> + <node data_index="100" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d_m1[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="100" tap_mode="classic" trigger_index="100" type="unknown"/> + <node data_index="99" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d_m1[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="99" tap_mode="classic" trigger_index="99" type="unknown"/> + </node> + <node is_selected="false" level-0="alt_or" name="mac_rgmii:mac_0|rx_state[3..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <node data_index="159" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_state[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="159" tap_mode="classic" trigger_index="159" type="unknown"/> + <node data_index="158" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_state[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="158" tap_mode="classic" trigger_index="158" type="unknown"/> + <node data_index="157" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_state[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="157" tap_mode="classic" trigger_index="157" type="unknown"/> + <node data_index="156" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_state[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="156" tap_mode="classic" trigger_index="156" type="unknown"/> + </node> + <node is_selected="false" level-0="alt_or" name="mac_rgmii:mac_0|rx_byte_cnt[10..0]" order="msb_to_lsb" radix="unsigned_dec" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <node data_index="75" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_byte_cnt[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="75" tap_mode="classic" trigger_index="75" type="unknown"/> + <node data_index="84" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_byte_cnt[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="84" tap_mode="classic" trigger_index="84" type="unknown"/> + <node data_index="83" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_byte_cnt[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="83" tap_mode="classic" trigger_index="83" type="unknown"/> + <node data_index="82" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_byte_cnt[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" 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tap_mode="classic" trigger_index="30" type="unknown"/> + <node data_index="29" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|crc[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="29" tap_mode="classic" trigger_index="29" type="unknown"/> + <node data_index="28" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|crc[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="28" tap_mode="classic" trigger_index="28" type="unknown"/> + <node data_index="27" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|crc[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="27" tap_mode="classic" trigger_index="27" type="unknown"/> + <node data_index="24" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|crc[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="24" tap_mode="classic" trigger_index="24" type="unknown"/> + <node data_index="13" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|crc[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="13" tap_mode="classic" trigger_index="13" type="unknown"/> + <node data_index="2" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|crc[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="2" tap_mode="classic" trigger_index="2" type="unknown"/> + </node> + <node is_selected="false" level-0="alt_or" name="fcs:fcs_rx_0|din[7..0]" order="lsb_to_msb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <node data_index="34" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|din[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="34" tap_mode="classic" trigger_index="34" type="unknown"/> + <node data_index="35" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|din[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="35" tap_mode="classic" trigger_index="35" type="unknown"/> + <node data_index="36" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|din[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="36" tap_mode="classic" trigger_index="36" type="unknown"/> + <node data_index="37" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|din[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="37" tap_mode="classic" trigger_index="37" type="unknown"/> + <node data_index="38" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|din[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="38" tap_mode="classic" trigger_index="38" type="unknown"/> + <node data_index="39" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|din[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="39" tap_mode="classic" trigger_index="39" type="unknown"/> + <node data_index="40" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|din[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="40" tap_mode="classic" trigger_index="40" type="unknown"/> + <node data_index="41" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|din[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="41" tap_mode="classic" trigger_index="41" type="unknown"/> + </node> + <node is_selected="false" level-0="alt_or" name="fcs:fcs_rx_0|dout[7..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <node data_index="49" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|dout[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="49" tap_mode="classic" trigger_index="49" type="unknown"/> + <node data_index="48" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|dout[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="48" tap_mode="classic" trigger_index="48" type="unknown"/> + <node data_index="47" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|dout[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="47" tap_mode="classic" trigger_index="47" type="unknown"/> + <node data_index="46" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|dout[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="46" tap_mode="classic" trigger_index="46" type="unknown"/> + <node data_index="45" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|dout[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="45" tap_mode="classic" trigger_index="45" type="unknown"/> + <node data_index="44" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|dout[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="44" tap_mode="classic" trigger_index="44" type="unknown"/> + <node data_index="43" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|dout[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="43" tap_mode="classic" trigger_index="43" type="unknown"/> + <node data_index="42" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|dout[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="42" tap_mode="classic" trigger_index="42" type="unknown"/> + </node> + <node data_index="50" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|enable" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="50" tap_mode="classic" trigger_index="50" type="unknown"/> + <node data_index="51" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|init" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="51" tap_mode="classic" trigger_index="51" type="unknown"/> + </unified_setup_data_view> + <data_view> + <bus is_selected="false" level-0="alt_or" name="mac_rgmii:mac_0|rx_ctl[1..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="86" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_ctl[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="86" tap_mode="classic" trigger_index="86" type="unknown"/> + <net data_index="85" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_ctl[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="85" tap_mode="classic" trigger_index="85" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="mac_rgmii:mac_0|rx_d[7..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="98" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="98" tap_mode="classic" trigger_index="98" type="unknown"/> + <net data_index="97" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="97" tap_mode="classic" trigger_index="97" type="unknown"/> + <net data_index="96" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="96" tap_mode="classic" trigger_index="96" type="unknown"/> + <net data_index="95" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="95" tap_mode="classic" trigger_index="95" type="unknown"/> + <net data_index="94" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="94" tap_mode="classic" trigger_index="94" type="unknown"/> + <net data_index="93" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="93" tap_mode="classic" trigger_index="93" type="unknown"/> + <net data_index="92" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="92" tap_mode="classic" trigger_index="92" type="unknown"/> + <net data_index="91" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="91" tap_mode="classic" trigger_index="91" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="mac_rgmii:mac_0|rx_ctl_m1[1..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="88" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_ctl_m1[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="88" tap_mode="classic" trigger_index="88" type="unknown"/> + <net data_index="87" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_ctl_m1[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="87" tap_mode="classic" trigger_index="87" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="mac_rgmii:mac_0|rx_d_m1[7..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="106" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d_m1[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="106" tap_mode="classic" trigger_index="106" type="unknown"/> + <net data_index="105" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d_m1[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="105" tap_mode="classic" trigger_index="105" type="unknown"/> + <net data_index="104" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d_m1[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="104" tap_mode="classic" trigger_index="104" type="unknown"/> + <net data_index="103" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d_m1[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="103" tap_mode="classic" trigger_index="103" type="unknown"/> + <net data_index="102" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d_m1[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="102" tap_mode="classic" trigger_index="102" type="unknown"/> + <net data_index="101" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d_m1[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="101" tap_mode="classic" trigger_index="101" type="unknown"/> + <net data_index="100" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d_m1[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="100" tap_mode="classic" trigger_index="100" type="unknown"/> + <net data_index="99" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d_m1[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="99" tap_mode="classic" trigger_index="99" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="mac_rgmii:mac_0|rx_state[3..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="159" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_state[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="159" tap_mode="classic" trigger_index="159" type="unknown"/> + <net data_index="158" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_state[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="158" tap_mode="classic" trigger_index="158" type="unknown"/> + <net data_index="157" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_state[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="157" tap_mode="classic" trigger_index="157" type="unknown"/> + <net data_index="156" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_state[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="156" tap_mode="classic" trigger_index="156" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="mac_rgmii:mac_0|rx_byte_cnt[10..0]" order="msb_to_lsb" radix="unsigned_dec" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="75" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_byte_cnt[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="75" tap_mode="classic" trigger_index="75" type="unknown"/> + <net data_index="84" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_byte_cnt[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="84" tap_mode="classic" trigger_index="84" type="unknown"/> + <net data_index="83" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_byte_cnt[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="83" tap_mode="classic" trigger_index="83" type="unknown"/> + <net data_index="82" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_byte_cnt[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="82" tap_mode="classic" trigger_index="82" type="unknown"/> + <net data_index="81" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_byte_cnt[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="81" tap_mode="classic" trigger_index="81" type="unknown"/> + <net data_index="80" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_byte_cnt[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="80" tap_mode="classic" trigger_index="80" type="unknown"/> + <net data_index="79" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_byte_cnt[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="79" tap_mode="classic" trigger_index="79" type="unknown"/> + <net data_index="78" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_byte_cnt[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="78" tap_mode="classic" trigger_index="78" type="unknown"/> + <net data_index="77" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_byte_cnt[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="77" tap_mode="classic" trigger_index="77" type="unknown"/> + <net data_index="76" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_byte_cnt[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="76" tap_mode="classic" trigger_index="76" type="unknown"/> + <net data_index="74" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_byte_cnt[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="74" tap_mode="classic" trigger_index="74" type="unknown"/> + </bus> + <net data_index="141" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_packet_complete" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="141" tap_mode="classic" trigger_index="141" type="unknown"/> + <net data_index="124" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_fifo_d[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="124" tap_mode="classic" trigger_index="124" type="unknown"/> + <bus is_selected="false" level-0="alt_or" name="mac_rgmii:mac_0|rx_fifo_d[7..0]" order="msb_to_lsb" state="collapse" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="123" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_fifo_d[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="123" tap_mode="classic" trigger_index="123" type="unknown"/> + <net data_index="122" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_fifo_d[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="122" tap_mode="classic" trigger_index="122" type="unknown"/> + <net data_index="121" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_fifo_d[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="121" tap_mode="classic" trigger_index="121" type="unknown"/> + <net data_index="120" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_fifo_d[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="120" tap_mode="classic" trigger_index="120" type="unknown"/> + <net data_index="119" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_fifo_d[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="119" tap_mode="classic" trigger_index="119" type="unknown"/> + <net data_index="118" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_fifo_d[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="118" tap_mode="classic" trigger_index="118" type="unknown"/> + <net data_index="117" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_fifo_d[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="117" tap_mode="classic" trigger_index="117" type="unknown"/> + <net data_index="116" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_fifo_d[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="116" tap_mode="classic" trigger_index="116" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="mac_rgmii:mac_0|rx_pkt_length[11..0]" order="msb_to_lsb" radix="unsigned_dec" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="144" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_length[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="144" tap_mode="classic" trigger_index="144" type="unknown"/> + <net data_index="143" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_length[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="143" tap_mode="classic" trigger_index="143" type="unknown"/> + <net data_index="153" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_length[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="153" tap_mode="classic" trigger_index="153" type="unknown"/> + <net data_index="152" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_length[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="152" tap_mode="classic" trigger_index="152" type="unknown"/> + <net data_index="151" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_length[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="151" tap_mode="classic" trigger_index="151" type="unknown"/> + <net data_index="150" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_length[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="150" tap_mode="classic" trigger_index="150" type="unknown"/> + <net data_index="149" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_length[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="149" tap_mode="classic" trigger_index="149" type="unknown"/> + <net data_index="148" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_length[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="148" tap_mode="classic" trigger_index="148" type="unknown"/> + <net data_index="147" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_length[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="147" tap_mode="classic" trigger_index="147" type="unknown"/> + <net data_index="146" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_length[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="146" tap_mode="classic" trigger_index="146" type="unknown"/> + <net data_index="145" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_length[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="145" tap_mode="classic" trigger_index="145" type="unknown"/> + <net data_index="142" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_length[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="142" tap_mode="classic" trigger_index="142" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="mac_rgmii:mac_0|rx_l3_proto[15..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="131" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_l3_proto[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="131" tap_mode="classic" trigger_index="131" type="unknown"/> + <net data_index="130" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_l3_proto[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="130" tap_mode="classic" trigger_index="130" type="unknown"/> + <net data_index="129" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_l3_proto[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="129" tap_mode="classic" trigger_index="129" type="unknown"/> + <net data_index="128" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_l3_proto[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="128" tap_mode="classic" trigger_index="128" type="unknown"/> + <net data_index="127" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_l3_proto[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="127" tap_mode="classic" trigger_index="127" type="unknown"/> + <net data_index="126" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_l3_proto[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="126" tap_mode="classic" trigger_index="126" type="unknown"/> + <net data_index="140" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_l3_proto[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="140" tap_mode="classic" trigger_index="140" type="unknown"/> + <net data_index="139" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_l3_proto[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="139" tap_mode="classic" trigger_index="139" type="unknown"/> + <net data_index="138" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_l3_proto[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="138" tap_mode="classic" trigger_index="138" type="unknown"/> + <net data_index="137" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_l3_proto[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="137" tap_mode="classic" trigger_index="137" type="unknown"/> + <net data_index="136" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_l3_proto[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="136" tap_mode="classic" trigger_index="136" type="unknown"/> + <net data_index="135" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_l3_proto[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="135" tap_mode="classic" trigger_index="135" type="unknown"/> + <net data_index="134" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_l3_proto[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="134" tap_mode="classic" trigger_index="134" type="unknown"/> + <net data_index="133" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_l3_proto[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="133" tap_mode="classic" trigger_index="133" type="unknown"/> + <net data_index="132" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_l3_proto[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="132" tap_mode="classic" trigger_index="132" type="unknown"/> + <net data_index="125" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_l3_proto[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="125" tap_mode="classic" trigger_index="125" type="unknown"/> + </bus> + <net data_index="160" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_wr_done" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="160" tap_mode="classic" trigger_index="160" type="unknown"/> + <net data_index="155" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_sop" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="155" tap_mode="classic" trigger_index="155" type="unknown"/> + <net data_index="115" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_eop" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="115" tap_mode="classic" trigger_index="115" type="unknown"/> + <net data_index="154" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_sample" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="154" tap_mode="classic" trigger_index="154" type="unknown"/> + <bus is_selected="false" level-0="alt_or" name="mac_rgmii:mac_0|rx_ctl_m2[1..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="90" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_ctl_m2[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="90" tap_mode="classic" trigger_index="90" type="unknown"/> + <net data_index="89" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_ctl_m2[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="89" tap_mode="classic" trigger_index="89" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="mac_rgmii:mac_0|rx_d_m2[7..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="114" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d_m2[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="114" tap_mode="classic" trigger_index="114" type="unknown"/> + <net data_index="113" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d_m2[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="113" tap_mode="classic" trigger_index="113" type="unknown"/> + <net data_index="112" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d_m2[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="112" tap_mode="classic" trigger_index="112" type="unknown"/> + <net data_index="111" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d_m2[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="111" tap_mode="classic" trigger_index="111" type="unknown"/> + <net data_index="110" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d_m2[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="110" tap_mode="classic" trigger_index="110" type="unknown"/> + <net data_index="109" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d_m2[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="109" tap_mode="classic" trigger_index="109" type="unknown"/> + <net data_index="108" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d_m2[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="108" tap_mode="classic" trigger_index="108" type="unknown"/> + <net data_index="107" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d_m2[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="107" tap_mode="classic" trigger_index="107" type="unknown"/> + </bus> + <net data_index="73" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|fcs_rx_init" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="73" tap_mode="classic" trigger_index="73" type="unknown"/> + <net data_index="71" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|fcs_rx_enable" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="71" tap_mode="classic" trigger_index="71" type="unknown"/> + <net data_index="54" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|fcs_rx_addr_e" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="54" tap_mode="classic" trigger_index="54" type="unknown"/> + <bus is_selected="false" level-0="alt_or" name="mac_rgmii:mac_0|fcs_rx_addr[1..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="53" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|fcs_rx_addr[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="53" tap_mode="classic" trigger_index="53" type="unknown"/> + <net data_index="52" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|fcs_rx_addr[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="52" tap_mode="classic" trigger_index="52" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="mac_rgmii:mac_0|fcs_rx_din[7..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="62" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|fcs_rx_din[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="62" tap_mode="classic" trigger_index="62" type="unknown"/> + <net data_index="61" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|fcs_rx_din[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="61" tap_mode="classic" trigger_index="61" type="unknown"/> + <net data_index="60" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|fcs_rx_din[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="60" tap_mode="classic" trigger_index="60" type="unknown"/> + <net data_index="59" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|fcs_rx_din[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="59" tap_mode="classic" trigger_index="59" type="unknown"/> + <net data_index="58" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|fcs_rx_din[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="58" tap_mode="classic" trigger_index="58" type="unknown"/> + <net data_index="57" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|fcs_rx_din[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="57" tap_mode="classic" trigger_index="57" type="unknown"/> + <net data_index="56" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|fcs_rx_din[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="56" tap_mode="classic" trigger_index="56" type="unknown"/> + <net data_index="55" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|fcs_rx_din[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="55" tap_mode="classic" trigger_index="55" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="mac_rgmii:mac_0|fcs_rx_dout[7..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="70" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|fcs_rx_dout[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="70" tap_mode="classic" trigger_index="70" type="unknown"/> + <net data_index="69" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|fcs_rx_dout[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="69" tap_mode="classic" trigger_index="69" type="unknown"/> + <net data_index="68" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|fcs_rx_dout[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="68" tap_mode="classic" trigger_index="68" type="unknown"/> + <net data_index="67" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|fcs_rx_dout[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="67" tap_mode="classic" trigger_index="67" type="unknown"/> + <net data_index="66" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|fcs_rx_dout[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="66" tap_mode="classic" trigger_index="66" type="unknown"/> + <net data_index="65" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|fcs_rx_dout[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="65" tap_mode="classic" trigger_index="65" type="unknown"/> + <net data_index="64" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|fcs_rx_dout[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="64" tap_mode="classic" trigger_index="64" type="unknown"/> + <net data_index="63" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|fcs_rx_dout[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="63" tap_mode="classic" trigger_index="63" type="unknown"/> + </bus> + <net data_index="72" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|fcs_rx_error" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="72" tap_mode="classic" trigger_index="72" type="unknown"/> + <bus is_selected="false" level-0="alt_or" name="fcs:fcs_rx_0|addr[1..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="1" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|addr[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="1" tap_mode="classic" trigger_index="1" type="unknown"/> + <net data_index="0" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|addr[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="0" tap_mode="classic" trigger_index="0" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="fcs:fcs_rx_0|crc[31..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="26" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|crc[31]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="26" tap_mode="classic" trigger_index="26" type="unknown"/> + <net data_index="25" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|crc[30]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="25" tap_mode="classic" trigger_index="25" type="unknown"/> + <net data_index="23" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|crc[29]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="23" tap_mode="classic" trigger_index="23" type="unknown"/> + <net data_index="22" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|crc[28]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="22" tap_mode="classic" trigger_index="22" type="unknown"/> + <net data_index="21" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|crc[27]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="21" tap_mode="classic" trigger_index="21" type="unknown"/> + <net data_index="20" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|crc[26]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="20" tap_mode="classic" trigger_index="20" type="unknown"/> + <net data_index="19" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|crc[25]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="19" tap_mode="classic" trigger_index="19" type="unknown"/> + <net data_index="18" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|crc[24]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="18" tap_mode="classic" trigger_index="18" type="unknown"/> + <net data_index="17" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|crc[23]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="17" tap_mode="classic" trigger_index="17" type="unknown"/> + <net data_index="16" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|crc[22]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="16" tap_mode="classic" trigger_index="16" type="unknown"/> + <net data_index="15" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|crc[21]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="15" tap_mode="classic" trigger_index="15" type="unknown"/> + <net data_index="14" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|crc[20]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="14" tap_mode="classic" trigger_index="14" type="unknown"/> + <net data_index="12" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|crc[19]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="12" tap_mode="classic" trigger_index="12" type="unknown"/> + <net data_index="11" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|crc[18]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="11" tap_mode="classic" trigger_index="11" type="unknown"/> + <net data_index="10" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|crc[17]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="10" tap_mode="classic" trigger_index="10" type="unknown"/> + <net data_index="9" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|crc[16]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="9" tap_mode="classic" trigger_index="9" type="unknown"/> + <net data_index="8" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|crc[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="8" tap_mode="classic" trigger_index="8" type="unknown"/> + <net data_index="7" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|crc[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="7" tap_mode="classic" trigger_index="7" type="unknown"/> + <net data_index="6" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|crc[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="6" tap_mode="classic" trigger_index="6" type="unknown"/> + <net data_index="5" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|crc[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="5" tap_mode="classic" trigger_index="5" type="unknown"/> + <net data_index="4" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|crc[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="4" tap_mode="classic" trigger_index="4" type="unknown"/> + <net data_index="3" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|crc[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="3" tap_mode="classic" trigger_index="3" type="unknown"/> + <net data_index="33" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|crc[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="33" tap_mode="classic" trigger_index="33" type="unknown"/> + <net data_index="32" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|crc[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="32" tap_mode="classic" trigger_index="32" type="unknown"/> + <net data_index="31" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|crc[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="31" tap_mode="classic" trigger_index="31" type="unknown"/> + <net data_index="30" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|crc[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="30" tap_mode="classic" trigger_index="30" type="unknown"/> + <net data_index="29" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|crc[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="29" tap_mode="classic" trigger_index="29" type="unknown"/> + <net data_index="28" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|crc[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="28" tap_mode="classic" trigger_index="28" type="unknown"/> + <net data_index="27" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|crc[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="27" tap_mode="classic" trigger_index="27" type="unknown"/> + <net data_index="24" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|crc[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="24" tap_mode="classic" trigger_index="24" type="unknown"/> + <net data_index="13" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|crc[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="13" tap_mode="classic" trigger_index="13" type="unknown"/> + <net data_index="2" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|crc[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="2" tap_mode="classic" trigger_index="2" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="fcs:fcs_rx_0|din[7..0]" order="lsb_to_msb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="34" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|din[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="34" tap_mode="classic" trigger_index="34" type="unknown"/> + <net data_index="35" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|din[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="35" tap_mode="classic" trigger_index="35" type="unknown"/> + <net data_index="36" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|din[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="36" tap_mode="classic" trigger_index="36" type="unknown"/> + <net data_index="37" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|din[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="37" tap_mode="classic" trigger_index="37" type="unknown"/> + <net data_index="38" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|din[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="38" tap_mode="classic" trigger_index="38" type="unknown"/> + <net data_index="39" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|din[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="39" tap_mode="classic" trigger_index="39" type="unknown"/> + <net data_index="40" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|din[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="40" tap_mode="classic" trigger_index="40" type="unknown"/> + <net data_index="41" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|din[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="41" tap_mode="classic" trigger_index="41" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="fcs:fcs_rx_0|dout[7..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="49" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|dout[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="49" tap_mode="classic" trigger_index="49" type="unknown"/> + <net data_index="48" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|dout[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="48" tap_mode="classic" trigger_index="48" type="unknown"/> + <net data_index="47" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|dout[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="47" tap_mode="classic" trigger_index="47" type="unknown"/> + <net data_index="46" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|dout[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="46" tap_mode="classic" trigger_index="46" type="unknown"/> + <net data_index="45" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|dout[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="45" tap_mode="classic" trigger_index="45" type="unknown"/> + <net data_index="44" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|dout[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="44" tap_mode="classic" trigger_index="44" type="unknown"/> + <net data_index="43" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|dout[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="43" tap_mode="classic" trigger_index="43" type="unknown"/> + <net data_index="42" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|dout[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="42" tap_mode="classic" trigger_index="42" type="unknown"/> + </bus> + <net data_index="50" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|enable" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="50" tap_mode="classic" trigger_index="50" type="unknown"/> + <net data_index="51" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|init" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="51" tap_mode="classic" trigger_index="51" type="unknown"/> + </data_view> + <setup_view> + <bus is_selected="false" level-0="alt_or" name="mac_rgmii:mac_0|rx_ctl[1..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="86" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_ctl[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="86" tap_mode="classic" trigger_index="86" type="unknown"/> + <net data_index="85" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_ctl[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="85" tap_mode="classic" trigger_index="85" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="mac_rgmii:mac_0|rx_d[7..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="98" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="98" tap_mode="classic" trigger_index="98" type="unknown"/> + <net data_index="97" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="97" tap_mode="classic" trigger_index="97" type="unknown"/> + <net data_index="96" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="96" tap_mode="classic" trigger_index="96" type="unknown"/> + <net data_index="95" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="95" tap_mode="classic" trigger_index="95" type="unknown"/> + <net data_index="94" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="94" tap_mode="classic" trigger_index="94" type="unknown"/> + <net data_index="93" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="93" tap_mode="classic" trigger_index="93" type="unknown"/> + <net data_index="92" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="92" tap_mode="classic" trigger_index="92" type="unknown"/> + <net data_index="91" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="91" tap_mode="classic" trigger_index="91" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="mac_rgmii:mac_0|rx_ctl_m1[1..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="88" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_ctl_m1[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="88" tap_mode="classic" trigger_index="88" type="unknown"/> + <net data_index="87" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_ctl_m1[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="87" tap_mode="classic" trigger_index="87" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="mac_rgmii:mac_0|rx_d_m1[7..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="106" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d_m1[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="106" tap_mode="classic" trigger_index="106" type="unknown"/> + <net data_index="105" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d_m1[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="105" tap_mode="classic" trigger_index="105" type="unknown"/> + <net data_index="104" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d_m1[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="104" tap_mode="classic" trigger_index="104" type="unknown"/> + <net data_index="103" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d_m1[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="103" tap_mode="classic" trigger_index="103" type="unknown"/> + <net data_index="102" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d_m1[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="102" tap_mode="classic" trigger_index="102" type="unknown"/> + <net data_index="101" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d_m1[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="101" tap_mode="classic" trigger_index="101" type="unknown"/> + <net data_index="100" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d_m1[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="100" tap_mode="classic" trigger_index="100" type="unknown"/> + <net data_index="99" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d_m1[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="99" tap_mode="classic" trigger_index="99" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="mac_rgmii:mac_0|rx_state[3..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="159" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_state[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="159" tap_mode="classic" trigger_index="159" type="unknown"/> + <net data_index="158" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_state[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="158" tap_mode="classic" trigger_index="158" type="unknown"/> + <net data_index="157" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_state[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="157" tap_mode="classic" trigger_index="157" type="unknown"/> + <net data_index="156" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_state[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="156" tap_mode="classic" trigger_index="156" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="mac_rgmii:mac_0|rx_byte_cnt[10..0]" order="msb_to_lsb" radix="unsigned_dec" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="75" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_byte_cnt[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="75" tap_mode="classic" trigger_index="75" type="unknown"/> + <net data_index="84" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_byte_cnt[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="84" tap_mode="classic" trigger_index="84" type="unknown"/> + <net data_index="83" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_byte_cnt[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="83" tap_mode="classic" trigger_index="83" type="unknown"/> + <net data_index="82" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_byte_cnt[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="82" tap_mode="classic" trigger_index="82" type="unknown"/> + <net data_index="81" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_byte_cnt[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="81" tap_mode="classic" trigger_index="81" type="unknown"/> + <net data_index="80" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_byte_cnt[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="80" tap_mode="classic" trigger_index="80" type="unknown"/> + <net data_index="79" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_byte_cnt[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="79" tap_mode="classic" trigger_index="79" type="unknown"/> + <net data_index="78" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_byte_cnt[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="78" tap_mode="classic" trigger_index="78" type="unknown"/> + <net data_index="77" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_byte_cnt[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="77" tap_mode="classic" trigger_index="77" type="unknown"/> + <net data_index="76" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_byte_cnt[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="76" tap_mode="classic" trigger_index="76" type="unknown"/> + <net data_index="74" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_byte_cnt[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="74" tap_mode="classic" trigger_index="74" type="unknown"/> + </bus> + <net data_index="141" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_packet_complete" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="141" tap_mode="classic" trigger_index="141" type="unknown"/> + <net data_index="124" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_fifo_d[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="124" tap_mode="classic" trigger_index="124" type="unknown"/> + <bus is_selected="false" level-0="alt_or" name="mac_rgmii:mac_0|rx_fifo_d[7..0]" order="msb_to_lsb" state="collapse" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="123" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_fifo_d[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="123" tap_mode="classic" trigger_index="123" type="unknown"/> + <net data_index="122" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_fifo_d[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="122" tap_mode="classic" trigger_index="122" type="unknown"/> + <net data_index="121" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_fifo_d[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="121" tap_mode="classic" trigger_index="121" type="unknown"/> + <net data_index="120" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_fifo_d[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="120" tap_mode="classic" trigger_index="120" type="unknown"/> + <net data_index="119" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_fifo_d[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="119" tap_mode="classic" trigger_index="119" type="unknown"/> + <net data_index="118" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_fifo_d[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="118" tap_mode="classic" trigger_index="118" type="unknown"/> + <net data_index="117" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_fifo_d[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="117" tap_mode="classic" trigger_index="117" type="unknown"/> + <net data_index="116" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_fifo_d[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="116" tap_mode="classic" trigger_index="116" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="mac_rgmii:mac_0|rx_pkt_length[11..0]" order="msb_to_lsb" radix="unsigned_dec" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="144" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_length[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="144" tap_mode="classic" trigger_index="144" type="unknown"/> + <net data_index="143" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_length[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="143" tap_mode="classic" trigger_index="143" type="unknown"/> + <net data_index="153" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_length[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="153" tap_mode="classic" trigger_index="153" type="unknown"/> + <net data_index="152" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_length[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="152" tap_mode="classic" trigger_index="152" type="unknown"/> + <net data_index="151" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_length[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="151" tap_mode="classic" trigger_index="151" type="unknown"/> + <net data_index="150" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_length[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="150" tap_mode="classic" trigger_index="150" type="unknown"/> + <net data_index="149" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_length[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="149" tap_mode="classic" trigger_index="149" type="unknown"/> + <net data_index="148" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_length[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="148" tap_mode="classic" trigger_index="148" type="unknown"/> + <net data_index="147" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_length[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="147" tap_mode="classic" trigger_index="147" type="unknown"/> + <net data_index="146" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_length[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="146" tap_mode="classic" trigger_index="146" type="unknown"/> + <net data_index="145" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_length[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="145" tap_mode="classic" trigger_index="145" type="unknown"/> + <net data_index="142" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_length[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="142" tap_mode="classic" trigger_index="142" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="mac_rgmii:mac_0|rx_l3_proto[15..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="131" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_l3_proto[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="131" tap_mode="classic" trigger_index="131" type="unknown"/> + <net data_index="130" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_l3_proto[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="130" tap_mode="classic" trigger_index="130" type="unknown"/> + <net data_index="129" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_l3_proto[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="129" tap_mode="classic" trigger_index="129" type="unknown"/> + <net data_index="128" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_l3_proto[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="128" tap_mode="classic" trigger_index="128" type="unknown"/> + <net data_index="127" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_l3_proto[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="127" tap_mode="classic" trigger_index="127" type="unknown"/> + <net data_index="126" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_l3_proto[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="126" tap_mode="classic" trigger_index="126" type="unknown"/> + <net data_index="140" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_l3_proto[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="140" tap_mode="classic" trigger_index="140" type="unknown"/> + <net data_index="139" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_l3_proto[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="139" tap_mode="classic" trigger_index="139" type="unknown"/> + <net data_index="138" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_l3_proto[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="138" tap_mode="classic" trigger_index="138" type="unknown"/> + <net data_index="137" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_l3_proto[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="137" tap_mode="classic" trigger_index="137" type="unknown"/> + <net data_index="136" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_l3_proto[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="136" tap_mode="classic" trigger_index="136" type="unknown"/> + <net data_index="135" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_l3_proto[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="135" tap_mode="classic" trigger_index="135" type="unknown"/> + <net data_index="134" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_l3_proto[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="134" tap_mode="classic" trigger_index="134" type="unknown"/> + <net data_index="133" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_l3_proto[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="133" tap_mode="classic" trigger_index="133" type="unknown"/> + <net data_index="132" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_l3_proto[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="132" tap_mode="classic" trigger_index="132" type="unknown"/> + <net data_index="125" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_l3_proto[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="125" tap_mode="classic" trigger_index="125" type="unknown"/> + </bus> + <net data_index="160" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_wr_done" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="160" tap_mode="classic" trigger_index="160" type="unknown"/> + <net data_index="155" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_sop" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="155" tap_mode="classic" trigger_index="155" type="unknown"/> + <net data_index="115" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_eop" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="115" tap_mode="classic" trigger_index="115" type="unknown"/> + <net data_index="154" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_sample" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="154" tap_mode="classic" trigger_index="154" type="unknown"/> + <bus is_selected="false" level-0="alt_or" name="mac_rgmii:mac_0|rx_ctl_m2[1..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="90" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_ctl_m2[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="90" tap_mode="classic" trigger_index="90" type="unknown"/> + <net data_index="89" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_ctl_m2[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="89" tap_mode="classic" trigger_index="89" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="mac_rgmii:mac_0|rx_d_m2[7..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="114" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d_m2[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="114" tap_mode="classic" trigger_index="114" type="unknown"/> + <net data_index="113" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d_m2[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="113" tap_mode="classic" trigger_index="113" type="unknown"/> + <net data_index="112" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d_m2[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="112" tap_mode="classic" trigger_index="112" type="unknown"/> + <net data_index="111" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d_m2[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="111" tap_mode="classic" trigger_index="111" type="unknown"/> + <net data_index="110" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d_m2[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="110" tap_mode="classic" trigger_index="110" type="unknown"/> + <net data_index="109" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d_m2[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="109" tap_mode="classic" trigger_index="109" type="unknown"/> + <net data_index="108" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d_m2[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="108" tap_mode="classic" trigger_index="108" type="unknown"/> + <net data_index="107" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d_m2[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="107" tap_mode="classic" trigger_index="107" type="unknown"/> + </bus> + <net data_index="73" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|fcs_rx_init" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="73" tap_mode="classic" trigger_index="73" type="unknown"/> + <net data_index="71" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|fcs_rx_enable" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="71" tap_mode="classic" trigger_index="71" type="unknown"/> + <net data_index="54" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|fcs_rx_addr_e" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="54" tap_mode="classic" trigger_index="54" type="unknown"/> + <bus is_selected="false" level-0="alt_or" name="mac_rgmii:mac_0|fcs_rx_addr[1..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="53" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|fcs_rx_addr[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="53" tap_mode="classic" trigger_index="53" type="unknown"/> + <net data_index="52" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|fcs_rx_addr[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="52" tap_mode="classic" trigger_index="52" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="mac_rgmii:mac_0|fcs_rx_din[7..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="62" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|fcs_rx_din[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="62" tap_mode="classic" trigger_index="62" type="unknown"/> + <net data_index="61" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|fcs_rx_din[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="61" tap_mode="classic" trigger_index="61" type="unknown"/> + <net data_index="60" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|fcs_rx_din[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="60" tap_mode="classic" trigger_index="60" type="unknown"/> + <net data_index="59" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|fcs_rx_din[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="59" tap_mode="classic" trigger_index="59" type="unknown"/> + <net data_index="58" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|fcs_rx_din[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="58" tap_mode="classic" trigger_index="58" type="unknown"/> + <net data_index="57" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|fcs_rx_din[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="57" tap_mode="classic" trigger_index="57" type="unknown"/> + <net data_index="56" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|fcs_rx_din[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="56" tap_mode="classic" trigger_index="56" type="unknown"/> + <net data_index="55" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|fcs_rx_din[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="55" tap_mode="classic" trigger_index="55" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="mac_rgmii:mac_0|fcs_rx_dout[7..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="70" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|fcs_rx_dout[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="70" tap_mode="classic" trigger_index="70" type="unknown"/> + <net data_index="69" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|fcs_rx_dout[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="69" tap_mode="classic" trigger_index="69" type="unknown"/> + <net data_index="68" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|fcs_rx_dout[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="68" tap_mode="classic" trigger_index="68" type="unknown"/> + <net data_index="67" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|fcs_rx_dout[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="67" tap_mode="classic" trigger_index="67" type="unknown"/> + <net data_index="66" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|fcs_rx_dout[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="66" tap_mode="classic" trigger_index="66" type="unknown"/> + <net data_index="65" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|fcs_rx_dout[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="65" tap_mode="classic" trigger_index="65" type="unknown"/> + <net data_index="64" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|fcs_rx_dout[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="64" tap_mode="classic" trigger_index="64" type="unknown"/> + <net data_index="63" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|fcs_rx_dout[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="63" tap_mode="classic" trigger_index="63" type="unknown"/> + </bus> + <net data_index="72" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|fcs_rx_error" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="72" tap_mode="classic" trigger_index="72" type="unknown"/> + <bus is_selected="false" level-0="alt_or" name="fcs:fcs_rx_0|addr[1..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="1" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|addr[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="1" tap_mode="classic" trigger_index="1" type="unknown"/> + <net data_index="0" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|addr[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="0" tap_mode="classic" trigger_index="0" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="fcs:fcs_rx_0|crc[31..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="26" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|crc[31]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="26" tap_mode="classic" trigger_index="26" type="unknown"/> + <net data_index="25" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|crc[30]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="25" tap_mode="classic" trigger_index="25" type="unknown"/> + <net data_index="23" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|crc[29]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="23" tap_mode="classic" trigger_index="23" type="unknown"/> + <net data_index="22" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|crc[28]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="22" tap_mode="classic" trigger_index="22" type="unknown"/> + <net data_index="21" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|crc[27]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="21" tap_mode="classic" trigger_index="21" type="unknown"/> + <net data_index="20" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|crc[26]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="20" tap_mode="classic" trigger_index="20" type="unknown"/> + <net data_index="19" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|crc[25]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="19" tap_mode="classic" trigger_index="19" type="unknown"/> + <net data_index="18" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|crc[24]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="18" tap_mode="classic" trigger_index="18" type="unknown"/> + <net data_index="17" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|crc[23]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="17" tap_mode="classic" trigger_index="17" type="unknown"/> + <net data_index="16" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|crc[22]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="16" tap_mode="classic" trigger_index="16" type="unknown"/> + <net data_index="15" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|crc[21]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="15" tap_mode="classic" trigger_index="15" type="unknown"/> + <net data_index="14" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|crc[20]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="14" tap_mode="classic" trigger_index="14" type="unknown"/> + <net data_index="12" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|crc[19]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="12" tap_mode="classic" trigger_index="12" type="unknown"/> + <net data_index="11" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|crc[18]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="11" tap_mode="classic" trigger_index="11" type="unknown"/> + <net data_index="10" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|crc[17]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="10" tap_mode="classic" trigger_index="10" type="unknown"/> + <net data_index="9" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|crc[16]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="9" tap_mode="classic" trigger_index="9" type="unknown"/> + <net data_index="8" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|crc[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="8" tap_mode="classic" trigger_index="8" type="unknown"/> + <net data_index="7" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|crc[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="7" tap_mode="classic" trigger_index="7" type="unknown"/> + <net data_index="6" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|crc[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="6" tap_mode="classic" trigger_index="6" type="unknown"/> + <net data_index="5" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|crc[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="5" tap_mode="classic" trigger_index="5" type="unknown"/> + <net data_index="4" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|crc[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="4" tap_mode="classic" trigger_index="4" type="unknown"/> + <net data_index="3" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|crc[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="3" tap_mode="classic" trigger_index="3" type="unknown"/> + <net data_index="33" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|crc[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="33" tap_mode="classic" trigger_index="33" type="unknown"/> + <net data_index="32" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|crc[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="32" tap_mode="classic" trigger_index="32" type="unknown"/> + <net data_index="31" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|crc[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="31" tap_mode="classic" trigger_index="31" type="unknown"/> + <net data_index="30" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|crc[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="30" tap_mode="classic" trigger_index="30" type="unknown"/> + <net data_index="29" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|crc[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="29" tap_mode="classic" trigger_index="29" type="unknown"/> + <net data_index="28" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|crc[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="28" tap_mode="classic" trigger_index="28" type="unknown"/> + <net data_index="27" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|crc[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="27" tap_mode="classic" trigger_index="27" type="unknown"/> + <net data_index="24" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|crc[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="24" tap_mode="classic" trigger_index="24" type="unknown"/> + <net data_index="13" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|crc[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="13" tap_mode="classic" trigger_index="13" type="unknown"/> + <net data_index="2" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|crc[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="2" tap_mode="classic" trigger_index="2" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="fcs:fcs_rx_0|din[7..0]" order="lsb_to_msb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="34" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|din[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="34" tap_mode="classic" trigger_index="34" type="unknown"/> + <net data_index="35" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|din[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="35" tap_mode="classic" trigger_index="35" type="unknown"/> + <net data_index="36" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|din[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="36" tap_mode="classic" trigger_index="36" type="unknown"/> + <net data_index="37" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|din[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="37" tap_mode="classic" trigger_index="37" type="unknown"/> + <net data_index="38" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|din[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="38" tap_mode="classic" trigger_index="38" type="unknown"/> + <net data_index="39" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|din[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="39" tap_mode="classic" trigger_index="39" type="unknown"/> + <net data_index="40" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|din[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="40" tap_mode="classic" trigger_index="40" type="unknown"/> + <net data_index="41" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|din[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="41" tap_mode="classic" trigger_index="41" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="fcs:fcs_rx_0|dout[7..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="49" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|dout[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="49" tap_mode="classic" trigger_index="49" type="unknown"/> + <net data_index="48" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|dout[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="48" tap_mode="classic" trigger_index="48" type="unknown"/> + <net data_index="47" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|dout[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="47" tap_mode="classic" trigger_index="47" type="unknown"/> + <net data_index="46" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|dout[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="46" tap_mode="classic" trigger_index="46" type="unknown"/> + <net data_index="45" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|dout[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="45" tap_mode="classic" trigger_index="45" type="unknown"/> + <net data_index="44" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|dout[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="44" tap_mode="classic" trigger_index="44" type="unknown"/> + <net data_index="43" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|dout[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="43" tap_mode="classic" trigger_index="43" type="unknown"/> + <net data_index="42" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|dout[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="42" tap_mode="classic" trigger_index="42" type="unknown"/> + </bus> + <net data_index="50" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|enable" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="50" tap_mode="classic" trigger_index="50" type="unknown"/> + <net data_index="51" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fcs:fcs_rx_0|init" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="51" tap_mode="classic" trigger_index="51" type="unknown"/> + </setup_view> + <trigger_in_editor/> + <trigger_out_editor/> + </presentation> + <trigger CRC="376037FC" attribute_mem_mode="false" gap_record="true" global_temp="1" is_expanded="true" name="trigger: 2025/07/03 12:58:17 #0" position="pre" power_up_trigger_mode="false" record_data_gap="true" segment_size="512" storage_mode="off" storage_qualifier_disabled="no" storage_qualifier_port_is_pin="false" storage_qualifier_port_name="auto_stp_external_storage_qualifier" storage_qualifier_port_tap_mode="classic" trigger_type="circular"> + <power_up_trigger position="pre" storage_qualifier_disabled="no"/> + <events use_custom_flow_control="no"> + <level enabled="yes" name="condition1" type="basic"> + <power_up enabled="yes"> + </power_up><op_node/> + </level> + </events> + <storage_qualifier_events> + <transitional>11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 + <pwr_up_transitional>11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111</pwr_up_transitional> + </transitional> + <storage_qualifier_level type="basic"> + <power_up> + </power_up> + <op_node/> + </storage_qualifier_level> + <storage_qualifier_level type="basic"> + <power_up> + </power_up> + <op_node/> + </storage_qualifier_level> + <storage_qualifier_level type="basic"> + <power_up> + </power_up> + <op_node/> + </storage_qualifier_level> + </storage_qualifier_events> + </trigger> + </signal_set> + <position_info> + <single attribute="active tab" value="1"/> + <single attribute="data horizontal scroll position" value="0"/> + <single attribute="data vertical scroll position" value="12"/> + <single attribute="setup horizontal scroll position" value="0"/> + <single attribute="setup vertical scroll position" value="13"/> + <single attribute="zoom level denominator" value="1"/> + <single attribute="zoom level numerator" value="256"/> + <single attribute="zoom offset denominator" value="1"/> + <single attribute="zoom offset numerator" value="0"/> + </position_info> + </instance> + <mnemonics/> + <static_plugin_mnemonics/> + <instance enabled="false" entity_name="sld_signaltap" is_auto_node="yes" is_expanded="true" name="rgmii_1" source_file="sld_signaltap.vhd"> + <node_ip_info instance_id="1" mfg_id="110" node_id="0" version="6"/> + <signal_set global_temp="1" is_expanded="true" name="signal_set: 2025/06/08 01:35:40 #0"> + <clock name="phy1_rx_clk" polarity="posedge" tap_mode="classic"/> + <config pipeline_level="2" ram_type="AUTO" reserved_data_nodes="0" reserved_storage_qualifier_nodes="0" reserved_trigger_nodes="0" sample_depth="128" trigger_in_enable="no" trigger_out_enable="no"/> + <top_entity/> + <signal_vec> + <trigger_input_vec> + <wire name="ddri:rgmi_rx_1|dataout_h[0]" tap_mode="classic"/> + <wire name="ddri:rgmi_rx_1|dataout_h[1]" tap_mode="classic"/> + <wire name="ddri:rgmi_rx_1|dataout_h[2]" tap_mode="classic"/> + <wire name="ddri:rgmi_rx_1|dataout_h[3]" tap_mode="classic"/> + <wire name="ddri:rgmi_rx_1|dataout_h[4]" tap_mode="classic"/> + <wire name="ddri:rgmi_rx_1|dataout_l[0]" tap_mode="classic"/> + <wire name="ddri:rgmi_rx_1|dataout_l[1]" tap_mode="classic"/> + <wire name="ddri:rgmi_rx_1|dataout_l[2]" tap_mode="classic"/> + <wire name="ddri:rgmi_rx_1|dataout_l[3]" tap_mode="classic"/> + <wire name="ddri:rgmi_rx_1|dataout_l[4]" tap_mode="classic"/> + <wire name="ddro:rgmii_tx_1|datain_h[0]" tap_mode="classic"/> + <wire name="ddro:rgmii_tx_1|datain_h[1]" tap_mode="classic"/> + <wire name="ddro:rgmii_tx_1|datain_h[2]" tap_mode="classic"/> + <wire name="ddro:rgmii_tx_1|datain_h[3]" tap_mode="classic"/> + <wire name="ddro:rgmii_tx_1|datain_h[4]" tap_mode="classic"/> + <wire name="ddro:rgmii_tx_1|datain_l[0]" tap_mode="classic"/> + <wire name="ddro:rgmii_tx_1|datain_l[1]" tap_mode="classic"/> + <wire name="ddro:rgmii_tx_1|datain_l[2]" tap_mode="classic"/> + <wire name="ddro:rgmii_tx_1|datain_l[3]" tap_mode="classic"/> + <wire name="ddro:rgmii_tx_1|datain_l[4]" tap_mode="classic"/> + <wire name="phy1_rx_ctl" tap_mode="classic"/> + <wire name="rx1_ctl_m1[0]" tap_mode="classic"/> + <wire name="rx1_ctl_m1[1]" tap_mode="classic"/> + <wire name="rx1_ctl_m2[0]" tap_mode="classic"/> + <wire name="rx1_ctl_m2[1]" tap_mode="classic"/> + <wire name="rx1_ctl_m3[0]" tap_mode="classic"/> + <wire name="rx1_ctl_m3[1]" tap_mode="classic"/> + <wire name="rx1_ctl_m4[0]" tap_mode="classic"/> + <wire name="rx1_ctl_m4[1]" tap_mode="classic"/> + <wire name="rx1_d_m1[0]" tap_mode="classic"/> + <wire name="rx1_d_m1[1]" tap_mode="classic"/> + <wire name="rx1_d_m1[2]" tap_mode="classic"/> + <wire name="rx1_d_m1[3]" tap_mode="classic"/> + <wire name="rx1_d_m1[4]" tap_mode="classic"/> + <wire name="rx1_d_m1[5]" tap_mode="classic"/> + <wire name="rx1_d_m1[6]" tap_mode="classic"/> + <wire name="rx1_d_m1[7]" tap_mode="classic"/> + <wire name="rx1_d_m2[0]" tap_mode="classic"/> + <wire name="rx1_d_m2[1]" tap_mode="classic"/> + <wire name="rx1_d_m2[2]" tap_mode="classic"/> + <wire name="rx1_d_m2[3]" tap_mode="classic"/> + <wire name="rx1_d_m2[4]" tap_mode="classic"/> + <wire name="rx1_d_m2[5]" tap_mode="classic"/> + <wire name="rx1_d_m2[6]" tap_mode="classic"/> + <wire name="rx1_d_m2[7]" tap_mode="classic"/> + <wire name="rx1_d_m3[0]" tap_mode="classic"/> + <wire name="rx1_d_m3[1]" tap_mode="classic"/> + <wire name="rx1_d_m3[2]" tap_mode="classic"/> + <wire name="rx1_d_m3[3]" tap_mode="classic"/> + <wire name="rx1_d_m3[4]" tap_mode="classic"/> + <wire name="rx1_d_m3[5]" tap_mode="classic"/> + <wire name="rx1_d_m3[6]" tap_mode="classic"/> + <wire name="rx1_d_m3[7]" tap_mode="classic"/> + <wire name="rx1_d_m4[0]" tap_mode="classic"/> + <wire name="rx1_d_m4[1]" tap_mode="classic"/> + <wire name="rx1_d_m4[2]" tap_mode="classic"/> + <wire name="rx1_d_m4[3]" tap_mode="classic"/> + <wire name="rx1_d_m4[4]" tap_mode="classic"/> + <wire name="rx1_d_m4[5]" tap_mode="classic"/> + <wire name="rx1_d_m4[6]" tap_mode="classic"/> + <wire name="rx1_d_m4[7]" tap_mode="classic"/> + </trigger_input_vec> + <data_input_vec> + <wire name="ddri:rgmi_rx_1|dataout_h[0]" tap_mode="classic"/> + <wire name="ddri:rgmi_rx_1|dataout_h[1]" tap_mode="classic"/> + <wire name="ddri:rgmi_rx_1|dataout_h[2]" tap_mode="classic"/> + <wire name="ddri:rgmi_rx_1|dataout_h[3]" tap_mode="classic"/> + <wire name="ddri:rgmi_rx_1|dataout_h[4]" tap_mode="classic"/> + <wire name="ddri:rgmi_rx_1|dataout_l[0]" tap_mode="classic"/> + <wire name="ddri:rgmi_rx_1|dataout_l[1]" tap_mode="classic"/> + <wire name="ddri:rgmi_rx_1|dataout_l[2]" tap_mode="classic"/> + <wire name="ddri:rgmi_rx_1|dataout_l[3]" tap_mode="classic"/> + <wire name="ddri:rgmi_rx_1|dataout_l[4]" tap_mode="classic"/> + <wire name="ddro:rgmii_tx_1|datain_h[0]" tap_mode="classic"/> + <wire name="ddro:rgmii_tx_1|datain_h[1]" tap_mode="classic"/> + <wire name="ddro:rgmii_tx_1|datain_h[2]" tap_mode="classic"/> + <wire name="ddro:rgmii_tx_1|datain_h[3]" tap_mode="classic"/> + <wire name="ddro:rgmii_tx_1|datain_h[4]" tap_mode="classic"/> + <wire name="ddro:rgmii_tx_1|datain_l[0]" tap_mode="classic"/> + <wire name="ddro:rgmii_tx_1|datain_l[1]" tap_mode="classic"/> + <wire name="ddro:rgmii_tx_1|datain_l[2]" tap_mode="classic"/> + <wire name="ddro:rgmii_tx_1|datain_l[3]" tap_mode="classic"/> + <wire name="ddro:rgmii_tx_1|datain_l[4]" tap_mode="classic"/> + <wire name="phy1_rx_ctl" tap_mode="classic"/> + <wire name="rx1_ctl_m1[0]" tap_mode="classic"/> + <wire name="rx1_ctl_m1[1]" tap_mode="classic"/> + <wire name="rx1_ctl_m2[0]" tap_mode="classic"/> + <wire name="rx1_ctl_m2[1]" tap_mode="classic"/> + <wire name="rx1_ctl_m3[0]" tap_mode="classic"/> + <wire name="rx1_ctl_m3[1]" tap_mode="classic"/> + <wire name="rx1_ctl_m4[0]" tap_mode="classic"/> + <wire name="rx1_ctl_m4[1]" tap_mode="classic"/> + <wire name="rx1_d_m1[0]" tap_mode="classic"/> + <wire name="rx1_d_m1[1]" tap_mode="classic"/> + <wire name="rx1_d_m1[2]" tap_mode="classic"/> + <wire name="rx1_d_m1[3]" tap_mode="classic"/> + <wire name="rx1_d_m1[4]" tap_mode="classic"/> + <wire name="rx1_d_m1[5]" tap_mode="classic"/> + <wire name="rx1_d_m1[6]" tap_mode="classic"/> + <wire name="rx1_d_m1[7]" tap_mode="classic"/> + <wire name="rx1_d_m2[0]" tap_mode="classic"/> + <wire name="rx1_d_m2[1]" tap_mode="classic"/> + <wire name="rx1_d_m2[2]" tap_mode="classic"/> + <wire name="rx1_d_m2[3]" tap_mode="classic"/> + <wire name="rx1_d_m2[4]" tap_mode="classic"/> + <wire name="rx1_d_m2[5]" tap_mode="classic"/> + <wire name="rx1_d_m2[6]" tap_mode="classic"/> + <wire name="rx1_d_m2[7]" tap_mode="classic"/> + <wire name="rx1_d_m3[0]" tap_mode="classic"/> + <wire name="rx1_d_m3[1]" tap_mode="classic"/> + <wire name="rx1_d_m3[2]" tap_mode="classic"/> + <wire name="rx1_d_m3[3]" tap_mode="classic"/> + <wire name="rx1_d_m3[4]" tap_mode="classic"/> + <wire name="rx1_d_m3[5]" tap_mode="classic"/> + <wire name="rx1_d_m3[6]" tap_mode="classic"/> + <wire name="rx1_d_m3[7]" tap_mode="classic"/> + <wire name="rx1_d_m4[0]" tap_mode="classic"/> + <wire name="rx1_d_m4[1]" tap_mode="classic"/> + <wire name="rx1_d_m4[2]" tap_mode="classic"/> + <wire name="rx1_d_m4[3]" tap_mode="classic"/> + <wire name="rx1_d_m4[4]" tap_mode="classic"/> + <wire name="rx1_d_m4[5]" tap_mode="classic"/> + <wire name="rx1_d_m4[6]" tap_mode="classic"/> + <wire name="rx1_d_m4[7]" tap_mode="classic"/> + </data_input_vec> + <storage_qualifier_input_vec> + <wire name="ddri:rgmi_rx_1|dataout_h[0]" tap_mode="classic"/> + <wire name="ddri:rgmi_rx_1|dataout_h[1]" tap_mode="classic"/> + <wire name="ddri:rgmi_rx_1|dataout_h[2]" tap_mode="classic"/> + <wire name="ddri:rgmi_rx_1|dataout_h[3]" tap_mode="classic"/> + <wire name="ddri:rgmi_rx_1|dataout_h[4]" tap_mode="classic"/> + <wire name="ddri:rgmi_rx_1|dataout_l[0]" tap_mode="classic"/> + <wire name="ddri:rgmi_rx_1|dataout_l[1]" tap_mode="classic"/> + <wire name="ddri:rgmi_rx_1|dataout_l[2]" tap_mode="classic"/> + <wire name="ddri:rgmi_rx_1|dataout_l[3]" tap_mode="classic"/> + <wire name="ddri:rgmi_rx_1|dataout_l[4]" tap_mode="classic"/> + <wire name="ddro:rgmii_tx_1|datain_h[0]" tap_mode="classic"/> + <wire name="ddro:rgmii_tx_1|datain_h[1]" tap_mode="classic"/> + <wire name="ddro:rgmii_tx_1|datain_h[2]" tap_mode="classic"/> + <wire name="ddro:rgmii_tx_1|datain_h[3]" tap_mode="classic"/> + <wire name="ddro:rgmii_tx_1|datain_h[4]" tap_mode="classic"/> + <wire name="ddro:rgmii_tx_1|datain_l[0]" tap_mode="classic"/> + <wire name="ddro:rgmii_tx_1|datain_l[1]" tap_mode="classic"/> + <wire name="ddro:rgmii_tx_1|datain_l[2]" tap_mode="classic"/> + <wire name="ddro:rgmii_tx_1|datain_l[3]" tap_mode="classic"/> + <wire name="ddro:rgmii_tx_1|datain_l[4]" tap_mode="classic"/> + <wire name="phy1_rx_ctl" tap_mode="classic"/> + <wire name="rx1_ctl_m1[0]" tap_mode="classic"/> + <wire name="rx1_ctl_m1[1]" tap_mode="classic"/> + <wire name="rx1_ctl_m2[0]" tap_mode="classic"/> + <wire name="rx1_ctl_m2[1]" tap_mode="classic"/> + <wire name="rx1_ctl_m3[0]" tap_mode="classic"/> + <wire name="rx1_ctl_m3[1]" tap_mode="classic"/> + <wire name="rx1_ctl_m4[0]" tap_mode="classic"/> + <wire name="rx1_ctl_m4[1]" tap_mode="classic"/> + <wire name="rx1_d_m1[0]" tap_mode="classic"/> + <wire name="rx1_d_m1[1]" tap_mode="classic"/> + <wire name="rx1_d_m1[2]" tap_mode="classic"/> + <wire name="rx1_d_m1[3]" tap_mode="classic"/> + <wire name="rx1_d_m1[4]" tap_mode="classic"/> + <wire name="rx1_d_m1[5]" tap_mode="classic"/> + <wire name="rx1_d_m1[6]" tap_mode="classic"/> + <wire name="rx1_d_m1[7]" tap_mode="classic"/> + <wire name="rx1_d_m2[0]" tap_mode="classic"/> + <wire name="rx1_d_m2[1]" tap_mode="classic"/> + <wire name="rx1_d_m2[2]" tap_mode="classic"/> + <wire name="rx1_d_m2[3]" tap_mode="classic"/> + <wire name="rx1_d_m2[4]" tap_mode="classic"/> + <wire name="rx1_d_m2[5]" tap_mode="classic"/> + <wire name="rx1_d_m2[6]" tap_mode="classic"/> + <wire name="rx1_d_m2[7]" tap_mode="classic"/> + <wire name="rx1_d_m3[0]" tap_mode="classic"/> + <wire name="rx1_d_m3[1]" tap_mode="classic"/> + <wire name="rx1_d_m3[2]" tap_mode="classic"/> + <wire name="rx1_d_m3[3]" tap_mode="classic"/> + <wire name="rx1_d_m3[4]" tap_mode="classic"/> + <wire name="rx1_d_m3[5]" tap_mode="classic"/> + <wire name="rx1_d_m3[6]" tap_mode="classic"/> + <wire name="rx1_d_m3[7]" tap_mode="classic"/> + <wire name="rx1_d_m4[0]" tap_mode="classic"/> + <wire name="rx1_d_m4[1]" tap_mode="classic"/> + <wire name="rx1_d_m4[2]" tap_mode="classic"/> + <wire name="rx1_d_m4[3]" tap_mode="classic"/> + <wire name="rx1_d_m4[4]" tap_mode="classic"/> + <wire name="rx1_d_m4[5]" tap_mode="classic"/> + <wire name="rx1_d_m4[6]" tap_mode="classic"/> + <wire name="rx1_d_m4[7]" tap_mode="classic"/> + </storage_qualifier_input_vec> + </signal_vec> + <presentation> + <unified_setup_data_view> + <node data_index="20" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="phy1_rx_ctl" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="20" tap_mode="classic" trigger_index="20" type="unknown"/> + <node is_selected="false" level-0="alt_or" name="ddri:rgmi_rx_1|dataout_h[4..0]" order="msb_to_lsb" state="collapse" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <node data_index="4" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="ddri:rgmi_rx_1|dataout_h[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="4" tap_mode="classic" trigger_index="4" type="unknown"/> + <node data_index="3" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="ddri:rgmi_rx_1|dataout_h[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="3" tap_mode="classic" trigger_index="3" type="unknown"/> + <node data_index="2" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="ddri:rgmi_rx_1|dataout_h[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="2" tap_mode="classic" trigger_index="2" type="unknown"/> + <node data_index="1" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="ddri:rgmi_rx_1|dataout_h[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="1" tap_mode="classic" trigger_index="1" type="unknown"/> + <node data_index="0" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="ddri:rgmi_rx_1|dataout_h[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="0" tap_mode="classic" trigger_index="0" type="unknown"/> + </node> + <node is_selected="false" level-0="alt_or" name="ddri:rgmi_rx_1|dataout_l[4..0]" order="msb_to_lsb" state="collapse" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <node data_index="9" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="ddri:rgmi_rx_1|dataout_l[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="9" tap_mode="classic" trigger_index="9" type="unknown"/> + <node data_index="8" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="ddri:rgmi_rx_1|dataout_l[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="8" tap_mode="classic" trigger_index="8" type="unknown"/> + <node data_index="7" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="ddri:rgmi_rx_1|dataout_l[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="7" tap_mode="classic" trigger_index="7" type="unknown"/> + <node data_index="6" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="ddri:rgmi_rx_1|dataout_l[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="6" tap_mode="classic" trigger_index="6" type="unknown"/> + <node data_index="5" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="ddri:rgmi_rx_1|dataout_l[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="5" tap_mode="classic" trigger_index="5" type="unknown"/> + </node> + <node is_selected="false" level-0="alt_or" name="rx1_ctl_m1[1..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <node data_index="22" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_ctl_m1[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="22" tap_mode="classic" trigger_index="22" type="unknown"/> + <node data_index="21" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_ctl_m1[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="21" tap_mode="classic" trigger_index="21" type="unknown"/> + </node> + <node is_selected="false" level-0="alt_or" name="rx1_ctl_m2[1..0]" order="msb_to_lsb" radix="hex" state="collapse" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <node data_index="24" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="high" name="rx1_ctl_m2[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="24" tap_mode="classic" trigger_index="24" type="unknown"/> + <node data_index="23" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="high" name="rx1_ctl_m2[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="23" tap_mode="classic" trigger_index="23" type="unknown"/> + </node> + <node is_selected="false" level-0="alt_or" name="rx1_ctl_m3[1..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <node data_index="26" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_ctl_m3[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="26" tap_mode="classic" trigger_index="26" type="unknown"/> + <node data_index="25" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_ctl_m3[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="25" tap_mode="classic" trigger_index="25" type="unknown"/> + </node> + <node is_selected="false" level-0="alt_or" name="rx1_ctl_m4[1..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <node data_index="28" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_ctl_m4[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="28" tap_mode="classic" trigger_index="28" type="unknown"/> + <node data_index="27" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_ctl_m4[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="27" tap_mode="classic" trigger_index="27" type="unknown"/> + </node> + <node is_selected="false" level-0="alt_or" name="rx1_d_m1[7..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <node data_index="36" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m1[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="36" tap_mode="classic" trigger_index="36" type="unknown"/> + <node data_index="35" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m1[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="35" tap_mode="classic" trigger_index="35" type="unknown"/> + <node data_index="34" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m1[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="34" tap_mode="classic" trigger_index="34" type="unknown"/> + <node data_index="33" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m1[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="33" tap_mode="classic" trigger_index="33" type="unknown"/> + <node data_index="32" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m1[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="32" tap_mode="classic" trigger_index="32" type="unknown"/> + <node data_index="31" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m1[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="31" tap_mode="classic" trigger_index="31" type="unknown"/> + <node data_index="30" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m1[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="30" tap_mode="classic" trigger_index="30" type="unknown"/> + <node data_index="29" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m1[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="29" tap_mode="classic" trigger_index="29" type="unknown"/> + </node> + <node is_selected="false" level-0="alt_or" name="rx1_d_m2[7..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <node data_index="44" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m2[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="44" tap_mode="classic" trigger_index="44" type="unknown"/> + <node data_index="43" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m2[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="43" tap_mode="classic" trigger_index="43" type="unknown"/> + <node data_index="42" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m2[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="42" tap_mode="classic" trigger_index="42" type="unknown"/> + <node data_index="41" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m2[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="41" tap_mode="classic" trigger_index="41" type="unknown"/> + <node data_index="40" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m2[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="40" tap_mode="classic" trigger_index="40" type="unknown"/> + <node data_index="39" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m2[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="39" tap_mode="classic" trigger_index="39" type="unknown"/> + <node data_index="38" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m2[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="38" tap_mode="classic" trigger_index="38" type="unknown"/> + <node data_index="37" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m2[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="37" tap_mode="classic" trigger_index="37" type="unknown"/> + </node> + <node is_selected="false" level-0="alt_or" name="rx1_d_m3[7..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <node data_index="52" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m3[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="52" tap_mode="classic" trigger_index="52" type="unknown"/> + <node data_index="51" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m3[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="51" tap_mode="classic" trigger_index="51" type="unknown"/> + <node data_index="50" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m3[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="50" tap_mode="classic" trigger_index="50" type="unknown"/> + <node data_index="49" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m3[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="49" tap_mode="classic" trigger_index="49" type="unknown"/> + <node data_index="48" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m3[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="48" tap_mode="classic" trigger_index="48" type="unknown"/> + <node data_index="47" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m3[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="47" tap_mode="classic" trigger_index="47" type="unknown"/> + <node data_index="46" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m3[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="46" tap_mode="classic" trigger_index="46" type="unknown"/> + <node data_index="45" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m3[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="45" tap_mode="classic" trigger_index="45" type="unknown"/> + </node> + <node is_selected="false" level-0="alt_or" name="rx1_d_m4[7..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <node data_index="60" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m4[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="60" tap_mode="classic" trigger_index="60" type="unknown"/> + <node data_index="59" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m4[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="59" tap_mode="classic" trigger_index="59" type="unknown"/> + <node data_index="58" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m4[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="58" tap_mode="classic" trigger_index="58" type="unknown"/> + <node data_index="57" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m4[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="57" tap_mode="classic" trigger_index="57" type="unknown"/> + <node data_index="56" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m4[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="56" tap_mode="classic" trigger_index="56" type="unknown"/> + <node data_index="55" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m4[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="55" tap_mode="classic" trigger_index="55" type="unknown"/> + <node data_index="54" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m4[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="54" tap_mode="classic" trigger_index="54" type="unknown"/> + <node data_index="53" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m4[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="53" tap_mode="classic" trigger_index="53" type="unknown"/> + </node> + <node is_selected="false" level-0="alt_or" name="ddro:rgmii_tx_1|datain_h[4..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <node data_index="14" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="ddro:rgmii_tx_1|datain_h[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="14" tap_mode="classic" trigger_index="14" type="unknown"/> + <node data_index="13" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="ddro:rgmii_tx_1|datain_h[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="13" tap_mode="classic" trigger_index="13" type="unknown"/> + <node data_index="12" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="ddro:rgmii_tx_1|datain_h[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="12" tap_mode="classic" trigger_index="12" type="unknown"/> + <node data_index="11" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="ddro:rgmii_tx_1|datain_h[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="11" tap_mode="classic" trigger_index="11" type="unknown"/> + <node data_index="10" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="ddro:rgmii_tx_1|datain_h[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="10" tap_mode="classic" trigger_index="10" type="unknown"/> + </node> + <node is_selected="false" level-0="alt_or" name="ddro:rgmii_tx_1|datain_l[4..0]" order="msb_to_lsb" state="collapse" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <node data_index="19" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="ddro:rgmii_tx_1|datain_l[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="19" tap_mode="classic" trigger_index="19" type="unknown"/> + <node data_index="18" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="ddro:rgmii_tx_1|datain_l[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="18" tap_mode="classic" trigger_index="18" type="unknown"/> + <node data_index="17" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="ddro:rgmii_tx_1|datain_l[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="17" tap_mode="classic" trigger_index="17" type="unknown"/> + <node data_index="16" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="ddro:rgmii_tx_1|datain_l[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="16" tap_mode="classic" trigger_index="16" type="unknown"/> + <node data_index="15" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="ddro:rgmii_tx_1|datain_l[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="15" tap_mode="classic" trigger_index="15" type="unknown"/> + </node> + </unified_setup_data_view> + <data_view> + <net data_index="20" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="phy1_rx_ctl" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="20" tap_mode="classic" trigger_index="20" type="unknown"/> + <bus is_selected="false" level-0="alt_or" name="ddri:rgmi_rx_1|dataout_h[4..0]" order="msb_to_lsb" state="collapse" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="4" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="ddri:rgmi_rx_1|dataout_h[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="4" tap_mode="classic" trigger_index="4" type="unknown"/> + <net data_index="3" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="ddri:rgmi_rx_1|dataout_h[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="3" tap_mode="classic" trigger_index="3" type="unknown"/> + <net data_index="2" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="ddri:rgmi_rx_1|dataout_h[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="2" tap_mode="classic" trigger_index="2" type="unknown"/> + <net data_index="1" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="ddri:rgmi_rx_1|dataout_h[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="1" tap_mode="classic" trigger_index="1" type="unknown"/> + <net data_index="0" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="ddri:rgmi_rx_1|dataout_h[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="0" tap_mode="classic" trigger_index="0" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="ddri:rgmi_rx_1|dataout_l[4..0]" order="msb_to_lsb" state="collapse" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="9" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="ddri:rgmi_rx_1|dataout_l[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="9" tap_mode="classic" trigger_index="9" type="unknown"/> + <net data_index="8" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="ddri:rgmi_rx_1|dataout_l[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="8" tap_mode="classic" trigger_index="8" type="unknown"/> + <net data_index="7" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="ddri:rgmi_rx_1|dataout_l[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="7" tap_mode="classic" trigger_index="7" type="unknown"/> + <net data_index="6" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="ddri:rgmi_rx_1|dataout_l[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="6" tap_mode="classic" trigger_index="6" type="unknown"/> + <net data_index="5" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="ddri:rgmi_rx_1|dataout_l[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="5" tap_mode="classic" trigger_index="5" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="rx1_ctl_m1[1..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="22" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_ctl_m1[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="22" tap_mode="classic" trigger_index="22" type="unknown"/> + <net data_index="21" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_ctl_m1[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="21" tap_mode="classic" trigger_index="21" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="rx1_ctl_m2[1..0]" order="msb_to_lsb" radix="hex" state="collapse" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="24" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="high" name="rx1_ctl_m2[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="24" tap_mode="classic" trigger_index="24" type="unknown"/> + <net data_index="23" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="high" name="rx1_ctl_m2[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="23" tap_mode="classic" trigger_index="23" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="rx1_ctl_m3[1..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="26" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_ctl_m3[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="26" tap_mode="classic" trigger_index="26" type="unknown"/> + <net data_index="25" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_ctl_m3[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="25" tap_mode="classic" trigger_index="25" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="rx1_ctl_m4[1..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="28" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_ctl_m4[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="28" tap_mode="classic" trigger_index="28" type="unknown"/> + <net data_index="27" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_ctl_m4[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="27" tap_mode="classic" trigger_index="27" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="rx1_d_m1[7..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="36" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m1[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="36" tap_mode="classic" trigger_index="36" type="unknown"/> + <net data_index="35" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m1[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="35" tap_mode="classic" trigger_index="35" type="unknown"/> + <net data_index="34" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m1[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="34" tap_mode="classic" trigger_index="34" type="unknown"/> + <net data_index="33" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m1[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="33" tap_mode="classic" trigger_index="33" type="unknown"/> + <net data_index="32" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m1[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="32" tap_mode="classic" trigger_index="32" type="unknown"/> + <net data_index="31" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m1[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="31" tap_mode="classic" trigger_index="31" type="unknown"/> + <net data_index="30" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m1[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="30" tap_mode="classic" trigger_index="30" type="unknown"/> + <net data_index="29" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m1[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="29" tap_mode="classic" trigger_index="29" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="rx1_d_m2[7..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="44" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m2[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="44" tap_mode="classic" trigger_index="44" type="unknown"/> + <net data_index="43" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m2[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="43" tap_mode="classic" trigger_index="43" type="unknown"/> + <net data_index="42" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m2[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="42" tap_mode="classic" trigger_index="42" type="unknown"/> + <net data_index="41" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m2[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="41" tap_mode="classic" trigger_index="41" type="unknown"/> + <net data_index="40" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m2[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="40" tap_mode="classic" trigger_index="40" type="unknown"/> + <net data_index="39" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m2[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="39" tap_mode="classic" trigger_index="39" type="unknown"/> + <net data_index="38" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m2[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="38" tap_mode="classic" trigger_index="38" type="unknown"/> + <net data_index="37" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m2[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="37" tap_mode="classic" trigger_index="37" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="rx1_d_m3[7..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="52" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m3[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="52" tap_mode="classic" trigger_index="52" type="unknown"/> + <net data_index="51" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m3[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="51" tap_mode="classic" trigger_index="51" type="unknown"/> + <net data_index="50" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m3[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="50" tap_mode="classic" trigger_index="50" type="unknown"/> + <net data_index="49" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m3[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="49" tap_mode="classic" trigger_index="49" type="unknown"/> + <net data_index="48" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m3[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="48" tap_mode="classic" trigger_index="48" type="unknown"/> + <net data_index="47" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m3[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="47" tap_mode="classic" trigger_index="47" type="unknown"/> + <net data_index="46" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m3[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="46" tap_mode="classic" trigger_index="46" type="unknown"/> + <net data_index="45" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m3[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="45" tap_mode="classic" trigger_index="45" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="rx1_d_m4[7..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="60" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m4[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="60" tap_mode="classic" trigger_index="60" type="unknown"/> + <net data_index="59" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m4[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="59" tap_mode="classic" trigger_index="59" type="unknown"/> + <net data_index="58" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m4[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="58" tap_mode="classic" trigger_index="58" type="unknown"/> + <net data_index="57" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m4[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="57" tap_mode="classic" trigger_index="57" type="unknown"/> + <net data_index="56" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m4[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="56" tap_mode="classic" trigger_index="56" type="unknown"/> + <net data_index="55" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m4[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="55" tap_mode="classic" trigger_index="55" type="unknown"/> + <net data_index="54" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m4[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="54" tap_mode="classic" trigger_index="54" type="unknown"/> + <net data_index="53" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m4[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="53" tap_mode="classic" trigger_index="53" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="ddro:rgmii_tx_1|datain_h[4..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="14" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="ddro:rgmii_tx_1|datain_h[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="14" tap_mode="classic" trigger_index="14" type="unknown"/> + <net data_index="13" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="ddro:rgmii_tx_1|datain_h[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="13" tap_mode="classic" trigger_index="13" type="unknown"/> + <net data_index="12" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="ddro:rgmii_tx_1|datain_h[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="12" tap_mode="classic" trigger_index="12" type="unknown"/> + <net data_index="11" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="ddro:rgmii_tx_1|datain_h[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="11" tap_mode="classic" trigger_index="11" type="unknown"/> + <net data_index="10" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="ddro:rgmii_tx_1|datain_h[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="10" tap_mode="classic" trigger_index="10" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="ddro:rgmii_tx_1|datain_l[4..0]" order="msb_to_lsb" state="collapse" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="19" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="ddro:rgmii_tx_1|datain_l[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="19" tap_mode="classic" trigger_index="19" type="unknown"/> + <net data_index="18" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="ddro:rgmii_tx_1|datain_l[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="18" tap_mode="classic" trigger_index="18" type="unknown"/> + <net data_index="17" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="ddro:rgmii_tx_1|datain_l[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="17" tap_mode="classic" trigger_index="17" type="unknown"/> + <net data_index="16" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="ddro:rgmii_tx_1|datain_l[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="16" tap_mode="classic" trigger_index="16" type="unknown"/> + <net data_index="15" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="ddro:rgmii_tx_1|datain_l[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="15" tap_mode="classic" trigger_index="15" type="unknown"/> + </bus> + </data_view> + <setup_view> + <net data_index="20" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="phy1_rx_ctl" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="20" tap_mode="classic" trigger_index="20" type="unknown"/> + <bus is_selected="false" level-0="alt_or" name="ddri:rgmi_rx_1|dataout_h[4..0]" order="msb_to_lsb" state="collapse" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="4" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="ddri:rgmi_rx_1|dataout_h[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="4" tap_mode="classic" trigger_index="4" type="unknown"/> + <net data_index="3" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="ddri:rgmi_rx_1|dataout_h[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="3" tap_mode="classic" trigger_index="3" type="unknown"/> + <net data_index="2" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="ddri:rgmi_rx_1|dataout_h[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="2" tap_mode="classic" trigger_index="2" type="unknown"/> + <net data_index="1" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="ddri:rgmi_rx_1|dataout_h[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="1" tap_mode="classic" trigger_index="1" type="unknown"/> + <net data_index="0" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="ddri:rgmi_rx_1|dataout_h[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="0" tap_mode="classic" trigger_index="0" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="ddri:rgmi_rx_1|dataout_l[4..0]" order="msb_to_lsb" state="collapse" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="9" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="ddri:rgmi_rx_1|dataout_l[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="9" tap_mode="classic" trigger_index="9" type="unknown"/> + <net data_index="8" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="ddri:rgmi_rx_1|dataout_l[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="8" tap_mode="classic" trigger_index="8" type="unknown"/> + <net data_index="7" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="ddri:rgmi_rx_1|dataout_l[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="7" tap_mode="classic" trigger_index="7" type="unknown"/> + <net data_index="6" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="ddri:rgmi_rx_1|dataout_l[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="6" tap_mode="classic" trigger_index="6" type="unknown"/> + <net data_index="5" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="ddri:rgmi_rx_1|dataout_l[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="5" tap_mode="classic" trigger_index="5" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="rx1_ctl_m1[1..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="22" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_ctl_m1[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="22" tap_mode="classic" trigger_index="22" type="unknown"/> + <net data_index="21" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_ctl_m1[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="21" tap_mode="classic" trigger_index="21" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="rx1_ctl_m2[1..0]" order="msb_to_lsb" radix="hex" state="collapse" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="24" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="high" name="rx1_ctl_m2[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="24" tap_mode="classic" trigger_index="24" type="unknown"/> + <net data_index="23" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="high" name="rx1_ctl_m2[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="23" tap_mode="classic" trigger_index="23" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="rx1_ctl_m3[1..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="26" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_ctl_m3[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="26" tap_mode="classic" trigger_index="26" type="unknown"/> + <net data_index="25" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_ctl_m3[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="25" tap_mode="classic" trigger_index="25" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="rx1_ctl_m4[1..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="28" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_ctl_m4[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="28" tap_mode="classic" trigger_index="28" type="unknown"/> + <net data_index="27" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_ctl_m4[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="27" tap_mode="classic" trigger_index="27" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="rx1_d_m1[7..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="36" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m1[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="36" tap_mode="classic" trigger_index="36" type="unknown"/> + <net data_index="35" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m1[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="35" tap_mode="classic" trigger_index="35" type="unknown"/> + <net data_index="34" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m1[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="34" tap_mode="classic" trigger_index="34" type="unknown"/> + <net data_index="33" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m1[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="33" tap_mode="classic" trigger_index="33" type="unknown"/> + <net data_index="32" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m1[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="32" tap_mode="classic" trigger_index="32" type="unknown"/> + <net data_index="31" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m1[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="31" tap_mode="classic" trigger_index="31" type="unknown"/> + <net data_index="30" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m1[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="30" tap_mode="classic" trigger_index="30" type="unknown"/> + <net data_index="29" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m1[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="29" tap_mode="classic" trigger_index="29" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="rx1_d_m2[7..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="44" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m2[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="44" tap_mode="classic" trigger_index="44" type="unknown"/> + <net data_index="43" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m2[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="43" tap_mode="classic" trigger_index="43" type="unknown"/> + <net data_index="42" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m2[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="42" tap_mode="classic" trigger_index="42" type="unknown"/> + <net data_index="41" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m2[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="41" tap_mode="classic" trigger_index="41" type="unknown"/> + <net data_index="40" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m2[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="40" tap_mode="classic" trigger_index="40" type="unknown"/> + <net data_index="39" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m2[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="39" tap_mode="classic" trigger_index="39" type="unknown"/> + <net data_index="38" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m2[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="38" tap_mode="classic" trigger_index="38" type="unknown"/> + <net data_index="37" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m2[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="37" tap_mode="classic" trigger_index="37" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="rx1_d_m3[7..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="52" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m3[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="52" tap_mode="classic" trigger_index="52" type="unknown"/> + <net data_index="51" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m3[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="51" tap_mode="classic" trigger_index="51" type="unknown"/> + <net data_index="50" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m3[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="50" tap_mode="classic" trigger_index="50" type="unknown"/> + <net data_index="49" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m3[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="49" tap_mode="classic" trigger_index="49" type="unknown"/> + <net data_index="48" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m3[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="48" tap_mode="classic" trigger_index="48" type="unknown"/> + <net data_index="47" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m3[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="47" tap_mode="classic" trigger_index="47" type="unknown"/> + <net data_index="46" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m3[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="46" tap_mode="classic" trigger_index="46" type="unknown"/> + <net data_index="45" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m3[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="45" tap_mode="classic" trigger_index="45" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="rx1_d_m4[7..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="60" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m4[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="60" tap_mode="classic" trigger_index="60" type="unknown"/> + <net data_index="59" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m4[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="59" tap_mode="classic" trigger_index="59" type="unknown"/> + <net data_index="58" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m4[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="58" tap_mode="classic" trigger_index="58" type="unknown"/> + <net data_index="57" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m4[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="57" tap_mode="classic" trigger_index="57" type="unknown"/> + <net data_index="56" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m4[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="56" tap_mode="classic" trigger_index="56" type="unknown"/> + <net data_index="55" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m4[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="55" tap_mode="classic" trigger_index="55" type="unknown"/> + <net data_index="54" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m4[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="54" tap_mode="classic" trigger_index="54" type="unknown"/> + <net data_index="53" duplicate_name_allowed="false" is_data_input="true" is_node_valid="false" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rx1_d_m4[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="53" tap_mode="classic" trigger_index="53" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="ddro:rgmii_tx_1|datain_h[4..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="14" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="ddro:rgmii_tx_1|datain_h[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="14" tap_mode="classic" trigger_index="14" type="unknown"/> + <net data_index="13" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="ddro:rgmii_tx_1|datain_h[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="13" tap_mode="classic" trigger_index="13" type="unknown"/> + <net data_index="12" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="ddro:rgmii_tx_1|datain_h[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="12" tap_mode="classic" trigger_index="12" type="unknown"/> + <net data_index="11" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="ddro:rgmii_tx_1|datain_h[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="11" tap_mode="classic" trigger_index="11" type="unknown"/> + <net data_index="10" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="ddro:rgmii_tx_1|datain_h[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="10" tap_mode="classic" trigger_index="10" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="ddro:rgmii_tx_1|datain_l[4..0]" order="msb_to_lsb" state="collapse" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="19" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="ddro:rgmii_tx_1|datain_l[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="19" tap_mode="classic" trigger_index="19" type="unknown"/> + <net data_index="18" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="ddro:rgmii_tx_1|datain_l[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="18" tap_mode="classic" trigger_index="18" type="unknown"/> + <net data_index="17" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="ddro:rgmii_tx_1|datain_l[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="17" tap_mode="classic" trigger_index="17" type="unknown"/> + <net data_index="16" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="ddro:rgmii_tx_1|datain_l[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="16" tap_mode="classic" trigger_index="16" type="unknown"/> + <net data_index="15" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="ddro:rgmii_tx_1|datain_l[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="15" tap_mode="classic" trigger_index="15" type="unknown"/> + </bus> + </setup_view> + <trigger_in_editor/> + <trigger_out_editor/> + </presentation> + <trigger CRC="6FFE4D9F" attribute_mem_mode="false" gap_record="true" global_temp="1" is_expanded="true" name="trigger: 2025/06/08 01:36:48 #0" position="pre" power_up_trigger_mode="false" record_data_gap="true" segment_size="1" storage_mode="off" storage_qualifier_disabled="no" storage_qualifier_port_is_pin="false" storage_qualifier_port_name="auto_stp_external_storage_qualifier" storage_qualifier_port_tap_mode="classic" trigger_type="circular"> + <power_up_trigger position="pre" storage_qualifier_disabled="no"/> + <events use_custom_flow_control="no"> + <level enabled="yes" name="condition1" type="basic">'rx1_ctl_m2[0]' == high && 'rx1_ctl_m2[1]' == high + <power_up enabled="yes"> + </power_up><op_node/> + </level> + </events> + <storage_qualifier_events> + <transitional>1111111111111111111111111111111111111111111111111111111111111 + <pwr_up_transitional>1111111111111111111111111111111111111111111111111111111111111</pwr_up_transitional> + </transitional> + <storage_qualifier_level type="basic"> + <power_up> + </power_up> + <op_node/> + </storage_qualifier_level> + <storage_qualifier_level type="basic"> + <power_up> + </power_up> + <op_node/> + </storage_qualifier_level> + <storage_qualifier_level type="basic"> + <power_up> + </power_up> + <op_node/> + </storage_qualifier_level> + </storage_qualifier_events> + <log> + <data global_temp="1" name="log: Trig @ 2025/06/08 01:41:09 (0:0:0.2 elapsed) #1" power_up_mode="false" sample_depth="127" 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+ <extradata>11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111</extradata> + </log> + </trigger> + </signal_set> + <position_info> + <single attribute="active tab" value="0"/> + <single attribute="data horizontal scroll position" value="6"/> + <single attribute="data vertical scroll position" value="0"/> + <single attribute="setup horizontal scroll position" value="0"/> + <single attribute="setup vertical scroll position" value="0"/> + <single attribute="zoom level denominator" value="1"/> + <single attribute="zoom level numerator" value="2048"/> + <single attribute="zoom offset denominator" value="1"/> + <single attribute="zoom offset numerator" value="30"/> + </position_info> + </instance> + <instance enabled="false" entity_name="sld_signaltap" is_auto_node="yes" is_expanded="true" name="top" source_file="sld_signaltap.vhd"> + <node_ip_info instance_id="2" mfg_id="110" node_id="0" version="6"/> + <signal_set global_temp="1" is_expanded="true" name="signal_set: 2025/06/11 14:45:51 #0"> + <clock name="pll:pll_0|c1" polarity="posedge" tap_mode="classic"/> + <config pipeline_level="0" ram_type="AUTO" reserved_data_nodes="0" reserved_storage_qualifier_nodes="0" reserved_trigger_nodes="0" sample_depth="256" trigger_in_enable="no" trigger_out_enable="no"/> + <top_entity/> + <signal_vec> + <trigger_input_vec> + <wire name="clk_i" tap_mode="classic"/> + <wire name="fpga_led[0]" tap_mode="classic"/> + <wire name="fpga_led[1]" tap_mode="classic"/> + <wire name="fpga_led[2]" tap_mode="classic"/> + <wire name="heart_beat_cnt[0]" tap_mode="classic"/> + <wire name="heart_beat_cnt[10]" tap_mode="classic"/> + <wire name="heart_beat_cnt[11]" tap_mode="classic"/> + <wire name="heart_beat_cnt[12]" tap_mode="classic"/> + <wire name="heart_beat_cnt[13]" tap_mode="classic"/> + <wire name="heart_beat_cnt[14]" tap_mode="classic"/> + <wire name="heart_beat_cnt[15]" tap_mode="classic"/> + <wire name="heart_beat_cnt[16]" tap_mode="classic"/> + <wire name="heart_beat_cnt[17]" tap_mode="classic"/> + <wire name="heart_beat_cnt[18]" tap_mode="classic"/> + <wire name="heart_beat_cnt[19]" tap_mode="classic"/> + <wire name="heart_beat_cnt[1]" tap_mode="classic"/> + <wire name="heart_beat_cnt[20]" tap_mode="classic"/> + <wire name="heart_beat_cnt[21]" tap_mode="classic"/> + <wire name="heart_beat_cnt[22]" tap_mode="classic"/> + <wire name="heart_beat_cnt[23]" tap_mode="classic"/> + <wire name="heart_beat_cnt[24]" tap_mode="classic"/> + <wire name="heart_beat_cnt[25]" tap_mode="classic"/> + <wire name="heart_beat_cnt[2]" tap_mode="classic"/> + <wire name="heart_beat_cnt[3]" tap_mode="classic"/> + <wire name="heart_beat_cnt[4]" tap_mode="classic"/> + <wire name="heart_beat_cnt[5]" tap_mode="classic"/> + <wire name="heart_beat_cnt[6]" tap_mode="classic"/> + <wire name="heart_beat_cnt[7]" tap_mode="classic"/> + <wire name="heart_beat_cnt[8]" tap_mode="classic"/> + <wire name="heart_beat_cnt[9]" tap_mode="classic"/> + <wire name="phy0_clk" tap_mode="classic"/> + <wire name="phy0_rstn" tap_mode="classic"/> + <wire name="phy1_clk" tap_mode="classic"/> + <wire name="phy1_rstn" tap_mode="classic"/> + <wire name="phy2_rstn" tap_mode="classic"/> + <wire name="pll:pll_0|locked" tap_mode="classic"/> + <wire name="rstn" tap_mode="classic"/> + <wire name="sys_rstn" tap_mode="classic"/> + </trigger_input_vec> + <data_input_vec> + <wire name="clk_i" tap_mode="classic"/> + <wire name="fpga_led[0]" tap_mode="classic"/> + <wire name="fpga_led[1]" tap_mode="classic"/> + <wire name="fpga_led[2]" tap_mode="classic"/> + <wire name="heart_beat_cnt[0]" tap_mode="classic"/> + <wire name="heart_beat_cnt[10]" tap_mode="classic"/> + <wire name="heart_beat_cnt[11]" tap_mode="classic"/> + <wire name="heart_beat_cnt[12]" tap_mode="classic"/> + <wire name="heart_beat_cnt[13]" tap_mode="classic"/> + <wire name="heart_beat_cnt[14]" tap_mode="classic"/> + <wire name="heart_beat_cnt[15]" tap_mode="classic"/> + <wire name="heart_beat_cnt[16]" tap_mode="classic"/> + <wire name="heart_beat_cnt[17]" tap_mode="classic"/> + <wire name="heart_beat_cnt[18]" tap_mode="classic"/> + <wire name="heart_beat_cnt[19]" tap_mode="classic"/> + <wire name="heart_beat_cnt[1]" tap_mode="classic"/> + <wire name="heart_beat_cnt[20]" tap_mode="classic"/> + <wire name="heart_beat_cnt[21]" tap_mode="classic"/> + <wire name="heart_beat_cnt[22]" tap_mode="classic"/> + <wire name="heart_beat_cnt[23]" tap_mode="classic"/> + <wire name="heart_beat_cnt[24]" tap_mode="classic"/> + <wire name="heart_beat_cnt[25]" tap_mode="classic"/> + <wire name="heart_beat_cnt[2]" tap_mode="classic"/> + <wire name="heart_beat_cnt[3]" tap_mode="classic"/> + <wire name="heart_beat_cnt[4]" tap_mode="classic"/> + <wire name="heart_beat_cnt[5]" tap_mode="classic"/> + <wire name="heart_beat_cnt[6]" tap_mode="classic"/> + <wire name="heart_beat_cnt[7]" tap_mode="classic"/> + <wire name="heart_beat_cnt[8]" tap_mode="classic"/> + <wire name="heart_beat_cnt[9]" tap_mode="classic"/> + <wire name="phy0_clk" tap_mode="classic"/> + <wire name="phy0_rstn" tap_mode="classic"/> + <wire name="phy1_clk" tap_mode="classic"/> + <wire name="phy1_rstn" tap_mode="classic"/> + <wire name="phy2_rstn" tap_mode="classic"/> + <wire name="pll:pll_0|locked" tap_mode="classic"/> + <wire name="rstn" tap_mode="classic"/> + <wire name="sys_rstn" tap_mode="classic"/> + </data_input_vec> + <storage_qualifier_input_vec> + <wire name="clk_i" tap_mode="classic"/> + <wire name="fpga_led[0]" tap_mode="classic"/> + <wire name="fpga_led[1]" tap_mode="classic"/> + <wire name="fpga_led[2]" tap_mode="classic"/> + <wire name="heart_beat_cnt[0]" tap_mode="classic"/> + <wire name="heart_beat_cnt[10]" tap_mode="classic"/> + <wire name="heart_beat_cnt[11]" tap_mode="classic"/> + <wire name="heart_beat_cnt[12]" tap_mode="classic"/> + <wire name="heart_beat_cnt[13]" tap_mode="classic"/> + <wire name="heart_beat_cnt[14]" tap_mode="classic"/> + <wire name="heart_beat_cnt[15]" tap_mode="classic"/> + <wire name="heart_beat_cnt[16]" tap_mode="classic"/> + <wire name="heart_beat_cnt[17]" tap_mode="classic"/> + <wire name="heart_beat_cnt[18]" tap_mode="classic"/> + <wire name="heart_beat_cnt[19]" tap_mode="classic"/> + <wire name="heart_beat_cnt[1]" tap_mode="classic"/> + <wire name="heart_beat_cnt[20]" tap_mode="classic"/> + <wire name="heart_beat_cnt[21]" tap_mode="classic"/> + <wire name="heart_beat_cnt[22]" tap_mode="classic"/> + <wire name="heart_beat_cnt[23]" tap_mode="classic"/> + <wire name="heart_beat_cnt[24]" tap_mode="classic"/> + <wire name="heart_beat_cnt[25]" tap_mode="classic"/> + <wire name="heart_beat_cnt[2]" tap_mode="classic"/> + <wire name="heart_beat_cnt[3]" tap_mode="classic"/> + <wire name="heart_beat_cnt[4]" tap_mode="classic"/> + <wire name="heart_beat_cnt[5]" tap_mode="classic"/> + <wire name="heart_beat_cnt[6]" tap_mode="classic"/> + <wire name="heart_beat_cnt[7]" tap_mode="classic"/> + <wire name="heart_beat_cnt[8]" tap_mode="classic"/> + <wire name="heart_beat_cnt[9]" tap_mode="classic"/> + <wire name="phy0_clk" tap_mode="classic"/> + <wire name="phy0_rstn" tap_mode="classic"/> + <wire name="phy1_clk" tap_mode="classic"/> + <wire name="phy1_rstn" tap_mode="classic"/> + <wire name="phy2_rstn" tap_mode="classic"/> + <wire name="pll:pll_0|locked" tap_mode="classic"/> + <wire name="rstn" tap_mode="classic"/> + <wire name="sys_rstn" tap_mode="classic"/> + </storage_qualifier_input_vec> + </signal_vec> + <presentation> + <unified_setup_data_view> + <node data_index="36" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rstn" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="36" tap_mode="classic" trigger_index="36" type="unknown"/> + <node data_index="0" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="clk_i" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="0" tap_mode="classic" trigger_index="0" type="unknown"/> + <node data_index="30" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="phy0_clk" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="30" tap_mode="classic" trigger_index="30" type="unknown"/> + <node data_index="32" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="phy1_clk" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="32" tap_mode="classic" trigger_index="32" type="unknown"/> + <node data_index="37" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="sys_rstn" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="37" tap_mode="classic" trigger_index="37" type="unknown"/> + <node data_index="31" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="phy0_rstn" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="31" tap_mode="classic" trigger_index="31" type="unknown"/> + <node data_index="33" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="phy1_rstn" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="33" tap_mode="classic" trigger_index="33" type="unknown"/> + <node data_index="34" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="phy2_rstn" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="34" tap_mode="classic" trigger_index="34" type="unknown"/> + <node data_index="35" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="high" name="pll:pll_0|locked" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="35" tap_mode="classic" trigger_index="35" type="unknown"/> + <node is_selected="false" level-0="alt_or" name="heart_beat_cnt[25..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <node data_index="21" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="heart_beat_cnt[25]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="21" tap_mode="classic" trigger_index="21" type="unknown"/> + <node data_index="20" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="heart_beat_cnt[24]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="20" tap_mode="classic" trigger_index="20" type="unknown"/> + <node data_index="19" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="heart_beat_cnt[23]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="19" tap_mode="classic" trigger_index="19" type="unknown"/> + <node data_index="18" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="heart_beat_cnt[22]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="18" tap_mode="classic" trigger_index="18" type="unknown"/> + <node data_index="17" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="heart_beat_cnt[21]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="17" tap_mode="classic" trigger_index="17" type="unknown"/> + <node data_index="16" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="heart_beat_cnt[20]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="16" tap_mode="classic" trigger_index="16" type="unknown"/> + <node data_index="14" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="heart_beat_cnt[19]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="14" tap_mode="classic" trigger_index="14" type="unknown"/> + <node data_index="13" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="heart_beat_cnt[18]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="13" tap_mode="classic" trigger_index="13" type="unknown"/> + <node data_index="12" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="heart_beat_cnt[17]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="12" tap_mode="classic" trigger_index="12" type="unknown"/> + <node data_index="11" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" 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pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="7" tap_mode="classic" trigger_index="7" type="unknown"/> + <node data_index="6" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="heart_beat_cnt[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="6" tap_mode="classic" trigger_index="6" type="unknown"/> + <node data_index="5" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="heart_beat_cnt[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="5" tap_mode="classic" trigger_index="5" type="unknown"/> + <node data_index="29" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="heart_beat_cnt[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="29" tap_mode="classic" trigger_index="29" type="unknown"/> + <node data_index="28" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="heart_beat_cnt[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="28" tap_mode="classic" trigger_index="28" type="unknown"/> + <node data_index="27" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="heart_beat_cnt[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="27" tap_mode="classic" trigger_index="27" type="unknown"/> + <node data_index="26" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="heart_beat_cnt[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="26" tap_mode="classic" trigger_index="26" type="unknown"/> + <node data_index="25" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" 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pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="15" tap_mode="classic" trigger_index="15" type="unknown"/> + <node data_index="4" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="heart_beat_cnt[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="4" tap_mode="classic" trigger_index="4" type="unknown"/> + </node> + <node is_selected="false" level-0="alt_or" name="fpga_led[2..0]" order="msb_to_lsb" state="collapse" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="output pin"> + <node data_index="3" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fpga_led[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="3" tap_mode="classic" trigger_index="3" type="unknown"/> + <node data_index="2" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fpga_led[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="2" tap_mode="classic" trigger_index="2" type="unknown"/> + <node data_index="1" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fpga_led[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="1" tap_mode="classic" trigger_index="1" type="unknown"/> + </node> + </unified_setup_data_view> + <data_view> + <net data_index="36" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rstn" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="36" tap_mode="classic" trigger_index="36" type="unknown"/> + <net data_index="0" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="clk_i" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="0" tap_mode="classic" trigger_index="0" type="unknown"/> + <net data_index="30" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="phy0_clk" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="30" tap_mode="classic" trigger_index="30" type="unknown"/> + <net data_index="32" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="phy1_clk" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="32" tap_mode="classic" trigger_index="32" type="unknown"/> + <net data_index="37" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="sys_rstn" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="37" tap_mode="classic" trigger_index="37" type="unknown"/> + <net data_index="31" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="phy0_rstn" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="31" tap_mode="classic" trigger_index="31" type="unknown"/> + <net data_index="33" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="phy1_rstn" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="33" tap_mode="classic" trigger_index="33" type="unknown"/> + <net data_index="34" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="phy2_rstn" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="34" tap_mode="classic" trigger_index="34" type="unknown"/> + <net data_index="35" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="high" name="pll:pll_0|locked" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="35" tap_mode="classic" trigger_index="35" type="unknown"/> + <bus is_selected="false" level-0="alt_or" name="heart_beat_cnt[25..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="21" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="heart_beat_cnt[25]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="21" tap_mode="classic" trigger_index="21" type="unknown"/> + <net data_index="20" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="heart_beat_cnt[24]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="20" tap_mode="classic" trigger_index="20" type="unknown"/> + <net data_index="19" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="heart_beat_cnt[23]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="19" tap_mode="classic" trigger_index="19" type="unknown"/> + <net data_index="18" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="heart_beat_cnt[22]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="18" tap_mode="classic" trigger_index="18" type="unknown"/> + <net data_index="17" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="heart_beat_cnt[21]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="17" tap_mode="classic" trigger_index="17" type="unknown"/> + <net data_index="16" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="heart_beat_cnt[20]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="16" tap_mode="classic" trigger_index="16" type="unknown"/> + <net data_index="14" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="heart_beat_cnt[19]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="14" tap_mode="classic" trigger_index="14" type="unknown"/> + <net data_index="13" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="heart_beat_cnt[18]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="13" tap_mode="classic" trigger_index="13" type="unknown"/> + <net data_index="12" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="heart_beat_cnt[17]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="12" tap_mode="classic" trigger_index="12" type="unknown"/> + <net data_index="11" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="heart_beat_cnt[16]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="11" tap_mode="classic" trigger_index="11" type="unknown"/> + <net data_index="10" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="heart_beat_cnt[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="10" tap_mode="classic" trigger_index="10" type="unknown"/> + <net data_index="9" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="heart_beat_cnt[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="9" tap_mode="classic" trigger_index="9" type="unknown"/> + <net data_index="8" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="heart_beat_cnt[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="8" tap_mode="classic" trigger_index="8" type="unknown"/> + <net data_index="7" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="heart_beat_cnt[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="7" tap_mode="classic" trigger_index="7" type="unknown"/> + <net data_index="6" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="heart_beat_cnt[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="6" tap_mode="classic" trigger_index="6" type="unknown"/> + <net data_index="5" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="heart_beat_cnt[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="5" tap_mode="classic" trigger_index="5" type="unknown"/> + <net data_index="29" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="heart_beat_cnt[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="29" tap_mode="classic" trigger_index="29" type="unknown"/> + <net data_index="28" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="heart_beat_cnt[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="28" tap_mode="classic" trigger_index="28" type="unknown"/> + <net data_index="27" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="heart_beat_cnt[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="27" tap_mode="classic" trigger_index="27" type="unknown"/> + <net data_index="26" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="heart_beat_cnt[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="26" tap_mode="classic" trigger_index="26" type="unknown"/> + <net data_index="25" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="heart_beat_cnt[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="25" tap_mode="classic" trigger_index="25" type="unknown"/> + <net data_index="24" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="heart_beat_cnt[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="24" tap_mode="classic" trigger_index="24" type="unknown"/> + <net data_index="23" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="heart_beat_cnt[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="23" tap_mode="classic" trigger_index="23" type="unknown"/> + <net data_index="22" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="heart_beat_cnt[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="22" tap_mode="classic" trigger_index="22" type="unknown"/> + <net data_index="15" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="heart_beat_cnt[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="15" tap_mode="classic" trigger_index="15" type="unknown"/> + <net data_index="4" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="heart_beat_cnt[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="4" tap_mode="classic" trigger_index="4" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="fpga_led[2..0]" order="msb_to_lsb" state="collapse" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="output pin"> + <net data_index="3" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fpga_led[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="3" tap_mode="classic" trigger_index="3" type="unknown"/> + <net data_index="2" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fpga_led[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="2" tap_mode="classic" trigger_index="2" type="unknown"/> + <net data_index="1" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="fpga_led[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="1" tap_mode="classic" trigger_index="1" type="unknown"/> + </bus> + </data_view> + <setup_view> + <net data_index="36" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="rstn" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="36" tap_mode="classic" trigger_index="36" type="unknown"/> + <net data_index="0" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="clk_i" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="0" tap_mode="classic" trigger_index="0" type="unknown"/> + <net data_index="30" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="phy0_clk" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="30" tap_mode="classic" trigger_index="30" type="unknown"/> + <net data_index="32" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="phy1_clk" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="32" tap_mode="classic" trigger_index="32" type="unknown"/> + <net data_index="37" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="sys_rstn" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="37" tap_mode="classic" trigger_index="37" type="unknown"/> + <net data_index="31" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="phy0_rstn" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="31" tap_mode="classic" trigger_index="31" type="unknown"/> + <net data_index="33" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="phy1_rstn" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="33" tap_mode="classic" trigger_index="33" type="unknown"/> + <net data_index="34" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="phy2_rstn" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="34" tap_mode="classic" trigger_index="34" type="unknown"/> + <net data_index="35" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="high" name="pll:pll_0|locked" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="35" tap_mode="classic" trigger_index="35" type="unknown"/> + <bus is_selected="false" level-0="alt_or" name="heart_beat_cnt[25..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="21" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="heart_beat_cnt[25]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="21" tap_mode="classic" trigger_index="21" type="unknown"/> + <net data_index="20" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="heart_beat_cnt[24]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="20" tap_mode="classic" trigger_index="20" type="unknown"/> + <net data_index="19" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="heart_beat_cnt[23]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="19" tap_mode="classic" trigger_index="19" type="unknown"/> + <net data_index="18" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="heart_beat_cnt[22]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="18" tap_mode="classic" trigger_index="18" type="unknown"/> + <net data_index="17" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="heart_beat_cnt[21]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="17" tap_mode="classic" trigger_index="17" type="unknown"/> + <net data_index="16" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="heart_beat_cnt[20]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="16" tap_mode="classic" trigger_index="16" type="unknown"/> + <net data_index="14" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="heart_beat_cnt[19]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="14" tap_mode="classic" trigger_index="14" type="unknown"/> + <net data_index="13" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="heart_beat_cnt[18]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="13" tap_mode="classic" trigger_index="13" type="unknown"/> + <net data_index="12" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="heart_beat_cnt[17]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="12" tap_mode="classic" trigger_index="12" type="unknown"/> + <net data_index="11" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="heart_beat_cnt[16]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="11" tap_mode="classic" trigger_index="11" type="unknown"/> + <net data_index="10" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="heart_beat_cnt[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="10" tap_mode="classic" trigger_index="10" type="unknown"/> + <net data_index="9" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" 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name="heart_beat_cnt[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="7" tap_mode="classic" trigger_index="7" type="unknown"/> + <net data_index="6" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="heart_beat_cnt[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="6" tap_mode="classic" trigger_index="6" type="unknown"/> + <net data_index="5" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="heart_beat_cnt[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="5" tap_mode="classic" trigger_index="5" type="unknown"/> + <net data_index="29" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="heart_beat_cnt[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="29" tap_mode="classic" trigger_index="29" type="unknown"/> + <net data_index="28" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="heart_beat_cnt[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="28" tap_mode="classic" trigger_index="28" type="unknown"/> + <net data_index="27" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="heart_beat_cnt[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="27" tap_mode="classic" trigger_index="27" type="unknown"/> + <net data_index="26" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="heart_beat_cnt[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="26" tap_mode="classic" trigger_index="26" type="unknown"/> + <net data_index="25" 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is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="heart_beat_cnt[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="23" tap_mode="classic" trigger_index="23" type="unknown"/> + <net data_index="22" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="heart_beat_cnt[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="22" tap_mode="classic" trigger_index="22" type="unknown"/> + <net data_index="15" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="heart_beat_cnt[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="15" tap_mode="classic" trigger_index="15" type="unknown"/> + <net data_index="4" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="heart_beat_cnt[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="4" tap_mode="classic" trigger_index="4" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="fpga_led[2..0]" order="msb_to_lsb" state="collapse" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="output pin"> + <net data_index="3" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" 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pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="1" tap_mode="classic" trigger_index="1" type="unknown"/> + </bus> + </setup_view> + <trigger_in_editor/> + <trigger_out_editor/> + </presentation> + <trigger CRC="3C68EE75" attribute_mem_mode="false" gap_record="true" global_temp="1" is_expanded="true" name="trigger: 2025/06/11 14:46:10 #0" position="pre" power_up_trigger_mode="false" record_data_gap="true" segment_size="64" storage_mode="off" storage_qualifier_disabled="no" storage_qualifier_port_is_pin="false" storage_qualifier_port_name="auto_stp_external_storage_qualifier" storage_qualifier_port_tap_mode="classic" trigger_type="circular"> + <power_up_trigger position="pre" storage_qualifier_disabled="no"/> + <events use_custom_flow_control="no"> + <level enabled="yes" name="condition1" type="basic">'pll:pll_0|locked' == high + <power_up enabled="yes"> + </power_up><op_node/> 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+ <extradata>11111111111111111111111111111111T1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111</extradata> + </log> + </trigger> + </signal_set> + <position_info> + <single attribute="active tab" value="1"/> + <single attribute="data horizontal scroll position" value="0"/> + <single attribute="data vertical scroll position" value="0"/> + <single attribute="setup horizontal scroll position" value="0"/> + <single attribute="setup vertical scroll position" value="0"/> + <single attribute="zoom level denominator" value="1"/> + <single attribute="zoom level numerator" value="8192"/> + <single attribute="zoom offset denominator" value="1"/> + <single attribute="zoom offset numerator" value="2"/> + </position_info> + </instance> + <instance enabled="false" entity_name="sld_signaltap" is_auto_node="yes" is_expanded="true" name="controller_mdio" source_file="sld_signaltap.vhd"> + <node_ip_info instance_id="3" mfg_id="110" node_id="0" version="6"/> + <signal_set global_temp="1" is_expanded="true" name="signal_set: 2025/11/23 22:55:59 #0"> + <clock name="pll:pll_0|c1" polarity="posedge" tap_mode="classic"/> + <config pipeline_level="4" ram_type="AUTO" reserved_data_nodes="0" reserved_storage_qualifier_nodes="0" reserved_trigger_nodes="0" sample_depth="256" trigger_in_enable="no" trigger_out_enable="no"/> + <top_entity/> + <signal_vec> + <trigger_input_vec> + <wire name="controller:controller_0|clk" tap_mode="classic"/> + <wire name="controller:controller_0|cont_state.CONT_ST_BUSY" tap_mode="classic"/> + <wire name="controller:controller_0|cont_state.CONT_ST_DONE" tap_mode="classic"/> + <wire name="controller:controller_0|cont_state.CONT_ST_IDLE" tap_mode="classic"/> + <wire name="controller:controller_0|cont_state.CONT_ST_INIT" tap_mode="classic"/> + <wire name="controller:controller_0|cont_state.CONT_ST_START" tap_mode="classic"/> + <wire name="controller:controller_0|hf_ptrs_sel" tap_mode="classic"/> + <wire name="controller:controller_0|hf_rx_sel" tap_mode="classic"/> + <wire name="controller:controller_0|hf_tx_sel" tap_mode="classic"/> + <wire name="controller:controller_0|mac_addr[0]" tap_mode="classic"/> + <wire name="controller:controller_0|mac_addr[1]" tap_mode="classic"/> + <wire name="controller:controller_0|mac_sel" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_cmd" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_cont_done" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_cont_start" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d[0]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d[10]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d[11]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d[12]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d[13]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d[14]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d[15]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d[1]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d[2]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d[3]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d[4]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d[5]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d[6]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d[7]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d[8]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d[9]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d_i[0]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d_i[10]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d_i[11]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d_i[12]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d_i[13]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d_i[14]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d_i[15]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d_i[1]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d_i[2]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d_i[3]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d_i[4]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d_i[5]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d_i[6]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d_i[7]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d_i[8]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d_i[9]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_init_routine_addr[0]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_init_routine_addr[1]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_init_routine_addr[2]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_init_routine_addr[3]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_init_routine_addr[4]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_init_routine_addr[5]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_init_routine_addr[6]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_init_w_data_h[0]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_init_w_data_h[1]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_init_w_data_h[2]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_init_w_data_h[3]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_init_w_data_h[4]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_init_w_data_h[5]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_init_w_data_h[6]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_init_w_data_h[7]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_init_w_data_l[0]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_init_w_data_l[1]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_init_w_data_l[2]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_init_w_data_l[3]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_init_w_data_l[4]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_init_w_data_l[5]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_init_w_data_l[6]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_init_w_data_l[7]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_mux_sel[0]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_mux_sel[1]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_phy_addr[0]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_phy_addr[1]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_phy_addr[2]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_phy_addr[3]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_phy_addr[4]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_reg_addr[0]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_reg_addr[1]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_reg_addr[2]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_reg_addr[3]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_reg_addr[4]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_routine_addr[0]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_routine_addr[1]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_routine_addr[2]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_routine_addr[3]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_routine_addr[4]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_routine_addr[5]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_routine_addr[6]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_run" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_w_data_h[0]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_w_data_h[1]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_w_data_h[2]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_w_data_h[3]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_w_data_h[4]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_w_data_h[5]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_w_data_h[6]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_w_data_h[7]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_w_data_l[0]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_w_data_l[1]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_w_data_l[2]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_w_data_l[3]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_w_data_l[4]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_w_data_l[5]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_w_data_l[6]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_w_data_l[7]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_we" tap_mode="classic"/> + <wire name="controller:controller_0|mem_addr[0]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_addr[10]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_addr[1]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_addr[2]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_addr[3]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_addr[4]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_addr[5]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_addr[6]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_addr[7]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_addr[8]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_addr[9]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[0]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[10]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[11]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[12]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[13]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[14]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[15]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[16]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[17]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[18]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[19]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[1]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[20]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[21]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[22]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[23]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[24]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[25]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[26]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[27]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[28]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[29]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[2]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[30]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[31]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[3]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[4]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[5]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[6]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[7]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[8]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[9]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_state[0]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_state[1]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_state[2]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_state[3]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[0]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[10]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[11]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[12]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[13]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[14]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[15]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[1]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[2]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[3]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[4]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[5]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[6]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[7]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[8]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[9]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr_ro" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr_valid" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[0]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[10]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[11]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[12]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[13]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[14]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[15]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[16]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[17]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[18]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[19]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[1]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[20]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[21]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[22]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[23]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[24]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[25]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[26]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[27]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[28]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[29]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[2]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[30]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[31]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[3]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[4]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[5]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[6]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[7]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[8]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[9]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_error" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[0]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[10]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[11]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[12]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[13]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[14]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[15]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[16]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[17]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[18]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[19]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[1]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[20]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[21]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[22]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[23]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[24]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[25]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[26]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[27]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[28]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[29]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[2]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[30]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[31]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[3]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[4]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[5]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[6]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[7]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[8]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[9]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_token[0]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_token[1]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_token[2]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_token[3]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_token[4]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_token[5]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_token[6]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_token[7]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_type[0]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_type[1]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_type[2]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_type[3]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_type[4]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_type[5]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_type[6]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_type[7]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_cnt[0]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_cnt[1]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_cnt[2]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_cnt[3]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_cnt[4]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_fifo_int" tap_mode="classic"/> + <wire name="controller:controller_0|rx_fifo_int_acked" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_captured" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[0]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[10]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[11]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[12]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[13]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[14]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[15]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[1]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[2]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[3]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[4]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[5]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[6]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[7]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[8]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[9]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_rd_ptr[0]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_rd_ptr[10]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_rd_ptr[1]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_rd_ptr[2]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_rd_ptr[3]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_rd_ptr[4]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_rd_ptr[5]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_rd_ptr[6]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_rd_ptr[7]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_rd_ptr[8]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_rd_ptr[9]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_wr_ptr[0]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_wr_ptr[10]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_wr_ptr[1]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_wr_ptr[2]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_wr_ptr[3]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_wr_ptr[4]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_wr_ptr[5]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_wr_ptr[6]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_wr_ptr[7]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_wr_ptr[8]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_wr_ptr[9]" tap_mode="classic"/> + <wire name="controller:controller_0|tx_msg_cnt[0]" tap_mode="classic"/> + <wire name="controller:controller_0|tx_msg_cnt[10]" tap_mode="classic"/> + <wire name="controller:controller_0|tx_msg_cnt[11]" tap_mode="classic"/> + <wire name="controller:controller_0|tx_msg_cnt[12]" tap_mode="classic"/> + <wire name="controller:controller_0|tx_msg_cnt[13]" tap_mode="classic"/> + <wire name="controller:controller_0|tx_msg_cnt[14]" tap_mode="classic"/> + <wire name="controller:controller_0|tx_msg_cnt[15]" tap_mode="classic"/> + <wire name="controller:controller_0|tx_msg_cnt[1]" tap_mode="classic"/> + <wire name="controller:controller_0|tx_msg_cnt[2]" tap_mode="classic"/> + <wire name="controller:controller_0|tx_msg_cnt[3]" tap_mode="classic"/> + <wire name="controller:controller_0|tx_msg_cnt[4]" tap_mode="classic"/> + <wire name="controller:controller_0|tx_msg_cnt[5]" tap_mode="classic"/> + <wire name="controller:controller_0|tx_msg_cnt[6]" tap_mode="classic"/> + <wire name="controller:controller_0|tx_msg_cnt[7]" tap_mode="classic"/> + <wire name="controller:controller_0|tx_msg_cnt[8]" tap_mode="classic"/> + <wire name="controller:controller_0|tx_msg_cnt[9]" tap_mode="classic"/> + </trigger_input_vec> + <data_input_vec> + <wire name="controller:controller_0|clk" tap_mode="classic"/> + <wire name="controller:controller_0|cont_state.CONT_ST_BUSY" tap_mode="classic"/> + <wire name="controller:controller_0|cont_state.CONT_ST_DONE" tap_mode="classic"/> + <wire name="controller:controller_0|cont_state.CONT_ST_IDLE" tap_mode="classic"/> + <wire name="controller:controller_0|cont_state.CONT_ST_INIT" tap_mode="classic"/> + <wire name="controller:controller_0|cont_state.CONT_ST_START" tap_mode="classic"/> + <wire name="controller:controller_0|hf_ptrs_sel" tap_mode="classic"/> + <wire name="controller:controller_0|hf_rx_sel" tap_mode="classic"/> + <wire name="controller:controller_0|hf_tx_sel" tap_mode="classic"/> + <wire name="controller:controller_0|mac_addr[0]" tap_mode="classic"/> + <wire name="controller:controller_0|mac_addr[1]" tap_mode="classic"/> + <wire name="controller:controller_0|mac_sel" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_cmd" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_cont_done" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_cont_start" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d[0]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d[10]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d[11]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d[12]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d[13]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d[14]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d[15]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d[1]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d[2]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d[3]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d[4]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d[5]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d[6]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d[7]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d[8]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d[9]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d_i[0]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d_i[10]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d_i[11]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d_i[12]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d_i[13]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d_i[14]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d_i[15]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d_i[1]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d_i[2]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d_i[3]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d_i[4]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d_i[5]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d_i[6]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d_i[7]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d_i[8]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d_i[9]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_init_routine_addr[0]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_init_routine_addr[1]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_init_routine_addr[2]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_init_routine_addr[3]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_init_routine_addr[4]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_init_routine_addr[5]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_init_routine_addr[6]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_init_w_data_h[0]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_init_w_data_h[1]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_init_w_data_h[2]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_init_w_data_h[3]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_init_w_data_h[4]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_init_w_data_h[5]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_init_w_data_h[6]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_init_w_data_h[7]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_init_w_data_l[0]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_init_w_data_l[1]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_init_w_data_l[2]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_init_w_data_l[3]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_init_w_data_l[4]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_init_w_data_l[5]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_init_w_data_l[6]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_init_w_data_l[7]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_mux_sel[0]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_mux_sel[1]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_phy_addr[0]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_phy_addr[1]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_phy_addr[2]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_phy_addr[3]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_phy_addr[4]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_reg_addr[0]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_reg_addr[1]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_reg_addr[2]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_reg_addr[3]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_reg_addr[4]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_routine_addr[0]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_routine_addr[1]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_routine_addr[2]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_routine_addr[3]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_routine_addr[4]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_routine_addr[5]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_routine_addr[6]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_run" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_w_data_h[0]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_w_data_h[1]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_w_data_h[2]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_w_data_h[3]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_w_data_h[4]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_w_data_h[5]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_w_data_h[6]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_w_data_h[7]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_w_data_l[0]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_w_data_l[1]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_w_data_l[2]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_w_data_l[3]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_w_data_l[4]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_w_data_l[5]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_w_data_l[6]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_w_data_l[7]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_we" tap_mode="classic"/> + <wire name="controller:controller_0|mem_addr[0]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_addr[10]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_addr[1]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_addr[2]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_addr[3]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_addr[4]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_addr[5]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_addr[6]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_addr[7]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_addr[8]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_addr[9]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[0]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[10]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[11]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[12]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[13]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[14]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[15]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[16]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[17]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[18]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[19]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[1]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[20]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[21]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[22]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[23]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[24]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[25]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[26]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[27]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[28]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[29]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[2]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[30]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[31]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[3]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[4]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[5]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[6]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[7]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[8]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[9]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_state[0]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_state[1]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_state[2]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_state[3]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[0]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[10]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[11]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[12]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[13]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[14]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[15]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[1]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[2]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[3]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[4]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[5]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[6]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[7]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[8]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[9]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr_ro" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr_valid" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[0]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[10]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[11]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[12]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[13]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[14]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[15]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[16]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[17]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[18]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[19]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[1]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[20]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[21]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[22]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[23]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[24]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[25]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[26]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[27]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[28]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[29]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[2]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[30]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[31]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[3]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[4]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[5]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[6]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[7]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[8]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[9]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_error" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[0]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[10]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[11]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[12]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[13]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[14]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[15]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[16]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[17]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[18]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[19]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[1]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[20]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[21]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[22]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[23]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[24]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[25]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[26]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[27]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[28]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[29]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[2]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[30]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[31]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[3]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[4]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[5]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[6]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[7]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[8]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[9]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_token[0]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_token[1]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_token[2]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_token[3]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_token[4]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_token[5]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_token[6]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_token[7]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_type[0]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_type[1]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_type[2]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_type[3]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_type[4]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_type[5]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_type[6]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_type[7]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_cnt[0]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_cnt[1]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_cnt[2]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_cnt[3]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_cnt[4]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_fifo_int" tap_mode="classic"/> + <wire name="controller:controller_0|rx_fifo_int_acked" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_captured" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[0]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[10]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[11]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[12]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[13]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[14]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[15]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[1]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[2]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[3]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[4]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[5]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[6]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[7]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[8]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[9]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_rd_ptr[0]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_rd_ptr[10]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_rd_ptr[1]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_rd_ptr[2]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_rd_ptr[3]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_rd_ptr[4]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_rd_ptr[5]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_rd_ptr[6]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_rd_ptr[7]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_rd_ptr[8]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_rd_ptr[9]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_wr_ptr[0]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_wr_ptr[10]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_wr_ptr[1]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_wr_ptr[2]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_wr_ptr[3]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_wr_ptr[4]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_wr_ptr[5]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_wr_ptr[6]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_wr_ptr[7]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_wr_ptr[8]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_wr_ptr[9]" tap_mode="classic"/> + <wire name="controller:controller_0|tx_msg_cnt[0]" tap_mode="classic"/> + <wire name="controller:controller_0|tx_msg_cnt[10]" tap_mode="classic"/> + <wire name="controller:controller_0|tx_msg_cnt[11]" tap_mode="classic"/> + <wire name="controller:controller_0|tx_msg_cnt[12]" tap_mode="classic"/> + <wire name="controller:controller_0|tx_msg_cnt[13]" tap_mode="classic"/> + <wire name="controller:controller_0|tx_msg_cnt[14]" tap_mode="classic"/> + <wire name="controller:controller_0|tx_msg_cnt[15]" tap_mode="classic"/> + <wire name="controller:controller_0|tx_msg_cnt[1]" tap_mode="classic"/> + <wire name="controller:controller_0|tx_msg_cnt[2]" tap_mode="classic"/> + <wire name="controller:controller_0|tx_msg_cnt[3]" tap_mode="classic"/> + <wire name="controller:controller_0|tx_msg_cnt[4]" tap_mode="classic"/> + <wire name="controller:controller_0|tx_msg_cnt[5]" tap_mode="classic"/> + <wire name="controller:controller_0|tx_msg_cnt[6]" tap_mode="classic"/> + <wire name="controller:controller_0|tx_msg_cnt[7]" tap_mode="classic"/> + <wire name="controller:controller_0|tx_msg_cnt[8]" tap_mode="classic"/> + <wire name="controller:controller_0|tx_msg_cnt[9]" tap_mode="classic"/> + </data_input_vec> + <storage_qualifier_input_vec> + <wire name="controller:controller_0|clk" tap_mode="classic"/> + <wire name="controller:controller_0|cont_state.CONT_ST_BUSY" tap_mode="classic"/> + <wire name="controller:controller_0|cont_state.CONT_ST_DONE" tap_mode="classic"/> + <wire name="controller:controller_0|cont_state.CONT_ST_IDLE" tap_mode="classic"/> + <wire name="controller:controller_0|cont_state.CONT_ST_INIT" tap_mode="classic"/> + <wire name="controller:controller_0|cont_state.CONT_ST_START" tap_mode="classic"/> + <wire name="controller:controller_0|hf_ptrs_sel" tap_mode="classic"/> + <wire name="controller:controller_0|hf_rx_sel" tap_mode="classic"/> + <wire name="controller:controller_0|hf_tx_sel" tap_mode="classic"/> + <wire name="controller:controller_0|mac_addr[0]" tap_mode="classic"/> + <wire name="controller:controller_0|mac_addr[1]" tap_mode="classic"/> + <wire name="controller:controller_0|mac_sel" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_cmd" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_cont_done" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_cont_start" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d[0]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d[10]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d[11]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d[12]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d[13]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d[14]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d[15]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d[1]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d[2]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d[3]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d[4]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d[5]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d[6]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d[7]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d[8]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d[9]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d_i[0]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d_i[10]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d_i[11]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d_i[12]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d_i[13]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d_i[14]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d_i[15]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d_i[1]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d_i[2]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d_i[3]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d_i[4]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d_i[5]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d_i[6]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d_i[7]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d_i[8]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_d_i[9]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_init_routine_addr[0]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_init_routine_addr[1]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_init_routine_addr[2]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_init_routine_addr[3]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_init_routine_addr[4]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_init_routine_addr[5]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_init_routine_addr[6]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_init_w_data_h[0]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_init_w_data_h[1]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_init_w_data_h[2]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_init_w_data_h[3]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_init_w_data_h[4]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_init_w_data_h[5]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_init_w_data_h[6]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_init_w_data_h[7]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_init_w_data_l[0]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_init_w_data_l[1]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_init_w_data_l[2]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_init_w_data_l[3]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_init_w_data_l[4]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_init_w_data_l[5]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_init_w_data_l[6]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_init_w_data_l[7]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_mux_sel[0]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_mux_sel[1]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_phy_addr[0]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_phy_addr[1]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_phy_addr[2]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_phy_addr[3]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_phy_addr[4]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_reg_addr[0]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_reg_addr[1]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_reg_addr[2]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_reg_addr[3]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_reg_addr[4]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_routine_addr[0]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_routine_addr[1]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_routine_addr[2]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_routine_addr[3]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_routine_addr[4]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_routine_addr[5]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_routine_addr[6]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_run" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_w_data_h[0]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_w_data_h[1]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_w_data_h[2]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_w_data_h[3]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_w_data_h[4]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_w_data_h[5]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_w_data_h[6]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_w_data_h[7]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_w_data_l[0]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_w_data_l[1]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_w_data_l[2]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_w_data_l[3]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_w_data_l[4]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_w_data_l[5]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_w_data_l[6]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_w_data_l[7]" tap_mode="classic"/> + <wire name="controller:controller_0|mdio_we" tap_mode="classic"/> + <wire name="controller:controller_0|mem_addr[0]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_addr[10]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_addr[1]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_addr[2]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_addr[3]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_addr[4]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_addr[5]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_addr[6]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_addr[7]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_addr[8]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_addr[9]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[0]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[10]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[11]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[12]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[13]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[14]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[15]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[16]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[17]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[18]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[19]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[1]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[20]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[21]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[22]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[23]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[24]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[25]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[26]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[27]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[28]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[29]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[2]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[30]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[31]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[3]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[4]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[5]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[6]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[7]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[8]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_d_i[9]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_state[0]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_state[1]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_state[2]" tap_mode="classic"/> + <wire name="controller:controller_0|mem_state[3]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[0]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[10]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[11]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[12]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[13]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[14]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[15]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[1]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[2]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[3]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[4]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[5]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[6]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[7]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[8]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[9]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr_ro" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr_valid" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[0]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[10]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[11]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[12]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[13]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[14]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[15]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[16]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[17]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[18]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[19]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[1]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[20]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[21]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[22]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[23]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[24]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[25]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[26]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[27]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[28]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[29]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[2]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[30]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[31]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[3]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[4]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[5]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[6]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[7]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[8]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[9]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_error" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[0]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[10]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[11]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[12]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[13]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[14]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[15]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[16]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[17]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[18]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[19]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[1]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[20]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[21]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[22]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[23]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[24]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[25]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[26]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[27]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[28]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[29]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[2]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[30]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[31]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[3]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[4]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[5]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[6]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[7]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[8]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[9]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_token[0]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_token[1]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_token[2]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_token[3]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_token[4]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_token[5]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_token[6]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_token[7]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_type[0]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_type[1]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_type[2]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_type[3]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_type[4]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_type[5]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_type[6]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_type[7]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_cnt[0]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_cnt[1]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_cnt[2]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_cnt[3]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_cnt[4]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_fifo_int" tap_mode="classic"/> + <wire name="controller:controller_0|rx_fifo_int_acked" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_captured" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[0]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[10]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[11]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[12]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[13]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[14]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[15]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[1]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[2]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[3]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[4]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[5]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[6]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[7]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[8]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[9]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_rd_ptr[0]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_rd_ptr[10]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_rd_ptr[1]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_rd_ptr[2]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_rd_ptr[3]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_rd_ptr[4]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_rd_ptr[5]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_rd_ptr[6]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_rd_ptr[7]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_rd_ptr[8]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_rd_ptr[9]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_wr_ptr[0]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_wr_ptr[10]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_wr_ptr[1]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_wr_ptr[2]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_wr_ptr[3]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_wr_ptr[4]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_wr_ptr[5]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_wr_ptr[6]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_wr_ptr[7]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_wr_ptr[8]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_wr_ptr[9]" tap_mode="classic"/> + <wire name="controller:controller_0|tx_msg_cnt[0]" tap_mode="classic"/> + <wire name="controller:controller_0|tx_msg_cnt[10]" tap_mode="classic"/> + <wire name="controller:controller_0|tx_msg_cnt[11]" tap_mode="classic"/> + <wire name="controller:controller_0|tx_msg_cnt[12]" tap_mode="classic"/> + <wire name="controller:controller_0|tx_msg_cnt[13]" tap_mode="classic"/> + <wire name="controller:controller_0|tx_msg_cnt[14]" tap_mode="classic"/> + <wire name="controller:controller_0|tx_msg_cnt[15]" tap_mode="classic"/> + <wire name="controller:controller_0|tx_msg_cnt[1]" tap_mode="classic"/> + <wire name="controller:controller_0|tx_msg_cnt[2]" tap_mode="classic"/> + <wire name="controller:controller_0|tx_msg_cnt[3]" tap_mode="classic"/> + <wire name="controller:controller_0|tx_msg_cnt[4]" tap_mode="classic"/> + <wire name="controller:controller_0|tx_msg_cnt[5]" tap_mode="classic"/> + <wire name="controller:controller_0|tx_msg_cnt[6]" tap_mode="classic"/> + <wire name="controller:controller_0|tx_msg_cnt[7]" tap_mode="classic"/> + <wire name="controller:controller_0|tx_msg_cnt[8]" tap_mode="classic"/> + <wire name="controller:controller_0|tx_msg_cnt[9]" tap_mode="classic"/> + </storage_qualifier_input_vec> + </signal_vec> + <presentation> + <unified_setup_data_view> + <node data_index="0" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|clk" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="0" tap_mode="classic" trigger_index="0" type="unknown"/> + <node data_index="5" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|cont_state.CONT_ST_START" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="5" tap_mode="classic" trigger_index="5" type="unknown"/> + <node data_index="4" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|cont_state.CONT_ST_INIT" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="4" tap_mode="classic" trigger_index="4" type="unknown"/> + <node data_index="3" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|cont_state.CONT_ST_IDLE" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="3" tap_mode="classic" trigger_index="3" type="unknown"/> + <node data_index="1" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|cont_state.CONT_ST_BUSY" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="1" tap_mode="classic" trigger_index="1" type="unknown"/> + <node data_index="2" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|cont_state.CONT_ST_DONE" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="2" tap_mode="classic" trigger_index="2" type="unknown"/> + <node data_index="258" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_fifo_int" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="258" tap_mode="classic" trigger_index="258" type="unknown"/> + <node data_index="259" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_fifo_int_acked" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="259" tap_mode="classic" trigger_index="259" type="unknown"/> + <node data_index="260" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="high" name="controller:controller_0|rx_msg_captured" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="260" tap_mode="classic" trigger_index="260" type="unknown"/> + <node is_selected="false" level-0="alt_or" level-1="alt_or" name="controller:controller_0|rx_wr_ptr[10..0]" order="msb_to_lsb" radix="hex" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <node data_index="289" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_wr_ptr[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="289" tap_mode="classic" trigger_index="289" type="unknown"/> + <node data_index="298" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_wr_ptr[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="298" tap_mode="classic" trigger_index="298" type="unknown"/> + <node data_index="297" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_wr_ptr[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="297" tap_mode="classic" trigger_index="297" type="unknown"/> + <node data_index="296" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_wr_ptr[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="296" tap_mode="classic" trigger_index="296" type="unknown"/> + <node data_index="295" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_wr_ptr[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="295" tap_mode="classic" trigger_index="295" type="unknown"/> + <node data_index="294" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_wr_ptr[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="294" tap_mode="classic" trigger_index="294" type="unknown"/> + <node data_index="293" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_wr_ptr[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="293" tap_mode="classic" trigger_index="293" type="unknown"/> + <node data_index="292" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_wr_ptr[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="292" tap_mode="classic" trigger_index="292" type="unknown"/> + <node data_index="291" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_wr_ptr[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="291" tap_mode="classic" trigger_index="291" type="unknown"/> + <node data_index="290" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_wr_ptr[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="290" tap_mode="classic" trigger_index="290" type="unknown"/> + <node data_index="288" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_wr_ptr[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="288" tap_mode="classic" trigger_index="288" type="unknown"/> + </node> + <node is_selected="false" level-0="alt_or" level-1="alt_or" name="controller:controller_0|rx_rd_ptr[10..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <node data_index="278" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_rd_ptr[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="278" tap_mode="classic" trigger_index="278" type="unknown"/> + <node data_index="287" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_rd_ptr[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="287" tap_mode="classic" trigger_index="287" type="unknown"/> + <node data_index="286" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_rd_ptr[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="286" tap_mode="classic" trigger_index="286" type="unknown"/> + <node data_index="285" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_rd_ptr[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="285" tap_mode="classic" trigger_index="285" type="unknown"/> + <node data_index="284" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_rd_ptr[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="284" tap_mode="classic" trigger_index="284" type="unknown"/> + <node data_index="283" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_rd_ptr[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="283" tap_mode="classic" trigger_index="283" type="unknown"/> + <node data_index="282" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_rd_ptr[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="282" tap_mode="classic" trigger_index="282" type="unknown"/> + <node data_index="281" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" 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trigger_index="251" type="unknown"/> + <node data_index="250" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_type[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="250" tap_mode="classic" trigger_index="250" type="unknown"/> + <node data_index="249" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_type[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="249" tap_mode="classic" trigger_index="249" type="unknown"/> + <node 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order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <node data_index="244" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_token[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="244" tap_mode="classic" trigger_index="244" type="unknown"/> + <node data_index="243" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_token[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="243" tap_mode="classic" trigger_index="243" type="unknown"/> + <node data_index="242" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_token[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="242" tap_mode="classic" trigger_index="242" type="unknown"/> + <node data_index="241" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_token[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="241" tap_mode="classic" trigger_index="241" type="unknown"/> + <node data_index="240" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_token[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="240" tap_mode="classic" trigger_index="240" type="unknown"/> + <node data_index="239" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_token[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="239" tap_mode="classic" trigger_index="239" type="unknown"/> + <node data_index="238" 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trigger_index="268" type="unknown"/> + <node data_index="261" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_msg_cnt[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="261" tap_mode="classic" trigger_index="261" type="unknown"/> + </node> + <node is_selected="false" level-0="alt_or" name="controller:controller_0|tx_msg_cnt[15..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <node data_index="305" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|tx_msg_cnt[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" 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storage-2="alt_or" type="combinatorial"> + <node data_index="10" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mac_addr[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="10" tap_mode="classic" trigger_index="10" type="unknown"/> + <node data_index="9" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mac_addr[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="9" tap_mode="classic" trigger_index="9" type="unknown"/> + </node> + <node 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storage-2="dont_care" storage_index="43" tap_mode="classic" trigger_index="43" type="unknown"/> + <node data_index="42" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_d_i[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="42" tap_mode="classic" trigger_index="42" type="unknown"/> + <node data_index="41" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_d_i[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="41" tap_mode="classic" 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storage-1="dont_care" storage-2="dont_care" storage_index="50" tap_mode="classic" trigger_index="50" type="unknown"/> + <node data_index="49" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_init_routine_addr[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="49" tap_mode="classic" trigger_index="49" type="unknown"/> + <node data_index="48" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_init_routine_addr[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="48" tap_mode="classic" trigger_index="48" type="unknown"/> + <node data_index="47" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_init_routine_addr[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="47" tap_mode="classic" trigger_index="47" type="unknown"/> + </node> + <node is_selected="false" level-0="alt_or" name="controller:controller_0|mdio_init_w_data_h[7..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <node data_index="61" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_init_w_data_h[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="61" tap_mode="classic" trigger_index="61" type="unknown"/> + <node data_index="60" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_init_w_data_h[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="60" tap_mode="classic" trigger_index="60" type="unknown"/> + <node data_index="59" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" 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name="controller:controller_0|mdio_init_w_data_h[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="55" tap_mode="classic" trigger_index="55" type="unknown"/> + <node data_index="54" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_init_w_data_h[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="54" tap_mode="classic" trigger_index="54" type="unknown"/> + </node> + <node is_selected="false" level-0="alt_or" name="controller:controller_0|mdio_init_w_data_l[7..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <node data_index="69" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_init_w_data_l[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="69" tap_mode="classic" trigger_index="69" type="unknown"/> + <node data_index="68" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_init_w_data_l[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="68" tap_mode="classic" trigger_index="68" type="unknown"/> + <node data_index="67" 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is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_init_w_data_l[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="63" tap_mode="classic" trigger_index="63" type="unknown"/> + <node data_index="62" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_init_w_data_l[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="62" tap_mode="classic" trigger_index="62" type="unknown"/> + </node> + <node is_selected="false" level-0="alt_or" name="controller:controller_0|mdio_mux_sel[1..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <node data_index="71" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_mux_sel[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="71" tap_mode="classic" trigger_index="71" type="unknown"/> + <node data_index="70" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_mux_sel[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="70" tap_mode="classic" trigger_index="70" type="unknown"/> + </node> + <node is_selected="false" level-0="alt_or" name="controller:controller_0|mdio_phy_addr[4..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <node data_index="76" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_phy_addr[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="76" tap_mode="classic" trigger_index="76" type="unknown"/> + <node data_index="75" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_phy_addr[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="75" tap_mode="classic" trigger_index="75" type="unknown"/> + <node data_index="74" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_phy_addr[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="74" tap_mode="classic" trigger_index="74" type="unknown"/> + <node data_index="73" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_phy_addr[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="73" tap_mode="classic" trigger_index="73" type="unknown"/> + <node data_index="72" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_phy_addr[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="72" tap_mode="classic" trigger_index="72" type="unknown"/> + </node> + <node is_selected="false" level-0="alt_or" name="controller:controller_0|mdio_reg_addr[4..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <node data_index="81" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" 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name="controller:controller_0|mdio_reg_addr[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="77" tap_mode="classic" trigger_index="77" type="unknown"/> + </node> + <node is_selected="false" level-0="alt_or" name="controller:controller_0|mdio_routine_addr[6..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <node data_index="88" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_routine_addr[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="88" tap_mode="classic" trigger_index="88" type="unknown"/> + <node data_index="87" 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is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_routine_addr[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="85" tap_mode="classic" trigger_index="85" type="unknown"/> + <node data_index="84" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_routine_addr[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="84" tap_mode="classic" trigger_index="84" type="unknown"/> + <node data_index="83" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_routine_addr[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="83" tap_mode="classic" trigger_index="83" type="unknown"/> + <node data_index="82" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_routine_addr[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="82" tap_mode="classic" trigger_index="82" type="unknown"/> + </node> + <node is_selected="false" level-0="alt_or" name="controller:controller_0|mdio_w_data_h[7..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <node data_index="97" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_w_data_h[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="97" tap_mode="classic" trigger_index="97" type="unknown"/> + <node data_index="96" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_w_data_h[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="96" tap_mode="classic" trigger_index="96" type="unknown"/> + <node data_index="95" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_w_data_h[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="95" tap_mode="classic" trigger_index="95" type="unknown"/> + <node data_index="94" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_w_data_h[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="94" tap_mode="classic" trigger_index="94" type="unknown"/> + <node data_index="93" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_w_data_h[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="93" tap_mode="classic" trigger_index="93" type="unknown"/> + <node data_index="92" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_w_data_h[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="92" tap_mode="classic" trigger_index="92" type="unknown"/> + <node data_index="91" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_w_data_h[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="91" tap_mode="classic" trigger_index="91" type="unknown"/> + <node data_index="90" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_w_data_h[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="90" tap_mode="classic" trigger_index="90" type="unknown"/> + </node> + <node is_selected="false" level-0="alt_or" name="controller:controller_0|mdio_w_data_l[7..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <node data_index="105" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_w_data_l[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="105" tap_mode="classic" trigger_index="105" type="unknown"/> + <node data_index="104" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_w_data_l[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="104" tap_mode="classic" trigger_index="104" type="unknown"/> + <node data_index="103" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_w_data_l[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="103" tap_mode="classic" trigger_index="103" type="unknown"/> + <node data_index="102" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_w_data_l[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="102" tap_mode="classic" trigger_index="102" type="unknown"/> + <node data_index="101" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_w_data_l[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="101" tap_mode="classic" trigger_index="101" type="unknown"/> + <node data_index="100" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_w_data_l[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="100" tap_mode="classic" trigger_index="100" type="unknown"/> + <node data_index="99" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_w_data_l[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="99" tap_mode="classic" trigger_index="99" type="unknown"/> + <node data_index="98" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_w_data_l[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="98" tap_mode="classic" trigger_index="98" type="unknown"/> + </node> + </unified_setup_data_view> + <data_view> + <net data_index="0" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|clk" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="0" tap_mode="classic" trigger_index="0" type="unknown"/> + <net data_index="5" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|cont_state.CONT_ST_START" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="5" tap_mode="classic" trigger_index="5" type="unknown"/> + <net data_index="4" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|cont_state.CONT_ST_INIT" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="4" tap_mode="classic" trigger_index="4" type="unknown"/> + <net data_index="3" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|cont_state.CONT_ST_IDLE" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="3" tap_mode="classic" trigger_index="3" type="unknown"/> + <net data_index="1" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|cont_state.CONT_ST_BUSY" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="1" tap_mode="classic" trigger_index="1" type="unknown"/> + <net data_index="2" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|cont_state.CONT_ST_DONE" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="2" tap_mode="classic" trigger_index="2" type="unknown"/> + <net data_index="258" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_fifo_int" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="258" tap_mode="classic" trigger_index="258" type="unknown"/> + <net data_index="259" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_fifo_int_acked" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="259" tap_mode="classic" trigger_index="259" type="unknown"/> + <net data_index="260" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="high" name="controller:controller_0|rx_msg_captured" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="260" tap_mode="classic" trigger_index="260" type="unknown"/> + <bus is_selected="false" level-0="alt_or" level-1="alt_or" name="controller:controller_0|rx_wr_ptr[10..0]" order="msb_to_lsb" radix="hex" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="289" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_wr_ptr[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="289" tap_mode="classic" trigger_index="289" type="unknown"/> + <net data_index="298" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_wr_ptr[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="298" tap_mode="classic" trigger_index="298" type="unknown"/> + <net data_index="297" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_wr_ptr[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="297" tap_mode="classic" trigger_index="297" type="unknown"/> + <net data_index="296" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_wr_ptr[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="296" tap_mode="classic" trigger_index="296" type="unknown"/> + <net data_index="295" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_wr_ptr[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="295" tap_mode="classic" trigger_index="295" type="unknown"/> + <net data_index="294" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_wr_ptr[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="294" tap_mode="classic" trigger_index="294" type="unknown"/> + <net data_index="293" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_wr_ptr[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="293" tap_mode="classic" trigger_index="293" type="unknown"/> + <net data_index="292" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_wr_ptr[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="292" tap_mode="classic" trigger_index="292" type="unknown"/> + <net data_index="291" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_wr_ptr[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="291" tap_mode="classic" trigger_index="291" type="unknown"/> + <net data_index="290" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_wr_ptr[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="290" tap_mode="classic" trigger_index="290" type="unknown"/> + <net data_index="288" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_wr_ptr[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="288" tap_mode="classic" trigger_index="288" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" level-1="alt_or" name="controller:controller_0|rx_rd_ptr[10..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="278" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_rd_ptr[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="278" tap_mode="classic" trigger_index="278" type="unknown"/> + <net data_index="287" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_rd_ptr[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="287" tap_mode="classic" trigger_index="287" type="unknown"/> + <net data_index="286" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_rd_ptr[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="286" tap_mode="classic" trigger_index="286" type="unknown"/> + <net data_index="285" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_rd_ptr[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="285" tap_mode="classic" trigger_index="285" type="unknown"/> + <net data_index="284" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_rd_ptr[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="284" tap_mode="classic" trigger_index="284" type="unknown"/> + <net data_index="283" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_rd_ptr[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="283" tap_mode="classic" trigger_index="283" type="unknown"/> + <net data_index="282" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_rd_ptr[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="282" tap_mode="classic" trigger_index="282" type="unknown"/> + <net data_index="281" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_rd_ptr[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="281" tap_mode="classic" trigger_index="281" type="unknown"/> + <net data_index="280" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_rd_ptr[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="280" tap_mode="classic" trigger_index="280" type="unknown"/> + <net data_index="279" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_rd_ptr[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="279" tap_mode="classic" trigger_index="279" type="unknown"/> + <net data_index="277" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_rd_ptr[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="277" tap_mode="classic" trigger_index="277" type="unknown"/> + </bus> + <net data_index="6" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|hf_ptrs_sel" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="6" tap_mode="classic" trigger_index="6" type="unknown"/> + <net data_index="7" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|hf_rx_sel" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="7" tap_mode="classic" trigger_index="7" type="unknown"/> + <net data_index="8" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|hf_tx_sel" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="8" tap_mode="classic" trigger_index="8" type="unknown"/> + <bus is_selected="false" level-0="alt_or" level-1="alt_or" name="controller:controller_0|mem_state[3..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="153" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_state[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="153" tap_mode="classic" trigger_index="153" type="unknown"/> + <net data_index="152" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_state[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="152" tap_mode="classic" trigger_index="152" type="unknown"/> + <net data_index="151" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_state[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="151" tap_mode="classic" trigger_index="151" type="unknown"/> + <net data_index="150" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_state[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="150" tap_mode="classic" trigger_index="150" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" level-1="alt_or" name="controller:controller_0|mem_addr[10..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="108" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_addr[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="108" tap_mode="classic" trigger_index="108" type="unknown"/> + <net data_index="117" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_addr[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="117" tap_mode="classic" trigger_index="117" type="unknown"/> + <net data_index="116" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_addr[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="116" tap_mode="classic" trigger_index="116" type="unknown"/> + <net data_index="115" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_addr[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="115" tap_mode="classic" trigger_index="115" type="unknown"/> + <net data_index="114" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_addr[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="114" tap_mode="classic" trigger_index="114" type="unknown"/> + <net data_index="113" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_addr[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="113" tap_mode="classic" trigger_index="113" type="unknown"/> + <net data_index="112" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_addr[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="112" tap_mode="classic" trigger_index="112" type="unknown"/> + <net data_index="111" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_addr[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="111" tap_mode="classic" trigger_index="111" type="unknown"/> + <net data_index="110" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_addr[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="110" tap_mode="classic" trigger_index="110" type="unknown"/> + <net data_index="109" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_addr[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="109" tap_mode="classic" trigger_index="109" type="unknown"/> + <net data_index="107" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_addr[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="107" tap_mode="classic" trigger_index="107" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" level-1="alt_or" name="controller:controller_0|mem_d_i[31..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="142" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_d_i[31]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="142" tap_mode="classic" trigger_index="142" type="unknown"/> + <net data_index="141" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_d_i[30]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="141" tap_mode="classic" trigger_index="141" type="unknown"/> + <net data_index="139" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_d_i[29]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="139" tap_mode="classic" trigger_index="139" type="unknown"/> + <net data_index="138" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_d_i[28]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="138" tap_mode="classic" trigger_index="138" type="unknown"/> + <net data_index="137" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_d_i[27]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="137" tap_mode="classic" trigger_index="137" type="unknown"/> + <net data_index="136" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_d_i[26]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="136" tap_mode="classic" trigger_index="136" type="unknown"/> + <net data_index="135" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_d_i[25]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="135" tap_mode="classic" trigger_index="135" type="unknown"/> + <net data_index="134" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_d_i[24]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="134" tap_mode="classic" trigger_index="134" type="unknown"/> + <net data_index="133" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_d_i[23]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="133" tap_mode="classic" trigger_index="133" type="unknown"/> + <net data_index="132" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_d_i[22]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="132" tap_mode="classic" trigger_index="132" type="unknown"/> + <net data_index="131" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_d_i[21]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="131" tap_mode="classic" trigger_index="131" type="unknown"/> + <net data_index="130" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_d_i[20]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="130" tap_mode="classic" trigger_index="130" type="unknown"/> + <net data_index="128" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_d_i[19]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="128" tap_mode="classic" trigger_index="128" type="unknown"/> + <net data_index="127" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_d_i[18]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="127" tap_mode="classic" trigger_index="127" type="unknown"/> + <net data_index="126" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_d_i[17]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="126" tap_mode="classic" trigger_index="126" type="unknown"/> + <net data_index="125" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_d_i[16]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="125" tap_mode="classic" trigger_index="125" type="unknown"/> + <net data_index="124" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_d_i[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="124" tap_mode="classic" trigger_index="124" type="unknown"/> + <net data_index="123" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_d_i[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="123" tap_mode="classic" trigger_index="123" type="unknown"/> + <net data_index="122" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_d_i[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="122" tap_mode="classic" trigger_index="122" type="unknown"/> + <net data_index="121" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_d_i[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="121" tap_mode="classic" trigger_index="121" type="unknown"/> + <net data_index="120" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_d_i[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="120" tap_mode="classic" trigger_index="120" type="unknown"/> + <net data_index="119" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_d_i[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="119" tap_mode="classic" trigger_index="119" type="unknown"/> + <net data_index="149" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_d_i[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="149" tap_mode="classic" trigger_index="149" type="unknown"/> + <net data_index="148" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_d_i[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="148" tap_mode="classic" trigger_index="148" type="unknown"/> + <net data_index="147" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_d_i[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="147" tap_mode="classic" trigger_index="147" type="unknown"/> + <net data_index="146" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_d_i[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="146" tap_mode="classic" trigger_index="146" type="unknown"/> + <net data_index="145" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_d_i[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="145" tap_mode="classic" trigger_index="145" type="unknown"/> + <net data_index="144" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_d_i[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="144" tap_mode="classic" trigger_index="144" type="unknown"/> + <net data_index="143" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_d_i[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="143" tap_mode="classic" trigger_index="143" type="unknown"/> + <net data_index="140" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_d_i[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="140" tap_mode="classic" trigger_index="140" type="unknown"/> + <net data_index="129" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_d_i[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="129" tap_mode="classic" trigger_index="129" type="unknown"/> + <net data_index="118" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_d_i[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="118" tap_mode="classic" trigger_index="118" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" level-1="alt_or" name="controller:controller_0|rx_cnt[4..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="257" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_cnt[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="257" tap_mode="classic" trigger_index="257" type="unknown"/> + <net data_index="256" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_cnt[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="256" tap_mode="classic" trigger_index="256" type="unknown"/> + <net data_index="255" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_cnt[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="255" tap_mode="classic" trigger_index="255" type="unknown"/> + <net data_index="254" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_cnt[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="254" tap_mode="classic" trigger_index="254" type="unknown"/> + <net data_index="253" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_cnt[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="253" tap_mode="classic" trigger_index="253" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="controller:controller_0|msg_type[7..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="252" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_type[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="252" tap_mode="classic" trigger_index="252" type="unknown"/> + <net data_index="251" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_type[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="251" tap_mode="classic" trigger_index="251" type="unknown"/> + <net data_index="250" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_type[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="250" tap_mode="classic" trigger_index="250" type="unknown"/> + <net data_index="249" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_type[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="249" tap_mode="classic" trigger_index="249" type="unknown"/> + <net data_index="248" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_type[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="248" tap_mode="classic" trigger_index="248" type="unknown"/> + <net data_index="247" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_type[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="247" tap_mode="classic" trigger_index="247" type="unknown"/> + <net data_index="246" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_type[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="246" tap_mode="classic" trigger_index="246" type="unknown"/> + <net data_index="245" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_type[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="245" tap_mode="classic" trigger_index="245" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="controller:controller_0|msg_token[7..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="244" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_token[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="244" tap_mode="classic" trigger_index="244" type="unknown"/> + <net data_index="243" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_token[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="243" tap_mode="classic" trigger_index="243" type="unknown"/> + <net data_index="242" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_token[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="242" tap_mode="classic" trigger_index="242" type="unknown"/> + <net data_index="241" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_token[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="241" tap_mode="classic" trigger_index="241" type="unknown"/> + <net data_index="240" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_token[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="240" tap_mode="classic" trigger_index="240" type="unknown"/> + <net data_index="239" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_token[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="239" tap_mode="classic" trigger_index="239" type="unknown"/> + <net data_index="238" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_token[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="238" tap_mode="classic" trigger_index="238" type="unknown"/> + <net data_index="237" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_token[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="237" tap_mode="classic" trigger_index="237" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="controller:controller_0|msg_addr[15..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="160" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="160" tap_mode="classic" trigger_index="160" type="unknown"/> + <net data_index="159" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="159" tap_mode="classic" trigger_index="159" type="unknown"/> + <net data_index="158" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="158" tap_mode="classic" trigger_index="158" type="unknown"/> + <net data_index="157" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="157" tap_mode="classic" trigger_index="157" type="unknown"/> + <net data_index="156" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="156" tap_mode="classic" trigger_index="156" type="unknown"/> + <net data_index="155" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="155" tap_mode="classic" trigger_index="155" type="unknown"/> + <net data_index="169" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="169" tap_mode="classic" trigger_index="169" type="unknown"/> + <net data_index="168" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="168" tap_mode="classic" trigger_index="168" type="unknown"/> + <net data_index="167" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="167" tap_mode="classic" trigger_index="167" type="unknown"/> + <net data_index="166" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="166" tap_mode="classic" trigger_index="166" type="unknown"/> + <net data_index="165" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="165" tap_mode="classic" trigger_index="165" type="unknown"/> + <net data_index="164" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="164" tap_mode="classic" trigger_index="164" type="unknown"/> + <net data_index="163" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="163" tap_mode="classic" trigger_index="163" type="unknown"/> + <net data_index="162" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="162" tap_mode="classic" trigger_index="162" type="unknown"/> + <net data_index="161" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="161" tap_mode="classic" trigger_index="161" type="unknown"/> + <net data_index="154" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="154" tap_mode="classic" trigger_index="154" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="controller:controller_0|msg_data[31..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="196" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[31]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="196" tap_mode="classic" trigger_index="196" type="unknown"/> + <net data_index="195" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[30]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="195" tap_mode="classic" trigger_index="195" type="unknown"/> + <net data_index="193" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[29]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="193" tap_mode="classic" trigger_index="193" type="unknown"/> + <net data_index="192" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[28]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="192" tap_mode="classic" trigger_index="192" type="unknown"/> + <net data_index="191" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[27]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="191" tap_mode="classic" trigger_index="191" type="unknown"/> + <net data_index="190" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[26]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="190" tap_mode="classic" trigger_index="190" type="unknown"/> + <net data_index="189" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[25]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="189" tap_mode="classic" trigger_index="189" type="unknown"/> + <net data_index="188" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[24]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="188" tap_mode="classic" trigger_index="188" type="unknown"/> + <net data_index="187" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[23]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="187" tap_mode="classic" trigger_index="187" type="unknown"/> + <net data_index="186" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[22]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="186" tap_mode="classic" trigger_index="186" type="unknown"/> + <net data_index="185" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[21]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="185" tap_mode="classic" trigger_index="185" type="unknown"/> + <net data_index="184" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[20]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="184" tap_mode="classic" trigger_index="184" type="unknown"/> + <net data_index="182" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[19]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="182" tap_mode="classic" trigger_index="182" type="unknown"/> + <net data_index="181" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[18]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="181" tap_mode="classic" trigger_index="181" type="unknown"/> + <net data_index="180" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[17]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="180" tap_mode="classic" trigger_index="180" type="unknown"/> + <net data_index="179" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[16]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="179" tap_mode="classic" trigger_index="179" type="unknown"/> + <net data_index="178" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="178" tap_mode="classic" trigger_index="178" type="unknown"/> + <net data_index="177" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="177" tap_mode="classic" trigger_index="177" type="unknown"/> + <net data_index="176" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="176" tap_mode="classic" trigger_index="176" type="unknown"/> + <net data_index="175" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="175" tap_mode="classic" trigger_index="175" type="unknown"/> + <net data_index="174" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="174" tap_mode="classic" trigger_index="174" type="unknown"/> + <net data_index="173" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="173" tap_mode="classic" trigger_index="173" type="unknown"/> + <net data_index="203" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="203" tap_mode="classic" trigger_index="203" type="unknown"/> + <net data_index="202" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="202" tap_mode="classic" trigger_index="202" type="unknown"/> + <net data_index="201" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="201" tap_mode="classic" trigger_index="201" type="unknown"/> + <net data_index="200" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="200" tap_mode="classic" trigger_index="200" type="unknown"/> + <net data_index="199" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="199" tap_mode="classic" trigger_index="199" type="unknown"/> + <net data_index="198" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="198" tap_mode="classic" trigger_index="198" type="unknown"/> + <net data_index="197" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="197" tap_mode="classic" trigger_index="197" type="unknown"/> + <net data_index="194" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="194" tap_mode="classic" trigger_index="194" type="unknown"/> + <net data_index="183" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="183" tap_mode="classic" trigger_index="183" type="unknown"/> + <net data_index="172" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="172" tap_mode="classic" trigger_index="172" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="controller:controller_0|msg_response[31..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="229" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[31]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="229" tap_mode="classic" trigger_index="229" type="unknown"/> + <net data_index="228" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[30]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="228" tap_mode="classic" trigger_index="228" type="unknown"/> + <net data_index="226" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[29]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="226" tap_mode="classic" trigger_index="226" type="unknown"/> + <net data_index="225" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[28]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="225" tap_mode="classic" trigger_index="225" type="unknown"/> + <net data_index="224" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[27]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="224" tap_mode="classic" trigger_index="224" type="unknown"/> + <net data_index="223" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[26]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="223" tap_mode="classic" trigger_index="223" type="unknown"/> + <net data_index="222" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[25]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="222" tap_mode="classic" trigger_index="222" type="unknown"/> + <net data_index="221" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[24]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="221" tap_mode="classic" trigger_index="221" type="unknown"/> + <net data_index="220" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[23]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="220" tap_mode="classic" trigger_index="220" type="unknown"/> + <net data_index="219" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[22]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="219" tap_mode="classic" trigger_index="219" type="unknown"/> + <net data_index="218" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[21]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="218" tap_mode="classic" trigger_index="218" type="unknown"/> + <net data_index="217" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[20]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="217" tap_mode="classic" trigger_index="217" type="unknown"/> + <net data_index="215" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[19]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="215" tap_mode="classic" trigger_index="215" type="unknown"/> + <net data_index="214" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[18]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="214" tap_mode="classic" trigger_index="214" type="unknown"/> + <net data_index="213" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[17]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="213" tap_mode="classic" trigger_index="213" type="unknown"/> + <net data_index="212" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[16]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="212" tap_mode="classic" trigger_index="212" type="unknown"/> + <net data_index="211" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="211" tap_mode="classic" trigger_index="211" type="unknown"/> + <net data_index="210" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="210" tap_mode="classic" trigger_index="210" type="unknown"/> + <net data_index="209" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="209" tap_mode="classic" trigger_index="209" type="unknown"/> + <net data_index="208" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="208" tap_mode="classic" trigger_index="208" type="unknown"/> + <net data_index="207" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="207" tap_mode="classic" trigger_index="207" type="unknown"/> + <net data_index="206" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="206" tap_mode="classic" trigger_index="206" type="unknown"/> + <net data_index="236" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="236" tap_mode="classic" trigger_index="236" type="unknown"/> + <net data_index="235" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="235" tap_mode="classic" trigger_index="235" type="unknown"/> + <net data_index="234" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="234" tap_mode="classic" trigger_index="234" type="unknown"/> + <net data_index="233" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="233" tap_mode="classic" trigger_index="233" type="unknown"/> + <net data_index="232" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="232" tap_mode="classic" trigger_index="232" type="unknown"/> + <net data_index="231" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="231" tap_mode="classic" trigger_index="231" type="unknown"/> + <net data_index="230" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="230" tap_mode="classic" trigger_index="230" type="unknown"/> + <net data_index="227" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="227" tap_mode="classic" trigger_index="227" type="unknown"/> + <net data_index="216" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="216" tap_mode="classic" trigger_index="216" type="unknown"/> + <net data_index="205" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="205" tap_mode="classic" trigger_index="205" type="unknown"/> + </bus> + <net data_index="171" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr_valid" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="171" tap_mode="classic" trigger_index="171" type="unknown"/> + <net data_index="170" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr_ro" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="170" tap_mode="classic" trigger_index="170" type="unknown"/> + <net data_index="204" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_error" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="204" tap_mode="classic" trigger_index="204" type="unknown"/> + <bus is_selected="false" level-0="alt_or" name="controller:controller_0|rx_msg_cnt[15..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="267" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_msg_cnt[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="267" tap_mode="classic" trigger_index="267" type="unknown"/> + <net data_index="266" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_msg_cnt[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="266" tap_mode="classic" trigger_index="266" type="unknown"/> + <net data_index="265" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_msg_cnt[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="265" tap_mode="classic" trigger_index="265" type="unknown"/> + <net data_index="264" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_msg_cnt[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="264" tap_mode="classic" trigger_index="264" type="unknown"/> + <net data_index="263" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_msg_cnt[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="263" tap_mode="classic" trigger_index="263" type="unknown"/> + <net data_index="262" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_msg_cnt[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="262" tap_mode="classic" trigger_index="262" type="unknown"/> + <net data_index="276" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_msg_cnt[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="276" tap_mode="classic" trigger_index="276" type="unknown"/> + <net data_index="275" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_msg_cnt[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="275" tap_mode="classic" trigger_index="275" type="unknown"/> + <net data_index="274" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_msg_cnt[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="274" tap_mode="classic" trigger_index="274" type="unknown"/> + <net data_index="273" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_msg_cnt[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="273" tap_mode="classic" trigger_index="273" type="unknown"/> + <net data_index="272" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_msg_cnt[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="272" tap_mode="classic" trigger_index="272" type="unknown"/> + <net data_index="271" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_msg_cnt[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="271" tap_mode="classic" trigger_index="271" type="unknown"/> + <net data_index="270" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_msg_cnt[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="270" tap_mode="classic" trigger_index="270" type="unknown"/> + <net data_index="269" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_msg_cnt[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="269" tap_mode="classic" trigger_index="269" type="unknown"/> + <net data_index="268" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_msg_cnt[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="268" tap_mode="classic" trigger_index="268" type="unknown"/> + <net data_index="261" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_msg_cnt[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="261" tap_mode="classic" trigger_index="261" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="controller:controller_0|tx_msg_cnt[15..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="305" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|tx_msg_cnt[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="305" tap_mode="classic" trigger_index="305" type="unknown"/> + <net data_index="304" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|tx_msg_cnt[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="304" tap_mode="classic" trigger_index="304" type="unknown"/> + <net data_index="303" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|tx_msg_cnt[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="303" tap_mode="classic" trigger_index="303" type="unknown"/> + <net data_index="302" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|tx_msg_cnt[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="302" tap_mode="classic" trigger_index="302" type="unknown"/> + <net data_index="301" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|tx_msg_cnt[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="301" tap_mode="classic" trigger_index="301" type="unknown"/> + <net data_index="300" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|tx_msg_cnt[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="300" tap_mode="classic" trigger_index="300" type="unknown"/> + <net data_index="314" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|tx_msg_cnt[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="314" tap_mode="classic" trigger_index="314" type="unknown"/> + <net data_index="313" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|tx_msg_cnt[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="313" tap_mode="classic" trigger_index="313" type="unknown"/> + <net data_index="312" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|tx_msg_cnt[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="312" tap_mode="classic" trigger_index="312" type="unknown"/> + <net data_index="311" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|tx_msg_cnt[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="311" tap_mode="classic" trigger_index="311" type="unknown"/> + <net data_index="310" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|tx_msg_cnt[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="310" tap_mode="classic" trigger_index="310" type="unknown"/> + <net data_index="309" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|tx_msg_cnt[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="309" tap_mode="classic" trigger_index="309" type="unknown"/> + <net data_index="308" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|tx_msg_cnt[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="308" tap_mode="classic" trigger_index="308" type="unknown"/> + <net data_index="307" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|tx_msg_cnt[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="307" tap_mode="classic" trigger_index="307" type="unknown"/> + <net data_index="306" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|tx_msg_cnt[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="306" tap_mode="classic" trigger_index="306" type="unknown"/> + <net data_index="299" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|tx_msg_cnt[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="299" tap_mode="classic" trigger_index="299" type="unknown"/> + </bus> + <net data_index="11" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mac_sel" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="11" tap_mode="classic" trigger_index="11" type="unknown"/> + <bus is_selected="false" level-0="alt_or" name="controller:controller_0|mac_addr[1..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="10" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mac_addr[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="10" tap_mode="classic" trigger_index="10" type="unknown"/> + <net data_index="9" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mac_addr[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="9" tap_mode="classic" trigger_index="9" type="unknown"/> + </bus> + <net data_index="12" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_cmd" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="12" tap_mode="classic" trigger_index="12" type="unknown"/> + <net data_index="13" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_cont_done" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="13" tap_mode="classic" trigger_index="13" type="unknown"/> + <net data_index="14" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_cont_start" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="14" tap_mode="classic" trigger_index="14" type="unknown"/> + <net data_index="89" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_run" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="89" tap_mode="classic" trigger_index="89" type="unknown"/> + <net data_index="106" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_we" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="106" tap_mode="classic" trigger_index="106" type="unknown"/> + <bus is_selected="false" level-0="alt_or" name="controller:controller_0|mdio_d[15..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="21" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_d[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="21" tap_mode="classic" trigger_index="21" type="unknown"/> + <net data_index="20" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_d[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="20" tap_mode="classic" trigger_index="20" type="unknown"/> + <net data_index="19" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_d[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="19" tap_mode="classic" trigger_index="19" type="unknown"/> + <net data_index="18" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_d[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="18" tap_mode="classic" trigger_index="18" type="unknown"/> + <net data_index="17" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_d[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="17" tap_mode="classic" trigger_index="17" type="unknown"/> + <net data_index="16" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_d[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="16" tap_mode="classic" trigger_index="16" type="unknown"/> + <net data_index="30" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_d[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="30" tap_mode="classic" trigger_index="30" type="unknown"/> + <net data_index="29" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_d[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="29" tap_mode="classic" trigger_index="29" type="unknown"/> + <net data_index="28" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_d[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="28" tap_mode="classic" trigger_index="28" type="unknown"/> + <net data_index="27" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_d[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="27" tap_mode="classic" trigger_index="27" type="unknown"/> + <net data_index="26" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_d[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="26" tap_mode="classic" trigger_index="26" type="unknown"/> + <net data_index="25" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_d[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="25" tap_mode="classic" trigger_index="25" type="unknown"/> + <net data_index="24" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_d[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="24" tap_mode="classic" trigger_index="24" type="unknown"/> + <net data_index="23" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_d[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="23" tap_mode="classic" trigger_index="23" type="unknown"/> + <net data_index="22" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_d[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="22" tap_mode="classic" trigger_index="22" type="unknown"/> + <net data_index="15" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_d[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="15" tap_mode="classic" trigger_index="15" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="controller:controller_0|mdio_d_i[15..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="37" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_d_i[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="37" tap_mode="classic" trigger_index="37" type="unknown"/> + <net data_index="36" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_d_i[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="36" tap_mode="classic" trigger_index="36" type="unknown"/> + <net data_index="35" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_d_i[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="35" tap_mode="classic" trigger_index="35" type="unknown"/> + <net data_index="34" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_d_i[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="34" tap_mode="classic" trigger_index="34" type="unknown"/> + <net data_index="33" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_d_i[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="33" tap_mode="classic" trigger_index="33" type="unknown"/> + <net data_index="32" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_d_i[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="32" tap_mode="classic" trigger_index="32" type="unknown"/> + <net data_index="46" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_d_i[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="46" tap_mode="classic" trigger_index="46" type="unknown"/> + <net data_index="45" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_d_i[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="45" tap_mode="classic" trigger_index="45" type="unknown"/> + <net data_index="44" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_d_i[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="44" tap_mode="classic" trigger_index="44" type="unknown"/> + <net data_index="43" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_d_i[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="43" tap_mode="classic" trigger_index="43" type="unknown"/> + <net data_index="42" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_d_i[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="42" tap_mode="classic" trigger_index="42" type="unknown"/> + <net data_index="41" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_d_i[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="41" tap_mode="classic" trigger_index="41" type="unknown"/> + <net data_index="40" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_d_i[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="40" tap_mode="classic" trigger_index="40" type="unknown"/> + <net data_index="39" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_d_i[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="39" tap_mode="classic" trigger_index="39" type="unknown"/> + <net data_index="38" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_d_i[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="38" tap_mode="classic" trigger_index="38" type="unknown"/> + <net data_index="31" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_d_i[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="31" tap_mode="classic" trigger_index="31" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="controller:controller_0|mdio_init_routine_addr[6..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="53" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_init_routine_addr[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="53" tap_mode="classic" trigger_index="53" type="unknown"/> + <net data_index="52" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_init_routine_addr[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="52" tap_mode="classic" trigger_index="52" type="unknown"/> + <net data_index="51" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_init_routine_addr[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="51" tap_mode="classic" trigger_index="51" type="unknown"/> + <net data_index="50" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_init_routine_addr[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="50" tap_mode="classic" trigger_index="50" type="unknown"/> + <net data_index="49" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_init_routine_addr[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="49" tap_mode="classic" trigger_index="49" type="unknown"/> + <net data_index="48" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_init_routine_addr[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="48" tap_mode="classic" trigger_index="48" type="unknown"/> + <net data_index="47" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_init_routine_addr[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="47" tap_mode="classic" trigger_index="47" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="controller:controller_0|mdio_init_w_data_h[7..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="61" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_init_w_data_h[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="61" tap_mode="classic" trigger_index="61" type="unknown"/> + <net data_index="60" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_init_w_data_h[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="60" tap_mode="classic" trigger_index="60" type="unknown"/> + <net data_index="59" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_init_w_data_h[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="59" tap_mode="classic" trigger_index="59" type="unknown"/> + <net data_index="58" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_init_w_data_h[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="58" tap_mode="classic" trigger_index="58" type="unknown"/> + <net data_index="57" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_init_w_data_h[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="57" tap_mode="classic" trigger_index="57" type="unknown"/> + <net data_index="56" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_init_w_data_h[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="56" tap_mode="classic" trigger_index="56" type="unknown"/> + <net data_index="55" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_init_w_data_h[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="55" tap_mode="classic" trigger_index="55" type="unknown"/> + <net data_index="54" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_init_w_data_h[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="54" tap_mode="classic" trigger_index="54" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="controller:controller_0|mdio_init_w_data_l[7..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="69" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_init_w_data_l[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="69" tap_mode="classic" trigger_index="69" type="unknown"/> + <net data_index="68" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_init_w_data_l[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="68" tap_mode="classic" trigger_index="68" type="unknown"/> + <net data_index="67" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_init_w_data_l[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="67" tap_mode="classic" trigger_index="67" type="unknown"/> + <net data_index="66" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_init_w_data_l[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="66" tap_mode="classic" trigger_index="66" type="unknown"/> + <net data_index="65" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_init_w_data_l[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="65" tap_mode="classic" trigger_index="65" type="unknown"/> + <net data_index="64" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_init_w_data_l[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="64" tap_mode="classic" trigger_index="64" type="unknown"/> + <net data_index="63" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_init_w_data_l[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="63" tap_mode="classic" trigger_index="63" type="unknown"/> + <net data_index="62" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_init_w_data_l[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="62" tap_mode="classic" trigger_index="62" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="controller:controller_0|mdio_mux_sel[1..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="71" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_mux_sel[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="71" tap_mode="classic" trigger_index="71" type="unknown"/> + <net data_index="70" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_mux_sel[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="70" tap_mode="classic" trigger_index="70" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="controller:controller_0|mdio_phy_addr[4..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="76" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_phy_addr[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="76" tap_mode="classic" trigger_index="76" type="unknown"/> + <net data_index="75" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_phy_addr[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="75" tap_mode="classic" trigger_index="75" type="unknown"/> + <net data_index="74" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_phy_addr[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="74" tap_mode="classic" trigger_index="74" type="unknown"/> + <net data_index="73" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_phy_addr[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="73" tap_mode="classic" trigger_index="73" type="unknown"/> + <net data_index="72" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_phy_addr[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="72" tap_mode="classic" trigger_index="72" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="controller:controller_0|mdio_reg_addr[4..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="81" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_reg_addr[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="81" tap_mode="classic" trigger_index="81" type="unknown"/> + <net data_index="80" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_reg_addr[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="80" tap_mode="classic" trigger_index="80" type="unknown"/> + <net data_index="79" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_reg_addr[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="79" tap_mode="classic" trigger_index="79" type="unknown"/> + <net data_index="78" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_reg_addr[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="78" tap_mode="classic" trigger_index="78" type="unknown"/> + <net data_index="77" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_reg_addr[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="77" tap_mode="classic" trigger_index="77" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="controller:controller_0|mdio_routine_addr[6..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="88" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_routine_addr[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="88" tap_mode="classic" trigger_index="88" type="unknown"/> + <net data_index="87" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_routine_addr[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="87" tap_mode="classic" trigger_index="87" type="unknown"/> + <net data_index="86" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_routine_addr[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="86" tap_mode="classic" trigger_index="86" type="unknown"/> + <net data_index="85" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_routine_addr[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="85" tap_mode="classic" trigger_index="85" type="unknown"/> + <net data_index="84" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_routine_addr[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="84" tap_mode="classic" trigger_index="84" type="unknown"/> + <net data_index="83" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_routine_addr[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="83" tap_mode="classic" trigger_index="83" type="unknown"/> + <net data_index="82" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_routine_addr[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="82" tap_mode="classic" trigger_index="82" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="controller:controller_0|mdio_w_data_h[7..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="97" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_w_data_h[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="97" tap_mode="classic" trigger_index="97" type="unknown"/> + <net data_index="96" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_w_data_h[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="96" tap_mode="classic" trigger_index="96" type="unknown"/> + <net data_index="95" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_w_data_h[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="95" tap_mode="classic" trigger_index="95" type="unknown"/> + <net data_index="94" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_w_data_h[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="94" tap_mode="classic" trigger_index="94" type="unknown"/> + <net data_index="93" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_w_data_h[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="93" tap_mode="classic" trigger_index="93" type="unknown"/> + <net data_index="92" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_w_data_h[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="92" tap_mode="classic" trigger_index="92" type="unknown"/> + <net data_index="91" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_w_data_h[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="91" tap_mode="classic" trigger_index="91" type="unknown"/> + <net data_index="90" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_w_data_h[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="90" tap_mode="classic" trigger_index="90" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="controller:controller_0|mdio_w_data_l[7..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="105" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_w_data_l[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="105" tap_mode="classic" trigger_index="105" type="unknown"/> + <net data_index="104" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_w_data_l[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="104" tap_mode="classic" trigger_index="104" type="unknown"/> + <net data_index="103" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_w_data_l[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="103" tap_mode="classic" trigger_index="103" type="unknown"/> + <net data_index="102" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_w_data_l[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="102" tap_mode="classic" trigger_index="102" type="unknown"/> + <net data_index="101" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_w_data_l[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="101" tap_mode="classic" trigger_index="101" type="unknown"/> + <net data_index="100" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_w_data_l[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="100" tap_mode="classic" trigger_index="100" type="unknown"/> + <net data_index="99" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_w_data_l[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="99" tap_mode="classic" trigger_index="99" type="unknown"/> + <net data_index="98" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_w_data_l[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="98" tap_mode="classic" trigger_index="98" type="unknown"/> + </bus> + </data_view> + <setup_view> + <net data_index="0" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|clk" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="0" tap_mode="classic" trigger_index="0" type="unknown"/> + <net data_index="5" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|cont_state.CONT_ST_START" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="5" tap_mode="classic" trigger_index="5" type="unknown"/> + <net data_index="4" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|cont_state.CONT_ST_INIT" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="4" tap_mode="classic" trigger_index="4" type="unknown"/> + <net data_index="3" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|cont_state.CONT_ST_IDLE" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="3" tap_mode="classic" trigger_index="3" type="unknown"/> + <net data_index="1" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|cont_state.CONT_ST_BUSY" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="1" tap_mode="classic" trigger_index="1" type="unknown"/> + <net data_index="2" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|cont_state.CONT_ST_DONE" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="2" tap_mode="classic" trigger_index="2" type="unknown"/> + <net data_index="258" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_fifo_int" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="258" tap_mode="classic" trigger_index="258" type="unknown"/> + <net data_index="259" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_fifo_int_acked" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="259" tap_mode="classic" trigger_index="259" type="unknown"/> + <net data_index="260" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="high" name="controller:controller_0|rx_msg_captured" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="260" tap_mode="classic" trigger_index="260" type="unknown"/> + <bus is_selected="false" level-0="alt_or" level-1="alt_or" name="controller:controller_0|rx_wr_ptr[10..0]" order="msb_to_lsb" radix="hex" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="289" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_wr_ptr[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="289" tap_mode="classic" trigger_index="289" type="unknown"/> + <net data_index="298" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_wr_ptr[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="298" tap_mode="classic" trigger_index="298" type="unknown"/> + <net data_index="297" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_wr_ptr[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="297" tap_mode="classic" trigger_index="297" type="unknown"/> + <net data_index="296" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_wr_ptr[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="296" tap_mode="classic" trigger_index="296" type="unknown"/> + <net data_index="295" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_wr_ptr[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="295" tap_mode="classic" trigger_index="295" type="unknown"/> + <net data_index="294" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_wr_ptr[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="294" tap_mode="classic" trigger_index="294" type="unknown"/> + <net data_index="293" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_wr_ptr[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="293" tap_mode="classic" trigger_index="293" type="unknown"/> + <net data_index="292" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_wr_ptr[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="292" tap_mode="classic" trigger_index="292" type="unknown"/> + <net data_index="291" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_wr_ptr[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="291" tap_mode="classic" trigger_index="291" type="unknown"/> + <net data_index="290" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_wr_ptr[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="290" tap_mode="classic" trigger_index="290" type="unknown"/> + <net data_index="288" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_wr_ptr[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="288" tap_mode="classic" trigger_index="288" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" level-1="alt_or" name="controller:controller_0|rx_rd_ptr[10..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="278" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_rd_ptr[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="278" tap_mode="classic" trigger_index="278" type="unknown"/> + <net data_index="287" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_rd_ptr[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="287" tap_mode="classic" trigger_index="287" type="unknown"/> + <net data_index="286" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_rd_ptr[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="286" tap_mode="classic" trigger_index="286" type="unknown"/> + <net data_index="285" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_rd_ptr[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="285" tap_mode="classic" trigger_index="285" type="unknown"/> + <net data_index="284" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_rd_ptr[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="284" tap_mode="classic" trigger_index="284" type="unknown"/> + <net data_index="283" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_rd_ptr[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="283" tap_mode="classic" trigger_index="283" type="unknown"/> + <net data_index="282" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_rd_ptr[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="282" tap_mode="classic" trigger_index="282" type="unknown"/> + <net data_index="281" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_rd_ptr[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="281" tap_mode="classic" trigger_index="281" type="unknown"/> + <net data_index="280" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_rd_ptr[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="280" tap_mode="classic" trigger_index="280" type="unknown"/> + <net data_index="279" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_rd_ptr[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="279" tap_mode="classic" trigger_index="279" type="unknown"/> + <net data_index="277" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_rd_ptr[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="277" tap_mode="classic" trigger_index="277" type="unknown"/> + </bus> + <net data_index="6" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|hf_ptrs_sel" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="6" tap_mode="classic" trigger_index="6" type="unknown"/> + <net data_index="7" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|hf_rx_sel" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="7" tap_mode="classic" trigger_index="7" type="unknown"/> + <net data_index="8" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|hf_tx_sel" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="8" tap_mode="classic" trigger_index="8" type="unknown"/> + <bus is_selected="false" level-0="alt_or" level-1="alt_or" name="controller:controller_0|mem_state[3..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="153" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_state[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="153" tap_mode="classic" trigger_index="153" type="unknown"/> + <net data_index="152" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_state[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="152" tap_mode="classic" trigger_index="152" type="unknown"/> + <net data_index="151" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_state[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="151" tap_mode="classic" trigger_index="151" type="unknown"/> + <net data_index="150" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_state[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="150" tap_mode="classic" trigger_index="150" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" level-1="alt_or" name="controller:controller_0|mem_addr[10..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="108" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_addr[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="108" tap_mode="classic" trigger_index="108" type="unknown"/> + <net data_index="117" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_addr[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="117" tap_mode="classic" trigger_index="117" type="unknown"/> + <net data_index="116" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_addr[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="116" tap_mode="classic" trigger_index="116" type="unknown"/> + <net data_index="115" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_addr[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="115" tap_mode="classic" trigger_index="115" type="unknown"/> + <net data_index="114" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_addr[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="114" tap_mode="classic" trigger_index="114" type="unknown"/> + <net data_index="113" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_addr[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="113" tap_mode="classic" trigger_index="113" type="unknown"/> + <net data_index="112" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_addr[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="112" tap_mode="classic" trigger_index="112" type="unknown"/> + <net data_index="111" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_addr[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="111" tap_mode="classic" trigger_index="111" type="unknown"/> + <net data_index="110" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_addr[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="110" tap_mode="classic" trigger_index="110" type="unknown"/> + <net data_index="109" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_addr[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="109" tap_mode="classic" trigger_index="109" type="unknown"/> + <net data_index="107" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_addr[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="107" tap_mode="classic" trigger_index="107" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" level-1="alt_or" name="controller:controller_0|mem_d_i[31..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="142" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_d_i[31]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="142" tap_mode="classic" trigger_index="142" type="unknown"/> + <net data_index="141" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_d_i[30]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="141" tap_mode="classic" trigger_index="141" type="unknown"/> + <net data_index="139" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_d_i[29]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="139" tap_mode="classic" trigger_index="139" type="unknown"/> + <net data_index="138" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_d_i[28]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="138" tap_mode="classic" trigger_index="138" type="unknown"/> + <net data_index="137" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_d_i[27]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="137" tap_mode="classic" trigger_index="137" type="unknown"/> + <net data_index="136" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_d_i[26]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="136" tap_mode="classic" trigger_index="136" type="unknown"/> + <net data_index="135" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_d_i[25]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="135" tap_mode="classic" trigger_index="135" type="unknown"/> + <net data_index="134" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_d_i[24]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="134" tap_mode="classic" trigger_index="134" type="unknown"/> + <net data_index="133" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_d_i[23]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="133" tap_mode="classic" trigger_index="133" type="unknown"/> + <net data_index="132" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_d_i[22]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="132" tap_mode="classic" trigger_index="132" type="unknown"/> + <net data_index="131" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_d_i[21]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="131" tap_mode="classic" trigger_index="131" type="unknown"/> + <net data_index="130" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_d_i[20]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="130" tap_mode="classic" trigger_index="130" type="unknown"/> + <net data_index="128" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_d_i[19]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="128" tap_mode="classic" trigger_index="128" type="unknown"/> + <net data_index="127" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_d_i[18]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="127" tap_mode="classic" trigger_index="127" type="unknown"/> + <net data_index="126" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_d_i[17]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="126" tap_mode="classic" trigger_index="126" type="unknown"/> + <net data_index="125" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_d_i[16]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="125" tap_mode="classic" trigger_index="125" type="unknown"/> + <net data_index="124" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_d_i[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="124" tap_mode="classic" trigger_index="124" type="unknown"/> + <net data_index="123" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_d_i[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="123" tap_mode="classic" trigger_index="123" type="unknown"/> + <net data_index="122" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_d_i[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="122" tap_mode="classic" trigger_index="122" type="unknown"/> + <net data_index="121" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_d_i[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="121" tap_mode="classic" trigger_index="121" type="unknown"/> + <net data_index="120" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_d_i[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="120" tap_mode="classic" trigger_index="120" type="unknown"/> + <net data_index="119" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_d_i[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="119" tap_mode="classic" trigger_index="119" type="unknown"/> + <net data_index="149" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_d_i[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="149" tap_mode="classic" trigger_index="149" type="unknown"/> + <net data_index="148" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_d_i[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="148" tap_mode="classic" trigger_index="148" type="unknown"/> + <net data_index="147" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_d_i[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="147" tap_mode="classic" trigger_index="147" type="unknown"/> + <net data_index="146" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_d_i[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="146" tap_mode="classic" trigger_index="146" type="unknown"/> + <net data_index="145" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_d_i[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="145" tap_mode="classic" trigger_index="145" type="unknown"/> + <net data_index="144" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_d_i[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="144" tap_mode="classic" trigger_index="144" type="unknown"/> + <net data_index="143" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_d_i[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="143" tap_mode="classic" trigger_index="143" type="unknown"/> + <net data_index="140" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_d_i[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="140" tap_mode="classic" trigger_index="140" type="unknown"/> + <net data_index="129" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_d_i[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="129" tap_mode="classic" trigger_index="129" type="unknown"/> + <net data_index="118" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mem_d_i[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="118" tap_mode="classic" trigger_index="118" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" level-1="alt_or" name="controller:controller_0|rx_cnt[4..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="257" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_cnt[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="257" tap_mode="classic" trigger_index="257" type="unknown"/> + <net data_index="256" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_cnt[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="256" tap_mode="classic" trigger_index="256" type="unknown"/> + <net data_index="255" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_cnt[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="255" tap_mode="classic" trigger_index="255" type="unknown"/> + <net data_index="254" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_cnt[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="254" tap_mode="classic" trigger_index="254" type="unknown"/> + <net data_index="253" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_cnt[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="253" tap_mode="classic" trigger_index="253" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="controller:controller_0|msg_type[7..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="252" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_type[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="252" tap_mode="classic" trigger_index="252" type="unknown"/> + <net data_index="251" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_type[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="251" tap_mode="classic" trigger_index="251" type="unknown"/> + <net data_index="250" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_type[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="250" tap_mode="classic" trigger_index="250" type="unknown"/> + <net data_index="249" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_type[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="249" tap_mode="classic" trigger_index="249" type="unknown"/> + <net data_index="248" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_type[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="248" tap_mode="classic" trigger_index="248" type="unknown"/> + <net data_index="247" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_type[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="247" tap_mode="classic" trigger_index="247" type="unknown"/> + <net data_index="246" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_type[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="246" tap_mode="classic" trigger_index="246" type="unknown"/> + <net data_index="245" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_type[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="245" tap_mode="classic" trigger_index="245" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="controller:controller_0|msg_token[7..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="244" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_token[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="244" tap_mode="classic" trigger_index="244" type="unknown"/> + <net data_index="243" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_token[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="243" tap_mode="classic" trigger_index="243" type="unknown"/> + <net data_index="242" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_token[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="242" tap_mode="classic" trigger_index="242" type="unknown"/> + <net data_index="241" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_token[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="241" tap_mode="classic" trigger_index="241" type="unknown"/> + <net data_index="240" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_token[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="240" tap_mode="classic" trigger_index="240" type="unknown"/> + <net data_index="239" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_token[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="239" tap_mode="classic" trigger_index="239" type="unknown"/> + <net data_index="238" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_token[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="238" tap_mode="classic" trigger_index="238" type="unknown"/> + <net data_index="237" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_token[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="237" tap_mode="classic" trigger_index="237" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="controller:controller_0|msg_addr[15..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="160" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="160" tap_mode="classic" trigger_index="160" type="unknown"/> + <net data_index="159" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="159" tap_mode="classic" trigger_index="159" type="unknown"/> + <net data_index="158" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="158" tap_mode="classic" trigger_index="158" type="unknown"/> + <net data_index="157" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="157" tap_mode="classic" trigger_index="157" type="unknown"/> + <net data_index="156" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="156" tap_mode="classic" trigger_index="156" type="unknown"/> + <net data_index="155" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="155" tap_mode="classic" trigger_index="155" type="unknown"/> + <net data_index="169" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="169" tap_mode="classic" trigger_index="169" type="unknown"/> + <net data_index="168" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="168" tap_mode="classic" trigger_index="168" type="unknown"/> + <net data_index="167" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="167" tap_mode="classic" trigger_index="167" type="unknown"/> + <net data_index="166" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="166" tap_mode="classic" trigger_index="166" type="unknown"/> + <net data_index="165" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="165" tap_mode="classic" trigger_index="165" type="unknown"/> + <net data_index="164" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="164" tap_mode="classic" trigger_index="164" type="unknown"/> + <net data_index="163" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="163" tap_mode="classic" trigger_index="163" type="unknown"/> + <net data_index="162" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="162" tap_mode="classic" trigger_index="162" type="unknown"/> + <net data_index="161" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="161" tap_mode="classic" trigger_index="161" type="unknown"/> + <net data_index="154" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="154" tap_mode="classic" trigger_index="154" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="controller:controller_0|msg_data[31..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="196" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[31]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="196" tap_mode="classic" trigger_index="196" type="unknown"/> + <net data_index="195" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[30]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="195" tap_mode="classic" trigger_index="195" type="unknown"/> + <net data_index="193" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[29]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="193" tap_mode="classic" trigger_index="193" type="unknown"/> + <net data_index="192" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[28]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="192" tap_mode="classic" trigger_index="192" type="unknown"/> + <net data_index="191" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[27]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="191" tap_mode="classic" trigger_index="191" type="unknown"/> + <net data_index="190" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[26]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="190" tap_mode="classic" trigger_index="190" type="unknown"/> + <net data_index="189" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[25]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="189" tap_mode="classic" trigger_index="189" type="unknown"/> + <net data_index="188" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[24]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="188" tap_mode="classic" trigger_index="188" type="unknown"/> + <net data_index="187" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[23]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="187" tap_mode="classic" trigger_index="187" type="unknown"/> + <net data_index="186" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[22]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="186" tap_mode="classic" trigger_index="186" type="unknown"/> + <net data_index="185" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[21]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="185" tap_mode="classic" trigger_index="185" type="unknown"/> + <net data_index="184" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[20]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="184" tap_mode="classic" trigger_index="184" type="unknown"/> + <net data_index="182" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[19]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="182" tap_mode="classic" trigger_index="182" type="unknown"/> + <net data_index="181" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[18]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="181" tap_mode="classic" trigger_index="181" type="unknown"/> + <net data_index="180" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[17]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="180" tap_mode="classic" trigger_index="180" type="unknown"/> + <net data_index="179" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[16]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="179" tap_mode="classic" trigger_index="179" type="unknown"/> + <net data_index="178" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="178" tap_mode="classic" trigger_index="178" type="unknown"/> + <net data_index="177" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="177" tap_mode="classic" trigger_index="177" type="unknown"/> + <net data_index="176" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="176" tap_mode="classic" trigger_index="176" type="unknown"/> + <net data_index="175" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="175" tap_mode="classic" trigger_index="175" type="unknown"/> + <net data_index="174" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="174" tap_mode="classic" trigger_index="174" type="unknown"/> + <net data_index="173" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="173" tap_mode="classic" trigger_index="173" type="unknown"/> + <net data_index="203" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="203" tap_mode="classic" trigger_index="203" type="unknown"/> + <net data_index="202" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="202" tap_mode="classic" trigger_index="202" type="unknown"/> + <net data_index="201" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="201" tap_mode="classic" trigger_index="201" type="unknown"/> + <net data_index="200" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="200" tap_mode="classic" trigger_index="200" type="unknown"/> + <net data_index="199" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="199" tap_mode="classic" trigger_index="199" type="unknown"/> + <net data_index="198" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="198" tap_mode="classic" trigger_index="198" type="unknown"/> + <net data_index="197" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="197" tap_mode="classic" trigger_index="197" type="unknown"/> + <net data_index="194" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="194" tap_mode="classic" trigger_index="194" type="unknown"/> + <net data_index="183" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="183" tap_mode="classic" trigger_index="183" type="unknown"/> + <net data_index="172" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="172" tap_mode="classic" trigger_index="172" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="controller:controller_0|msg_response[31..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="229" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[31]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="229" tap_mode="classic" trigger_index="229" type="unknown"/> + <net data_index="228" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[30]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="228" tap_mode="classic" trigger_index="228" type="unknown"/> + <net data_index="226" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[29]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="226" tap_mode="classic" trigger_index="226" type="unknown"/> + <net data_index="225" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[28]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="225" tap_mode="classic" trigger_index="225" type="unknown"/> + <net data_index="224" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[27]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="224" tap_mode="classic" trigger_index="224" type="unknown"/> + <net data_index="223" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[26]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="223" tap_mode="classic" trigger_index="223" type="unknown"/> + <net data_index="222" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[25]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="222" tap_mode="classic" trigger_index="222" type="unknown"/> + <net data_index="221" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[24]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="221" tap_mode="classic" trigger_index="221" type="unknown"/> + <net data_index="220" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[23]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="220" tap_mode="classic" trigger_index="220" type="unknown"/> + <net data_index="219" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[22]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="219" tap_mode="classic" trigger_index="219" type="unknown"/> + <net data_index="218" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[21]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="218" tap_mode="classic" trigger_index="218" type="unknown"/> + <net data_index="217" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[20]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="217" tap_mode="classic" trigger_index="217" type="unknown"/> + <net data_index="215" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[19]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="215" tap_mode="classic" trigger_index="215" type="unknown"/> + <net data_index="214" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[18]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="214" tap_mode="classic" trigger_index="214" type="unknown"/> + <net data_index="213" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[17]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="213" tap_mode="classic" trigger_index="213" type="unknown"/> + <net data_index="212" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[16]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="212" tap_mode="classic" trigger_index="212" type="unknown"/> + <net data_index="211" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="211" tap_mode="classic" trigger_index="211" type="unknown"/> + <net data_index="210" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="210" tap_mode="classic" trigger_index="210" type="unknown"/> + <net data_index="209" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="209" tap_mode="classic" trigger_index="209" type="unknown"/> + <net data_index="208" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="208" tap_mode="classic" trigger_index="208" type="unknown"/> + <net data_index="207" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="207" tap_mode="classic" trigger_index="207" type="unknown"/> + <net data_index="206" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="206" tap_mode="classic" trigger_index="206" type="unknown"/> + <net data_index="236" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="236" tap_mode="classic" trigger_index="236" type="unknown"/> + <net data_index="235" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="235" tap_mode="classic" trigger_index="235" type="unknown"/> + <net data_index="234" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="234" tap_mode="classic" trigger_index="234" type="unknown"/> + <net data_index="233" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="233" tap_mode="classic" trigger_index="233" type="unknown"/> + <net data_index="232" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="232" tap_mode="classic" trigger_index="232" type="unknown"/> + <net data_index="231" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="231" tap_mode="classic" trigger_index="231" type="unknown"/> + <net data_index="230" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="230" tap_mode="classic" trigger_index="230" type="unknown"/> + <net data_index="227" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="227" tap_mode="classic" trigger_index="227" type="unknown"/> + <net data_index="216" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="216" tap_mode="classic" trigger_index="216" type="unknown"/> + <net data_index="205" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="205" tap_mode="classic" trigger_index="205" type="unknown"/> + </bus> + <net data_index="171" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr_valid" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="171" tap_mode="classic" trigger_index="171" type="unknown"/> + <net data_index="170" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr_ro" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="170" tap_mode="classic" trigger_index="170" type="unknown"/> + <net data_index="204" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_error" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="204" tap_mode="classic" trigger_index="204" type="unknown"/> + <bus is_selected="false" level-0="alt_or" name="controller:controller_0|rx_msg_cnt[15..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="267" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_msg_cnt[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="267" tap_mode="classic" trigger_index="267" type="unknown"/> + <net data_index="266" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_msg_cnt[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="266" tap_mode="classic" trigger_index="266" type="unknown"/> + <net data_index="265" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_msg_cnt[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="265" tap_mode="classic" trigger_index="265" type="unknown"/> + <net data_index="264" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_msg_cnt[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="264" tap_mode="classic" trigger_index="264" type="unknown"/> + <net data_index="263" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_msg_cnt[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="263" tap_mode="classic" trigger_index="263" type="unknown"/> + <net data_index="262" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_msg_cnt[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="262" tap_mode="classic" trigger_index="262" type="unknown"/> + <net data_index="276" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_msg_cnt[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="276" tap_mode="classic" trigger_index="276" type="unknown"/> + <net data_index="275" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_msg_cnt[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="275" tap_mode="classic" trigger_index="275" type="unknown"/> + <net data_index="274" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_msg_cnt[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="274" tap_mode="classic" trigger_index="274" type="unknown"/> + <net data_index="273" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_msg_cnt[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="273" tap_mode="classic" trigger_index="273" type="unknown"/> + <net data_index="272" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_msg_cnt[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="272" tap_mode="classic" trigger_index="272" type="unknown"/> + <net data_index="271" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_msg_cnt[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="271" tap_mode="classic" trigger_index="271" type="unknown"/> + <net data_index="270" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_msg_cnt[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="270" tap_mode="classic" trigger_index="270" type="unknown"/> + <net data_index="269" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_msg_cnt[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="269" tap_mode="classic" trigger_index="269" type="unknown"/> + <net data_index="268" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_msg_cnt[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="268" tap_mode="classic" trigger_index="268" type="unknown"/> + <net data_index="261" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_msg_cnt[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="261" tap_mode="classic" trigger_index="261" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="controller:controller_0|tx_msg_cnt[15..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="305" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|tx_msg_cnt[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="305" tap_mode="classic" trigger_index="305" type="unknown"/> + <net data_index="304" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|tx_msg_cnt[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="304" tap_mode="classic" trigger_index="304" type="unknown"/> + <net data_index="303" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|tx_msg_cnt[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="303" tap_mode="classic" trigger_index="303" type="unknown"/> + <net data_index="302" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|tx_msg_cnt[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="302" tap_mode="classic" trigger_index="302" type="unknown"/> + <net data_index="301" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|tx_msg_cnt[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="301" tap_mode="classic" trigger_index="301" type="unknown"/> + <net data_index="300" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|tx_msg_cnt[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="300" tap_mode="classic" trigger_index="300" type="unknown"/> + <net data_index="314" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|tx_msg_cnt[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="314" tap_mode="classic" trigger_index="314" type="unknown"/> + <net data_index="313" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|tx_msg_cnt[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="313" tap_mode="classic" trigger_index="313" type="unknown"/> + <net data_index="312" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|tx_msg_cnt[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="312" tap_mode="classic" trigger_index="312" type="unknown"/> + <net data_index="311" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|tx_msg_cnt[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="311" tap_mode="classic" trigger_index="311" type="unknown"/> + <net data_index="310" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|tx_msg_cnt[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="310" tap_mode="classic" trigger_index="310" type="unknown"/> + <net data_index="309" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|tx_msg_cnt[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="309" tap_mode="classic" trigger_index="309" type="unknown"/> + <net data_index="308" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|tx_msg_cnt[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="308" tap_mode="classic" trigger_index="308" type="unknown"/> + <net data_index="307" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|tx_msg_cnt[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="307" tap_mode="classic" trigger_index="307" type="unknown"/> + <net data_index="306" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|tx_msg_cnt[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="306" tap_mode="classic" trigger_index="306" type="unknown"/> + <net data_index="299" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|tx_msg_cnt[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="299" tap_mode="classic" trigger_index="299" type="unknown"/> + </bus> + <net data_index="11" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mac_sel" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="11" tap_mode="classic" trigger_index="11" type="unknown"/> + <bus is_selected="false" level-0="alt_or" name="controller:controller_0|mac_addr[1..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="10" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mac_addr[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="10" tap_mode="classic" trigger_index="10" type="unknown"/> + <net data_index="9" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mac_addr[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="9" tap_mode="classic" trigger_index="9" type="unknown"/> + </bus> + <net data_index="12" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_cmd" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="12" tap_mode="classic" trigger_index="12" type="unknown"/> + <net data_index="13" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_cont_done" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="13" tap_mode="classic" trigger_index="13" type="unknown"/> + <net data_index="14" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_cont_start" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="14" tap_mode="classic" trigger_index="14" type="unknown"/> + <net data_index="89" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_run" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="89" tap_mode="classic" trigger_index="89" type="unknown"/> + <net data_index="106" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_we" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="106" tap_mode="classic" trigger_index="106" type="unknown"/> + <bus is_selected="false" level-0="alt_or" name="controller:controller_0|mdio_d[15..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="21" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_d[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="21" tap_mode="classic" trigger_index="21" type="unknown"/> + <net data_index="20" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_d[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="20" tap_mode="classic" trigger_index="20" type="unknown"/> + <net data_index="19" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_d[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="19" tap_mode="classic" trigger_index="19" type="unknown"/> + <net data_index="18" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_d[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="18" tap_mode="classic" trigger_index="18" type="unknown"/> + <net data_index="17" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_d[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="17" tap_mode="classic" trigger_index="17" type="unknown"/> + <net data_index="16" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_d[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="16" tap_mode="classic" trigger_index="16" type="unknown"/> + <net data_index="30" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_d[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="30" tap_mode="classic" trigger_index="30" type="unknown"/> + <net data_index="29" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_d[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="29" tap_mode="classic" trigger_index="29" type="unknown"/> + <net data_index="28" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_d[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="28" tap_mode="classic" trigger_index="28" type="unknown"/> + <net data_index="27" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_d[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="27" tap_mode="classic" trigger_index="27" type="unknown"/> + <net data_index="26" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_d[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="26" tap_mode="classic" trigger_index="26" type="unknown"/> + <net data_index="25" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_d[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="25" tap_mode="classic" trigger_index="25" type="unknown"/> + <net data_index="24" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_d[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="24" tap_mode="classic" trigger_index="24" type="unknown"/> + <net data_index="23" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_d[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="23" tap_mode="classic" trigger_index="23" type="unknown"/> + <net data_index="22" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_d[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="22" tap_mode="classic" trigger_index="22" type="unknown"/> + <net data_index="15" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_d[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="15" tap_mode="classic" trigger_index="15" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="controller:controller_0|mdio_d_i[15..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="37" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_d_i[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="37" tap_mode="classic" trigger_index="37" type="unknown"/> + <net data_index="36" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_d_i[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="36" tap_mode="classic" trigger_index="36" type="unknown"/> + <net data_index="35" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_d_i[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="35" tap_mode="classic" trigger_index="35" type="unknown"/> + <net data_index="34" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_d_i[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="34" tap_mode="classic" trigger_index="34" type="unknown"/> + <net data_index="33" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_d_i[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="33" tap_mode="classic" trigger_index="33" type="unknown"/> + <net data_index="32" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_d_i[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="32" tap_mode="classic" trigger_index="32" type="unknown"/> + <net data_index="46" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_d_i[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="46" tap_mode="classic" trigger_index="46" type="unknown"/> + <net data_index="45" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_d_i[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="45" tap_mode="classic" trigger_index="45" type="unknown"/> + <net data_index="44" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_d_i[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="44" tap_mode="classic" trigger_index="44" type="unknown"/> + <net data_index="43" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_d_i[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="43" tap_mode="classic" trigger_index="43" type="unknown"/> + <net data_index="42" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_d_i[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="42" tap_mode="classic" trigger_index="42" type="unknown"/> + <net data_index="41" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_d_i[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="41" tap_mode="classic" trigger_index="41" type="unknown"/> + <net data_index="40" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_d_i[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="40" tap_mode="classic" trigger_index="40" type="unknown"/> + <net data_index="39" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_d_i[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="39" tap_mode="classic" trigger_index="39" type="unknown"/> + <net data_index="38" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_d_i[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="38" tap_mode="classic" trigger_index="38" type="unknown"/> + <net data_index="31" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_d_i[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="31" tap_mode="classic" trigger_index="31" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="controller:controller_0|mdio_init_routine_addr[6..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="53" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_init_routine_addr[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="53" tap_mode="classic" trigger_index="53" type="unknown"/> + <net data_index="52" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_init_routine_addr[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="52" tap_mode="classic" trigger_index="52" type="unknown"/> + <net data_index="51" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_init_routine_addr[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="51" tap_mode="classic" trigger_index="51" type="unknown"/> + <net data_index="50" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_init_routine_addr[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="50" tap_mode="classic" trigger_index="50" type="unknown"/> + <net data_index="49" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_init_routine_addr[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="49" tap_mode="classic" trigger_index="49" type="unknown"/> + <net data_index="48" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_init_routine_addr[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="48" tap_mode="classic" trigger_index="48" type="unknown"/> + <net data_index="47" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_init_routine_addr[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="47" tap_mode="classic" trigger_index="47" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="controller:controller_0|mdio_init_w_data_h[7..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="61" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_init_w_data_h[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="61" tap_mode="classic" trigger_index="61" type="unknown"/> + <net data_index="60" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_init_w_data_h[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="60" tap_mode="classic" trigger_index="60" type="unknown"/> + <net data_index="59" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_init_w_data_h[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="59" tap_mode="classic" trigger_index="59" type="unknown"/> + <net data_index="58" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_init_w_data_h[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="58" tap_mode="classic" trigger_index="58" type="unknown"/> + <net data_index="57" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_init_w_data_h[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="57" tap_mode="classic" trigger_index="57" type="unknown"/> + <net data_index="56" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_init_w_data_h[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="56" tap_mode="classic" trigger_index="56" type="unknown"/> + <net data_index="55" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_init_w_data_h[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="55" tap_mode="classic" trigger_index="55" type="unknown"/> + <net data_index="54" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_init_w_data_h[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="54" tap_mode="classic" trigger_index="54" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="controller:controller_0|mdio_init_w_data_l[7..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="69" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_init_w_data_l[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="69" tap_mode="classic" trigger_index="69" type="unknown"/> + <net data_index="68" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_init_w_data_l[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="68" tap_mode="classic" trigger_index="68" type="unknown"/> + <net data_index="67" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_init_w_data_l[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="67" tap_mode="classic" trigger_index="67" type="unknown"/> + <net data_index="66" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_init_w_data_l[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="66" tap_mode="classic" trigger_index="66" type="unknown"/> + <net data_index="65" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_init_w_data_l[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="65" tap_mode="classic" trigger_index="65" type="unknown"/> + <net data_index="64" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_init_w_data_l[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="64" tap_mode="classic" trigger_index="64" type="unknown"/> + <net data_index="63" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_init_w_data_l[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="63" tap_mode="classic" trigger_index="63" type="unknown"/> + <net data_index="62" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_init_w_data_l[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="62" tap_mode="classic" trigger_index="62" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="controller:controller_0|mdio_mux_sel[1..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="71" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_mux_sel[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="71" tap_mode="classic" trigger_index="71" type="unknown"/> + <net data_index="70" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_mux_sel[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="70" tap_mode="classic" trigger_index="70" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="controller:controller_0|mdio_phy_addr[4..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="76" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_phy_addr[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="76" tap_mode="classic" trigger_index="76" type="unknown"/> + <net data_index="75" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_phy_addr[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="75" tap_mode="classic" trigger_index="75" type="unknown"/> + <net data_index="74" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_phy_addr[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="74" tap_mode="classic" trigger_index="74" type="unknown"/> + <net data_index="73" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_phy_addr[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="73" tap_mode="classic" trigger_index="73" type="unknown"/> + <net data_index="72" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_phy_addr[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="72" tap_mode="classic" trigger_index="72" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="controller:controller_0|mdio_reg_addr[4..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="81" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_reg_addr[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="81" tap_mode="classic" trigger_index="81" type="unknown"/> + <net data_index="80" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_reg_addr[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="80" tap_mode="classic" trigger_index="80" type="unknown"/> + <net data_index="79" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_reg_addr[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="79" tap_mode="classic" trigger_index="79" type="unknown"/> + <net data_index="78" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_reg_addr[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="78" tap_mode="classic" trigger_index="78" type="unknown"/> + <net data_index="77" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_reg_addr[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="77" tap_mode="classic" trigger_index="77" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="controller:controller_0|mdio_routine_addr[6..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="88" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_routine_addr[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="88" tap_mode="classic" trigger_index="88" type="unknown"/> + <net data_index="87" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_routine_addr[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="87" tap_mode="classic" trigger_index="87" type="unknown"/> + <net data_index="86" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_routine_addr[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="86" tap_mode="classic" trigger_index="86" type="unknown"/> + <net data_index="85" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_routine_addr[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="85" tap_mode="classic" trigger_index="85" type="unknown"/> + <net data_index="84" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_routine_addr[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="84" tap_mode="classic" trigger_index="84" type="unknown"/> + <net data_index="83" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_routine_addr[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="83" tap_mode="classic" trigger_index="83" type="unknown"/> + <net data_index="82" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_routine_addr[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="82" tap_mode="classic" trigger_index="82" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="controller:controller_0|mdio_w_data_h[7..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="97" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_w_data_h[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="97" tap_mode="classic" trigger_index="97" type="unknown"/> + <net data_index="96" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_w_data_h[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="96" tap_mode="classic" trigger_index="96" type="unknown"/> + <net data_index="95" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_w_data_h[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="95" tap_mode="classic" trigger_index="95" type="unknown"/> + <net data_index="94" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_w_data_h[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="94" tap_mode="classic" trigger_index="94" type="unknown"/> + <net data_index="93" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_w_data_h[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="93" tap_mode="classic" trigger_index="93" type="unknown"/> + <net data_index="92" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_w_data_h[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="92" tap_mode="classic" trigger_index="92" type="unknown"/> + <net data_index="91" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_w_data_h[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="91" tap_mode="classic" trigger_index="91" type="unknown"/> + <net data_index="90" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_w_data_h[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="90" tap_mode="classic" trigger_index="90" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="controller:controller_0|mdio_w_data_l[7..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="105" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_w_data_l[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="105" tap_mode="classic" trigger_index="105" type="unknown"/> + <net data_index="104" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_w_data_l[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="104" tap_mode="classic" trigger_index="104" type="unknown"/> + <net data_index="103" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_w_data_l[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="103" tap_mode="classic" trigger_index="103" type="unknown"/> + <net data_index="102" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_w_data_l[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="102" tap_mode="classic" trigger_index="102" type="unknown"/> + <net data_index="101" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_w_data_l[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="101" tap_mode="classic" trigger_index="101" type="unknown"/> + <net data_index="100" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_w_data_l[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="100" tap_mode="classic" trigger_index="100" type="unknown"/> + <net data_index="99" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_w_data_l[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="99" tap_mode="classic" trigger_index="99" type="unknown"/> + <net data_index="98" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|mdio_w_data_l[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="98" tap_mode="classic" trigger_index="98" type="unknown"/> + </bus> + </setup_view> + <trigger_in_editor/> + <trigger_out_editor/> + </presentation> + <trigger attribute_mem_mode="false" gap_record="true" global_temp="1" is_expanded="true" name="trigger: 2025/11/23 22:55:59 #1" position="center" power_up_trigger_mode="false" record_data_gap="true" segment_size="64" storage_mode="off" storage_qualifier_disabled="no" storage_qualifier_port_is_pin="false" storage_qualifier_port_name="auto_stp_external_storage_qualifier" storage_qualifier_port_tap_mode="classic" trigger_type="circular"> + <power_up_trigger position="pre" storage_qualifier_disabled="no"/> + <events use_custom_flow_control="no"> + <level enabled="yes" name="condition1" type="basic">'controller:controller_0|rx_msg_captured' == high + <power_up enabled="yes"> + </power_up><op_node/> + </level> + </events> + <storage_qualifier_events> + <transitional>111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 + <pwr_up_transitional>111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111</pwr_up_transitional> + </transitional> + <storage_qualifier_level type="basic"> + <power_up> + </power_up> + <op_node/> + </storage_qualifier_level> + <storage_qualifier_level type="basic"> + <power_up> + </power_up> + <op_node/> + </storage_qualifier_level> + <storage_qualifier_level type="basic"> + <power_up> + </power_up> + <op_node/> + </storage_qualifier_level> + </storage_qualifier_events> + </trigger> + </signal_set> + <position_info> + <single attribute="active tab" value="1"/> + <single attribute="data horizontal scroll position" value="0"/> + <single attribute="data vertical scroll position" value="29"/> + <single attribute="setup horizontal scroll position" value="0"/> + <single attribute="setup vertical scroll position" value="23"/> + <single attribute="zoom level denominator" value="1"/> + <single attribute="zoom level numerator" value="1"/> + <single attribute="zoom offset denominator" value="1"/> + <single attribute="zoom offset numerator" value="130048"/> + </position_info> + </instance> + <instance enabled="false" entity_name="sld_signaltap" is_auto_node="yes" is_expanded="true" name="tst_mac0" source_file="sld_signaltap.vhd"> + <node_ip_info instance_id="7" mfg_id="110" node_id="0" version="6"/> + <signal_set global_temp="1" is_expanded="true" name="signal_set: 2025/09/22 23:01:50 #0"> + <clock name="mac_rgmii:mac_0|rx_clk" polarity="posedge" tap_mode="classic"/> + <config pipeline_level="0" ram_type="AUTO" reserved_data_nodes="0" reserved_storage_qualifier_nodes="0" reserved_trigger_nodes="0" sample_depth="512" trigger_in_enable="no" trigger_out_enable="no"/> + <top_entity/> + <signal_vec> + <trigger_input_vec> + <wire name="mac_rgmii:mac_0|rx_byte_cnt[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_byte_cnt[10]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_byte_cnt[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_byte_cnt[2]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_byte_cnt[3]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_byte_cnt[4]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_byte_cnt[5]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_byte_cnt[6]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_byte_cnt[7]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_byte_cnt[8]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_byte_cnt[9]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_ctl[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_ctl[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_ctl_m1[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_ctl_m1[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d[2]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d[3]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d[4]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d[5]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d[6]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d[7]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m1[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m1[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m1[2]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m1[3]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m1[4]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m1[5]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m1[6]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m1[7]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_eop" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_error" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_fifo_d[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_fifo_d[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_fifo_d[2]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_fifo_d[3]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_fifo_d[4]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_fifo_d[5]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_fifo_d[6]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_fifo_d[7]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_fifo_d[8]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_fifo_we" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_keep" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_cnt[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_cnt[10]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_cnt[11]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_cnt[12]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_cnt[13]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_cnt[14]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_cnt[15]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_cnt[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_cnt[2]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_cnt[3]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_cnt[4]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_cnt[5]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_cnt[6]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_cnt[7]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_cnt[8]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_cnt[9]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[10]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[11]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[2]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[3]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[4]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[5]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[6]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[7]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[8]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[9]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_sop" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_state[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_state[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_state[2]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_state[3]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_wr_done" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|tx_pkt_cnt[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|tx_pkt_cnt[10]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|tx_pkt_cnt[11]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|tx_pkt_cnt[12]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|tx_pkt_cnt[13]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|tx_pkt_cnt[14]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|tx_pkt_cnt[15]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|tx_pkt_cnt[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|tx_pkt_cnt[2]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|tx_pkt_cnt[3]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|tx_pkt_cnt[4]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|tx_pkt_cnt[5]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|tx_pkt_cnt[6]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|tx_pkt_cnt[7]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|tx_pkt_cnt[8]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|tx_pkt_cnt[9]" tap_mode="classic"/> + </trigger_input_vec> + <data_input_vec> + <wire name="mac_rgmii:mac_0|rx_byte_cnt[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_byte_cnt[10]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_byte_cnt[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_byte_cnt[2]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_byte_cnt[3]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_byte_cnt[4]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_byte_cnt[5]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_byte_cnt[6]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_byte_cnt[7]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_byte_cnt[8]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_byte_cnt[9]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_ctl[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_ctl[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_ctl_m1[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_ctl_m1[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d[2]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d[3]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d[4]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d[5]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d[6]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d[7]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m1[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m1[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m1[2]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m1[3]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m1[4]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m1[5]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m1[6]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m1[7]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_eop" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_error" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_fifo_d[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_fifo_d[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_fifo_d[2]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_fifo_d[3]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_fifo_d[4]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_fifo_d[5]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_fifo_d[6]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_fifo_d[7]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_fifo_d[8]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_fifo_we" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_keep" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_cnt[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_cnt[10]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_cnt[11]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_cnt[12]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_cnt[13]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_cnt[14]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_cnt[15]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_cnt[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_cnt[2]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_cnt[3]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_cnt[4]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_cnt[5]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_cnt[6]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_cnt[7]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_cnt[8]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_cnt[9]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[10]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[11]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[2]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[3]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[4]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[5]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[6]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[7]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[8]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[9]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_sop" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_state[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_state[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_state[2]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_state[3]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_wr_done" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|tx_pkt_cnt[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|tx_pkt_cnt[10]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|tx_pkt_cnt[11]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|tx_pkt_cnt[12]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|tx_pkt_cnt[13]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|tx_pkt_cnt[14]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|tx_pkt_cnt[15]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|tx_pkt_cnt[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|tx_pkt_cnt[2]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|tx_pkt_cnt[3]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|tx_pkt_cnt[4]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|tx_pkt_cnt[5]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|tx_pkt_cnt[6]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|tx_pkt_cnt[7]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|tx_pkt_cnt[8]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|tx_pkt_cnt[9]" tap_mode="classic"/> + </data_input_vec> + <storage_qualifier_input_vec> + <wire name="mac_rgmii:mac_0|rx_byte_cnt[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_byte_cnt[10]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_byte_cnt[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_byte_cnt[2]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_byte_cnt[3]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_byte_cnt[4]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_byte_cnt[5]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_byte_cnt[6]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_byte_cnt[7]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_byte_cnt[8]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_byte_cnt[9]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_ctl[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_ctl[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_ctl_m1[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_ctl_m1[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d[2]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d[3]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d[4]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d[5]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d[6]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d[7]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m1[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m1[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m1[2]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m1[3]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m1[4]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m1[5]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m1[6]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_d_m1[7]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_eop" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_error" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_fifo_d[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_fifo_d[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_fifo_d[2]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_fifo_d[3]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_fifo_d[4]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_fifo_d[5]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_fifo_d[6]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_fifo_d[7]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_fifo_d[8]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_fifo_we" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_keep" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_cnt[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_cnt[10]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_cnt[11]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_cnt[12]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_cnt[13]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_cnt[14]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_cnt[15]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_cnt[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_cnt[2]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_cnt[3]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_cnt[4]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_cnt[5]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_cnt[6]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_cnt[7]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_cnt[8]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_cnt[9]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[10]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[11]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[2]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[3]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[4]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[5]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[6]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[7]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[8]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_pkt_length[9]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_sop" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_state[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_state[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_state[2]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_state[3]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_wr_done" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|tx_pkt_cnt[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|tx_pkt_cnt[10]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|tx_pkt_cnt[11]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|tx_pkt_cnt[12]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|tx_pkt_cnt[13]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|tx_pkt_cnt[14]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|tx_pkt_cnt[15]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|tx_pkt_cnt[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|tx_pkt_cnt[2]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|tx_pkt_cnt[3]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|tx_pkt_cnt[4]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|tx_pkt_cnt[5]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|tx_pkt_cnt[6]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|tx_pkt_cnt[7]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|tx_pkt_cnt[8]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|tx_pkt_cnt[9]" tap_mode="classic"/> + </storage_qualifier_input_vec> + </signal_vec> + <presentation> + <unified_setup_data_view> + <node data_index="72" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="high" name="mac_rgmii:mac_0|rx_sop" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="72" tap_mode="classic" trigger_index="72" type="unknown"/> + <node data_index="31" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_eop" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="31" tap_mode="classic" trigger_index="31" type="unknown"/> + <node is_selected="false" level-0="alt_or" name="mac_rgmii:mac_0|rx_state[3..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <node data_index="76" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_state[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="76" tap_mode="classic" trigger_index="76" type="unknown"/> + <node data_index="75" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_state[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="75" tap_mode="classic" trigger_index="75" type="unknown"/> + <node data_index="74" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_state[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="74" tap_mode="classic" trigger_index="74" type="unknown"/> + <node data_index="73" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_state[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="73" tap_mode="classic" trigger_index="73" type="unknown"/> + </node> + <node data_index="32" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_error" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="32" tap_mode="classic" trigger_index="32" type="unknown"/> + <node is_selected="false" level-0="alt_or" name="mac_rgmii:mac_0|rx_pkt_length[11..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <node data_index="62" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_length[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="62" tap_mode="classic" trigger_index="62" type="unknown"/> + <node data_index="61" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_length[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="61" tap_mode="classic" trigger_index="61" type="unknown"/> + <node data_index="71" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_length[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="71" tap_mode="classic" trigger_index="71" type="unknown"/> + <node data_index="70" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_length[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="70" tap_mode="classic" trigger_index="70" type="unknown"/> + <node data_index="69" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_length[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="69" tap_mode="classic" trigger_index="69" type="unknown"/> + <node data_index="68" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_length[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="68" tap_mode="classic" trigger_index="68" type="unknown"/> + <node data_index="67" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_length[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="67" tap_mode="classic" trigger_index="67" type="unknown"/> + <node data_index="66" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_length[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="66" tap_mode="classic" trigger_index="66" type="unknown"/> + <node data_index="65" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_length[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="65" tap_mode="classic" trigger_index="65" type="unknown"/> + <node data_index="64" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_length[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="64" tap_mode="classic" trigger_index="64" type="unknown"/> + <node data_index="63" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_length[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="63" tap_mode="classic" trigger_index="63" type="unknown"/> + <node data_index="60" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_length[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="60" tap_mode="classic" trigger_index="60" type="unknown"/> + </node> + <node is_selected="false" level-0="alt_or" name="mac_rgmii:mac_0|rx_byte_cnt[10..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <node data_index="1" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_byte_cnt[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="1" tap_mode="classic" trigger_index="1" type="unknown"/> + <node data_index="10" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_byte_cnt[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="10" tap_mode="classic" trigger_index="10" type="unknown"/> + <node data_index="9" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_byte_cnt[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="9" tap_mode="classic" trigger_index="9" type="unknown"/> + <node data_index="8" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_byte_cnt[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="8" tap_mode="classic" trigger_index="8" type="unknown"/> + <node data_index="7" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_byte_cnt[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="7" tap_mode="classic" trigger_index="7" type="unknown"/> + <node data_index="6" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_byte_cnt[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="6" tap_mode="classic" trigger_index="6" type="unknown"/> + <node data_index="5" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_byte_cnt[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="5" tap_mode="classic" trigger_index="5" type="unknown"/> + <node data_index="4" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_byte_cnt[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="4" tap_mode="classic" trigger_index="4" type="unknown"/> + <node data_index="3" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_byte_cnt[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="3" tap_mode="classic" trigger_index="3" type="unknown"/> + <node data_index="2" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_byte_cnt[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="2" tap_mode="classic" trigger_index="2" type="unknown"/> + <node data_index="0" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_byte_cnt[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="0" tap_mode="classic" trigger_index="0" type="unknown"/> + </node> + <node is_selected="false" level-0="alt_or" name="mac_rgmii:mac_0|rx_ctl[1..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <node data_index="12" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_ctl[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="12" tap_mode="classic" trigger_index="12" type="unknown"/> + <node data_index="11" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_ctl[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="11" tap_mode="classic" trigger_index="11" type="unknown"/> + </node> + <node is_selected="false" level-0="alt_or" name="mac_rgmii:mac_0|rx_d[7..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <node data_index="22" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="22" tap_mode="classic" trigger_index="22" type="unknown"/> + <node data_index="21" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="21" tap_mode="classic" trigger_index="21" type="unknown"/> + <node data_index="20" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="20" tap_mode="classic" trigger_index="20" type="unknown"/> + <node data_index="19" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="19" tap_mode="classic" trigger_index="19" type="unknown"/> + <node data_index="18" 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type="unknown"/> + <node data_index="54" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_cnt[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="54" tap_mode="classic" trigger_index="54" type="unknown"/> + <node data_index="53" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_cnt[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="53" tap_mode="classic" trigger_index="53" type="unknown"/> + <node data_index="52" duplicate_name_allowed="false" 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is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_cnt[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="44" tap_mode="classic" trigger_index="44" type="unknown"/> + </node> + <node is_selected="false" level-0="alt_or" name="mac_rgmii:mac_0|tx_pkt_cnt[15..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <node data_index="84" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|tx_pkt_cnt[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="84" tap_mode="classic" trigger_index="84" type="unknown"/> + <node data_index="83" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|tx_pkt_cnt[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="83" tap_mode="classic" trigger_index="83" type="unknown"/> + <node data_index="82" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|tx_pkt_cnt[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="82" tap_mode="classic" trigger_index="82" type="unknown"/> + <node data_index="81" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|tx_pkt_cnt[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="81" tap_mode="classic" trigger_index="81" type="unknown"/> + <node data_index="80" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|tx_pkt_cnt[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="80" tap_mode="classic" trigger_index="80" type="unknown"/> + <node data_index="79" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|tx_pkt_cnt[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="79" tap_mode="classic" trigger_index="79" type="unknown"/> + <node data_index="93" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|tx_pkt_cnt[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="93" tap_mode="classic" trigger_index="93" type="unknown"/> + <node data_index="92" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|tx_pkt_cnt[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="92" tap_mode="classic" trigger_index="92" type="unknown"/> + <node data_index="91" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|tx_pkt_cnt[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="91" tap_mode="classic" trigger_index="91" type="unknown"/> + <node data_index="90" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|tx_pkt_cnt[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="90" tap_mode="classic" trigger_index="90" type="unknown"/> + <node data_index="89" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|tx_pkt_cnt[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="89" tap_mode="classic" trigger_index="89" type="unknown"/> + <node data_index="88" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|tx_pkt_cnt[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="88" tap_mode="classic" trigger_index="88" type="unknown"/> + <node data_index="87" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|tx_pkt_cnt[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="87" tap_mode="classic" trigger_index="87" type="unknown"/> + <node data_index="86" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|tx_pkt_cnt[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="86" tap_mode="classic" trigger_index="86" type="unknown"/> + <node data_index="85" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|tx_pkt_cnt[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="85" tap_mode="classic" trigger_index="85" type="unknown"/> + <node data_index="78" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|tx_pkt_cnt[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="78" tap_mode="classic" trigger_index="78" type="unknown"/> + </node> + </unified_setup_data_view> + <data_view> + <net data_index="72" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="high" name="mac_rgmii:mac_0|rx_sop" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="72" tap_mode="classic" trigger_index="72" type="unknown"/> + <net data_index="31" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_eop" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="31" tap_mode="classic" trigger_index="31" type="unknown"/> + <bus is_selected="false" level-0="alt_or" name="mac_rgmii:mac_0|rx_state[3..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="76" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_state[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="76" tap_mode="classic" trigger_index="76" type="unknown"/> + <net data_index="75" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_state[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="75" tap_mode="classic" trigger_index="75" type="unknown"/> + <net data_index="74" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_state[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="74" tap_mode="classic" trigger_index="74" type="unknown"/> + <net data_index="73" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_state[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="73" tap_mode="classic" trigger_index="73" type="unknown"/> + </bus> + <net data_index="32" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_error" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="32" tap_mode="classic" trigger_index="32" type="unknown"/> + <bus is_selected="false" level-0="alt_or" name="mac_rgmii:mac_0|rx_pkt_length[11..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="62" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_length[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="62" tap_mode="classic" trigger_index="62" type="unknown"/> + <net data_index="61" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_length[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="61" tap_mode="classic" trigger_index="61" type="unknown"/> + <net data_index="71" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_length[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="71" tap_mode="classic" trigger_index="71" type="unknown"/> + <net data_index="70" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_length[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="70" tap_mode="classic" trigger_index="70" type="unknown"/> + <net data_index="69" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_length[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="69" tap_mode="classic" trigger_index="69" type="unknown"/> + <net data_index="68" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_length[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="68" tap_mode="classic" trigger_index="68" type="unknown"/> + <net data_index="67" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_length[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="67" tap_mode="classic" trigger_index="67" type="unknown"/> + <net data_index="66" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_length[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="66" tap_mode="classic" trigger_index="66" type="unknown"/> + <net data_index="65" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_length[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="65" tap_mode="classic" trigger_index="65" type="unknown"/> + <net data_index="64" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_length[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="64" tap_mode="classic" trigger_index="64" type="unknown"/> + <net data_index="63" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_length[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="63" tap_mode="classic" trigger_index="63" type="unknown"/> + <net data_index="60" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_length[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="60" tap_mode="classic" trigger_index="60" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="mac_rgmii:mac_0|rx_byte_cnt[10..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="1" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_byte_cnt[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="1" tap_mode="classic" trigger_index="1" type="unknown"/> + <net data_index="10" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_byte_cnt[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="10" tap_mode="classic" trigger_index="10" type="unknown"/> + <net data_index="9" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_byte_cnt[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="9" tap_mode="classic" trigger_index="9" type="unknown"/> + <net data_index="8" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_byte_cnt[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="8" tap_mode="classic" trigger_index="8" type="unknown"/> + <net data_index="7" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_byte_cnt[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="7" tap_mode="classic" trigger_index="7" type="unknown"/> + <net data_index="6" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_byte_cnt[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="6" tap_mode="classic" trigger_index="6" type="unknown"/> + <net data_index="5" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_byte_cnt[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="5" tap_mode="classic" trigger_index="5" type="unknown"/> + <net data_index="4" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_byte_cnt[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="4" tap_mode="classic" trigger_index="4" type="unknown"/> + <net data_index="3" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_byte_cnt[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="3" tap_mode="classic" trigger_index="3" type="unknown"/> + <net data_index="2" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_byte_cnt[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="2" tap_mode="classic" trigger_index="2" type="unknown"/> + <net data_index="0" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_byte_cnt[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="0" tap_mode="classic" trigger_index="0" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="mac_rgmii:mac_0|rx_ctl[1..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="12" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_ctl[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="12" tap_mode="classic" trigger_index="12" type="unknown"/> + <net data_index="11" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_ctl[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="11" tap_mode="classic" trigger_index="11" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="mac_rgmii:mac_0|rx_d[7..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="22" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="22" tap_mode="classic" trigger_index="22" type="unknown"/> + <net data_index="21" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="21" tap_mode="classic" trigger_index="21" type="unknown"/> + <net data_index="20" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="20" tap_mode="classic" trigger_index="20" type="unknown"/> + <net data_index="19" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="19" tap_mode="classic" trigger_index="19" type="unknown"/> + <net data_index="18" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="18" tap_mode="classic" trigger_index="18" type="unknown"/> + <net data_index="17" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="17" tap_mode="classic" trigger_index="17" type="unknown"/> + <net data_index="16" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="16" tap_mode="classic" trigger_index="16" type="unknown"/> + <net data_index="15" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="15" tap_mode="classic" trigger_index="15" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="mac_rgmii:mac_0|rx_ctl_m1[1..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="14" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_ctl_m1[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="14" tap_mode="classic" trigger_index="14" type="unknown"/> + <net data_index="13" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_ctl_m1[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="13" tap_mode="classic" trigger_index="13" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="mac_rgmii:mac_0|rx_d_m1[7..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="30" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d_m1[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="30" tap_mode="classic" trigger_index="30" type="unknown"/> + <net data_index="29" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d_m1[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="29" tap_mode="classic" trigger_index="29" type="unknown"/> + <net data_index="28" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d_m1[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="28" tap_mode="classic" trigger_index="28" type="unknown"/> + <net data_index="27" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d_m1[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="27" tap_mode="classic" trigger_index="27" type="unknown"/> + <net data_index="26" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d_m1[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="26" tap_mode="classic" trigger_index="26" type="unknown"/> + <net data_index="25" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d_m1[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="25" tap_mode="classic" trigger_index="25" type="unknown"/> + <net data_index="24" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d_m1[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="24" tap_mode="classic" trigger_index="24" type="unknown"/> + <net data_index="23" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d_m1[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="23" tap_mode="classic" trigger_index="23" type="unknown"/> + </bus> + <net data_index="42" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_fifo_we" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="42" tap_mode="classic" trigger_index="42" type="unknown"/> + <bus is_selected="false" level-0="alt_or" name="mac_rgmii:mac_0|rx_fifo_d[8..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="41" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_fifo_d[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="41" tap_mode="classic" trigger_index="41" type="unknown"/> + <net data_index="40" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_fifo_d[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="40" tap_mode="classic" trigger_index="40" type="unknown"/> + <net data_index="39" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_fifo_d[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="39" tap_mode="classic" trigger_index="39" type="unknown"/> + <net data_index="38" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_fifo_d[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="38" tap_mode="classic" trigger_index="38" type="unknown"/> + <net data_index="37" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_fifo_d[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="37" tap_mode="classic" trigger_index="37" type="unknown"/> + <net data_index="36" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_fifo_d[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="36" tap_mode="classic" trigger_index="36" type="unknown"/> + <net data_index="35" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_fifo_d[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="35" tap_mode="classic" trigger_index="35" type="unknown"/> + <net data_index="34" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_fifo_d[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="34" tap_mode="classic" trigger_index="34" type="unknown"/> + <net data_index="33" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_fifo_d[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="33" tap_mode="classic" trigger_index="33" type="unknown"/> + </bus> + <net data_index="77" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_wr_done" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="77" tap_mode="classic" trigger_index="77" type="unknown"/> + <net data_index="43" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_keep" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="43" tap_mode="classic" trigger_index="43" type="unknown"/> + <bus is_selected="false" level-0="alt_or" name="mac_rgmii:mac_0|rx_pkt_cnt[15..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="50" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_cnt[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="50" tap_mode="classic" trigger_index="50" type="unknown"/> + <net data_index="49" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_cnt[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="49" tap_mode="classic" trigger_index="49" type="unknown"/> + <net data_index="48" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_cnt[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="48" tap_mode="classic" trigger_index="48" type="unknown"/> + <net data_index="47" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_cnt[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="47" tap_mode="classic" trigger_index="47" type="unknown"/> + <net data_index="46" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_cnt[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="46" tap_mode="classic" trigger_index="46" type="unknown"/> + <net data_index="45" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_cnt[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="45" tap_mode="classic" trigger_index="45" type="unknown"/> + <net data_index="59" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_cnt[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="59" tap_mode="classic" trigger_index="59" type="unknown"/> + <net data_index="58" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_cnt[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="58" tap_mode="classic" trigger_index="58" type="unknown"/> + <net data_index="57" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_cnt[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="57" tap_mode="classic" trigger_index="57" type="unknown"/> + <net data_index="56" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_cnt[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="56" tap_mode="classic" trigger_index="56" type="unknown"/> + <net data_index="55" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_cnt[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="55" tap_mode="classic" trigger_index="55" type="unknown"/> + <net data_index="54" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_cnt[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="54" tap_mode="classic" trigger_index="54" type="unknown"/> + <net data_index="53" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_cnt[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="53" tap_mode="classic" trigger_index="53" type="unknown"/> + <net data_index="52" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_cnt[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="52" tap_mode="classic" trigger_index="52" type="unknown"/> + <net data_index="51" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_cnt[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="51" tap_mode="classic" trigger_index="51" type="unknown"/> + <net data_index="44" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_cnt[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="44" tap_mode="classic" trigger_index="44" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="mac_rgmii:mac_0|tx_pkt_cnt[15..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="84" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|tx_pkt_cnt[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="84" tap_mode="classic" trigger_index="84" type="unknown"/> + <net data_index="83" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|tx_pkt_cnt[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="83" tap_mode="classic" trigger_index="83" type="unknown"/> + <net data_index="82" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|tx_pkt_cnt[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="82" tap_mode="classic" trigger_index="82" type="unknown"/> + <net data_index="81" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|tx_pkt_cnt[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="81" tap_mode="classic" trigger_index="81" type="unknown"/> + <net data_index="80" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|tx_pkt_cnt[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="80" tap_mode="classic" trigger_index="80" type="unknown"/> + <net data_index="79" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|tx_pkt_cnt[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="79" tap_mode="classic" trigger_index="79" type="unknown"/> + <net data_index="93" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|tx_pkt_cnt[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="93" tap_mode="classic" trigger_index="93" type="unknown"/> + <net data_index="92" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|tx_pkt_cnt[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="92" tap_mode="classic" trigger_index="92" type="unknown"/> + <net data_index="91" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|tx_pkt_cnt[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="91" tap_mode="classic" trigger_index="91" type="unknown"/> + <net data_index="90" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|tx_pkt_cnt[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="90" tap_mode="classic" trigger_index="90" type="unknown"/> + <net data_index="89" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|tx_pkt_cnt[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="89" tap_mode="classic" trigger_index="89" type="unknown"/> + <net data_index="88" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|tx_pkt_cnt[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="88" tap_mode="classic" trigger_index="88" type="unknown"/> + <net data_index="87" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|tx_pkt_cnt[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="87" tap_mode="classic" trigger_index="87" type="unknown"/> + <net data_index="86" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|tx_pkt_cnt[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="86" tap_mode="classic" trigger_index="86" type="unknown"/> + <net data_index="85" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|tx_pkt_cnt[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="85" tap_mode="classic" trigger_index="85" type="unknown"/> + <net data_index="78" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|tx_pkt_cnt[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="78" tap_mode="classic" trigger_index="78" type="unknown"/> + </bus> + </data_view> + <setup_view> + <net data_index="72" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="high" name="mac_rgmii:mac_0|rx_sop" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="72" tap_mode="classic" trigger_index="72" type="unknown"/> + <net data_index="31" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_eop" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="31" tap_mode="classic" trigger_index="31" type="unknown"/> + <bus is_selected="false" level-0="alt_or" name="mac_rgmii:mac_0|rx_state[3..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="76" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_state[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="76" tap_mode="classic" trigger_index="76" type="unknown"/> + <net data_index="75" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_state[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="75" tap_mode="classic" trigger_index="75" type="unknown"/> + <net data_index="74" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_state[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="74" tap_mode="classic" trigger_index="74" type="unknown"/> + <net data_index="73" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_state[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="73" tap_mode="classic" trigger_index="73" type="unknown"/> + </bus> + <net data_index="32" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_error" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="32" tap_mode="classic" trigger_index="32" type="unknown"/> + <bus is_selected="false" level-0="alt_or" name="mac_rgmii:mac_0|rx_pkt_length[11..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="62" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_length[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="62" tap_mode="classic" trigger_index="62" type="unknown"/> + <net data_index="61" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_length[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="61" tap_mode="classic" trigger_index="61" type="unknown"/> + <net data_index="71" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_length[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="71" tap_mode="classic" trigger_index="71" type="unknown"/> + <net data_index="70" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_length[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="70" tap_mode="classic" trigger_index="70" type="unknown"/> + <net data_index="69" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_length[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="69" tap_mode="classic" trigger_index="69" type="unknown"/> + <net data_index="68" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_length[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="68" tap_mode="classic" trigger_index="68" type="unknown"/> + <net data_index="67" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_length[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="67" tap_mode="classic" trigger_index="67" type="unknown"/> + <net data_index="66" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_length[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="66" tap_mode="classic" trigger_index="66" type="unknown"/> + <net data_index="65" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_length[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="65" tap_mode="classic" trigger_index="65" type="unknown"/> + <net data_index="64" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_length[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="64" tap_mode="classic" trigger_index="64" type="unknown"/> + <net data_index="63" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_length[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="63" tap_mode="classic" trigger_index="63" type="unknown"/> + <net data_index="60" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_length[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="60" tap_mode="classic" trigger_index="60" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="mac_rgmii:mac_0|rx_byte_cnt[10..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="1" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_byte_cnt[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="1" tap_mode="classic" trigger_index="1" type="unknown"/> + <net data_index="10" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_byte_cnt[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="10" tap_mode="classic" trigger_index="10" type="unknown"/> + <net data_index="9" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_byte_cnt[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="9" tap_mode="classic" trigger_index="9" type="unknown"/> + <net data_index="8" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_byte_cnt[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="8" tap_mode="classic" trigger_index="8" type="unknown"/> + <net data_index="7" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_byte_cnt[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="7" tap_mode="classic" trigger_index="7" type="unknown"/> + <net data_index="6" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_byte_cnt[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="6" tap_mode="classic" trigger_index="6" type="unknown"/> + <net data_index="5" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_byte_cnt[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="5" tap_mode="classic" trigger_index="5" type="unknown"/> + <net data_index="4" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_byte_cnt[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="4" tap_mode="classic" trigger_index="4" type="unknown"/> + <net data_index="3" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_byte_cnt[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="3" tap_mode="classic" trigger_index="3" type="unknown"/> + <net data_index="2" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_byte_cnt[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="2" tap_mode="classic" trigger_index="2" type="unknown"/> + <net data_index="0" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_byte_cnt[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="0" tap_mode="classic" trigger_index="0" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="mac_rgmii:mac_0|rx_ctl[1..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="12" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_ctl[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="12" tap_mode="classic" trigger_index="12" type="unknown"/> + <net data_index="11" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_ctl[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="11" tap_mode="classic" trigger_index="11" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="mac_rgmii:mac_0|rx_d[7..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="22" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="22" tap_mode="classic" trigger_index="22" type="unknown"/> + <net data_index="21" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="21" tap_mode="classic" trigger_index="21" type="unknown"/> + <net data_index="20" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="20" tap_mode="classic" trigger_index="20" type="unknown"/> + <net data_index="19" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="19" tap_mode="classic" trigger_index="19" type="unknown"/> + <net data_index="18" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="18" tap_mode="classic" trigger_index="18" type="unknown"/> + <net data_index="17" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="17" tap_mode="classic" trigger_index="17" type="unknown"/> + <net data_index="16" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="16" tap_mode="classic" trigger_index="16" type="unknown"/> + <net data_index="15" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="15" tap_mode="classic" trigger_index="15" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="mac_rgmii:mac_0|rx_ctl_m1[1..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="14" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_ctl_m1[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="14" tap_mode="classic" trigger_index="14" type="unknown"/> + <net data_index="13" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_ctl_m1[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="13" tap_mode="classic" trigger_index="13" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="mac_rgmii:mac_0|rx_d_m1[7..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="30" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d_m1[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="30" tap_mode="classic" trigger_index="30" type="unknown"/> + <net data_index="29" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d_m1[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="29" tap_mode="classic" trigger_index="29" type="unknown"/> + <net data_index="28" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d_m1[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="28" tap_mode="classic" trigger_index="28" type="unknown"/> + <net data_index="27" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d_m1[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="27" tap_mode="classic" trigger_index="27" type="unknown"/> + <net data_index="26" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d_m1[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="26" tap_mode="classic" trigger_index="26" type="unknown"/> + <net data_index="25" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d_m1[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="25" tap_mode="classic" trigger_index="25" type="unknown"/> + <net data_index="24" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d_m1[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="24" tap_mode="classic" trigger_index="24" type="unknown"/> + <net data_index="23" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_d_m1[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="23" tap_mode="classic" trigger_index="23" type="unknown"/> + </bus> + <net data_index="42" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_fifo_we" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="42" tap_mode="classic" trigger_index="42" type="unknown"/> + <bus is_selected="false" level-0="alt_or" name="mac_rgmii:mac_0|rx_fifo_d[8..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="41" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_fifo_d[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="41" tap_mode="classic" trigger_index="41" type="unknown"/> + <net data_index="40" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_fifo_d[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="40" tap_mode="classic" trigger_index="40" type="unknown"/> + <net data_index="39" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_fifo_d[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="39" tap_mode="classic" trigger_index="39" type="unknown"/> + <net data_index="38" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_fifo_d[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="38" tap_mode="classic" trigger_index="38" type="unknown"/> + <net data_index="37" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_fifo_d[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="37" tap_mode="classic" trigger_index="37" type="unknown"/> + <net data_index="36" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_fifo_d[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="36" tap_mode="classic" trigger_index="36" type="unknown"/> + <net data_index="35" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_fifo_d[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="35" tap_mode="classic" trigger_index="35" type="unknown"/> + <net data_index="34" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_fifo_d[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="34" tap_mode="classic" trigger_index="34" type="unknown"/> + <net data_index="33" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_fifo_d[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="33" tap_mode="classic" trigger_index="33" type="unknown"/> + </bus> + <net data_index="77" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_wr_done" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="77" tap_mode="classic" trigger_index="77" type="unknown"/> + <net data_index="43" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_keep" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="43" tap_mode="classic" trigger_index="43" type="unknown"/> + <bus is_selected="false" level-0="alt_or" name="mac_rgmii:mac_0|rx_pkt_cnt[15..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="50" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_cnt[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="50" tap_mode="classic" trigger_index="50" type="unknown"/> + <net data_index="49" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_cnt[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="49" tap_mode="classic" trigger_index="49" type="unknown"/> + <net data_index="48" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_cnt[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="48" tap_mode="classic" trigger_index="48" type="unknown"/> + <net data_index="47" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_cnt[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="47" tap_mode="classic" trigger_index="47" type="unknown"/> + <net data_index="46" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_cnt[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="46" tap_mode="classic" trigger_index="46" type="unknown"/> + <net data_index="45" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_cnt[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="45" tap_mode="classic" trigger_index="45" type="unknown"/> + <net data_index="59" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_cnt[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="59" tap_mode="classic" trigger_index="59" type="unknown"/> + <net data_index="58" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_cnt[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="58" tap_mode="classic" trigger_index="58" type="unknown"/> + <net data_index="57" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_cnt[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="57" tap_mode="classic" trigger_index="57" type="unknown"/> + <net data_index="56" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_cnt[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="56" tap_mode="classic" trigger_index="56" type="unknown"/> + <net data_index="55" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_pkt_cnt[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="55" tap_mode="classic" trigger_index="55" type="unknown"/> + <net data_index="54" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" 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pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="44" tap_mode="classic" trigger_index="44" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="mac_rgmii:mac_0|tx_pkt_cnt[15..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="84" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|tx_pkt_cnt[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="84" tap_mode="classic" trigger_index="84" type="unknown"/> + <net data_index="83" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" 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value="8192"/> + <single attribute="zoom offset denominator" value="1"/> + <single attribute="zoom offset numerator" value="2"/> + </position_info> + </instance> + <instance enabled="false" entity_name="sld_signaltap" is_auto_node="yes" is_expanded="true" name="tst_mac2_rx" source_file="sld_signaltap.vhd"> + <node_ip_info instance_id="8" mfg_id="110" node_id="0" version="6"/> + <signal_set global_temp="1" is_expanded="true" name="signal_set: 2025/11/18 12:41:39 #0"> + <clock name="phy2_rx_clk" polarity="posedge" tap_mode="classic"/> + <config pipeline_level="0" ram_type="AUTO" reserved_data_nodes="0" reserved_storage_qualifier_nodes="0" reserved_trigger_nodes="0" sample_depth="256" trigger_in_enable="no" trigger_out_enable="no"/> + <top_entity/> + <signal_vec> + <trigger_input_vec> + <wire name="mac_rgmii:mac_0|rx_eop" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_sop" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_state[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_state[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_state[2]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_state[3]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_wr_done" tap_mode="classic"/> + <wire name="mac_rgmii:mac_2|rx_ctl[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_2|rx_ctl[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_2|rx_ctl_m1[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_2|rx_ctl_m1[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_2|rx_d[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_2|rx_d[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_2|rx_d[2]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_2|rx_d[3]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_2|rx_d[4]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_2|rx_d[5]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_2|rx_d[6]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_2|rx_d[7]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_2|rx_d_m1[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_2|rx_d_m1[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_2|rx_d_m1[2]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_2|rx_d_m1[3]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_2|rx_d_m1[4]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_2|rx_d_m1[5]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_2|rx_d_m1[6]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_2|rx_d_m1[7]" tap_mode="classic"/> + </trigger_input_vec> + <data_input_vec> + <wire name="mac_rgmii:mac_0|rx_eop" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_sop" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_state[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_state[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_state[2]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_state[3]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_wr_done" tap_mode="classic"/> + <wire name="mac_rgmii:mac_2|rx_ctl[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_2|rx_ctl[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_2|rx_ctl_m1[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_2|rx_ctl_m1[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_2|rx_d[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_2|rx_d[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_2|rx_d[2]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_2|rx_d[3]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_2|rx_d[4]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_2|rx_d[5]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_2|rx_d[6]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_2|rx_d[7]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_2|rx_d_m1[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_2|rx_d_m1[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_2|rx_d_m1[2]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_2|rx_d_m1[3]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_2|rx_d_m1[4]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_2|rx_d_m1[5]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_2|rx_d_m1[6]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_2|rx_d_m1[7]" tap_mode="classic"/> + </data_input_vec> + <storage_qualifier_input_vec> + <wire name="mac_rgmii:mac_0|rx_eop" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_sop" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_state[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_state[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_state[2]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_state[3]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_0|rx_wr_done" tap_mode="classic"/> + <wire name="mac_rgmii:mac_2|rx_ctl[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_2|rx_ctl[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_2|rx_ctl_m1[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_2|rx_ctl_m1[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_2|rx_d[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_2|rx_d[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_2|rx_d[2]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_2|rx_d[3]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_2|rx_d[4]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_2|rx_d[5]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_2|rx_d[6]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_2|rx_d[7]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_2|rx_d_m1[0]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_2|rx_d_m1[1]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_2|rx_d_m1[2]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_2|rx_d_m1[3]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_2|rx_d_m1[4]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_2|rx_d_m1[5]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_2|rx_d_m1[6]" tap_mode="classic"/> + <wire name="mac_rgmii:mac_2|rx_d_m1[7]" tap_mode="classic"/> + </storage_qualifier_input_vec> + </signal_vec> + <presentation> + <unified_setup_data_view> + <node is_selected="false" level-0="alt_or" name="mac_rgmii:mac_2|rx_d[7..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <node data_index="18" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_2|rx_d[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="18" tap_mode="classic" trigger_index="18" type="unknown"/> + <node data_index="17" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_2|rx_d[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="17" tap_mode="classic" trigger_index="17" type="unknown"/> + <node data_index="16" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_2|rx_d[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="16" tap_mode="classic" trigger_index="16" type="unknown"/> + <node data_index="15" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_2|rx_d[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="15" tap_mode="classic" trigger_index="15" type="unknown"/> + <node data_index="14" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_2|rx_d[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="14" tap_mode="classic" trigger_index="14" type="unknown"/> + <node data_index="13" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_2|rx_d[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="13" tap_mode="classic" trigger_index="13" type="unknown"/> + <node data_index="12" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_2|rx_d[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="12" tap_mode="classic" trigger_index="12" type="unknown"/> + <node data_index="11" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_2|rx_d[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="11" tap_mode="classic" trigger_index="11" type="unknown"/> + </node> + <node is_selected="false" level-0="alt_or" name="mac_rgmii:mac_2|rx_d_m1[7..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <node data_index="26" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_2|rx_d_m1[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="26" tap_mode="classic" trigger_index="26" type="unknown"/> + <node data_index="25" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_2|rx_d_m1[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="25" tap_mode="classic" trigger_index="25" type="unknown"/> + <node data_index="24" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_2|rx_d_m1[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="24" tap_mode="classic" trigger_index="24" type="unknown"/> + <node data_index="23" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_2|rx_d_m1[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="23" tap_mode="classic" trigger_index="23" type="unknown"/> + <node data_index="22" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_2|rx_d_m1[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="22" tap_mode="classic" trigger_index="22" type="unknown"/> + <node data_index="21" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_2|rx_d_m1[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="21" tap_mode="classic" trigger_index="21" type="unknown"/> + <node data_index="20" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_2|rx_d_m1[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="20" tap_mode="classic" trigger_index="20" type="unknown"/> + <node data_index="19" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_2|rx_d_m1[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="19" tap_mode="classic" trigger_index="19" type="unknown"/> + </node> + <node is_selected="false" level-0="alt_or" name="mac_rgmii:mac_2|rx_ctl[1..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <node data_index="8" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_2|rx_ctl[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="8" tap_mode="classic" trigger_index="8" type="unknown"/> + <node data_index="7" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_2|rx_ctl[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="7" tap_mode="classic" trigger_index="7" type="unknown"/> + </node> + <node is_selected="false" level-0="alt_or" name="mac_rgmii:mac_2|rx_ctl_m1[1..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <node data_index="10" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="rising edge" name="mac_rgmii:mac_2|rx_ctl_m1[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="10" tap_mode="classic" trigger_index="10" type="unknown"/> + <node data_index="9" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="rising edge" name="mac_rgmii:mac_2|rx_ctl_m1[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="9" tap_mode="classic" trigger_index="9" type="unknown"/> + </node> + <node is_selected="false" level-0="alt_or" name="mac_rgmii:mac_0|rx_state[3..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <node data_index="5" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_state[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="5" tap_mode="classic" trigger_index="5" type="unknown"/> + <node data_index="4" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_state[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="4" tap_mode="classic" trigger_index="4" type="unknown"/> + <node data_index="3" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_state[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="3" tap_mode="classic" trigger_index="3" type="unknown"/> + <node data_index="2" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_state[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="2" tap_mode="classic" trigger_index="2" type="unknown"/> + </node> + <node data_index="6" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_wr_done" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="6" tap_mode="classic" trigger_index="6" type="unknown"/> + <node data_index="1" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_sop" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="1" tap_mode="classic" trigger_index="1" type="unknown"/> + <node data_index="0" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_eop" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="0" tap_mode="classic" trigger_index="0" type="unknown"/> + </unified_setup_data_view> + <data_view> + <bus is_selected="false" level-0="alt_or" name="mac_rgmii:mac_2|rx_d[7..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="18" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_2|rx_d[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="18" tap_mode="classic" trigger_index="18" type="unknown"/> + <net data_index="17" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_2|rx_d[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="17" tap_mode="classic" trigger_index="17" type="unknown"/> + <net data_index="16" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_2|rx_d[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="16" tap_mode="classic" trigger_index="16" type="unknown"/> + <net data_index="15" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_2|rx_d[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="15" tap_mode="classic" trigger_index="15" type="unknown"/> + <net data_index="14" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_2|rx_d[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="14" tap_mode="classic" trigger_index="14" type="unknown"/> + <net data_index="13" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_2|rx_d[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="13" tap_mode="classic" trigger_index="13" type="unknown"/> + <net data_index="12" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_2|rx_d[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="12" tap_mode="classic" trigger_index="12" type="unknown"/> + <net data_index="11" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_2|rx_d[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="11" tap_mode="classic" trigger_index="11" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="mac_rgmii:mac_2|rx_d_m1[7..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="26" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_2|rx_d_m1[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="26" tap_mode="classic" trigger_index="26" type="unknown"/> + <net data_index="25" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_2|rx_d_m1[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="25" tap_mode="classic" trigger_index="25" type="unknown"/> + <net data_index="24" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_2|rx_d_m1[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="24" tap_mode="classic" trigger_index="24" type="unknown"/> + <net data_index="23" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_2|rx_d_m1[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="23" tap_mode="classic" trigger_index="23" type="unknown"/> + <net data_index="22" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_2|rx_d_m1[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="22" tap_mode="classic" trigger_index="22" type="unknown"/> + <net data_index="21" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_2|rx_d_m1[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="21" tap_mode="classic" trigger_index="21" type="unknown"/> + <net data_index="20" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_2|rx_d_m1[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="20" tap_mode="classic" trigger_index="20" type="unknown"/> + <net data_index="19" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_2|rx_d_m1[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="19" tap_mode="classic" trigger_index="19" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="mac_rgmii:mac_2|rx_ctl[1..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="8" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_2|rx_ctl[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="8" tap_mode="classic" trigger_index="8" type="unknown"/> + <net data_index="7" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_2|rx_ctl[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="7" tap_mode="classic" trigger_index="7" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="mac_rgmii:mac_2|rx_ctl_m1[1..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="10" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="rising edge" name="mac_rgmii:mac_2|rx_ctl_m1[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="10" tap_mode="classic" trigger_index="10" type="unknown"/> + <net data_index="9" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="rising edge" name="mac_rgmii:mac_2|rx_ctl_m1[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="9" tap_mode="classic" trigger_index="9" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="mac_rgmii:mac_0|rx_state[3..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="5" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_state[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="5" tap_mode="classic" trigger_index="5" type="unknown"/> + <net data_index="4" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_state[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="4" tap_mode="classic" trigger_index="4" type="unknown"/> + <net data_index="3" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_state[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="3" tap_mode="classic" trigger_index="3" type="unknown"/> + <net data_index="2" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_state[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="2" tap_mode="classic" trigger_index="2" type="unknown"/> + </bus> + <net data_index="6" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_wr_done" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="6" tap_mode="classic" trigger_index="6" type="unknown"/> + <net data_index="1" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_sop" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="1" tap_mode="classic" trigger_index="1" type="unknown"/> + <net data_index="0" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_eop" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="0" tap_mode="classic" trigger_index="0" type="unknown"/> + </data_view> + <setup_view> + <bus is_selected="false" level-0="alt_or" name="mac_rgmii:mac_2|rx_d[7..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="18" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_2|rx_d[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="18" tap_mode="classic" trigger_index="18" type="unknown"/> + <net data_index="17" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_2|rx_d[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="17" tap_mode="classic" trigger_index="17" type="unknown"/> + <net data_index="16" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_2|rx_d[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="16" tap_mode="classic" trigger_index="16" type="unknown"/> + <net data_index="15" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_2|rx_d[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="15" tap_mode="classic" trigger_index="15" type="unknown"/> + <net data_index="14" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_2|rx_d[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="14" tap_mode="classic" trigger_index="14" type="unknown"/> + <net data_index="13" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_2|rx_d[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="13" tap_mode="classic" trigger_index="13" type="unknown"/> + <net data_index="12" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_2|rx_d[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="12" tap_mode="classic" trigger_index="12" type="unknown"/> + <net data_index="11" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_2|rx_d[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="11" tap_mode="classic" trigger_index="11" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="mac_rgmii:mac_2|rx_d_m1[7..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="26" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_2|rx_d_m1[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="26" tap_mode="classic" trigger_index="26" type="unknown"/> + <net data_index="25" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_2|rx_d_m1[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="25" tap_mode="classic" trigger_index="25" type="unknown"/> + <net data_index="24" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_2|rx_d_m1[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="24" tap_mode="classic" trigger_index="24" type="unknown"/> + <net data_index="23" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_2|rx_d_m1[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="23" tap_mode="classic" trigger_index="23" type="unknown"/> + <net data_index="22" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_2|rx_d_m1[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="22" tap_mode="classic" trigger_index="22" type="unknown"/> + <net data_index="21" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_2|rx_d_m1[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="21" tap_mode="classic" trigger_index="21" type="unknown"/> + <net data_index="20" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_2|rx_d_m1[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="20" tap_mode="classic" trigger_index="20" type="unknown"/> + <net data_index="19" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_2|rx_d_m1[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="19" tap_mode="classic" trigger_index="19" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="mac_rgmii:mac_2|rx_ctl[1..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="8" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_2|rx_ctl[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="8" tap_mode="classic" trigger_index="8" type="unknown"/> + <net data_index="7" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_2|rx_ctl[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="7" tap_mode="classic" trigger_index="7" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="mac_rgmii:mac_2|rx_ctl_m1[1..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="10" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="rising edge" name="mac_rgmii:mac_2|rx_ctl_m1[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="10" tap_mode="classic" trigger_index="10" type="unknown"/> + <net data_index="9" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="rising edge" name="mac_rgmii:mac_2|rx_ctl_m1[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="9" tap_mode="classic" trigger_index="9" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="mac_rgmii:mac_0|rx_state[3..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="5" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_state[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="5" tap_mode="classic" trigger_index="5" type="unknown"/> + <net data_index="4" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_state[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="4" tap_mode="classic" trigger_index="4" type="unknown"/> + <net data_index="3" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_state[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="3" tap_mode="classic" trigger_index="3" type="unknown"/> + <net data_index="2" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_state[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="2" tap_mode="classic" trigger_index="2" type="unknown"/> + </bus> + <net data_index="6" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_wr_done" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="6" tap_mode="classic" trigger_index="6" type="unknown"/> + <net data_index="1" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_sop" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="1" tap_mode="classic" trigger_index="1" type="unknown"/> + <net data_index="0" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="mac_rgmii:mac_0|rx_eop" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="0" tap_mode="classic" trigger_index="0" type="unknown"/> + </setup_view> + <trigger_in_editor/> + <trigger_out_editor/> + </presentation> + <trigger CRC="3CC256E7" attribute_mem_mode="false" gap_record="true" global_temp="1" is_expanded="true" name="trigger: 2025/11/18 12:41:39 #1" position="pre" power_up_trigger_mode="false" record_data_gap="true" segment_size="64" storage_mode="off" storage_qualifier_disabled="no" storage_qualifier_port_is_pin="false" storage_qualifier_port_name="auto_stp_external_storage_qualifier" storage_qualifier_port_tap_mode="classic" trigger_type="circular"> + <power_up_trigger position="pre" storage_qualifier_disabled="no"/> + <events use_custom_flow_control="no"> + <level enabled="yes" name="condition1" type="basic">'mac_rgmii:mac_2|rx_ctl_m1[0]' == rising edge && 'mac_rgmii:mac_2|rx_ctl_m1[1]' == rising edge + <power_up enabled="yes"> + </power_up><op_node/> + </level> + </events> + <storage_qualifier_events> + <transitional>111111111111111111111111111 + <pwr_up_transitional>111111111111111111111111111</pwr_up_transitional> + </transitional> + <storage_qualifier_level type="basic"> + <power_up> + </power_up> + <op_node/> + </storage_qualifier_level> + <storage_qualifier_level type="basic"> + <power_up> + </power_up> + <op_node/> + </storage_qualifier_level> + <storage_qualifier_level type="basic"> + <power_up> + </power_up> + <op_node/> + </storage_qualifier_level> + </storage_qualifier_events> + </trigger> + </signal_set> + <position_info> + <single attribute="active tab" value="1"/> + <single attribute="data horizontal scroll position" value="44"/> + <single attribute="data vertical scroll position" value="0"/> + <single attribute="setup horizontal scroll position" value="0"/> + <single attribute="setup vertical scroll position" value="0"/> + <single attribute="zoom level denominator" value="1"/> + <single attribute="zoom level numerator" value="8192"/> + <single attribute="zoom offset denominator" value="1"/> + <single attribute="zoom offset numerator" value="2"/> + </position_info> + </instance> + <instance enabled="false" entity_name="sld_signaltap" is_auto_node="yes" is_expanded="true" name="tst_switch" source_file="sld_signaltap.vhd"> + <node_ip_info instance_id="9" mfg_id="110" node_id="0" version="6"/> + <signal_set global_temp="1" is_expanded="true" name="signal_set: 2025/11/18 12:41:39 #2"> + <clock name="pll:pll_0|c1" polarity="posedge" tap_mode="classic"/> + <config pipeline_level="0" ram_type="AUTO" reserved_data_nodes="0" reserved_storage_qualifier_nodes="0" reserved_trigger_nodes="0" sample_depth="128" trigger_in_enable="no" trigger_out_enable="no"/> + <top_entity/> + <signal_vec> + <trigger_input_vec> + <wire name="switch:switch_0|tx1_byte_cnt[0]" tap_mode="classic"/> + <wire name="switch:switch_0|tx1_byte_cnt[10]" tap_mode="classic"/> + <wire name="switch:switch_0|tx1_byte_cnt[1]" tap_mode="classic"/> + <wire name="switch:switch_0|tx1_byte_cnt[2]" tap_mode="classic"/> + <wire name="switch:switch_0|tx1_byte_cnt[3]" tap_mode="classic"/> + <wire name="switch:switch_0|tx1_byte_cnt[4]" tap_mode="classic"/> + <wire name="switch:switch_0|tx1_byte_cnt[5]" tap_mode="classic"/> + <wire name="switch:switch_0|tx1_byte_cnt[6]" tap_mode="classic"/> + <wire name="switch:switch_0|tx1_byte_cnt[7]" tap_mode="classic"/> + <wire name="switch:switch_0|tx1_byte_cnt[8]" tap_mode="classic"/> + <wire name="switch:switch_0|tx1_byte_cnt[9]" tap_mode="classic"/> + <wire name="switch:switch_0|tx1_src_sel[0]" tap_mode="classic"/> + <wire name="switch:switch_0|tx1_src_sel[1]" tap_mode="classic"/> + <wire name="switch:switch_0|tx1_src_sel[2]" tap_mode="classic"/> + <wire name="switch:switch_0|tx_d1[0]" tap_mode="classic"/> + <wire name="switch:switch_0|tx_d1[1]" tap_mode="classic"/> + <wire name="switch:switch_0|tx_d1[2]" tap_mode="classic"/> + <wire name="switch:switch_0|tx_d1[3]" tap_mode="classic"/> + <wire name="switch:switch_0|tx_d1[4]" tap_mode="classic"/> + <wire name="switch:switch_0|tx_d1[5]" tap_mode="classic"/> + <wire name="switch:switch_0|tx_d1[6]" tap_mode="classic"/> + <wire name="switch:switch_0|tx_d1[7]" tap_mode="classic"/> + <wire name="switch:switch_0|tx_d1[8]" tap_mode="classic"/> + <wire name="switch:switch_0|tx_fifo_empty[0]" tap_mode="classic"/> + <wire name="switch:switch_0|tx_fifo_empty[1]" tap_mode="classic"/> + <wire name="switch:switch_0|tx_fifo_empty[2]" tap_mode="classic"/> + <wire name="switch:switch_0|tx_fifo_re[0]" tap_mode="classic"/> + <wire name="switch:switch_0|tx_fifo_re[1]" tap_mode="classic"/> + <wire name="switch:switch_0|tx_fifo_re[2]" tap_mode="classic"/> + <wire name="switch:switch_0|tx_mode1[0]" tap_mode="classic"/> + <wire name="switch:switch_0|tx_mode1[1]" tap_mode="classic"/> + <wire name="switch:switch_0|tx_mode1[2]" tap_mode="classic"/> + </trigger_input_vec> + <data_input_vec> + <wire name="switch:switch_0|tx1_byte_cnt[0]" tap_mode="classic"/> + <wire name="switch:switch_0|tx1_byte_cnt[10]" tap_mode="classic"/> + <wire name="switch:switch_0|tx1_byte_cnt[1]" tap_mode="classic"/> + <wire name="switch:switch_0|tx1_byte_cnt[2]" tap_mode="classic"/> + <wire name="switch:switch_0|tx1_byte_cnt[3]" tap_mode="classic"/> + <wire name="switch:switch_0|tx1_byte_cnt[4]" tap_mode="classic"/> + <wire name="switch:switch_0|tx1_byte_cnt[5]" tap_mode="classic"/> + <wire name="switch:switch_0|tx1_byte_cnt[6]" tap_mode="classic"/> + <wire name="switch:switch_0|tx1_byte_cnt[7]" tap_mode="classic"/> + <wire name="switch:switch_0|tx1_byte_cnt[8]" tap_mode="classic"/> + <wire name="switch:switch_0|tx1_byte_cnt[9]" tap_mode="classic"/> + <wire name="switch:switch_0|tx1_src_sel[0]" tap_mode="classic"/> + <wire name="switch:switch_0|tx1_src_sel[1]" tap_mode="classic"/> + <wire name="switch:switch_0|tx1_src_sel[2]" tap_mode="classic"/> + <wire name="switch:switch_0|tx_d1[0]" tap_mode="classic"/> + <wire name="switch:switch_0|tx_d1[1]" tap_mode="classic"/> + <wire name="switch:switch_0|tx_d1[2]" tap_mode="classic"/> + <wire name="switch:switch_0|tx_d1[3]" tap_mode="classic"/> + <wire name="switch:switch_0|tx_d1[4]" tap_mode="classic"/> + <wire name="switch:switch_0|tx_d1[5]" tap_mode="classic"/> + <wire name="switch:switch_0|tx_d1[6]" tap_mode="classic"/> + <wire name="switch:switch_0|tx_d1[7]" tap_mode="classic"/> + <wire name="switch:switch_0|tx_d1[8]" tap_mode="classic"/> + <wire name="switch:switch_0|tx_fifo_empty[0]" tap_mode="classic"/> + <wire name="switch:switch_0|tx_fifo_empty[1]" tap_mode="classic"/> + <wire name="switch:switch_0|tx_fifo_empty[2]" tap_mode="classic"/> + <wire name="switch:switch_0|tx_fifo_re[0]" tap_mode="classic"/> + <wire name="switch:switch_0|tx_fifo_re[1]" tap_mode="classic"/> + <wire name="switch:switch_0|tx_fifo_re[2]" tap_mode="classic"/> + <wire name="switch:switch_0|tx_mode1[0]" tap_mode="classic"/> + <wire name="switch:switch_0|tx_mode1[1]" tap_mode="classic"/> + <wire name="switch:switch_0|tx_mode1[2]" tap_mode="classic"/> + </data_input_vec> + <storage_qualifier_input_vec> + <wire name="switch:switch_0|tx1_byte_cnt[0]" tap_mode="classic"/> + <wire name="switch:switch_0|tx1_byte_cnt[10]" tap_mode="classic"/> + <wire name="switch:switch_0|tx1_byte_cnt[1]" tap_mode="classic"/> + <wire name="switch:switch_0|tx1_byte_cnt[2]" tap_mode="classic"/> + <wire name="switch:switch_0|tx1_byte_cnt[3]" tap_mode="classic"/> + <wire name="switch:switch_0|tx1_byte_cnt[4]" tap_mode="classic"/> + <wire name="switch:switch_0|tx1_byte_cnt[5]" tap_mode="classic"/> + <wire name="switch:switch_0|tx1_byte_cnt[6]" tap_mode="classic"/> + <wire name="switch:switch_0|tx1_byte_cnt[7]" tap_mode="classic"/> + <wire name="switch:switch_0|tx1_byte_cnt[8]" tap_mode="classic"/> + <wire name="switch:switch_0|tx1_byte_cnt[9]" tap_mode="classic"/> + <wire name="switch:switch_0|tx1_src_sel[0]" tap_mode="classic"/> + <wire name="switch:switch_0|tx1_src_sel[1]" tap_mode="classic"/> + <wire name="switch:switch_0|tx1_src_sel[2]" tap_mode="classic"/> + <wire name="switch:switch_0|tx_d1[0]" tap_mode="classic"/> + <wire name="switch:switch_0|tx_d1[1]" tap_mode="classic"/> + <wire name="switch:switch_0|tx_d1[2]" tap_mode="classic"/> + <wire name="switch:switch_0|tx_d1[3]" tap_mode="classic"/> + <wire name="switch:switch_0|tx_d1[4]" tap_mode="classic"/> + <wire name="switch:switch_0|tx_d1[5]" tap_mode="classic"/> + <wire name="switch:switch_0|tx_d1[6]" tap_mode="classic"/> + <wire name="switch:switch_0|tx_d1[7]" tap_mode="classic"/> + <wire name="switch:switch_0|tx_d1[8]" tap_mode="classic"/> + <wire name="switch:switch_0|tx_fifo_empty[0]" tap_mode="classic"/> + <wire name="switch:switch_0|tx_fifo_empty[1]" tap_mode="classic"/> + <wire name="switch:switch_0|tx_fifo_empty[2]" tap_mode="classic"/> + <wire name="switch:switch_0|tx_fifo_re[0]" tap_mode="classic"/> + <wire name="switch:switch_0|tx_fifo_re[1]" tap_mode="classic"/> + <wire name="switch:switch_0|tx_fifo_re[2]" tap_mode="classic"/> + <wire name="switch:switch_0|tx_mode1[0]" tap_mode="classic"/> + <wire name="switch:switch_0|tx_mode1[1]" tap_mode="classic"/> + <wire name="switch:switch_0|tx_mode1[2]" tap_mode="classic"/> + </storage_qualifier_input_vec> + </signal_vec> + <presentation> + <unified_setup_data_view> + <node is_selected="false" level-0="alt_or" name="switch:switch_0|tx1_byte_cnt[10..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <node data_index="1" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx1_byte_cnt[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="1" tap_mode="classic" trigger_index="1" type="unknown"/> + <node data_index="10" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx1_byte_cnt[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="10" tap_mode="classic" trigger_index="10" type="unknown"/> + <node data_index="9" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx1_byte_cnt[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="9" tap_mode="classic" trigger_index="9" type="unknown"/> + <node data_index="8" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx1_byte_cnt[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="8" tap_mode="classic" trigger_index="8" type="unknown"/> + <node data_index="7" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx1_byte_cnt[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="7" tap_mode="classic" trigger_index="7" type="unknown"/> + <node data_index="6" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx1_byte_cnt[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="6" tap_mode="classic" trigger_index="6" type="unknown"/> + <node data_index="5" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx1_byte_cnt[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="5" tap_mode="classic" trigger_index="5" type="unknown"/> + <node data_index="4" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx1_byte_cnt[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="4" tap_mode="classic" trigger_index="4" type="unknown"/> + <node data_index="3" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx1_byte_cnt[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="3" tap_mode="classic" trigger_index="3" type="unknown"/> + <node data_index="2" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx1_byte_cnt[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="2" tap_mode="classic" trigger_index="2" type="unknown"/> + <node data_index="0" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx1_byte_cnt[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="0" tap_mode="classic" trigger_index="0" type="unknown"/> + </node> + <node is_selected="false" level-0="alt_or" name="switch:switch_0|tx1_src_sel[2..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <node data_index="13" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx1_src_sel[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="13" tap_mode="classic" trigger_index="13" type="unknown"/> + <node data_index="12" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx1_src_sel[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="12" tap_mode="classic" trigger_index="12" type="unknown"/> + <node data_index="11" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx1_src_sel[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="11" tap_mode="classic" trigger_index="11" type="unknown"/> + </node> + <node is_selected="false" level-0="alt_or" name="switch:switch_0|tx_d1[8..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <node data_index="22" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx_d1[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="22" tap_mode="classic" trigger_index="22" type="unknown"/> + <node data_index="21" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx_d1[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="21" tap_mode="classic" trigger_index="21" type="unknown"/> + <node data_index="20" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx_d1[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="20" tap_mode="classic" trigger_index="20" type="unknown"/> + <node data_index="19" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx_d1[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="19" tap_mode="classic" trigger_index="19" type="unknown"/> + <node data_index="18" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx_d1[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="18" tap_mode="classic" trigger_index="18" type="unknown"/> + <node data_index="17" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx_d1[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="17" tap_mode="classic" trigger_index="17" type="unknown"/> + <node data_index="16" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx_d1[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="16" tap_mode="classic" trigger_index="16" type="unknown"/> + <node data_index="15" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx_d1[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="15" tap_mode="classic" trigger_index="15" type="unknown"/> + <node data_index="14" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx_d1[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="14" tap_mode="classic" trigger_index="14" type="unknown"/> + </node> + <node is_selected="false" level-0="alt_or" name="switch:switch_0|tx_fifo_empty[2..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <node data_index="25" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx_fifo_empty[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="25" tap_mode="classic" trigger_index="25" type="unknown"/> + <node data_index="24" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx_fifo_empty[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="24" tap_mode="classic" trigger_index="24" type="unknown"/> + <node data_index="23" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx_fifo_empty[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="23" tap_mode="classic" trigger_index="23" type="unknown"/> + </node> + <node is_selected="false" level-0="alt_or" name="switch:switch_0|tx_fifo_re[2..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <node data_index="28" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx_fifo_re[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="28" tap_mode="classic" trigger_index="28" type="unknown"/> + <node data_index="27" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx_fifo_re[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="27" tap_mode="classic" trigger_index="27" type="unknown"/> + <node data_index="26" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx_fifo_re[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="26" tap_mode="classic" trigger_index="26" type="unknown"/> + </node> + <node is_selected="false" level-0="alt_or" name="switch:switch_0|tx_mode1[2..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <node data_index="31" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx_mode1[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="31" tap_mode="classic" trigger_index="31" type="unknown"/> + <node data_index="30" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx_mode1[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="30" tap_mode="classic" trigger_index="30" type="unknown"/> + <node data_index="29" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx_mode1[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="29" tap_mode="classic" trigger_index="29" type="unknown"/> + </node> + </unified_setup_data_view> + <data_view> + <bus is_selected="false" level-0="alt_or" name="switch:switch_0|tx1_byte_cnt[10..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="1" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx1_byte_cnt[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="1" tap_mode="classic" trigger_index="1" type="unknown"/> + <net data_index="10" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx1_byte_cnt[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="10" tap_mode="classic" trigger_index="10" type="unknown"/> + <net data_index="9" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx1_byte_cnt[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="9" tap_mode="classic" trigger_index="9" type="unknown"/> + <net data_index="8" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx1_byte_cnt[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="8" tap_mode="classic" trigger_index="8" type="unknown"/> + <net data_index="7" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx1_byte_cnt[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="7" tap_mode="classic" trigger_index="7" type="unknown"/> + <net data_index="6" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx1_byte_cnt[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="6" tap_mode="classic" trigger_index="6" type="unknown"/> + <net data_index="5" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx1_byte_cnt[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="5" tap_mode="classic" trigger_index="5" type="unknown"/> + <net data_index="4" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx1_byte_cnt[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="4" tap_mode="classic" trigger_index="4" type="unknown"/> + <net data_index="3" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx1_byte_cnt[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="3" tap_mode="classic" trigger_index="3" type="unknown"/> + <net data_index="2" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx1_byte_cnt[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="2" tap_mode="classic" trigger_index="2" type="unknown"/> + <net data_index="0" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx1_byte_cnt[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="0" tap_mode="classic" trigger_index="0" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="switch:switch_0|tx1_src_sel[2..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="13" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx1_src_sel[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="13" tap_mode="classic" trigger_index="13" type="unknown"/> + <net data_index="12" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx1_src_sel[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="12" tap_mode="classic" trigger_index="12" type="unknown"/> + <net data_index="11" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx1_src_sel[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="11" tap_mode="classic" trigger_index="11" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="switch:switch_0|tx_d1[8..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="22" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx_d1[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="22" tap_mode="classic" trigger_index="22" type="unknown"/> + <net data_index="21" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx_d1[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="21" tap_mode="classic" trigger_index="21" type="unknown"/> + <net data_index="20" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx_d1[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="20" tap_mode="classic" trigger_index="20" type="unknown"/> + <net data_index="19" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx_d1[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="19" tap_mode="classic" trigger_index="19" type="unknown"/> + <net data_index="18" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx_d1[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="18" tap_mode="classic" trigger_index="18" type="unknown"/> + <net data_index="17" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx_d1[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="17" tap_mode="classic" trigger_index="17" type="unknown"/> + <net data_index="16" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx_d1[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="16" tap_mode="classic" trigger_index="16" type="unknown"/> + <net data_index="15" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx_d1[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="15" tap_mode="classic" trigger_index="15" type="unknown"/> + <net data_index="14" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx_d1[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="14" tap_mode="classic" trigger_index="14" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="switch:switch_0|tx_fifo_empty[2..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="25" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx_fifo_empty[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="25" tap_mode="classic" trigger_index="25" type="unknown"/> + <net data_index="24" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx_fifo_empty[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="24" tap_mode="classic" trigger_index="24" type="unknown"/> + <net data_index="23" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx_fifo_empty[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="23" tap_mode="classic" trigger_index="23" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="switch:switch_0|tx_fifo_re[2..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="28" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx_fifo_re[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="28" tap_mode="classic" trigger_index="28" type="unknown"/> + <net data_index="27" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx_fifo_re[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="27" tap_mode="classic" trigger_index="27" type="unknown"/> + <net data_index="26" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx_fifo_re[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="26" tap_mode="classic" trigger_index="26" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="switch:switch_0|tx_mode1[2..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="31" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx_mode1[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="31" tap_mode="classic" trigger_index="31" type="unknown"/> + <net data_index="30" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx_mode1[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="30" tap_mode="classic" trigger_index="30" type="unknown"/> + <net data_index="29" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx_mode1[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="29" tap_mode="classic" trigger_index="29" type="unknown"/> + </bus> + </data_view> + <setup_view> + <bus is_selected="false" level-0="alt_or" name="switch:switch_0|tx1_byte_cnt[10..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="1" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx1_byte_cnt[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="1" tap_mode="classic" trigger_index="1" type="unknown"/> + <net data_index="10" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx1_byte_cnt[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="10" tap_mode="classic" trigger_index="10" type="unknown"/> + <net data_index="9" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx1_byte_cnt[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="9" tap_mode="classic" trigger_index="9" type="unknown"/> + <net data_index="8" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx1_byte_cnt[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="8" tap_mode="classic" trigger_index="8" type="unknown"/> + <net data_index="7" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx1_byte_cnt[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="7" tap_mode="classic" trigger_index="7" type="unknown"/> + <net data_index="6" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx1_byte_cnt[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="6" tap_mode="classic" trigger_index="6" type="unknown"/> + <net data_index="5" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx1_byte_cnt[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="5" tap_mode="classic" trigger_index="5" type="unknown"/> + <net data_index="4" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx1_byte_cnt[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="4" tap_mode="classic" trigger_index="4" type="unknown"/> + <net data_index="3" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx1_byte_cnt[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="3" tap_mode="classic" trigger_index="3" type="unknown"/> + <net data_index="2" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx1_byte_cnt[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="2" tap_mode="classic" trigger_index="2" type="unknown"/> + <net data_index="0" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx1_byte_cnt[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="0" tap_mode="classic" trigger_index="0" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="switch:switch_0|tx1_src_sel[2..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="13" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx1_src_sel[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="13" tap_mode="classic" trigger_index="13" type="unknown"/> + <net data_index="12" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx1_src_sel[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="12" tap_mode="classic" trigger_index="12" type="unknown"/> + <net data_index="11" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx1_src_sel[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="11" tap_mode="classic" trigger_index="11" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="switch:switch_0|tx_d1[8..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="22" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx_d1[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="22" tap_mode="classic" trigger_index="22" type="unknown"/> + <net data_index="21" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx_d1[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="21" tap_mode="classic" trigger_index="21" type="unknown"/> + <net data_index="20" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx_d1[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="20" tap_mode="classic" trigger_index="20" type="unknown"/> + <net data_index="19" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx_d1[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="19" tap_mode="classic" trigger_index="19" type="unknown"/> + <net data_index="18" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx_d1[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="18" tap_mode="classic" trigger_index="18" type="unknown"/> + <net data_index="17" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx_d1[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="17" tap_mode="classic" trigger_index="17" type="unknown"/> + <net data_index="16" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx_d1[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="16" tap_mode="classic" trigger_index="16" type="unknown"/> + <net data_index="15" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx_d1[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="15" tap_mode="classic" trigger_index="15" type="unknown"/> + <net data_index="14" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx_d1[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="14" tap_mode="classic" trigger_index="14" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="switch:switch_0|tx_fifo_empty[2..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="25" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx_fifo_empty[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="25" tap_mode="classic" trigger_index="25" type="unknown"/> + <net data_index="24" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx_fifo_empty[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="24" tap_mode="classic" trigger_index="24" type="unknown"/> + <net data_index="23" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx_fifo_empty[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="23" tap_mode="classic" trigger_index="23" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="switch:switch_0|tx_fifo_re[2..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="28" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx_fifo_re[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="28" tap_mode="classic" trigger_index="28" type="unknown"/> + <net data_index="27" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx_fifo_re[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="27" tap_mode="classic" trigger_index="27" type="unknown"/> + <net data_index="26" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx_fifo_re[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="26" tap_mode="classic" trigger_index="26" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="switch:switch_0|tx_mode1[2..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial"> + <net data_index="31" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx_mode1[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="31" tap_mode="classic" trigger_index="31" type="unknown"/> + <net data_index="30" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx_mode1[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="30" tap_mode="classic" trigger_index="30" type="unknown"/> + <net data_index="29" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="switch:switch_0|tx_mode1[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="29" tap_mode="classic" trigger_index="29" type="unknown"/> + </bus> + </setup_view> + <trigger_in_editor/> + <trigger_out_editor/> + </presentation> + <trigger CRC="9AD27CE" attribute_mem_mode="false" gap_record="true" global_temp="1" is_expanded="true" name="trigger: 2025/11/18 12:41:39 #3" position="pre" power_up_trigger_mode="false" record_data_gap="true" segment_size="1" storage_mode="off" storage_qualifier_disabled="no" storage_qualifier_port_is_pin="false" storage_qualifier_port_name="auto_stp_external_storage_qualifier" storage_qualifier_port_tap_mode="classic" trigger_type="circular"> + <power_up_trigger position="pre" storage_qualifier_disabled="no"/> + <events use_custom_flow_control="no"> + <level enabled="yes" name="condition1" type="basic"> + <power_up enabled="yes"> + </power_up><op_node/> + </level> + </events> + <storage_qualifier_events> + <transitional>11111111111111111111111111111111 + <pwr_up_transitional>11111111111111111111111111111111</pwr_up_transitional> + </transitional> + <storage_qualifier_level type="basic"> + <power_up> + </power_up> + <op_node/> + </storage_qualifier_level> + <storage_qualifier_level type="basic"> + <power_up> + </power_up> + <op_node/> + </storage_qualifier_level> + <storage_qualifier_level type="basic"> + <power_up> + </power_up> + <op_node/> + </storage_qualifier_level> + </storage_qualifier_events> + </trigger> + </signal_set> + <position_info> + <single attribute="active tab" value="1"/> + <single attribute="setup horizontal scroll position" value="0"/> + <single attribute="setup vertical scroll position" value="0"/> + </position_info> + </instance> + <instance enabled="true" entity_name="sld_signaltap" is_auto_node="yes" is_expanded="true" name="tst_controller" source_file="sld_signaltap.vhd"> + <node_ip_info instance_id="10" mfg_id="110" node_id="0" version="6"/> + <signal_set global_temp="1" is_expanded="true" name="signal_set: 2025/11/23 22:55:59 #2"> + <clock name="pll:pll_0|c0" polarity="posedge" tap_mode="classic"/> + <config pipeline_level="0" ram_type="AUTO" reserved_data_nodes="0" reserved_storage_qualifier_nodes="0" reserved_trigger_nodes="0" sample_depth="256" trigger_in_enable="no" trigger_out_enable="no"/> + <top_entity/> + <signal_vec> + <trigger_input_vec> + <wire name="controller:controller_0|msg_addr[0]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[10]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[11]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[12]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[13]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[14]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[15]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[1]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[2]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[3]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[4]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[5]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[6]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[7]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[8]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[9]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr_ro" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr_valid" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[0]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[10]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[11]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[12]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[13]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[14]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[15]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[16]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[17]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[18]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[19]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[1]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[20]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[21]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[22]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[23]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[24]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[25]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[26]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[27]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[28]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[29]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[2]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[30]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[31]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[3]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[4]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[5]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[6]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[7]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[8]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[9]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_error" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[0]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[10]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[11]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[12]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[13]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[14]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[15]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[16]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[17]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[18]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[19]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[1]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[20]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[21]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[22]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[23]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[24]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[25]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[26]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[27]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[28]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[29]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[2]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[30]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[31]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[3]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[4]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[5]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[6]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[7]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[8]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[9]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_token[0]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_token[1]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_token[2]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_token[3]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_token[4]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_token[5]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_token[6]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_token[7]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_type[0]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_type[1]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_type[2]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_type[3]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_type[4]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_type[5]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_type[6]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_type[7]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_cnt[0]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_cnt[1]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_cnt[2]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_cnt[3]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_cnt[4]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_fifo_int" tap_mode="classic"/> + <wire name="controller:controller_0|rx_fifo_int_acked" tap_mode="classic"/> + <wire name="controller:controller_0|rx_fifo_int_m1" tap_mode="classic"/> + <wire name="controller:controller_0|rx_fifo_int_m2" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_captured" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[0]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[10]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[11]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[12]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[13]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[14]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[15]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[1]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[2]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[3]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[4]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[5]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[6]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[7]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[8]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[9]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_rd_active" tap_mode="classic"/> + <wire name="controller:controller_0|rx_rd_ptr[0]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_rd_ptr[10]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_rd_ptr[1]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_rd_ptr[2]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_rd_ptr[3]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_rd_ptr[4]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_rd_ptr[5]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_rd_ptr[6]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_rd_ptr[7]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_rd_ptr[8]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_rd_ptr[9]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_wr_ptr[0]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_wr_ptr[10]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_wr_ptr[1]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_wr_ptr[2]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_wr_ptr[3]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_wr_ptr[4]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_wr_ptr[5]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_wr_ptr[6]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_wr_ptr[7]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_wr_ptr[8]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_wr_ptr[9]" tap_mode="classic"/> + </trigger_input_vec> + <data_input_vec> + <wire name="controller:controller_0|msg_addr[0]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[10]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[11]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[12]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[13]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[14]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[15]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[1]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[2]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[3]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[4]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[5]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[6]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[7]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[8]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[9]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr_ro" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr_valid" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[0]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[10]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[11]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[12]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[13]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[14]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[15]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[16]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[17]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[18]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[19]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[1]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[20]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[21]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[22]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[23]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[24]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[25]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[26]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[27]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[28]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[29]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[2]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[30]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[31]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[3]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[4]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[5]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[6]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[7]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[8]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[9]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_error" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[0]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[10]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[11]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[12]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[13]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[14]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[15]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[16]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[17]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[18]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[19]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[1]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[20]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[21]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[22]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[23]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[24]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[25]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[26]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[27]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[28]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[29]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[2]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[30]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[31]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[3]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[4]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[5]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[6]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[7]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[8]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[9]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_token[0]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_token[1]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_token[2]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_token[3]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_token[4]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_token[5]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_token[6]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_token[7]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_type[0]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_type[1]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_type[2]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_type[3]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_type[4]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_type[5]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_type[6]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_type[7]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_cnt[0]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_cnt[1]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_cnt[2]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_cnt[3]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_cnt[4]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_fifo_int" tap_mode="classic"/> + <wire name="controller:controller_0|rx_fifo_int_acked" tap_mode="classic"/> + <wire name="controller:controller_0|rx_fifo_int_m1" tap_mode="classic"/> + <wire name="controller:controller_0|rx_fifo_int_m2" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_captured" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[0]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[10]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[11]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[12]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[13]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[14]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[15]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[1]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[2]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[3]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[4]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[5]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[6]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[7]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[8]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[9]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_rd_active" tap_mode="classic"/> + <wire name="controller:controller_0|rx_rd_ptr[0]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_rd_ptr[10]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_rd_ptr[1]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_rd_ptr[2]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_rd_ptr[3]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_rd_ptr[4]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_rd_ptr[5]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_rd_ptr[6]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_rd_ptr[7]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_rd_ptr[8]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_rd_ptr[9]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_wr_ptr[0]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_wr_ptr[10]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_wr_ptr[1]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_wr_ptr[2]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_wr_ptr[3]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_wr_ptr[4]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_wr_ptr[5]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_wr_ptr[6]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_wr_ptr[7]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_wr_ptr[8]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_wr_ptr[9]" tap_mode="classic"/> + </data_input_vec> + <storage_qualifier_input_vec> + <wire name="controller:controller_0|msg_addr[0]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[10]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[11]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[12]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[13]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[14]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[15]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[1]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[2]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[3]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[4]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[5]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[6]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[7]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[8]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr[9]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr_ro" tap_mode="classic"/> + <wire name="controller:controller_0|msg_addr_valid" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[0]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[10]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[11]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[12]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[13]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[14]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[15]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[16]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[17]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[18]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[19]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[1]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[20]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[21]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[22]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[23]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[24]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[25]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[26]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[27]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[28]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[29]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[2]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[30]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[31]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[3]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[4]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[5]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[6]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[7]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[8]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_data[9]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_error" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[0]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[10]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[11]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[12]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[13]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[14]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[15]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[16]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[17]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[18]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[19]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[1]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[20]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[21]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[22]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[23]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[24]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[25]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[26]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[27]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[28]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[29]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[2]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[30]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[31]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[3]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[4]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[5]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[6]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[7]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[8]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_response[9]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_token[0]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_token[1]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_token[2]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_token[3]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_token[4]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_token[5]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_token[6]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_token[7]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_type[0]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_type[1]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_type[2]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_type[3]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_type[4]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_type[5]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_type[6]" tap_mode="classic"/> + <wire name="controller:controller_0|msg_type[7]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_cnt[0]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_cnt[1]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_cnt[2]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_cnt[3]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_cnt[4]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_fifo_int" tap_mode="classic"/> + <wire name="controller:controller_0|rx_fifo_int_acked" tap_mode="classic"/> + <wire name="controller:controller_0|rx_fifo_int_m1" tap_mode="classic"/> + <wire name="controller:controller_0|rx_fifo_int_m2" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_captured" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[0]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[10]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[11]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[12]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[13]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[14]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[15]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[1]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[2]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[3]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[4]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[5]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[6]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[7]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[8]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_msg_cnt[9]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_rd_active" tap_mode="classic"/> + <wire name="controller:controller_0|rx_rd_ptr[0]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_rd_ptr[10]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_rd_ptr[1]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_rd_ptr[2]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_rd_ptr[3]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_rd_ptr[4]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_rd_ptr[5]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_rd_ptr[6]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_rd_ptr[7]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_rd_ptr[8]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_rd_ptr[9]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_wr_ptr[0]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_wr_ptr[10]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_wr_ptr[1]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_wr_ptr[2]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_wr_ptr[3]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_wr_ptr[4]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_wr_ptr[5]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_wr_ptr[6]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_wr_ptr[7]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_wr_ptr[8]" tap_mode="classic"/> + <wire name="controller:controller_0|rx_wr_ptr[9]" tap_mode="classic"/> + </storage_qualifier_input_vec> + </signal_vec> + <presentation> + <unified_setup_data_view> + <node data_index="104" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_fifo_int" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="104" tap_mode="classic" trigger_index="104" type="unknown"/> + <node data_index="105" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_fifo_int_acked" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="105" tap_mode="classic" trigger_index="105" type="unknown"/> + <node data_index="106" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_fifo_int_m1" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="106" tap_mode="classic" trigger_index="106" type="unknown"/> + <node data_index="107" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_fifo_int_m2" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="107" tap_mode="classic" trigger_index="107" type="unknown"/> + <node data_index="108" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="high" name="controller:controller_0|rx_msg_captured" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="108" tap_mode="classic" trigger_index="108" type="unknown"/> + <node data_index="125" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_rd_active" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="125" tap_mode="classic" trigger_index="125" type="unknown"/> + <node is_selected="false" level-0="alt_or" name="controller:controller_0|rx_cnt[4..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <node data_index="103" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_cnt[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="103" tap_mode="classic" trigger_index="103" type="unknown"/> + <node data_index="102" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_cnt[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="102" tap_mode="classic" trigger_index="102" type="unknown"/> + <node data_index="101" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_cnt[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="101" tap_mode="classic" trigger_index="101" type="unknown"/> + <node data_index="100" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_cnt[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="100" tap_mode="classic" trigger_index="100" type="unknown"/> + <node data_index="99" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_cnt[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="99" tap_mode="classic" trigger_index="99" type="unknown"/> + </node> + <node is_selected="false" level-0="alt_or" name="controller:controller_0|rx_msg_cnt[15..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <node data_index="115" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_msg_cnt[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="115" tap_mode="classic" trigger_index="115" type="unknown"/> + <node data_index="114" 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pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="117" tap_mode="classic" trigger_index="117" type="unknown"/> + <node data_index="116" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_msg_cnt[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="116" tap_mode="classic" trigger_index="116" type="unknown"/> + <node data_index="109" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_msg_cnt[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="109" tap_mode="classic" trigger_index="109" type="unknown"/> + </node> + <node is_selected="false" level-0="alt_or" name="controller:controller_0|rx_rd_ptr[10..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <node data_index="127" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_rd_ptr[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="127" tap_mode="classic" trigger_index="127" type="unknown"/> + <node data_index="136" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" 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storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="128" tap_mode="classic" trigger_index="128" type="unknown"/> + <node data_index="126" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_rd_ptr[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="126" tap_mode="classic" trigger_index="126" type="unknown"/> + </node> + <node is_selected="false" level-0="alt_or" name="controller:controller_0|rx_wr_ptr[10..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <node data_index="138" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_wr_ptr[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="138" tap_mode="classic" trigger_index="138" type="unknown"/> + <node data_index="147" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_wr_ptr[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="147" tap_mode="classic" trigger_index="147" type="unknown"/> + <node data_index="146" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_wr_ptr[8]" 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name="controller:controller_0|msg_response[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="73" tap_mode="classic" trigger_index="73" type="unknown"/> + <node data_index="62" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="62" tap_mode="classic" trigger_index="62" type="unknown"/> + <node data_index="51" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="51" tap_mode="classic" trigger_index="51" type="unknown"/> + </node> + <node is_selected="false" level-0="alt_or" name="controller:controller_0|msg_token[7..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <node data_index="90" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_token[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="90" tap_mode="classic" trigger_index="90" type="unknown"/> + <node data_index="89" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_token[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="89" tap_mode="classic" trigger_index="89" type="unknown"/> + <node data_index="88" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_token[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="88" tap_mode="classic" trigger_index="88" type="unknown"/> + <node data_index="87" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_token[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="87" tap_mode="classic" trigger_index="87" type="unknown"/> + <node data_index="86" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_token[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="86" tap_mode="classic" trigger_index="86" type="unknown"/> + <node data_index="85" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_token[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="85" tap_mode="classic" trigger_index="85" type="unknown"/> + <node data_index="84" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_token[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="84" tap_mode="classic" trigger_index="84" type="unknown"/> + <node data_index="83" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_token[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="83" tap_mode="classic" trigger_index="83" type="unknown"/> + </node> + <node is_selected="false" level-0="alt_or" name="controller:controller_0|msg_type[7..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <node data_index="98" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_type[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="98" tap_mode="classic" trigger_index="98" type="unknown"/> + <node data_index="97" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_type[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="97" tap_mode="classic" trigger_index="97" type="unknown"/> + <node data_index="96" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_type[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="96" tap_mode="classic" trigger_index="96" type="unknown"/> + <node data_index="95" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_type[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="95" tap_mode="classic" trigger_index="95" type="unknown"/> + <node data_index="94" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_type[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="94" tap_mode="classic" trigger_index="94" type="unknown"/> + <node data_index="93" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_type[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="93" tap_mode="classic" trigger_index="93" type="unknown"/> + <node data_index="92" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_type[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="92" tap_mode="classic" trigger_index="92" type="unknown"/> + <node data_index="91" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_type[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="91" tap_mode="classic" trigger_index="91" type="unknown"/> + </node> + </unified_setup_data_view> + <data_view> + <net data_index="104" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_fifo_int" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="104" tap_mode="classic" trigger_index="104" type="unknown"/> + <net data_index="105" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_fifo_int_acked" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="105" tap_mode="classic" trigger_index="105" type="unknown"/> + <net data_index="106" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_fifo_int_m1" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="106" tap_mode="classic" trigger_index="106" type="unknown"/> + <net data_index="107" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_fifo_int_m2" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="107" tap_mode="classic" trigger_index="107" type="unknown"/> + <net data_index="108" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="high" name="controller:controller_0|rx_msg_captured" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="108" tap_mode="classic" trigger_index="108" type="unknown"/> + <net data_index="125" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_rd_active" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="125" tap_mode="classic" trigger_index="125" type="unknown"/> + <bus is_selected="false" level-0="alt_or" name="controller:controller_0|rx_cnt[4..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="103" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_cnt[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="103" tap_mode="classic" trigger_index="103" type="unknown"/> + <net data_index="102" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_cnt[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="102" tap_mode="classic" trigger_index="102" type="unknown"/> + <net data_index="101" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_cnt[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="101" tap_mode="classic" trigger_index="101" type="unknown"/> + <net data_index="100" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_cnt[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="100" tap_mode="classic" trigger_index="100" type="unknown"/> + <net data_index="99" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_cnt[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="99" tap_mode="classic" trigger_index="99" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="controller:controller_0|rx_msg_cnt[15..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="115" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_msg_cnt[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="115" tap_mode="classic" trigger_index="115" type="unknown"/> + <net data_index="114" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_msg_cnt[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="114" tap_mode="classic" trigger_index="114" type="unknown"/> + <net data_index="113" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_msg_cnt[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="113" tap_mode="classic" trigger_index="113" type="unknown"/> + <net data_index="112" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_msg_cnt[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="112" tap_mode="classic" trigger_index="112" type="unknown"/> + <net data_index="111" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_msg_cnt[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="111" tap_mode="classic" trigger_index="111" type="unknown"/> + <net data_index="110" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_msg_cnt[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="110" tap_mode="classic" trigger_index="110" type="unknown"/> + <net data_index="124" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_msg_cnt[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="124" tap_mode="classic" trigger_index="124" type="unknown"/> + <net data_index="123" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_msg_cnt[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="123" tap_mode="classic" trigger_index="123" type="unknown"/> + <net data_index="122" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_msg_cnt[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="122" tap_mode="classic" trigger_index="122" type="unknown"/> + <net data_index="121" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_msg_cnt[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="121" tap_mode="classic" trigger_index="121" type="unknown"/> + <net data_index="120" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_msg_cnt[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="120" tap_mode="classic" trigger_index="120" type="unknown"/> + <net data_index="119" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_msg_cnt[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="119" tap_mode="classic" trigger_index="119" type="unknown"/> + <net data_index="118" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_msg_cnt[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="118" tap_mode="classic" trigger_index="118" type="unknown"/> + <net data_index="117" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_msg_cnt[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="117" tap_mode="classic" trigger_index="117" type="unknown"/> + <net data_index="116" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_msg_cnt[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="116" tap_mode="classic" trigger_index="116" type="unknown"/> + <net data_index="109" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_msg_cnt[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="109" tap_mode="classic" trigger_index="109" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="controller:controller_0|rx_rd_ptr[10..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="127" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_rd_ptr[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="127" tap_mode="classic" trigger_index="127" type="unknown"/> + <net data_index="136" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_rd_ptr[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="136" tap_mode="classic" trigger_index="136" type="unknown"/> + <net data_index="135" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_rd_ptr[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="135" tap_mode="classic" trigger_index="135" type="unknown"/> + <net data_index="134" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_rd_ptr[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="134" tap_mode="classic" trigger_index="134" type="unknown"/> + <net data_index="133" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_rd_ptr[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="133" tap_mode="classic" trigger_index="133" type="unknown"/> + <net data_index="132" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_rd_ptr[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="132" tap_mode="classic" trigger_index="132" type="unknown"/> + <net data_index="131" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_rd_ptr[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="131" tap_mode="classic" trigger_index="131" type="unknown"/> + <net data_index="130" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_rd_ptr[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="130" tap_mode="classic" trigger_index="130" type="unknown"/> + <net data_index="129" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_rd_ptr[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="129" tap_mode="classic" trigger_index="129" type="unknown"/> + <net data_index="128" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_rd_ptr[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="128" tap_mode="classic" trigger_index="128" type="unknown"/> + <net data_index="126" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_rd_ptr[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="126" tap_mode="classic" trigger_index="126" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="controller:controller_0|rx_wr_ptr[10..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="138" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_wr_ptr[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="138" tap_mode="classic" trigger_index="138" type="unknown"/> + <net data_index="147" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_wr_ptr[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="147" tap_mode="classic" trigger_index="147" type="unknown"/> + <net data_index="146" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_wr_ptr[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="146" tap_mode="classic" trigger_index="146" type="unknown"/> + <net data_index="145" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_wr_ptr[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="145" tap_mode="classic" trigger_index="145" type="unknown"/> + <net data_index="144" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_wr_ptr[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="144" tap_mode="classic" trigger_index="144" type="unknown"/> + <net data_index="143" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_wr_ptr[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="143" tap_mode="classic" trigger_index="143" type="unknown"/> + <net data_index="142" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_wr_ptr[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="142" tap_mode="classic" trigger_index="142" type="unknown"/> + <net data_index="141" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_wr_ptr[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="141" tap_mode="classic" trigger_index="141" type="unknown"/> + <net data_index="140" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_wr_ptr[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="140" tap_mode="classic" trigger_index="140" type="unknown"/> + <net data_index="139" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_wr_ptr[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="139" tap_mode="classic" trigger_index="139" type="unknown"/> + <net data_index="137" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_wr_ptr[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="137" tap_mode="classic" trigger_index="137" type="unknown"/> + </bus> + <net data_index="16" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr_ro" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="16" tap_mode="classic" trigger_index="16" type="unknown"/> + <net data_index="17" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr_valid" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="17" tap_mode="classic" trigger_index="17" type="unknown"/> + <net data_index="50" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_error" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="50" tap_mode="classic" trigger_index="50" type="unknown"/> + <bus is_selected="false" level-0="alt_or" name="controller:controller_0|msg_addr[15..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="6" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="6" tap_mode="classic" trigger_index="6" type="unknown"/> + <net data_index="5" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="5" tap_mode="classic" trigger_index="5" type="unknown"/> + <net data_index="4" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="4" tap_mode="classic" trigger_index="4" type="unknown"/> + <net data_index="3" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="3" tap_mode="classic" trigger_index="3" type="unknown"/> + <net data_index="2" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="2" tap_mode="classic" trigger_index="2" type="unknown"/> + <net data_index="1" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="1" tap_mode="classic" trigger_index="1" type="unknown"/> + <net data_index="15" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="15" tap_mode="classic" trigger_index="15" type="unknown"/> + <net data_index="14" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="14" tap_mode="classic" trigger_index="14" type="unknown"/> + <net data_index="13" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="13" tap_mode="classic" trigger_index="13" type="unknown"/> + <net data_index="12" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="12" tap_mode="classic" trigger_index="12" type="unknown"/> + <net data_index="11" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="11" tap_mode="classic" trigger_index="11" type="unknown"/> + <net data_index="10" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="10" tap_mode="classic" trigger_index="10" type="unknown"/> + <net data_index="9" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="9" tap_mode="classic" trigger_index="9" type="unknown"/> + <net data_index="8" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="8" tap_mode="classic" trigger_index="8" type="unknown"/> + <net data_index="7" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="7" tap_mode="classic" trigger_index="7" type="unknown"/> + <net data_index="0" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="0" tap_mode="classic" trigger_index="0" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="controller:controller_0|msg_data[31..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="42" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[31]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="42" tap_mode="classic" trigger_index="42" type="unknown"/> + <net data_index="41" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[30]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="41" tap_mode="classic" trigger_index="41" type="unknown"/> + <net data_index="39" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[29]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="39" tap_mode="classic" trigger_index="39" type="unknown"/> + <net data_index="38" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[28]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="38" tap_mode="classic" trigger_index="38" type="unknown"/> + <net data_index="37" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[27]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="37" tap_mode="classic" trigger_index="37" type="unknown"/> + <net data_index="36" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[26]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="36" tap_mode="classic" trigger_index="36" type="unknown"/> + <net data_index="35" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[25]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="35" tap_mode="classic" trigger_index="35" type="unknown"/> + <net data_index="34" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[24]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="34" tap_mode="classic" trigger_index="34" type="unknown"/> + <net data_index="33" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[23]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="33" tap_mode="classic" trigger_index="33" type="unknown"/> + <net data_index="32" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[22]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="32" tap_mode="classic" trigger_index="32" type="unknown"/> + <net data_index="31" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[21]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="31" tap_mode="classic" trigger_index="31" type="unknown"/> + <net data_index="30" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[20]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="30" tap_mode="classic" trigger_index="30" type="unknown"/> + <net data_index="28" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[19]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="28" tap_mode="classic" trigger_index="28" type="unknown"/> + <net data_index="27" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[18]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="27" tap_mode="classic" trigger_index="27" type="unknown"/> + <net data_index="26" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[17]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="26" tap_mode="classic" trigger_index="26" type="unknown"/> + <net data_index="25" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[16]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="25" tap_mode="classic" trigger_index="25" type="unknown"/> + <net data_index="24" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="24" tap_mode="classic" trigger_index="24" type="unknown"/> + <net data_index="23" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="23" tap_mode="classic" trigger_index="23" type="unknown"/> + <net data_index="22" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="22" tap_mode="classic" trigger_index="22" type="unknown"/> + <net data_index="21" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="21" tap_mode="classic" trigger_index="21" type="unknown"/> + <net data_index="20" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="20" tap_mode="classic" trigger_index="20" type="unknown"/> + <net data_index="19" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="19" tap_mode="classic" trigger_index="19" type="unknown"/> + <net data_index="49" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="49" tap_mode="classic" trigger_index="49" type="unknown"/> + <net data_index="48" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="48" tap_mode="classic" trigger_index="48" type="unknown"/> + <net data_index="47" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="47" tap_mode="classic" trigger_index="47" type="unknown"/> + <net data_index="46" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="46" tap_mode="classic" trigger_index="46" type="unknown"/> + <net data_index="45" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="45" tap_mode="classic" trigger_index="45" type="unknown"/> + <net data_index="44" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="44" tap_mode="classic" trigger_index="44" type="unknown"/> + <net data_index="43" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="43" tap_mode="classic" trigger_index="43" type="unknown"/> + <net data_index="40" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="40" tap_mode="classic" trigger_index="40" type="unknown"/> + <net data_index="29" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="29" tap_mode="classic" trigger_index="29" type="unknown"/> + <net data_index="18" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="18" tap_mode="classic" trigger_index="18" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="controller:controller_0|msg_response[31..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="75" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[31]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="75" tap_mode="classic" trigger_index="75" type="unknown"/> + <net data_index="74" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[30]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="74" tap_mode="classic" trigger_index="74" type="unknown"/> + <net data_index="72" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[29]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="72" tap_mode="classic" trigger_index="72" type="unknown"/> + <net data_index="71" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[28]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="71" tap_mode="classic" trigger_index="71" type="unknown"/> + <net data_index="70" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[27]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="70" tap_mode="classic" trigger_index="70" type="unknown"/> + <net data_index="69" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[26]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="69" tap_mode="classic" trigger_index="69" type="unknown"/> + <net data_index="68" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[25]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="68" tap_mode="classic" trigger_index="68" type="unknown"/> + <net data_index="67" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[24]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="67" tap_mode="classic" trigger_index="67" type="unknown"/> + <net data_index="66" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[23]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="66" tap_mode="classic" trigger_index="66" type="unknown"/> + <net data_index="65" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[22]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="65" tap_mode="classic" trigger_index="65" type="unknown"/> + <net data_index="64" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[21]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="64" tap_mode="classic" trigger_index="64" type="unknown"/> + <net data_index="63" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[20]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="63" tap_mode="classic" trigger_index="63" type="unknown"/> + <net data_index="61" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[19]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="61" tap_mode="classic" trigger_index="61" type="unknown"/> + <net data_index="60" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[18]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="60" tap_mode="classic" trigger_index="60" type="unknown"/> + <net data_index="59" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[17]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="59" tap_mode="classic" trigger_index="59" type="unknown"/> + <net data_index="58" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[16]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="58" tap_mode="classic" trigger_index="58" type="unknown"/> + <net data_index="57" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="57" tap_mode="classic" trigger_index="57" type="unknown"/> + <net data_index="56" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="56" tap_mode="classic" trigger_index="56" type="unknown"/> + <net data_index="55" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="55" tap_mode="classic" trigger_index="55" type="unknown"/> + <net data_index="54" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="54" tap_mode="classic" trigger_index="54" type="unknown"/> + <net data_index="53" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="53" tap_mode="classic" trigger_index="53" type="unknown"/> + <net data_index="52" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="52" tap_mode="classic" trigger_index="52" type="unknown"/> + <net data_index="82" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="82" tap_mode="classic" trigger_index="82" type="unknown"/> + <net data_index="81" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="81" tap_mode="classic" trigger_index="81" type="unknown"/> + <net data_index="80" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="80" tap_mode="classic" trigger_index="80" type="unknown"/> + <net data_index="79" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="79" tap_mode="classic" trigger_index="79" type="unknown"/> + <net data_index="78" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="78" tap_mode="classic" trigger_index="78" type="unknown"/> + <net data_index="77" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="77" tap_mode="classic" trigger_index="77" type="unknown"/> + <net data_index="76" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="76" tap_mode="classic" trigger_index="76" type="unknown"/> + <net data_index="73" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="73" tap_mode="classic" trigger_index="73" type="unknown"/> + <net data_index="62" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="62" tap_mode="classic" trigger_index="62" type="unknown"/> + <net data_index="51" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="51" tap_mode="classic" trigger_index="51" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="controller:controller_0|msg_token[7..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="90" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_token[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="90" tap_mode="classic" trigger_index="90" type="unknown"/> + <net data_index="89" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_token[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="89" tap_mode="classic" trigger_index="89" type="unknown"/> + <net data_index="88" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_token[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="88" tap_mode="classic" trigger_index="88" type="unknown"/> + <net data_index="87" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_token[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="87" tap_mode="classic" trigger_index="87" type="unknown"/> + <net data_index="86" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_token[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="86" tap_mode="classic" trigger_index="86" type="unknown"/> + <net data_index="85" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_token[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="85" tap_mode="classic" trigger_index="85" type="unknown"/> + <net data_index="84" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_token[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="84" tap_mode="classic" trigger_index="84" type="unknown"/> + <net data_index="83" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_token[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="83" tap_mode="classic" trigger_index="83" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="controller:controller_0|msg_type[7..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="98" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_type[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="98" tap_mode="classic" trigger_index="98" type="unknown"/> + <net data_index="97" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_type[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="97" tap_mode="classic" trigger_index="97" type="unknown"/> + <net data_index="96" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_type[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="96" tap_mode="classic" trigger_index="96" type="unknown"/> + <net data_index="95" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_type[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="95" tap_mode="classic" trigger_index="95" type="unknown"/> + <net data_index="94" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_type[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="94" tap_mode="classic" trigger_index="94" type="unknown"/> + <net data_index="93" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_type[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="93" tap_mode="classic" trigger_index="93" type="unknown"/> + <net data_index="92" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_type[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="92" tap_mode="classic" trigger_index="92" type="unknown"/> + <net data_index="91" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_type[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="91" tap_mode="classic" trigger_index="91" type="unknown"/> + </bus> + </data_view> + <setup_view> + <net data_index="104" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_fifo_int" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="104" tap_mode="classic" trigger_index="104" type="unknown"/> + <net data_index="105" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_fifo_int_acked" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="105" tap_mode="classic" trigger_index="105" type="unknown"/> + <net data_index="106" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_fifo_int_m1" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="106" tap_mode="classic" trigger_index="106" type="unknown"/> + <net data_index="107" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_fifo_int_m2" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="107" tap_mode="classic" trigger_index="107" type="unknown"/> + <net data_index="108" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="high" name="controller:controller_0|rx_msg_captured" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="108" tap_mode="classic" trigger_index="108" type="unknown"/> + <net data_index="125" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_rd_active" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="125" tap_mode="classic" trigger_index="125" type="unknown"/> + <bus is_selected="false" level-0="alt_or" name="controller:controller_0|rx_cnt[4..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="103" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_cnt[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="103" tap_mode="classic" trigger_index="103" type="unknown"/> + <net data_index="102" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_cnt[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="102" tap_mode="classic" trigger_index="102" type="unknown"/> + <net data_index="101" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_cnt[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="101" tap_mode="classic" trigger_index="101" type="unknown"/> + <net data_index="100" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_cnt[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="100" tap_mode="classic" trigger_index="100" type="unknown"/> + <net data_index="99" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_cnt[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="99" tap_mode="classic" trigger_index="99" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="controller:controller_0|rx_msg_cnt[15..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="115" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_msg_cnt[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="115" tap_mode="classic" trigger_index="115" type="unknown"/> + <net data_index="114" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_msg_cnt[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="114" tap_mode="classic" trigger_index="114" type="unknown"/> + <net data_index="113" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_msg_cnt[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="113" tap_mode="classic" trigger_index="113" type="unknown"/> + <net data_index="112" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_msg_cnt[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="112" tap_mode="classic" trigger_index="112" type="unknown"/> + <net data_index="111" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_msg_cnt[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="111" tap_mode="classic" trigger_index="111" type="unknown"/> + <net data_index="110" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_msg_cnt[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="110" tap_mode="classic" trigger_index="110" type="unknown"/> + <net data_index="124" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_msg_cnt[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="124" tap_mode="classic" trigger_index="124" type="unknown"/> + <net data_index="123" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_msg_cnt[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="123" tap_mode="classic" trigger_index="123" type="unknown"/> + <net data_index="122" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_msg_cnt[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="122" tap_mode="classic" trigger_index="122" type="unknown"/> + <net data_index="121" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_msg_cnt[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="121" tap_mode="classic" trigger_index="121" type="unknown"/> + <net data_index="120" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_msg_cnt[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="120" tap_mode="classic" trigger_index="120" type="unknown"/> + <net data_index="119" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_msg_cnt[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="119" tap_mode="classic" trigger_index="119" type="unknown"/> + <net data_index="118" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_msg_cnt[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="118" tap_mode="classic" trigger_index="118" type="unknown"/> + <net data_index="117" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_msg_cnt[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="117" tap_mode="classic" trigger_index="117" type="unknown"/> + <net data_index="116" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_msg_cnt[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="116" tap_mode="classic" trigger_index="116" type="unknown"/> + <net data_index="109" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_msg_cnt[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="109" tap_mode="classic" trigger_index="109" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="controller:controller_0|rx_rd_ptr[10..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="127" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_rd_ptr[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="127" tap_mode="classic" trigger_index="127" type="unknown"/> + <net data_index="136" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_rd_ptr[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="136" tap_mode="classic" trigger_index="136" type="unknown"/> + <net data_index="135" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_rd_ptr[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="135" tap_mode="classic" trigger_index="135" type="unknown"/> + <net data_index="134" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_rd_ptr[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="134" tap_mode="classic" trigger_index="134" type="unknown"/> + <net data_index="133" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_rd_ptr[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="133" tap_mode="classic" trigger_index="133" type="unknown"/> + <net data_index="132" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_rd_ptr[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="132" tap_mode="classic" trigger_index="132" type="unknown"/> + <net data_index="131" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_rd_ptr[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="131" tap_mode="classic" trigger_index="131" type="unknown"/> + <net data_index="130" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_rd_ptr[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="130" tap_mode="classic" trigger_index="130" type="unknown"/> + <net data_index="129" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_rd_ptr[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="129" tap_mode="classic" trigger_index="129" type="unknown"/> + <net data_index="128" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_rd_ptr[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="128" tap_mode="classic" trigger_index="128" type="unknown"/> + <net data_index="126" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_rd_ptr[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="126" tap_mode="classic" trigger_index="126" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="controller:controller_0|rx_wr_ptr[10..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="138" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_wr_ptr[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="138" tap_mode="classic" trigger_index="138" type="unknown"/> + <net data_index="147" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_wr_ptr[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="147" tap_mode="classic" trigger_index="147" type="unknown"/> + <net data_index="146" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_wr_ptr[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="146" tap_mode="classic" trigger_index="146" type="unknown"/> + <net data_index="145" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_wr_ptr[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="145" tap_mode="classic" trigger_index="145" type="unknown"/> + <net data_index="144" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_wr_ptr[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="144" tap_mode="classic" trigger_index="144" type="unknown"/> + <net data_index="143" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_wr_ptr[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="143" tap_mode="classic" trigger_index="143" type="unknown"/> + <net data_index="142" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_wr_ptr[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="142" tap_mode="classic" trigger_index="142" type="unknown"/> + <net data_index="141" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_wr_ptr[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="141" tap_mode="classic" trigger_index="141" type="unknown"/> + <net data_index="140" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_wr_ptr[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="140" tap_mode="classic" trigger_index="140" type="unknown"/> + <net data_index="139" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_wr_ptr[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="139" tap_mode="classic" trigger_index="139" type="unknown"/> + <net data_index="137" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|rx_wr_ptr[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="137" tap_mode="classic" trigger_index="137" type="unknown"/> + </bus> + <net data_index="16" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr_ro" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="16" tap_mode="classic" trigger_index="16" type="unknown"/> + <net data_index="17" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr_valid" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="17" tap_mode="classic" trigger_index="17" type="unknown"/> + <net data_index="50" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_error" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="50" tap_mode="classic" trigger_index="50" type="unknown"/> + <bus is_selected="false" level-0="alt_or" name="controller:controller_0|msg_addr[15..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="6" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="6" tap_mode="classic" trigger_index="6" type="unknown"/> + <net data_index="5" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="5" tap_mode="classic" trigger_index="5" type="unknown"/> + <net data_index="4" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="4" tap_mode="classic" trigger_index="4" type="unknown"/> + <net data_index="3" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="3" tap_mode="classic" trigger_index="3" type="unknown"/> + <net data_index="2" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="2" tap_mode="classic" trigger_index="2" type="unknown"/> + <net data_index="1" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="1" tap_mode="classic" trigger_index="1" type="unknown"/> + <net data_index="15" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="15" tap_mode="classic" trigger_index="15" type="unknown"/> + <net data_index="14" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="14" tap_mode="classic" trigger_index="14" type="unknown"/> + <net data_index="13" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="13" tap_mode="classic" trigger_index="13" type="unknown"/> + <net data_index="12" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="12" tap_mode="classic" trigger_index="12" type="unknown"/> + <net data_index="11" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="11" tap_mode="classic" trigger_index="11" type="unknown"/> + <net data_index="10" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="10" tap_mode="classic" trigger_index="10" type="unknown"/> + <net data_index="9" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="9" tap_mode="classic" trigger_index="9" type="unknown"/> + <net data_index="8" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="8" tap_mode="classic" trigger_index="8" type="unknown"/> + <net data_index="7" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="7" tap_mode="classic" trigger_index="7" type="unknown"/> + <net data_index="0" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_addr[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="0" tap_mode="classic" trigger_index="0" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="controller:controller_0|msg_data[31..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="42" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[31]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="42" tap_mode="classic" trigger_index="42" type="unknown"/> + <net data_index="41" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[30]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="41" tap_mode="classic" trigger_index="41" type="unknown"/> + <net data_index="39" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[29]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="39" tap_mode="classic" trigger_index="39" type="unknown"/> + <net data_index="38" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[28]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="38" tap_mode="classic" trigger_index="38" type="unknown"/> + <net data_index="37" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[27]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="37" tap_mode="classic" trigger_index="37" type="unknown"/> + <net data_index="36" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[26]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="36" tap_mode="classic" trigger_index="36" type="unknown"/> + <net data_index="35" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[25]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="35" tap_mode="classic" trigger_index="35" type="unknown"/> + <net data_index="34" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[24]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="34" tap_mode="classic" trigger_index="34" type="unknown"/> + <net data_index="33" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[23]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="33" tap_mode="classic" trigger_index="33" type="unknown"/> + <net data_index="32" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[22]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="32" tap_mode="classic" trigger_index="32" type="unknown"/> + <net data_index="31" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[21]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="31" tap_mode="classic" trigger_index="31" type="unknown"/> + <net data_index="30" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[20]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="30" tap_mode="classic" trigger_index="30" type="unknown"/> + <net data_index="28" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[19]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="28" tap_mode="classic" trigger_index="28" type="unknown"/> + <net data_index="27" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[18]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="27" tap_mode="classic" trigger_index="27" type="unknown"/> + <net data_index="26" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[17]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="26" tap_mode="classic" trigger_index="26" type="unknown"/> + <net data_index="25" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[16]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="25" tap_mode="classic" trigger_index="25" type="unknown"/> + <net data_index="24" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="24" tap_mode="classic" trigger_index="24" type="unknown"/> + <net data_index="23" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="23" tap_mode="classic" trigger_index="23" type="unknown"/> + <net data_index="22" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="22" tap_mode="classic" trigger_index="22" type="unknown"/> + <net data_index="21" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="21" tap_mode="classic" trigger_index="21" type="unknown"/> + <net data_index="20" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="20" tap_mode="classic" trigger_index="20" type="unknown"/> + <net data_index="19" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="19" tap_mode="classic" trigger_index="19" type="unknown"/> + <net data_index="49" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="49" tap_mode="classic" trigger_index="49" type="unknown"/> + <net data_index="48" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="48" tap_mode="classic" trigger_index="48" type="unknown"/> + <net data_index="47" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="47" tap_mode="classic" trigger_index="47" type="unknown"/> + <net data_index="46" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="46" tap_mode="classic" trigger_index="46" type="unknown"/> + <net data_index="45" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="45" tap_mode="classic" trigger_index="45" type="unknown"/> + <net data_index="44" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="44" tap_mode="classic" trigger_index="44" type="unknown"/> + <net data_index="43" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="43" tap_mode="classic" trigger_index="43" type="unknown"/> + <net data_index="40" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="40" tap_mode="classic" trigger_index="40" type="unknown"/> + <net data_index="29" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="29" tap_mode="classic" trigger_index="29" type="unknown"/> + <net data_index="18" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_data[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="18" tap_mode="classic" trigger_index="18" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="controller:controller_0|msg_response[31..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="75" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[31]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="75" tap_mode="classic" trigger_index="75" type="unknown"/> + <net data_index="74" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[30]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="74" tap_mode="classic" trigger_index="74" type="unknown"/> + <net data_index="72" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[29]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="72" tap_mode="classic" trigger_index="72" type="unknown"/> + <net data_index="71" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[28]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="71" tap_mode="classic" trigger_index="71" type="unknown"/> + <net data_index="70" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[27]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="70" tap_mode="classic" trigger_index="70" type="unknown"/> + <net data_index="69" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[26]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="69" tap_mode="classic" trigger_index="69" type="unknown"/> + <net data_index="68" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[25]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="68" tap_mode="classic" trigger_index="68" type="unknown"/> + <net data_index="67" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[24]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="67" tap_mode="classic" trigger_index="67" type="unknown"/> + <net data_index="66" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[23]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="66" tap_mode="classic" trigger_index="66" type="unknown"/> + <net data_index="65" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[22]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="65" tap_mode="classic" trigger_index="65" type="unknown"/> + <net data_index="64" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[21]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="64" tap_mode="classic" trigger_index="64" type="unknown"/> + <net data_index="63" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[20]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="63" tap_mode="classic" trigger_index="63" type="unknown"/> + <net data_index="61" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[19]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="61" tap_mode="classic" trigger_index="61" type="unknown"/> + <net data_index="60" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[18]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="60" tap_mode="classic" trigger_index="60" type="unknown"/> + <net data_index="59" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[17]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="59" tap_mode="classic" trigger_index="59" type="unknown"/> + <net data_index="58" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[16]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="58" tap_mode="classic" trigger_index="58" type="unknown"/> + <net data_index="57" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="57" tap_mode="classic" trigger_index="57" type="unknown"/> + <net data_index="56" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="56" tap_mode="classic" trigger_index="56" type="unknown"/> + <net data_index="55" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="55" tap_mode="classic" trigger_index="55" type="unknown"/> + <net data_index="54" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="54" tap_mode="classic" trigger_index="54" type="unknown"/> + <net data_index="53" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="53" tap_mode="classic" trigger_index="53" type="unknown"/> + <net data_index="52" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="52" tap_mode="classic" trigger_index="52" type="unknown"/> + <net data_index="82" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="82" tap_mode="classic" trigger_index="82" type="unknown"/> + <net data_index="81" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="81" tap_mode="classic" trigger_index="81" type="unknown"/> + <net data_index="80" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="80" tap_mode="classic" trigger_index="80" type="unknown"/> + <net data_index="79" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="79" tap_mode="classic" trigger_index="79" type="unknown"/> + <net data_index="78" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="78" tap_mode="classic" trigger_index="78" type="unknown"/> + <net data_index="77" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="77" tap_mode="classic" trigger_index="77" type="unknown"/> + <net data_index="76" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="76" tap_mode="classic" trigger_index="76" type="unknown"/> + <net data_index="73" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="73" tap_mode="classic" trigger_index="73" type="unknown"/> + <net data_index="62" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="62" tap_mode="classic" trigger_index="62" type="unknown"/> + <net data_index="51" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_response[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="51" tap_mode="classic" trigger_index="51" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="controller:controller_0|msg_token[7..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="90" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_token[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="90" tap_mode="classic" trigger_index="90" type="unknown"/> + <net data_index="89" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_token[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="89" tap_mode="classic" trigger_index="89" type="unknown"/> + <net data_index="88" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_token[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="88" tap_mode="classic" trigger_index="88" type="unknown"/> + <net data_index="87" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_token[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="87" tap_mode="classic" trigger_index="87" type="unknown"/> + <net data_index="86" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_token[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="86" tap_mode="classic" trigger_index="86" type="unknown"/> + <net data_index="85" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_token[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="85" tap_mode="classic" trigger_index="85" type="unknown"/> + <net data_index="84" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_token[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="84" tap_mode="classic" trigger_index="84" type="unknown"/> + <net data_index="83" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_token[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="83" tap_mode="classic" trigger_index="83" type="unknown"/> + </bus> + <bus is_selected="false" level-0="alt_or" name="controller:controller_0|msg_type[7..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register"> + <net data_index="98" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_type[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="98" tap_mode="classic" trigger_index="98" type="unknown"/> + <net data_index="97" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_type[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="97" tap_mode="classic" trigger_index="97" type="unknown"/> + <net data_index="96" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_type[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="96" tap_mode="classic" trigger_index="96" type="unknown"/> + <net data_index="95" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_type[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="95" tap_mode="classic" trigger_index="95" type="unknown"/> + <net data_index="94" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_type[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="94" tap_mode="classic" trigger_index="94" type="unknown"/> + <net data_index="93" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_type[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="93" tap_mode="classic" trigger_index="93" type="unknown"/> + <net data_index="92" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_type[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="92" tap_mode="classic" trigger_index="92" type="unknown"/> + <net data_index="91" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="controller:controller_0|msg_type[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="91" tap_mode="classic" trigger_index="91" type="unknown"/> + </bus> + </setup_view> + <trigger_in_editor/> + <trigger_out_editor/> + </presentation> + <trigger CRC="86485084" attribute_mem_mode="false" gap_record="true" global_temp="1" is_expanded="true" name="trigger: 2025/11/23 22:56:08 #0" position="pre" power_up_trigger_mode="false" record_data_gap="true" segment_size="64" storage_mode="off" storage_qualifier_disabled="no" storage_qualifier_port_is_pin="true" storage_qualifier_port_name="auto_stp_external_storage_qualifier" storage_qualifier_port_tap_mode="classic" trigger_type="circular"> + <power_up_trigger position="pre" storage_qualifier_disabled="no"/> + <events use_custom_flow_control="no"> + <level enabled="yes" name="condition1" type="basic">'controller:controller_0|rx_msg_captured' == high + <power_up enabled="yes"> + </power_up><op_node/> + </level> + </events> + <storage_qualifier_events> + <transitional>1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 + <pwr_up_transitional>1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111</pwr_up_transitional> + </transitional> + <storage_qualifier_level type="basic"> + <power_up> + </power_up> + <op_node/> + </storage_qualifier_level> + <storage_qualifier_level type="basic"> + <power_up> + </power_up> + <op_node/> + </storage_qualifier_level> + <storage_qualifier_level type="basic"> + <power_up> + </power_up> + <op_node/> + </storage_qualifier_level> + </storage_qualifier_events> + <log> + <data global_temp="1" name="log: Trig @ 2025/12/21 16:42:50 (0:0:1.2 elapsed) #1" power_up_mode="false" sample_depth="255" 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attribute="advanced trigger node widget height" value="204"/> + <single attribute="advanced trigger node widget width" value="409"/> + <single attribute="config widget visible" value="1"/> + <single attribute="data log widget visible" value="1"/> + <single attribute="hierarchy widget height" value="222"/> + <single attribute="hierarchy widget visible" value="1"/> + <single attribute="instance widget visible" value="1"/> + <single attribute="jtag widget visible" value="1"/> + <single attribute="lock mode" value="0"/> + <multi attribute="column width" size="23" value="34,34,390,74,68,78,95,96,98,98,88,88,110,101,101,101,101,101,101,101,101,107,78"/> + <multi attribute="frame size" size="2" value="1920,1011"/> + <multi attribute="jtag widget size" size="2" value="506,228"/> + </global_info> +</session> diff --git a/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio.bsf b/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio.bsf new file mode 100644 index 0000000..9eba5e3 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio.bsf @@ -0,0 +1,114 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 2025 Altera Corporation. All rights reserved. +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, the Altera Quartus Prime License Agreement, +the Altera IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Altera and sold by Altera or its authorized distributors. Please +refer to the Altera Software License Subscription Agreements +on the Quartus Prime software download page. +*/ +(header "symbol" (version "1.2")) +(symbol + (rect 0 0 224 192) + (text "ddrio" (rect 98 -2 136 16)(font "Dialog" (font_size 10))) + (text "inst" (rect 8 177 24 188)(font "Arial" )) + (port + (pt 0 48) + (input) + (text "datain_h[7..0]" (rect 0 0 82 15)(font "Dialog" (font_size 8))) + (text "datain_h[7..0]" (rect 4 33 73 47)(font "Dialog" (font_size 8))) + (line (pt 0 48)(pt 80 48)(line_width 3)) + ) + (port + (pt 0 64) + (input) + (text "datain_l[7..0]" (rect 0 0 79 15)(font "Dialog" (font_size 8))) + (text "datain_l[7..0]" (rect 4 49 69 63)(font "Dialog" (font_size 8))) + (line (pt 0 64)(pt 80 64)(line_width 3)) + ) + (port + (pt 0 80) + (input) + (text "oe" (rect 0 0 15 15)(font "Dialog" (font_size 8))) + (text "oe" (rect 4 65 16 79)(font "Dialog" (font_size 8))) + (line (pt 0 80)(pt 80 80)) + ) + (port + (pt 0 96) + (input) + (text "inclock" (rect 0 0 42 15)(font "Dialog" (font_size 8))) + (text "inclock" (rect 4 81 39 95)(font "Dialog" (font_size 8))) + (line (pt 0 96)(pt 80 96)) + ) + (port + (pt 0 112) + (input) + (text "inclocken" (rect 0 0 57 15)(font "Dialog" (font_size 8))) + (text "inclocken" (rect 4 97 51 111)(font "Dialog" (font_size 8))) + (line (pt 0 112)(pt 80 112)) + ) + (port + (pt 0 128) + (input) + (text "outclock" (rect 0 0 51 15)(font "Dialog" (font_size 8))) + (text "outclock" (rect 4 113 47 127)(font "Dialog" (font_size 8))) + (line (pt 0 128)(pt 80 128)) + ) + (port + (pt 0 144) + (input) + (text "outclocken" (rect 0 0 67 15)(font "Dialog" (font_size 8))) + (text "outclocken" (rect 4 129 59 143)(font "Dialog" (font_size 8))) + (line (pt 0 144)(pt 80 144)) + ) + (port + (pt 0 160) + (input) + (text "aclr" (rect 0 0 22 15)(font "Dialog" (font_size 8))) + (text "aclr" (rect 4 145 23 159)(font "Dialog" (font_size 8))) + (line (pt 0 160)(pt 80 160)) + ) + (port + (pt 224 48) + (output) + (text "dataout_h[7..0]" (rect 0 0 92 15)(font "Dialog" (font_size 8))) + (text "dataout_h[7..0]" (rect 158 33 235 47)(font "Dialog" (font_size 8))) + (line (pt 224 48)(pt 144 48)(line_width 3)) + ) + (port + (pt 224 64) + (output) + (text "dataout_l[7..0]" (rect 0 0 87 15)(font "Dialog" (font_size 8))) + (text "dataout_l[7..0]" (rect 162 49 235 63)(font "Dialog" (font_size 8))) + (line (pt 224 64)(pt 144 64)(line_width 3)) + ) + (port + (pt 224 80) + (output) + (text "padio[7..0]" (rect 0 0 64 15)(font "Dialog" (font_size 8))) + (text "padio[7..0]" (rect 177 65 231 79)(font "Dialog" (font_size 8))) + (line (pt 224 80)(pt 144 80)(line_width 3)) + ) + (drawing + (line (pt 80 32)(pt 144 32)) + (line (pt 144 32)(pt 144 176)) + (line (pt 80 176)(pt 144 176)) + (line (pt 80 32)(pt 80 176)) + (line (pt 0 0)(pt 224 0)) + (line (pt 224 0)(pt 224 192)) + (line (pt 0 192)(pt 224 192)) + (line (pt 0 0)(pt 0 192)) + ) +) diff --git a/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio.ppf b/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio.ppf new file mode 100644 index 0000000..03c4cef --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio.ppf @@ -0,0 +1,18 @@ +<?xml version="1.0" encoding="UTF-8" ?> +<!DOCTYPE pinplan> +<pinplan intended_family="Cyclone 10 LP" variation_name="ddrio" megafunction_name="ALTDDIO_BIDIR" specifies="all_ports"> +<global> +<pin name="aclr" direction="input" scope="external" /> +<pin name="datain_h[7..0]" direction="input" scope="external" /> +<pin name="datain_l[7..0]" direction="input" scope="external" /> +<pin name="inclock" direction="input" scope="external" source="clock" /> +<pin name="inclocken" direction="input" scope="external" /> +<pin name="oe" direction="input" scope="external" /> +<pin name="outclock" direction="input" scope="external" source="clock" /> +<pin name="outclocken" direction="input" scope="external" /> +<pin name="dataout_h[7..0]" direction="output" scope="external" /> +<pin name="dataout_l[7..0]" direction="output" scope="external" /> +<pin name="padio[7..0]" direction="bidir" scope="external" /> + +</global> +</pinplan> diff --git a/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio.qip b/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio.qip new file mode 100644 index 0000000..b3dfeb4 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio.qip @@ -0,0 +1,8 @@ +set_global_assignment -name IP_TOOL_NAME "ALTDDIO_BIDIR" +set_global_assignment -name IP_TOOL_VERSION "25.1" +set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone 10 LP}" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ddrio.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddrio.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddrio_inst.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddrio_bb.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddrio.ppf"] diff --git a/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio.v b/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio.v new file mode 100644 index 0000000..44b81db --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio.v @@ -0,0 +1,145 @@ +// megafunction wizard: %ALTDDIO_BIDIR% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: ALTDDIO_BIDIR + +// ============================================================ +// File Name: ddrio.v +// Megafunction Name(s): +// ALTDDIO_BIDIR +// +// Simulation Library Files(s): +// +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 25.1std.0 Build 1129 10/21/2025 SC Standard Edition +// ************************************************************ + + +//Copyright (C) 2025 Altera Corporation. All rights reserved. +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and any partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, the Altera Quartus Prime License Agreement, +//the Altera IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Altera and sold by Altera or its authorized distributors. Please +//refer to the Altera Software License Subscription Agreements +//on the Quartus Prime software download page. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module ddrio ( + aclr, + datain_h, + datain_l, + inclock, + inclocken, + oe, + outclock, + outclocken, + dataout_h, + dataout_l, + padio); + + input aclr; + input [7:0] datain_h; + input [7:0] datain_l; + input inclock; + input inclocken; + input oe; + input outclock; + input outclocken; + output [7:0] dataout_h; + output [7:0] dataout_l; + inout [7:0] padio; + + wire [7:0] sub_wire0; + wire [7:0] sub_wire1; + wire [7:0] dataout_h = sub_wire0[7:0]; + wire [7:0] dataout_l = sub_wire1[7:0]; + + altddio_bidir ALTDDIO_BIDIR_component ( + .padio (padio), + .aclr (aclr), + .datain_h (datain_h), + .datain_l (datain_l), + .inclock (inclock), + .inclocken (inclocken), + .oe (oe), + .outclock (outclock), + .outclocken (outclocken), + .dataout_h (sub_wire0), + .dataout_l (sub_wire1), + .aset (1'b0), + .combout (), + .dqsundelayedout (), + .oe_out (), + .sclr (1'b0), + .sset (1'b0)); + defparam + ALTDDIO_BIDIR_component.extend_oe_disable = "ON", + ALTDDIO_BIDIR_component.implement_input_in_lcell = "ON", + ALTDDIO_BIDIR_component.intended_device_family = "Cyclone 10 LP", + ALTDDIO_BIDIR_component.invert_output = "OFF", + ALTDDIO_BIDIR_component.lpm_hint = "UNUSED", + ALTDDIO_BIDIR_component.lpm_type = "altddio_bidir", + ALTDDIO_BIDIR_component.oe_reg = "REGISTERED", + ALTDDIO_BIDIR_component.power_up_high = "OFF", + ALTDDIO_BIDIR_component.width = 8; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP" +// Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "ON" +// Retrieval info: CONSTANT: IMPLEMENT_INPUT_IN_LCELL STRING "ON" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP" +// Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF" +// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_bidir" +// Retrieval info: CONSTANT: OE_REG STRING "REGISTERED" +// Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF" +// Retrieval info: CONSTANT: WIDTH NUMERIC "8" +// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr" +// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +// Retrieval info: USED_PORT: datain_h 0 0 8 0 INPUT NODEFVAL "datain_h[7..0]" +// Retrieval info: CONNECT: @datain_h 0 0 8 0 datain_h 0 0 8 0 +// Retrieval info: USED_PORT: datain_l 0 0 8 0 INPUT NODEFVAL "datain_l[7..0]" +// Retrieval info: CONNECT: @datain_l 0 0 8 0 datain_l 0 0 8 0 +// Retrieval info: USED_PORT: dataout_h 0 0 8 0 OUTPUT NODEFVAL "dataout_h[7..0]" +// Retrieval info: CONNECT: dataout_h 0 0 8 0 @dataout_h 0 0 8 0 +// Retrieval info: USED_PORT: dataout_l 0 0 8 0 OUTPUT NODEFVAL "dataout_l[7..0]" +// Retrieval info: CONNECT: dataout_l 0 0 8 0 @dataout_l 0 0 8 0 +// Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "inclock" +// Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0 +// Retrieval info: USED_PORT: inclocken 0 0 0 0 INPUT NODEFVAL "inclocken" +// Retrieval info: CONNECT: @inclocken 0 0 0 0 inclocken 0 0 0 0 +// Retrieval info: USED_PORT: oe 0 0 0 0 INPUT NODEFVAL "oe" +// Retrieval info: CONNECT: @oe 0 0 0 0 oe 0 0 0 0 +// Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "outclock" +// Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0 +// Retrieval info: USED_PORT: outclocken 0 0 0 0 INPUT NODEFVAL "outclocken" +// Retrieval info: CONNECT: @outclocken 0 0 0 0 outclocken 0 0 0 0 +// Retrieval info: USED_PORT: padio 0 0 8 0 BIDIR NODEFVAL "padio[7..0]" +// Retrieval info: CONNECT: padio 0 0 8 0 @padio 0 0 8 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio.v TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio.qip TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio.bsf TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio_inst.v TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio_bb.v TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio.inc FALSE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio.cmp FALSE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio.ppf TRUE FALSE diff --git a/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio_bb.v b/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio_bb.v new file mode 100644 index 0000000..f489c24 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio_bb.v @@ -0,0 +1,105 @@ +// megafunction wizard: %ALTDDIO_BIDIR%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: ALTDDIO_BIDIR + +// ============================================================ +// File Name: ddrio.v +// Megafunction Name(s): +// ALTDDIO_BIDIR +// +// Simulation Library Files(s): +// +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 25.1std.0 Build 1129 10/21/2025 SC Standard Edition +// ************************************************************ + +//Copyright (C) 2025 Altera Corporation. All rights reserved. +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and any partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, the Altera Quartus Prime License Agreement, +//the Altera IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Altera and sold by Altera or its authorized distributors. Please +//refer to the Altera Software License Subscription Agreements +//on the Quartus Prime software download page. + +module ddrio ( + aclr, + datain_h, + datain_l, + inclock, + inclocken, + oe, + outclock, + outclocken, + dataout_h, + dataout_l, + padio); + + input aclr; + input [7:0] datain_h; + input [7:0] datain_l; + input inclock; + input inclocken; + input oe; + input outclock; + input outclocken; + output [7:0] dataout_h; + output [7:0] dataout_l; + inout [7:0] padio; + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP" +// Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "ON" +// Retrieval info: CONSTANT: IMPLEMENT_INPUT_IN_LCELL STRING "ON" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP" +// Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF" +// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_bidir" +// Retrieval info: CONSTANT: OE_REG STRING "REGISTERED" +// Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF" +// Retrieval info: CONSTANT: WIDTH NUMERIC "8" +// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr" +// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +// Retrieval info: USED_PORT: datain_h 0 0 8 0 INPUT NODEFVAL "datain_h[7..0]" +// Retrieval info: CONNECT: @datain_h 0 0 8 0 datain_h 0 0 8 0 +// Retrieval info: USED_PORT: datain_l 0 0 8 0 INPUT NODEFVAL "datain_l[7..0]" +// Retrieval info: CONNECT: @datain_l 0 0 8 0 datain_l 0 0 8 0 +// Retrieval info: USED_PORT: dataout_h 0 0 8 0 OUTPUT NODEFVAL "dataout_h[7..0]" +// Retrieval info: CONNECT: dataout_h 0 0 8 0 @dataout_h 0 0 8 0 +// Retrieval info: USED_PORT: dataout_l 0 0 8 0 OUTPUT NODEFVAL "dataout_l[7..0]" +// Retrieval info: CONNECT: dataout_l 0 0 8 0 @dataout_l 0 0 8 0 +// Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "inclock" +// Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0 +// Retrieval info: USED_PORT: inclocken 0 0 0 0 INPUT NODEFVAL "inclocken" +// Retrieval info: CONNECT: @inclocken 0 0 0 0 inclocken 0 0 0 0 +// Retrieval info: USED_PORT: oe 0 0 0 0 INPUT NODEFVAL "oe" +// Retrieval info: CONNECT: @oe 0 0 0 0 oe 0 0 0 0 +// Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "outclock" +// Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0 +// Retrieval info: USED_PORT: outclocken 0 0 0 0 INPUT NODEFVAL "outclocken" +// Retrieval info: CONNECT: @outclocken 0 0 0 0 outclocken 0 0 0 0 +// Retrieval info: USED_PORT: padio 0 0 8 0 BIDIR NODEFVAL "padio[7..0]" +// Retrieval info: CONNECT: padio 0 0 8 0 @padio 0 0 8 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio.v TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio.qip TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio.bsf TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio_inst.v TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio_bb.v TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio.inc FALSE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio.cmp FALSE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio.ppf TRUE FALSE diff --git a/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio_inst.v b/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio_inst.v new file mode 100644 index 0000000..a999d47 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio_inst.v @@ -0,0 +1,13 @@ +ddrio ddrio_inst ( + .aclr ( aclr_sig ), + .datain_h ( datain_h_sig ), + .datain_l ( datain_l_sig ), + .inclock ( inclock_sig ), + .inclocken ( inclocken_sig ), + .oe ( oe_sig ), + .outclock ( outclock_sig ), + .outclocken ( outclocken_sig ), + .dataout_h ( dataout_h_sig ), + .dataout_l ( dataout_l_sig ), + .padio ( padio_sig ) + ); diff --git a/manufacturer/altera/cyclone10_lp/ip/pll/pll.bsf b/manufacturer/altera/cyclone10_lp/ip/pll/pll.bsf new file mode 100644 index 0000000..0e82eda --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/pll/pll.bsf @@ -0,0 +1,96 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 2025 Altera Corporation. All rights reserved. +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, the Altera Quartus Prime License Agreement, +the Altera IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Altera and sold by Altera or its authorized distributors. Please +refer to the Altera Software License Subscription Agreements +on the Quartus Prime software download page. +*/ +(header "symbol" (version "1.2")) +(symbol + (rect 0 0 272 160) + (text "pll" (rect 129 0 144 15)(font "Arial" (font_size 10))) + (text "inst" (rect 8 145 24 156)(font "Arial" )) + (port + (pt 0 64) + (input) + (text "inclk0" (rect 0 0 34 13)(font "Arial" (font_size 8))) + (text "inclk0" (rect 4 52 31 63)(font "Arial" (font_size 8))) + (line (pt 0 64)(pt 48 64)) + ) + (port + (pt 0 80) + (input) + (text "areset" (rect 0 0 36 13)(font "Arial" (font_size 8))) + (text "areset" (rect 4 68 34 79)(font "Arial" (font_size 8))) + (line (pt 0 80)(pt 48 80)) + ) + (port + (pt 272 64) + (output) + (text "c0" (rect 0 0 14 13)(font "Arial" (font_size 8))) + (text "c0" (rect 255 52 266 63)(font "Arial" (font_size 8))) + ) + (port + (pt 272 80) + (output) + (text "c1" (rect 0 0 14 13)(font "Arial" (font_size 8))) + (text "c1" (rect 255 68 266 79)(font "Arial" (font_size 8))) + ) + (port + (pt 272 96) + (output) + (text "locked" (rect 0 0 37 13)(font "Arial" (font_size 8))) + (text "locked" (rect 232 84 263 95)(font "Arial" (font_size 8))) + ) + (drawing + (text "Cyclone 10 LP" (rect 186 147 430 303)(font "Arial" )) + (text "inclk0 frequency: 25.000 MHz" (rect 58 60 234 129)(font "Arial" )) + (text "Operation Mode: Normal" (rect 58 71 214 151)(font "Arial" )) + (text "Clk " (rect 59 89 131 187)(font "Arial" )) + (text "Ratio" (rect 80 89 180 187)(font "Arial" )) + (text "Ph (dg)" (rect 107 89 243 187)(font "Arial" )) + (text "DC (%)" (rect 143 89 315 187)(font "Arial" )) + (text "c0" (rect 62 101 133 211)(font "Arial" )) + (text "1/1" (rect 84 101 180 211)(font "Arial" )) + (text "0.00" (rect 113 101 243 211)(font "Arial" )) + (text "50.00" (rect 146 101 314 211)(font "Arial" )) + (text "c1" (rect 62 113 133 235)(font "Arial" )) + (text "5/1" (rect 84 113 180 235)(font "Arial" )) + (text "0.00" (rect 113 113 243 235)(font "Arial" )) + (text "50.00" (rect 146 113 314 235)(font "Arial" )) + (line (pt 0 0)(pt 273 0)) + (line (pt 273 0)(pt 273 161)) + (line (pt 0 161)(pt 273 161)) + (line (pt 0 0)(pt 0 161)) + (line (pt 56 87)(pt 176 87)) + (line (pt 56 98)(pt 176 98)) + (line (pt 56 110)(pt 176 110)) + (line (pt 56 122)(pt 176 122)) + (line (pt 56 87)(pt 56 122)) + (line (pt 77 87)(pt 77 122)(line_width 3)) + (line (pt 104 87)(pt 104 122)(line_width 3)) + (line (pt 140 87)(pt 140 122)(line_width 3)) + (line (pt 175 87)(pt 175 122)) + (line (pt 48 48)(pt 223 48)) + (line (pt 223 48)(pt 223 143)) + (line (pt 48 143)(pt 223 143)) + (line (pt 48 48)(pt 48 143)) + (line (pt 271 64)(pt 223 64)) + (line (pt 271 80)(pt 223 80)) + (line (pt 271 96)(pt 223 96)) + ) +) diff --git a/manufacturer/altera/cyclone10_lp/ip/pll/pll.ppf b/manufacturer/altera/cyclone10_lp/ip/pll/pll.ppf new file mode 100644 index 0000000..f563c40 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/pll/pll.ppf @@ -0,0 +1,12 @@ +<?xml version="1.0" encoding="UTF-8" ?> +<!DOCTYPE pinplan> +<pinplan intended_family="Cyclone 10 LP" variation_name="pll" megafunction_name="ALTPLL" specifies="all_ports"> +<global> +<pin name="areset" direction="input" scope="external" /> +<pin name="inclk0" direction="input" scope="external" source="clock" /> +<pin name="c0" direction="output" scope="external" source="clock" /> +<pin name="c1" direction="output" scope="external" source="clock" /> +<pin name="locked" direction="output" scope="external" /> + +</global> +</pinplan> diff --git a/manufacturer/altera/cyclone10_lp/ip/pll/pll.qip b/manufacturer/altera/cyclone10_lp/ip/pll/pll.qip new file mode 100644 index 0000000..5df3c41 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/pll/pll.qip @@ -0,0 +1,8 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "25.1" +set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone 10 LP}" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_inst.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_bb.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/manufacturer/altera/cyclone10_lp/ip/pll/pll.v b/manufacturer/altera/cyclone10_lp/ip/pll/pll.v new file mode 100644 index 0000000..cbe5878 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/pll/pll.v @@ -0,0 +1,348 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: pll.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 25.1std.0 Build 1129 10/21/2025 SC Standard Edition +// ************************************************************ + + +//Copyright (C) 2025 Altera Corporation. All rights reserved. +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and any partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, the Altera Quartus Prime License Agreement, +//the Altera IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Altera and sold by Altera or its authorized distributors. Please +//refer to the Altera Software License Subscription Agreements +//on the Quartus Prime software download page. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module pll ( + areset, + inclk0, + c0, + c1, + locked); + + input areset; + input inclk0; + output c0; + output c1; + output locked; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri0 areset; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [4:0] sub_wire0; + wire sub_wire3; + wire [0:0] sub_wire6 = 1'h0; + wire [1:1] sub_wire2 = sub_wire0[1:1]; + wire [0:0] sub_wire1 = sub_wire0[0:0]; + wire c0 = sub_wire1; + wire c1 = sub_wire2; + wire locked = sub_wire3; + wire sub_wire4 = inclk0; + wire [1:0] sub_wire5 = {sub_wire6, sub_wire4}; + + altpll altpll_component ( + .areset (areset), + .inclk (sub_wire5), + .clk (sub_wire0), + .locked (sub_wire3), + .activeclock (), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .fref (), + .icdrclk (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.bandwidth_type = "AUTO", + altpll_component.clk0_divide_by = 1, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 1, + altpll_component.clk0_phase_shift = "0", + altpll_component.clk1_divide_by = 1, + altpll_component.clk1_duty_cycle = 50, + altpll_component.clk1_multiply_by = 5, + altpll_component.clk1_phase_shift = "0", + altpll_component.compensate_clock = "CLK0", + altpll_component.inclk0_input_frequency = 40000, + altpll_component.intended_device_family = "Cyclone 10 LP", + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_USED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_USED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_USED", + altpll_component.port_clk2 = "PORT_UNUSED", + altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.self_reset_on_loss_lock = "OFF", + altpll_component.width_clock = 5; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "25.000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "125.000000" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "25.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "125.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLK1 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "5" +// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "40000" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v TRUE +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/manufacturer/altera/cyclone10_lp/ip/pll/pll_bb.v b/manufacturer/altera/cyclone10_lp/ip/pll/pll_bb.v new file mode 100644 index 0000000..0f86c48 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/pll/pll_bb.v @@ -0,0 +1,232 @@ +// megafunction wizard: %ALTPLL%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: pll.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 25.1std.0 Build 1129 10/21/2025 SC Standard Edition +// ************************************************************ + +//Copyright (C) 2025 Altera Corporation. All rights reserved. +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and any partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, the Altera Quartus Prime License Agreement, +//the Altera IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Altera and sold by Altera or its authorized distributors. Please +//refer to the Altera Software License Subscription Agreements +//on the Quartus Prime software download page. + +module pll ( + areset, + inclk0, + c0, + c1, + locked); + + input areset; + input inclk0; + output c0; + output c1; + output locked; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri0 areset; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "25.000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "125.000000" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "25.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "125.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLK1 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "5" +// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "40000" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v TRUE +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/manufacturer/altera/cyclone10_lp/ip/pll/pll_inst.v b/manufacturer/altera/cyclone10_lp/ip/pll/pll_inst.v new file mode 100644 index 0000000..6da79e5 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/pll/pll_inst.v @@ -0,0 +1,7 @@ +pll pll_inst ( + .areset ( areset_sig ), + .inclk0 ( inclk0_sig ), + .c0 ( c0_sig ), + .c1 ( c1_sig ), + .locked ( locked_sig ) + ); diff --git a/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.bsf b/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.bsf new file mode 100644 index 0000000..c5f6b16 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.bsf @@ -0,0 +1,65 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 2025 Altera Corporation. All rights reserved. +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, the Altera Quartus Prime License Agreement, +the Altera IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Altera and sold by Altera or its authorized distributors. Please +refer to the Altera Software License Subscription Agreements +on the Quartus Prime software download page. +*/ +(header "symbol" (version "1.2")) +(symbol + (rect 0 0 208 96) + (text "ddri" (rect 93 -2 122 16)(font "Dialog" (font_size 10))) + (text "inst" (rect 8 81 24 92)(font "Arial" )) + (port + (pt 0 48) + (input) + (text "datain[4..0]" (rect 0 0 69 15)(font "Dialog" (font_size 8))) + (text "datain[4..0]" (rect 4 33 61 47)(font "Dialog" (font_size 8))) + (line (pt 0 48)(pt 64 48)(line_width 3)) + ) + (port + (pt 0 64) + (input) + (text "inclock" (rect 0 0 42 15)(font "Dialog" (font_size 8))) + (text "inclock" (rect 4 49 39 63)(font "Dialog" (font_size 8))) + (line (pt 0 64)(pt 64 64)) + ) + (port + (pt 208 48) + (output) + (text "dataout_l[4..0]" (rect 0 0 87 15)(font "Dialog" (font_size 8))) + (text "dataout_l[4..0]" (rect 146 33 219 47)(font "Dialog" (font_size 8))) + (line (pt 208 48)(pt 128 48)(line_width 3)) + ) + (port + (pt 208 64) + (output) + (text "dataout_h[4..0]" (rect 0 0 92 15)(font "Dialog" (font_size 8))) + (text "dataout_h[4..0]" (rect 142 49 219 63)(font "Dialog" (font_size 8))) + (line (pt 208 64)(pt 128 64)(line_width 3)) + ) + (drawing + (line (pt 64 32)(pt 128 32)) + (line (pt 128 32)(pt 128 80)) + (line (pt 64 80)(pt 128 80)) + (line (pt 64 32)(pt 64 80)) + (line (pt 0 0)(pt 208 0)) + (line (pt 208 0)(pt 208 96)) + (line (pt 0 96)(pt 208 96)) + (line (pt 0 0)(pt 0 96)) + ) +) diff --git a/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.cmp b/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.cmp new file mode 100644 index 0000000..86f1250 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.cmp @@ -0,0 +1,25 @@ +--Copyright (C) 2025 Altera Corporation. All rights reserved. +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and any partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, the Altera Quartus Prime License Agreement, +--the Altera IP License Agreement, or other applicable license +--agreement, including, without limitation, that your use is for +--the sole purpose of programming logic devices manufactured by +--Altera and sold by Altera or its authorized distributors. Please +--refer to the Altera Software License Subscription Agreements +--on the Quartus Prime software download page. + + +component ddri + PORT + ( + datain : IN STD_LOGIC_VECTOR (4 DOWNTO 0); + inclock : IN STD_LOGIC ; + dataout_h : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + dataout_l : OUT STD_LOGIC_VECTOR (4 DOWNTO 0) + ); +end component; diff --git a/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.inc b/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.inc new file mode 100644 index 0000000..3418b17 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.inc @@ -0,0 +1,26 @@ +--Copyright (C) 2025 Altera Corporation. All rights reserved. +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and any partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, the Altera Quartus Prime License Agreement, +--the Altera IP License Agreement, or other applicable license +--agreement, including, without limitation, that your use is for +--the sole purpose of programming logic devices manufactured by +--Altera and sold by Altera or its authorized distributors. Please +--refer to the Altera Software License Subscription Agreements +--on the Quartus Prime software download page. + + +FUNCTION ddri +( + datain[4..0], + inclock +) + +RETURNS ( + dataout_h[4..0], + dataout_l[4..0] +); diff --git a/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.ppf b/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.ppf new file mode 100644 index 0000000..b1742aa --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.ppf @@ -0,0 +1,11 @@ +<?xml version="1.0" encoding="UTF-8" ?> +<!DOCTYPE pinplan> +<pinplan intended_family="Cyclone 10 LP" variation_name="ddri" megafunction_name="ALTDDIO_IN" specifies="all_ports"> +<global> +<pin name="datain[4..0]" direction="input" scope="external" /> +<pin name="inclock" direction="input" scope="external" source="clock" /> +<pin name="dataout_h[4..0]" direction="output" scope="external" /> +<pin name="dataout_l[4..0]" direction="output" scope="external" /> + +</global> +</pinplan> diff --git a/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.qip b/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.qip new file mode 100644 index 0000000..18f0cc0 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.qip @@ -0,0 +1,10 @@ +set_global_assignment -name IP_TOOL_NAME "ALTDDIO_IN" +set_global_assignment -name IP_TOOL_VERSION "25.1" +set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone 10 LP}" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ddri.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddri.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddri_inst.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddri_bb.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddri.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddri.cmp"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddri.ppf"] diff --git a/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.v b/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.v new file mode 100644 index 0000000..f2d0c47 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.v @@ -0,0 +1,103 @@ +// megafunction wizard: %ALTDDIO_IN% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: ALTDDIO_IN + +// ============================================================ +// File Name: ddri.v +// Megafunction Name(s): +// ALTDDIO_IN +// +// Simulation Library Files(s): +// +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 25.1std.0 Build 1129 10/21/2025 SC Standard Edition +// ************************************************************ + + +//Copyright (C) 2025 Altera Corporation. All rights reserved. +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and any partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, the Altera Quartus Prime License Agreement, +//the Altera IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Altera and sold by Altera or its authorized distributors. Please +//refer to the Altera Software License Subscription Agreements +//on the Quartus Prime software download page. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module ddri ( + datain, + inclock, + dataout_h, + dataout_l); + + input [4:0] datain; + input inclock; + output [4:0] dataout_h; + output [4:0] dataout_l; + + wire [4:0] sub_wire0; + wire [4:0] sub_wire1; + wire [4:0] dataout_h = sub_wire0[4:0]; + wire [4:0] dataout_l = sub_wire1[4:0]; + + altddio_in ALTDDIO_IN_component ( + .datain (datain), + .inclock (inclock), + .dataout_h (sub_wire0), + .dataout_l (sub_wire1), + .aclr (1'b0), + .aset (1'b0), + .inclocken (1'b1), + .sclr (1'b0), + .sset (1'b0)); + defparam + ALTDDIO_IN_component.intended_device_family = "Cyclone 10 LP", + ALTDDIO_IN_component.invert_input_clocks = "OFF", + ALTDDIO_IN_component.lpm_hint = "UNUSED", + ALTDDIO_IN_component.lpm_type = "altddio_in", + ALTDDIO_IN_component.power_up_high = "ON", + ALTDDIO_IN_component.width = 5; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP" +// Retrieval info: CONSTANT: INVERT_INPUT_CLOCKS STRING "OFF" +// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_in" +// Retrieval info: CONSTANT: POWER_UP_HIGH STRING "ON" +// Retrieval info: CONSTANT: WIDTH NUMERIC "5" +// Retrieval info: USED_PORT: datain 0 0 5 0 INPUT NODEFVAL "datain[4..0]" +// Retrieval info: CONNECT: @datain 0 0 5 0 datain 0 0 5 0 +// Retrieval info: USED_PORT: dataout_h 0 0 5 0 OUTPUT NODEFVAL "dataout_h[4..0]" +// Retrieval info: CONNECT: dataout_h 0 0 5 0 @dataout_h 0 0 5 0 +// Retrieval info: USED_PORT: dataout_l 0 0 5 0 OUTPUT NODEFVAL "dataout_l[4..0]" +// Retrieval info: CONNECT: dataout_l 0 0 5 0 @dataout_l 0 0 5 0 +// Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "inclock" +// Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL ddri.v TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddri.qip TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddri.bsf TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddri_inst.v TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddri_bb.v TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddri.inc TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddri.cmp TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddri.ppf TRUE FALSE diff --git a/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri_bb.v b/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri_bb.v new file mode 100644 index 0000000..ec7ac20 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri_bb.v @@ -0,0 +1,74 @@ +// megafunction wizard: %ALTDDIO_IN%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: ALTDDIO_IN + +// ============================================================ +// File Name: ddri.v +// Megafunction Name(s): +// ALTDDIO_IN +// +// Simulation Library Files(s): +// +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 25.1std.0 Build 1129 10/21/2025 SC Standard Edition +// ************************************************************ + +//Copyright (C) 2025 Altera Corporation. All rights reserved. +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and any partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, the Altera Quartus Prime License Agreement, +//the Altera IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Altera and sold by Altera or its authorized distributors. Please +//refer to the Altera Software License Subscription Agreements +//on the Quartus Prime software download page. + +module ddri ( + datain, + inclock, + dataout_h, + dataout_l); + + input [4:0] datain; + input inclock; + output [4:0] dataout_h; + output [4:0] dataout_l; + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP" +// Retrieval info: CONSTANT: INVERT_INPUT_CLOCKS STRING "OFF" +// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_in" +// Retrieval info: CONSTANT: POWER_UP_HIGH STRING "ON" +// Retrieval info: CONSTANT: WIDTH NUMERIC "5" +// Retrieval info: USED_PORT: datain 0 0 5 0 INPUT NODEFVAL "datain[4..0]" +// Retrieval info: CONNECT: @datain 0 0 5 0 datain 0 0 5 0 +// Retrieval info: USED_PORT: dataout_h 0 0 5 0 OUTPUT NODEFVAL "dataout_h[4..0]" +// Retrieval info: CONNECT: dataout_h 0 0 5 0 @dataout_h 0 0 5 0 +// Retrieval info: USED_PORT: dataout_l 0 0 5 0 OUTPUT NODEFVAL "dataout_l[4..0]" +// Retrieval info: CONNECT: dataout_l 0 0 5 0 @dataout_l 0 0 5 0 +// Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "inclock" +// Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL ddri.v TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddri.qip TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddri.bsf TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddri_inst.v TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddri_bb.v TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddri.inc TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddri.cmp TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddri.ppf TRUE FALSE diff --git a/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri_inst.v b/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri_inst.v new file mode 100644 index 0000000..0574ba9 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri_inst.v @@ -0,0 +1,6 @@ +ddri ddri_inst ( + .datain ( datain_sig ), + .inclock ( inclock_sig ), + .dataout_h ( dataout_h_sig ), + .dataout_l ( dataout_l_sig ) + ); diff --git a/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.bsf b/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.bsf new file mode 100644 index 0000000..1cf5c0d --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.bsf @@ -0,0 +1,79 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 2025 Altera Corporation. All rights reserved. +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, the Altera Quartus Prime License Agreement, +the Altera IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Altera and sold by Altera or its authorized distributors. Please +refer to the Altera Software License Subscription Agreements +on the Quartus Prime software download page. +*/ +(header "symbol" (version "1.2")) +(symbol + (rect 0 0 224 144) + (text "ddro" (rect 99 -2 133 16)(font "Dialog" (font_size 10))) + (text "inst" (rect 8 129 24 140)(font "Arial" )) + (port + (pt 0 48) + (input) + (text "datain_h[5..0]" (rect 0 0 82 15)(font "Dialog" (font_size 8))) + (text "datain_h[5..0]" (rect 4 33 73 47)(font "Dialog" (font_size 8))) + (line (pt 0 48)(pt 80 48)(line_width 3)) + ) + (port + (pt 0 64) + (input) + (text "datain_l[5..0]" (rect 0 0 79 15)(font "Dialog" (font_size 8))) + (text "datain_l[5..0]" (rect 4 49 69 63)(font "Dialog" (font_size 8))) + (line (pt 0 64)(pt 80 64)(line_width 3)) + ) + (port + (pt 0 80) + (input) + (text "oe" (rect 0 0 15 15)(font "Dialog" (font_size 8))) + (text "oe" (rect 4 65 16 79)(font "Dialog" (font_size 8))) + (line (pt 0 80)(pt 80 80)) + ) + (port + (pt 0 96) + (input) + (text "outclock" (rect 0 0 51 15)(font "Dialog" (font_size 8))) + (text "outclock" (rect 4 81 47 95)(font "Dialog" (font_size 8))) + (line (pt 0 96)(pt 80 96)) + ) + (port + (pt 0 112) + (input) + (text "aclr" (rect 0 0 22 15)(font "Dialog" (font_size 8))) + (text "aclr" (rect 4 97 23 111)(font "Dialog" (font_size 8))) + (line (pt 0 112)(pt 80 112)) + ) + (port + (pt 224 48) + (output) + (text "dataout[5..0]" (rect 0 0 79 15)(font "Dialog" (font_size 8))) + (text "dataout[5..0]" (rect 168 33 233 47)(font "Dialog" (font_size 8))) + (line (pt 224 48)(pt 144 48)(line_width 3)) + ) + (drawing + (line (pt 80 32)(pt 144 32)) + (line (pt 144 32)(pt 144 128)) + (line (pt 80 128)(pt 144 128)) + (line (pt 80 32)(pt 80 128)) + (line (pt 0 0)(pt 224 0)) + (line (pt 224 0)(pt 224 144)) + (line (pt 0 144)(pt 224 144)) + (line (pt 0 0)(pt 0 144)) + ) +) diff --git a/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.cmp b/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.cmp new file mode 100644 index 0000000..dbbc5a8 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.cmp @@ -0,0 +1,27 @@ +--Copyright (C) 2025 Altera Corporation. All rights reserved. +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and any partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, the Altera Quartus Prime License Agreement, +--the Altera IP License Agreement, or other applicable license +--agreement, including, without limitation, that your use is for +--the sole purpose of programming logic devices manufactured by +--Altera and sold by Altera or its authorized distributors. Please +--refer to the Altera Software License Subscription Agreements +--on the Quartus Prime software download page. + + +component ddro + PORT + ( + aclr : IN STD_LOGIC ; + datain_h : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + datain_l : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + oe : IN STD_LOGIC ; + outclock : IN STD_LOGIC ; + dataout : OUT STD_LOGIC_VECTOR (5 DOWNTO 0) + ); +end component; diff --git a/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.inc b/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.inc new file mode 100644 index 0000000..98c6145 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.inc @@ -0,0 +1,28 @@ +--Copyright (C) 2025 Altera Corporation. All rights reserved. +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and any partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, the Altera Quartus Prime License Agreement, +--the Altera IP License Agreement, or other applicable license +--agreement, including, without limitation, that your use is for +--the sole purpose of programming logic devices manufactured by +--Altera and sold by Altera or its authorized distributors. Please +--refer to the Altera Software License Subscription Agreements +--on the Quartus Prime software download page. + + +FUNCTION ddro +( + aclr, + datain_h[5..0], + datain_l[5..0], + oe, + outclock +) + +RETURNS ( + dataout[5..0] +); diff --git a/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.ppf b/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.ppf new file mode 100644 index 0000000..2d6a4da --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.ppf @@ -0,0 +1,13 @@ +<?xml version="1.0" encoding="UTF-8" ?> +<!DOCTYPE pinplan> +<pinplan intended_family="Cyclone 10 LP" variation_name="ddro" megafunction_name="ALTDDIO_OUT" specifies="all_ports"> +<global> +<pin name="aclr" direction="input" scope="external" /> +<pin name="datain_h[5..0]" direction="input" scope="external" /> +<pin name="datain_l[5..0]" direction="input" scope="external" /> +<pin name="oe" direction="input" scope="external" /> +<pin name="outclock" direction="input" scope="external" source="clock" /> +<pin name="dataout[5..0]" direction="output" scope="external" /> + +</global> +</pinplan> diff --git a/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.qip b/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.qip new file mode 100644 index 0000000..3eb030b --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.qip @@ -0,0 +1,10 @@ +set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT" +set_global_assignment -name IP_TOOL_VERSION "25.1" +set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone 10 LP}" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ddro.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddro.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddro_inst.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddro_bb.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddro.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddro.cmp"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddro.ppf"] diff --git a/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.v b/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.v new file mode 100644 index 0000000..87d2856 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.v @@ -0,0 +1,115 @@ +// megafunction wizard: %ALTDDIO_OUT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: ALTDDIO_OUT + +// ============================================================ +// File Name: ddro.v +// Megafunction Name(s): +// ALTDDIO_OUT +// +// Simulation Library Files(s): +// +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 25.1std.0 Build 1129 10/21/2025 SC Standard Edition +// ************************************************************ + + +//Copyright (C) 2025 Altera Corporation. All rights reserved. +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and any partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, the Altera Quartus Prime License Agreement, +//the Altera IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Altera and sold by Altera or its authorized distributors. Please +//refer to the Altera Software License Subscription Agreements +//on the Quartus Prime software download page. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module ddro ( + aclr, + datain_h, + datain_l, + oe, + outclock, + dataout); + + input aclr; + input [5:0] datain_h; + input [5:0] datain_l; + input oe; + input outclock; + output [5:0] dataout; + + wire [5:0] sub_wire0; + wire [5:0] dataout = sub_wire0[5:0]; + + altddio_out ALTDDIO_OUT_component ( + .aclr (aclr), + .datain_h (datain_h), + .datain_l (datain_l), + .oe (oe), + .outclock (outclock), + .dataout (sub_wire0), + .aset (1'b0), + .oe_out (), + .outclocken (1'b1), + .sclr (1'b0), + .sset (1'b0)); + defparam + ALTDDIO_OUT_component.extend_oe_disable = "OFF", + ALTDDIO_OUT_component.intended_device_family = "Cyclone 10 LP", + ALTDDIO_OUT_component.invert_output = "OFF", + ALTDDIO_OUT_component.lpm_hint = "UNUSED", + ALTDDIO_OUT_component.lpm_type = "altddio_out", + ALTDDIO_OUT_component.oe_reg = "UNREGISTERED", + ALTDDIO_OUT_component.power_up_high = "OFF", + ALTDDIO_OUT_component.width = 6; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP" +// Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "OFF" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP" +// Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF" +// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out" +// Retrieval info: CONSTANT: OE_REG STRING "UNREGISTERED" +// Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF" +// Retrieval info: CONSTANT: WIDTH NUMERIC "6" +// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr" +// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +// Retrieval info: USED_PORT: datain_h 0 0 6 0 INPUT NODEFVAL "datain_h[5..0]" +// Retrieval info: CONNECT: @datain_h 0 0 6 0 datain_h 0 0 6 0 +// Retrieval info: USED_PORT: datain_l 0 0 6 0 INPUT NODEFVAL "datain_l[5..0]" +// Retrieval info: CONNECT: @datain_l 0 0 6 0 datain_l 0 0 6 0 +// Retrieval info: USED_PORT: dataout 0 0 6 0 OUTPUT NODEFVAL "dataout[5..0]" +// Retrieval info: CONNECT: dataout 0 0 6 0 @dataout 0 0 6 0 +// Retrieval info: USED_PORT: oe 0 0 0 0 INPUT NODEFVAL "oe" +// Retrieval info: CONNECT: @oe 0 0 0 0 oe 0 0 0 0 +// Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "outclock" +// Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL ddro.v TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddro.qip TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddro.bsf TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddro_inst.v TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddro_bb.v TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddro.inc TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddro.cmp TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddro.ppf TRUE FALSE diff --git a/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro_bb.v b/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro_bb.v new file mode 100644 index 0000000..1529ff1 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro_bb.v @@ -0,0 +1,84 @@ +// megafunction wizard: %ALTDDIO_OUT%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: ALTDDIO_OUT + +// ============================================================ +// File Name: ddro.v +// Megafunction Name(s): +// ALTDDIO_OUT +// +// Simulation Library Files(s): +// +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 25.1std.0 Build 1129 10/21/2025 SC Standard Edition +// ************************************************************ + +//Copyright (C) 2025 Altera Corporation. All rights reserved. +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and any partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, the Altera Quartus Prime License Agreement, +//the Altera IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Altera and sold by Altera or its authorized distributors. Please +//refer to the Altera Software License Subscription Agreements +//on the Quartus Prime software download page. + +module ddro ( + aclr, + datain_h, + datain_l, + oe, + outclock, + dataout); + + input aclr; + input [5:0] datain_h; + input [5:0] datain_l; + input oe; + input outclock; + output [5:0] dataout; + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP" +// Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "OFF" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP" +// Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF" +// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out" +// Retrieval info: CONSTANT: OE_REG STRING "UNREGISTERED" +// Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF" +// Retrieval info: CONSTANT: WIDTH NUMERIC "6" +// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr" +// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +// Retrieval info: USED_PORT: datain_h 0 0 6 0 INPUT NODEFVAL "datain_h[5..0]" +// Retrieval info: CONNECT: @datain_h 0 0 6 0 datain_h 0 0 6 0 +// Retrieval info: USED_PORT: datain_l 0 0 6 0 INPUT NODEFVAL "datain_l[5..0]" +// Retrieval info: CONNECT: @datain_l 0 0 6 0 datain_l 0 0 6 0 +// Retrieval info: USED_PORT: dataout 0 0 6 0 OUTPUT NODEFVAL "dataout[5..0]" +// Retrieval info: CONNECT: dataout 0 0 6 0 @dataout 0 0 6 0 +// Retrieval info: USED_PORT: oe 0 0 0 0 INPUT NODEFVAL "oe" +// Retrieval info: CONNECT: @oe 0 0 0 0 oe 0 0 0 0 +// Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "outclock" +// Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL ddro.v TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddro.qip TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddro.bsf TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddro_inst.v TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddro_bb.v TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddro.inc TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddro.cmp TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddro.ppf TRUE FALSE diff --git a/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro_inst.v b/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro_inst.v new file mode 100644 index 0000000..32dfbbb --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro_inst.v @@ -0,0 +1,8 @@ +ddro ddro_inst ( + .aclr ( aclr_sig ), + .datain_h ( datain_h_sig ), + .datain_l ( datain_l_sig ), + .oe ( oe_sig ), + .outclock ( outclock_sig ), + .dataout ( dataout_sig ) + ); diff --git a/manufacturer/altera/cyclone10_lp/mle_ram_0.txt b/manufacturer/altera/cyclone10_lp/mle_ram_0.txt new file mode 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\ No newline at end of file diff --git a/manufacturer/altera/cyclone10_lp/param_ram_2.txt b/manufacturer/altera/cyclone10_lp/param_ram_2.txt new file mode 100644 index 0000000..dee4dca --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/param_ram_2.txt @@ -0,0 +1,1024 @@ +000 +000 +000 +0FF // DEST MAC Address +0FF +0FF +0FF +0FF +0FF +002 // SRC MAC Address +00a +00b +00c +00d +00e +008 // Ether Type +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +080 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 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\ No newline at end of file diff --git a/manufacturer/altera/cyclone10_lp/sim/.gitignore b/manufacturer/altera/cyclone10_lp/sim/.gitignore new file mode 100644 index 0000000..d2f09b4 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/sim/.gitignore @@ -0,0 +1,12 @@ +aldec/ +libraries/ +work/ +rtl_work/ +vsim.wlf +wlf* +transcript +*.mti +*.orig +*.bak +tcl_* +msim_transcript diff --git a/manufacturer/altera/cyclone10_lp/sim/data/cont_mle_w.dat b/manufacturer/altera/cyclone10_lp/sim/data/cont_mle_w.dat new file mode 100644 index 0000000..6f337f3 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/sim/data/cont_mle_w.dat @@ -0,0 +1,145 @@ +55 // Preamble +55 +55 +55 +55 +55 +D5 +02 // Dest MAC Address +0A +0B +0C +0D +0E +C8 // Source MAC Address +F7 +50 +F3 +AB +DE +08 // Type IPv4 +00 +45 // IP Packet (Version, IHL)s +00 +00 // Total Length +23 +42 // Identification +41 +00 +00 +80 // TTL +11 // Identification (UDP) +70 // IP Checksum +C1 +C0 // IP Source Address +A8 +05 +14 +C0 // IP Dest Address, 192 +A8 // 168 +05 +64 // 100 +30 // UDP Source Port +00 +90 // UDP Dest Port +20 +00 // UDP Length +0f +AC // UDP Checksum +E6 +01 // Msg Type +ed // Token +07 // Address MSByte +00 // Address LSByte +00 // Data MSbyte +00 +00 +01 // Data LSbyte +00 // PAD +00 +00 +00 +00 +00 +00 +00 +00 +00 +71 // FCS +E3 // +95 +184 +20 // Idle Clocks * 16 +55 // Preamble +55 +55 +55 +55 +55 +D5 +02 // Dest MAC Address +00 +0A +0B +0C +0D +C8 // Source MAC Address +F7 +50 +F3 +AB +DE +08 // Type IPv4 +00 +45 // IP Packet (Version, IHL)s +00 +00 // Total Length +23 +42 // Identification +41 +00 +00 +80 // TTL +11 // Identification (UDP) +70 // IP Checksum +C1 +C0 // IP Source Address +A8 +05 +14 +C0 // IP Dest Address, 192 +A8 // 168 +05 +64 // 100 +30 // UDP Source Port +00 +90 // UDP Dest Port +20 +00 // UDP Length +0f +AC // UDP Checksum +E6 +02 // Msg Type +c3 // Token +00 // Address MSByte +10 // Address LSByte +01 // Data MSbyte +02 +03 +04 // Data LSbyte +00 // Pad +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +71 // FCS +E3 // +95 +184 +ff // Idle Clocks * 16
\ No newline at end of file diff --git a/manufacturer/altera/cyclone10_lp/sim/data/cont_query.dat b/manufacturer/altera/cyclone10_lp/sim/data/cont_query.dat new file mode 100644 index 0000000..4590ab9 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/sim/data/cont_query.dat @@ -0,0 +1,145 @@ +55 // Preamble +55 +55 +55 +55 +55 +D5 +02 // Dest MAC Address +0A +0B +0C +0D +0E +C8 // Source MAC Address +F7 +50 +F3 +AB +DE +08 // Type IPv4 +00 +45 // IP Packet (Version, IHL)s +00 +00 // Total Length +23 +42 // Identification +41 +00 +00 +80 // TTL +11 // Identification (UDP) +70 // IP Checksum +C1 +C0 // IP Source Address +A8 +05 +14 +C0 // IP Dest Address, 192 +A8 // 168 +05 +64 // 100 +30 // UDP Source Port +00 +90 // UDP Dest Port +20 +00 // UDP Length +0f +AC // UDP Checksum +E6 +02 // Msg Type +ed // Token +01 // Address MSByte +04 // Address LSByte +00 // Data MSbyte +00 +00 +00 // Data LSbyte +00 // PAD +00 +00 +00 +00 +00 +00 +00 +00 +00 +71 // FCS +E3 // +95 +184 +40 // Idle Clocks * 16 +55 // Preamble +55 +55 +55 +55 +55 +D5 +02 // Dest MAC Address +00 +0A +0B +0C +0D +C8 // Source MAC Address +F7 +50 +F3 +AB +DE +08 // Type IPv4 +00 +45 // IP Packet (Version, IHL)s +00 +00 // Total Length +23 +42 // Identification +41 +00 +00 +80 // TTL +11 // Identification (UDP) +70 // IP Checksum +C1 +C0 // IP Source Address +A8 +05 +14 +C0 // IP Dest Address, 192 +A8 // 168 +05 +64 // 100 +30 // UDP Source Port +00 +90 // UDP Dest Port +20 +00 // UDP Length +0f +AC // UDP Checksum +E6 +02 // Msg Type +c3 // Token +00 // Address MSByte +10 // Address LSByte +01 // Data MSbyte +02 +03 +04 // Data LSbyte +00 // Pad +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +71 // FCS +E3 // +95 +184 +ff // Idle Clocks * 16
\ No newline at end of file diff --git a/manufacturer/altera/cyclone10_lp/sim/data/cont_query_fcs.dat b/manufacturer/altera/cyclone10_lp/sim/data/cont_query_fcs.dat new file mode 100644 index 0000000..2b9d4b1 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/sim/data/cont_query_fcs.dat @@ -0,0 +1,72 @@ +55 // Preamble +55 +55 +55 +55 +55 +D5 +02 // Dest MAC Address +00 +02 +03 +04 +05 +C8 // Source MAC Address +F7 +50 +F3 +AB +DE +08 // Type IPv4 +00 +45 // IP Packet (Version, IHL)s +00 +00 // Total Length +23 +42 // Identification +41 +00 +00 +80 // TTL +11 // Identification (UDP) +70 // IP Checksum +C1 +C0 // IP Source Address +A8 +03 +12 +C0 // IP Dest Address +A8 +03 +65 +30 // UDP Source Port +00 +90 // UDP Dest Port +20 +00 // UDP Length +0f +AC // UDP Checksum +E6 +07 // Msg Size +01 // Device +02 // Command +00 // Controller Address +02 // FW Increment +00 // Data +00 // PAD +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +70 // FCS +E3 // +95 +1DA +40 // Idle Clocks
\ No newline at end of file diff --git a/manufacturer/altera/cyclone10_lp/sim/data/etoe0.dat b/manufacturer/altera/cyclone10_lp/sim/data/etoe0.dat new file mode 100644 index 0000000..59e747a --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/sim/data/etoe0.dat @@ -0,0 +1,144 @@ +55 // Preamble +55 +55 +55 +55 +55 +D5 +02 // Dest MAC Address +00 +02 +03 +04 +05 +C8 // Source MAC Address +F7 +50 +F3 +AB +DE +08 // Type IPv4 +00 +45 // IP Packet (Version, IHL)s +00 +00 // Total Length +23 +42 // Identification +41 +00 +00 +80 // TTL +11 // Identification (UDP) +70 // IP Checksum +C1 +C0 // IP Source Address +A8 +03 +12 +C0 // IP Dest Address +A8 +03 +65 +30 // UDP Source Port +00 +90 // UDP Dest Port +20 +00 // UDP Length +0f +AC // UDP Checksum +E6 +00 +00 +00 +00 +05 +06 +07 +08 +09 +0A +0B +0C +0D +0E +0F +10 +11 +12 +71 // FCS +E3 // +95 +184 +ff // Idle Clocks * 16 +55 // Preamble +55 +55 +55 +55 +55 +D5 +02 // Dest MAC Address +00 +02 +03 +04 +05 +C8 // Source MAC Address +F7 +50 +F3 +AB +DE +08 // Type IPv4 +00 +45 // IP Packet (Version, IHL)s +00 +00 // Total Length +23 +42 // Identification +41 +00 +00 +80 // TTL +11 // Identification (UDP) +70 // IP Checksum +C1 +C0 // IP Source Address +A8 +03 +12 +C0 // IP Dest Address +A8 +03 +65 +30 // UDP Source Port +00 +90 // UDP Dest Port +20 +00 // UDP Length +0f +AC // UDP Checksum +E6 +00 +00 +00 +00 +05 +06 +07 +08 +09 +0A +0B +0C +0D +0E +0F +10 +11 +12 +71 // FCS +E3 // +95 +184 +ff
\ No newline at end of file diff --git a/manufacturer/altera/cyclone10_lp/sim/data/etoe1.dat b/manufacturer/altera/cyclone10_lp/sim/data/etoe1.dat new file mode 100644 index 0000000..ca1df41 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/sim/data/etoe1.dat @@ -0,0 +1,144 @@ +55 // Preamble +55 +55 +55 +55 +55 +D5 +02 // Dest MAC Address +00 +02 +03 +04 +05 +C8 // Source MAC Address +F7 +50 +F3 +AB +DE +08 // Type IPv4 +00 +45 // IP Packet (Version, IHL)s +00 +00 // Total Length +23 +42 // Identification +41 +00 +00 +80 // TTL +11 // Identification (UDP) +70 // IP Checksum +C1 +C0 // IP Source Address +A8 +03 +12 +C0 // IP Dest Address +A8 +03 +65 +30 // UDP Source Port +00 +90 // UDP Dest Port +00 +00 // UDP Length +0f +AC // UDP Checksum +E6 +01 +01 +01 +01 +05 +06 +07 +08 +09 +0A +0B +0C +0D +0E +0F +10 +11 +12 +71 // FCS +E3 // +95 +184 +ff // Idle Clocks * 16 +55 // Preamble +55 +55 +55 +55 +55 +D5 +02 // Dest MAC Address +00 +02 +03 +04 +05 +C8 // Source MAC Address +F7 +50 +F3 +AB +DE +08 // Type IPv4 +00 +45 // IP Packet (Version, IHL)s +00 +00 // Total Length +23 +42 // Identification +41 +00 +00 +80 // TTL +11 // Identification (UDP) +70 // IP Checksum +C1 +C0 // IP Source Address +A8 +03 +12 +C0 // IP Dest Address +A8 +03 +65 +30 // UDP Source Port +00 +90 // UDP Dest Port +20 +00 // UDP Length +0f +AC // UDP Checksum +E6 +01 +02 +03 +04 +05 +06 +07 +08 +09 +0A +0B +0C +0D +0E +0F +10 +11 +12 +71 // FCS +E3 // +95 +184 +ff
\ No newline at end of file diff --git a/manufacturer/altera/cyclone10_lp/sim/data/etoe2.dat b/manufacturer/altera/cyclone10_lp/sim/data/etoe2.dat new file mode 100644 index 0000000..ad08f1b --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/sim/data/etoe2.dat @@ -0,0 +1,144 @@ +55 // Preamble +55 +55 +55 +55 +55 +D5 +02 // Dest MAC Address +00 +02 +03 +04 +05 +C8 // Source MAC Address +F7 +50 +F3 +AB +DE +08 // Type IPv4 +00 +45 // IP Packet (Version, IHL) +00 +00 // Total Length +23 +42 // Identification +41 +00 +00 +80 // TTL +11 // Identification (UDP) +70 // IP Checksum +C1 +C0 // IP Source Address +A8 +03 +12 +C0 // IP Dest Address +A8 +03 +65 +30 // UDP Source Port +00 +90 // UDP Dest Port +00 +00 // UDP Length +0f +AC // UDP Checksum +E6 +02 +02 +02 +02 +05 +06 +07 +08 +09 +0A +0B +0C +0D +0E +0F +10 +11 +12 +71 // FCS +E3 // +95 +184 +ff // Idle Clocks * 16 +55 // Preamble +55 +55 +55 +55 +55 +D5 +02 // Dest MAC Address +00 +02 +03 +04 +05 +C8 // Source MAC Address +F7 +50 +F3 +AB +DE +08 // Type IPv4 +00 +45 // IP Packet (Version, IHL)s +00 +00 // Total Length +23 +42 // Identification +41 +00 +00 +80 // TTL +11 // Identification (UDP) +70 // IP Checksum +C1 +C0 // IP Source Address +A8 +03 +12 +C0 // IP Dest Address +A8 +03 +65 +30 // UDP Source Port +00 +90 // UDP Dest Port +20 +00 // UDP Length +0f +AC // UDP Checksum +E6 +01 +02 +03 +04 +05 +06 +07 +08 +09 +0A +0B +0C +0D +0E +0F +10 +11 +12 +71 // FCS +E3 // +95 +184 +ff
\ No newline at end of file diff --git a/manufacturer/altera/cyclone10_lp/sim/lin/README b/manufacturer/altera/cyclone10_lp/sim/lin/README new file mode 100644 index 0000000..3aa3193 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/sim/lin/README @@ -0,0 +1,33 @@ +GEODSS Simulation Project README + +Simulator: questa Intel edition + +questa project file: geodss_sim.mpf + +Run project by launching vsim in the questa_fse/bin directory and open project using File->Open + +In the command console: + +do geodss.do + +do wave.do // brings up nets suitable for viewing end-to-end packet transmission from Camera to Ethernet + +run 10 us + +Project Description: + +Simulation of the GEODSS Cyclone 10 GX FPGA project that includes all IP blocks. Project has been most recently updated for simulating end-to-end connectivity between Camera Fiber 1 (phy1) and Etherent (phy0) + +Test bench file is source/tb.sv and has support for emulating the camera's TX path into the FPGA's RX SERDES receiver with disparity accurate data. + +If the FPGA project is modified, then be sure to re-run Tools->Generate Simulator Simulator Script inside Quartus. + +Make sure the SIMULATION directive is defined for top.v and mac_geodss.v + + + + + + + + diff --git a/manufacturer/altera/cyclone10_lp/sim/lin/betsy.mpf b/manufacturer/altera/cyclone10_lp/sim/lin/betsy.mpf new file mode 100644 index 0000000..bc3671a --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/sim/lin/betsy.mpf @@ -0,0 +1,2329 @@ +; vsim modelsim.ini file +[Version] +INIVersion = "QA Baseline: 2021.1 Beta - 4536908" + +; Copyright 1991-2020 Mentor Graphics Corporation +; +; All Rights Reserved. +; +; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF +; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. +; + +[Library] +others = $MODEL_TECH/../modelsim.ini +; +; VITAL concerns: +; +; The library ieee contains (among other packages) the packages of the +; VITAL 2000 standard. When a design uses VITAL 2000 exclusively, it should use +; the physical library ieee (recommended), or use the physical library +; vital2000, but not both. The design can use logical library ieee and/or +; vital2000 as long as each of these maps to the same physical library, either +; ieee or vital2000. +; +; A design using the 1995 version of the VITAL packages, whether or not +; it also uses the 2000 version of the VITAL packages, must have logical library +; name ieee mapped to physical library vital1995. (A design cannot use library +; vital1995 directly because some packages in this library use logical name ieee +; when referring to the other packages in the library.) The design source +; should use logical name ieee when referring to any packages there except the +; VITAL 2000 packages. Any VITAL 2000 present in the design must use logical +; name vital2000 (mapped to physical library vital2000) to refer to those +; packages. +; ieee = $MODEL_TECH/../vital1995 +; +; For compatiblity with previous releases, logical library name vital2000 maps +; to library vital2000 (a different library than library ieee, containing the +; same packages). +; A design should not reference VITAL from both the ieee library and the +; vital2000 library because the vital packages are effectively different. +; A design that references both the ieee and vital2000 libraries must have +; both logical names ieee and vital2000 mapped to the same library, either of +; these: +; $MODEL_TECH/../ieee +; $MODEL_TECH/../vital2000 +; + +; added mapping for ADMS + +;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers // Source files only for this release +;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release +;mvc_lib = $MODEL_TECH/../mvc_lib + +; Altera Primitive libraries +; +; VHDL Section +; +; +; Verilog Section +; + + +; Automatically perform logical->physical mapping for physical libraries that +; appear in -L/-Lf options with filesystem path delimiters (e.g. '.' or '/'). +; The tail of the filesystem path name is chosen as the logical library name. +; For example, in the command "vopt -L ./path/to/lib1 -o opttop top", +; vopt automatically performs the mapping "lib1 -> ./path/to/lib1". +; See the User Manual for more details. +; +; AutoLibMapping = 0 + +work = rtl_work +work_lib = ./libraries/work/ +ram_2port_2050 = ./libraries/ram_2port_2050 +dpram_2kx9 = ./libraries/dpram_2kx9 +altera_common_sv_packages = ./libraries/altera_common_sv_packages +altera_xcvr_atx_pll_a10_191 = ./libraries/altera_xcvr_atx_pll_a10_191 +gige_pll_atx = ./libraries/gige_pll_atx +altera_xcvr_fpll_a10_191 = ./libraries/altera_xcvr_fpll_a10_191 +gige_pll_fract = ./libraries/gige_pll_fract +altera_xcvr_reset_control_1911 = ./libraries/altera_xcvr_reset_control_1911 +gige_reset_cont = ./libraries/gige_reset_cont +altera_xcvr_native_a10_1911 = ./libraries/altera_xcvr_native_a10_1911 +gige_xcvr = ./libraries/gige_xcvr +altera_int_osc_1910 = ./libraries/altera_int_osc_1910 +internal_osc = ./libraries/internal_osc +param_ram = ./libraries/param_ram +sgmii_xcvr = ./libraries/sgmii_xcvr +altera_temp_sense_1910 = ./libraries/altera_temp_sense_1910 +temp_sensor = ./libraries/temp_sensor +[DefineOptionset] +; Define optionset entries for the various compilers, vmake, and vsim. +; These option sets can be used with the "-optionset <optionsetname>" syntax. +; i.e. +; vlog -optionset COMPILEDEBUG top.sv +; vsim -optionset UVMDEBUG my_top +; +; Following are some useful examples. + +; define a vsim optionset for uvm debugging +UVMDEBUG = -uvmcontrol=all -msgmode both -displaymsgmode both -classdebug -onfinish stop + +; define a vopt optionset for debugging +VOPTDEBUG = +acc -debugdb + +[encryption] +; For vencrypt and vhencrypt. + +; Controls whether to encrypt whole files by ignoring all protect directives +; (except "viewport" and "interface_viewport") that are present in the input. +; The default is 0, use embedded protect directives to control the encryption. +; Set this to 1 to encrypt whole files by ignoring embedded protect directives. +; wholefile = 0 + +; Sets the data_method to use for the symmetric session key. +; The session key is a symmetric key that is randomly generated for each +; protected region (envelope) and is the heart of all encryption. This is used +; to set the length of the session key to generate and use when encrypting the +; HDL text. Supported values are aes128, aes192, and aes256. +; data_method = aes128 + +; The following 2 are for specifying an IEEE Std. 1735 Version 2 (V2) encryption +; "recipe" comprising an optional common block, at least one tool block (which +; contains the key public key), and the text to be encrypted. The common block +; and any of the tool blocks may contain rights in the form of the "control" +; directive. The text to be encrypted is specified either by setting +; "wholefile" to 1 or by embedding protect "begin" and "end" directives in +; the input HDL files. + +; Common recipe specification file. This file is optional. Its presence will +; require at least one "toolblock" to be specified. +; Directives such as "author" "author_info" and "data_method", +; as well as the common block license specification, go in this file. +; common = <file name> + +; Tool block specification recipe(s). Public key file with optional tool block +; file name. May be multiply-defined; at least one tool block is required if +; a recipe is being specified. +; Key file is a file name with no extension (.deprecated or .active will be +; supplied by the encryption tool). +; Rights file name is optional. +; toolblock = <key file name>[,<rights file name>]{:<key file name>[,<rights file name>]} + +; Location of directory containing recipe files. +; The default location is in the product installation directory. +; keyring = $MODEL_TECH/../keyring + +; Enable encryption statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list] +; Add '-' to disable specific statistics. Default is [cmd,msg]. +Stats = cmd,msg + +[vcom] +; VHDL93 variable selects language version as the default. +; Default is VHDL-2002. +; Value of 0 or 1987 for VHDL-1987. +; Value of 1 or 1993 for VHDL-1993. +; Default or value of 2 or 2002 for VHDL-2002. +; Value of 3 or 2008 for VHDL-2008 +; Value of 4 or ams99 for VHDL-AMS-1999 +; Value of 5 or ams07 for VHDL-AMS-2007 +VHDL93 = 2002 + +; Ignore VHDL-2008 declaration of REAL_VECTOR in package STANDARD. Default is off. +; ignoreStandardRealVector = 1 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn off unbound-component warnings. Default is on. +; Show_Warning1 = 0 + +; Turn off process-without-a-wait-statement warnings. Default is on. +; Show_Warning2 = 0 + +; Turn off null-range warnings. Default is on. +; Show_Warning3 = 0 + +; Turn off no-space-in-time-literal warnings. Default is on. +; Show_Warning4 = 0 + +; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. +; Show_Warning5 = 0 + +; Turn off optimization for IEEE std_logic_1164 package. Default is on. +; Optimize_1164 = 0 + +; Enable compiler statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list] +; Add '-' to disable specific statistics. Default is [time,cmd,msg]. +; Stats = time,cmd,msg + +; Turn on resolving of ambiguous function overloading in favor of the +; "explicit" function declaration (not the one automatically created by +; the compiler for each type declaration). Default is off. +; The .ini file has Explicit enabled so that std_logic_signed/unsigned +; will match the behavior of synthesis tools. +Explicit = 1 + +; Turn off acceleration of the VITAL packages. Default is to accelerate. +; NoVital = 1 + +; Turn off VITAL compliance checking. Default is checking on. +; NoVitalCheck = 1 + +; Ignore VITAL compliance checking errors. Default is to not ignore. +; IgnoreVitalErrors = 1 + +; Turn off VITAL compliance checking warnings. Default is to show warnings. +; Show_VitalChecksWarnings = 0 + +; Turn off PSL assertion warning messages. Default is to show warnings. +; Show_PslChecksWarnings = 0 + +; Enable parsing of embedded PSL assertions. Default is enabled. +; EmbeddedPsl = 0 + +; Keep silent about case statement static warnings. +; Default is to give a warning. +; NoCaseStaticError = 1 + +; Keep silent about warnings caused by aggregates that are not locally static. +; Default is to give a warning. +; NoOthersStaticError = 1 + +; Treat as errors: +; case statement static warnings +; warnings caused by aggregates that are not locally static +; Overrides NoCaseStaticError, NoOthersStaticError settings. +; PedanticErrors = 1 + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on some limited synthesis rule compliance checking. Checks only: +; -- signals used (read) by a process must be in the sensitivity list +; CheckSynthesis = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +; Require the user to specify a configuration for all bindings, +; and do not generate a compile time default binding for the +; component. This will result in an elaboration error of +; 'component not bound' if the user fails to do so. Avoids the rare +; issue of a false dependency upon the unused default binding. +; RequireConfigForAllDefaultBinding = 1 + +; Perform default binding at compile time. +; Default is to do default binding at load time. +; BindAtCompile = 1; + +; Inhibit range checking on subscripts of arrays. Range checking on +; scalars defined with subtypes is inhibited by default. +; NoIndexCheck = 1 + +; Inhibit range checks on all (implicit and explicit) assignments to +; scalar objects defined with subtypes. +; NoRangeCheck = 1 + +; Set the prefix to be honored for synthesis/coverage pragma recognition. +; Default is "". +; AddPragmaPrefix = "" + +; Ignore synthesis and coverage pragmas with this prefix. +; Default is "". +; IgnorePragmaPrefix = "" + +; Turn on code coverage in VHDL design units. Default is off. +; Coverage = sbceft + +; Turn off code coverage in VHDL subprograms. Default is on. +; CoverSub = 0 + +; Automatically exclude VHDL case statement OTHERS choice branches. +; This includes OTHERS choices in selected signal assigment statements. +; Default is to not exclude. +; CoverExcludeDefault = 1 + +; Control compiler and VOPT optimizations that are allowed when +; code coverage is on. Refer to the comment for this in the [vlog] area. +; CoverOpt = 3 + +; Turn on or off clkOpt optimization for code coverage. Default is on. +; CoverClkOpt = 1 + +; Turn on or off clkOpt optimization builtins for code coverage. Default is on. +; CoverClkOptBuiltins = 0 + +; Inform code coverage optimizations to respect VHDL 'H' and 'L' +; values on signals in conditions and expressions, and to not automatically +; convert them to '1' and '0'. Default is to not convert. +; CoverRespectHandL = 0 + +; Increase or decrease the maximum number of rows allowed in a UDP table +; implementing a VHDL condition coverage or expression coverage expression. +; More rows leads to a longer compile time, but more expressions covered. +; CoverMaxUDPRows = 192 + +; Increase or decrease the maximum number of input patterns that are present +; in FEC table. This leads to a longer compile time with more expressions +; covered with FEC metric. +; CoverMaxFECRows = 192 + +; Increase or decrease the limit on the size of expressions and conditions +; considered for expression and condition coverages. Higher FecUdpEffort leads +; to higher compile, optimize and simulation time, but more expressions and +; conditions are considered for coverage in the design. FecUdpEffort can +; be set to a number ranging from 1 (low) to 3 (high), defined as: +; 1 - (low) Only small expressions and conditions considered for coverage. +; 2 - (medium) Bigger expressions and conditions considered for coverage. +; 3 - (high) Very large expressions and conditions considered for coverage. +; The default setting is 1 (low). +; FecUdpEffort = 1 + +; Enable or disable Focused Expression Coverage analysis for conditions and +; expressions. Focused Expression Coverage data is provided by default when +; expression and/or condition coverage is active. +; CoverFEC = 0 + +; Enable or disable UDP Coverage analysis for conditions and expressions. +; UDP Coverage data is disabled by default when expression and/or condition +; coverage is active. +; CoverUDP = 1 + +; Enable or disable Rapid Expression Coverage mode for conditions and expressions. +; Disabling this would convert non-masking conditions in FEC tables to matching +; input patterns. +; CoverREC = 1 + +; Enable or disable bit-blasting multi-bit operands of reduction prefix expressions +; for expression/condition coverage. +; NOTE: Enabling this may have a negative impact on simulation performance. +; CoverExpandReductionPrefix = 0 + +; Enable or disable short circuit evaluation of conditions and expressions when +; condition or expression coverage is active. Short circuit evaluation is enabled +; by default. +; CoverShortCircuit = 0 + +; Enable code coverage reporting of code that has been optimized away. +; The default is not to report. +; CoverReportCancelled = 1 + +; Enable deglitching of code coverage in combinatorial, non-clocked, processes. +; Default is no deglitching. +; CoverDeglitchOn = 1 + +; Control the code coverage deglitching period. A period of 0, eliminates delta +; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a +; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". +; CoverDeglitchPeriod = 0 + +; Use this directory for compiler temporary files instead of "work/_temp" +; CompilerTempDir = /tmp + +; Set this to cause the compilers to force data to be committed to disk +; when the files are closed. +; SyncCompilerFiles = 1 + +; Add VHDL-AMS declarations to package STANDARD +; Default is not to add +; AmsStandard = 1 + +; Range and length checking will be performed on array indices and discrete +; ranges, and when violations are found within subprograms, errors will be +; reported. Default is to issue warnings for violations, because subprograms +; may not be invoked. +; NoDeferSubpgmCheck = 0 + +; Turn ON detection of FSMs having single bit current state variable. +; FsmSingle = 1 + +; Turn off reset state transitions in FSM. +; FsmResetTrans = 0 + +; Turn ON detection of FSM Implicit Transitions. +; FsmImplicitTrans = 1 + +; Controls whether or not to show immediate assertions with constant expressions +; in GUI/report/UCDB etc. By default, immediate assertions with constant +; expressions are shown in GUI/report/UCDB etc. This does not affect +; evaluation of immediate assertions. +; ShowConstantImmediateAsserts = 0 + +; Controls how VHDL basic identifiers are stored with the design unit. +; Does not make the language case-sensitive, affects only how declarations +; declared with basic identifiers have their names stored and printed +; (in the GUI, examine, etc.). +; Default is to preserve the case as originally depicted in the VHDL source. +; Value of 0 indicates to change all basic identifiers to lower case. +; PreserveCase = 0 + +; For Configuration Declarations, controls the effect that USE clauses have +; on visibility inside the configuration items being configured. If 1 +; (the default), then use pre-10.0 behavior. If 0, then for stricter LRM-compliance, +; extend the visibility of objects made visible through USE clauses into nested +; component configurations. +; OldVHDLConfigurationVisibility = 0 + +; Allows VHDL configuration declarations to be in a different library from +; the corresponding configured entity. Default is to not allow this for +; stricter LRM-compliance. +; SeparateConfigLibrary = 1; + +; Determine how mode OUT subprogram parameters of type array and record are treated. +; If 0 (the default), then only VHDL 2008 will do this initialization. +; If 1, always initialize the mode OUT parameter to its default value. +; If 2, do not initialize the mode OUT out parameter. +; Note that prior to release 10.1, all language versions did not initialize mode +; OUT array and record type parameters, unless overridden here via this mechanism. +; In release 10.1 and later, only files compiled with VHDL 2008 will cause this +; initialization, unless overridden here. +; InitOutCompositeParam = 0 + +; Generate symbols debugging database in only some special cases to save on +; the number of files in the library. For other design-units, this database is +; generated on-demand in vsim. +; Default is to to generate debugging database for all design-units. +; SmartDbgSym = 1 + +; Enable or disable automatic creation of missing libraries. +; Default is 1 (enabled) +; CreateLib = 1 + +; Describe compilation options according to matching file patterns. +; File pattern * matches all printing characters other than '/'. +; File pattern **/x matches all paths containing file/directory x. +; File pattern x/** matches all paths beginning at directory x. +; FileOptMap = (**/*.vhd => -2008); + +; Describe library targets of compilation according to matching file patterns. +; LibMap = (**/*.vhd => work); + +[vlog] +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on Verilog hazard checking (order-dependent accessing of global vars). +; Default is off. +; Hazard = 1 + +; Turn on converting regular Verilog identifiers to uppercase. Allows case +; insensitivity for module names. Default is no conversion. +; UpCase = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn on bad option warning. Default is off. +; Show_BadOptionWarning = 1 + +; Revert back to IEEE 1364-1995 syntax, default is 0 (off). +; vlog95compat = 1 + +; Turn off PSL warning messages. Default is to show warnings. +; Show_PslChecksWarnings = 0 + +; Enable parsing of embedded PSL assertions. Default is enabled. +; EmbeddedPsl = 0 + +; Enable compiler statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list,kb] +; Add '-' to disable specific statistics. Default is [time,cmd,msg]. +; Stats = time,cmd,msg + +; Set the threshold for automatically identifying sparse Verilog memories. +; A memory with total size in bytes equal to or more than the sparse memory +; threshold gets marked as sparse automatically, unless specified otherwise +; in source code or by the +nosparse commandline option of vlog or vopt. +; The default is 1M. (i.e. memories with total size equal +; to or greater than 1Mb are marked as sparse) +; SparseMemThreshold = 1048576 + +; Set the prefix to be honored for synthesis and coverage pragma recognition. +; Default is "". +; AddPragmaPrefix = "" + +; Ignore synthesis and coverage pragmas with this prefix. +; Default is "". +; IgnorePragmaPrefix = "" + +; Set the option to treat all files specified in a vlog invocation as a +; single compilation unit. The default value is set to 0 which will treat +; each file as a separate compilation unit as specified in the P1800 draft standard. +; MultiFileCompilationUnit = 1 + +; Turn on code coverage in Verilog design units. Default is off. +; Coverage = sbceft + +; Automatically exclude Verilog case statement default branches. +; Default is to not automatically exclude defaults. +; CoverExcludeDefault = 1 + +; Increase or decrease the maximum number of rows allowed in a UDP table +; implementing a VHDL condition coverage or expression coverage expression. +; More rows leads to a longer compile time, but more expressions covered. +; CoverMaxUDPRows = 192 + +; Increase or decrease the maximum number of input patterns that are present +; in FEC table. This leads to a longer compile time with more expressions +; covered with FEC metric. +; CoverMaxFECRows = 192 + +; Enable Multi Bit Expression Coverage in a Design, If design has expression with +; multi bit operands, this option enables its Expression Coverage. +; The default value is 0. +; CoverFecMultiBit = 1 + +; Increase or decrease the limit on the size of expressions and conditions +; considered for expression and condition coverages. Higher FecUdpEffort leads +; to higher compile, optimize and simulation time, but more expressions and +; conditions are considered for coverage in the design. FecUdpEffort can +; be set to a number ranging from 1 (low) to 3 (high), defined as: +; 1 - (low) Only small expressions and conditions considered for coverage. +; 2 - (medium) Bigger expressions and conditions considered for coverage. +; 3 - (high) Very large expressions and conditions considered for coverage. +; The default setting is 1 (low). +; FecUdpEffort = 1 + +; Enable or disable Focused Expression Coverage analysis for conditions and +; expressions. Focused Expression Coverage data is provided by default when +; expression and/or condition coverage is active. +; CoverFEC = 0 + +; Enable or disable UDP Coverage analysis for conditions and expressions. +; UDP Coverage data is disabled by default when expression and/or condition +; coverage is active. +; CoverUDP = 1 + +; Enable or disable Rapid Expression Coverage mode for conditions and expressions. +; Disabling this would convert non-masking conditions in FEC tables to matching +; input patterns. +; CoverREC = 1 + +; Enable or disable bit-blasting multi-bit operands of reduction prefix expressions +; for expression/condition coverage. +; NOTE: Enabling this may have a negative impact on simulation performance. +; CoverExpandReductionPrefix = 0 + +; Enable or disable short circuit evaluation of conditions and expressions when +; condition or expression coverage is active. Short circuit evaluation is enabled +; by default. +; CoverShortCircuit = 0 + +; Enable deglitching of code coverage in combinatorial, non-clocked, processes. +; Default is no deglitching. +; CoverDeglitchOn = 1 + +; Control the code coverage deglitching period. A period of 0, eliminates delta +; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a +; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". +; CoverDeglitchPeriod = 0 + +; Turn on code coverage in VLOG `celldefine modules, modules containing +; specify blocks, and modules included using vlog -v and -y. Default is off. +; CoverCells = 1 + +; Enable code coverage reporting of code that has been optimized away. +; The default is not to report. +; CoverReportCancelled = 1 + +; Control compiler and VOPT optimizations that are allowed when +; code coverage is on. This is a number from 0 to 5, with the following +; meanings (the default is 3): +; 5 -- All allowable optimizations are on. +; 4 -- Turn off removing unreferenced code. +; 3 -- Turn off process, always block and if statement merging. +; 2 -- Turn off expression optimization, converting primitives +; to continuous assignments, VHDL subprogram inlining. +; and VHDL clkOpt (converting FF's to builtins). +; 1 -- Turn off continuous assignment optimizations and clock suppression. +; 0 -- Turn off Verilog module inlining and VHDL arch inlining. +; HOWEVER, if fsm coverage is turned on, optimizations will be forced to +; level 3, with also turning off converting primitives to continuous assigns. +; CoverOpt = 3 + +; Specify the override for the default value of "cross_num_print_missing" +; option for the Cross in Covergroups. If not specified then LRM default +; value of 0 (zero) is used. This is a compile time option. +; SVCrossNumPrintMissingDefault = 0 + +; Setting following to 1 would cause creation of variables which +; would represent the value of Coverpoint expressions. This is used +; in conjunction with "SVCoverpointExprVariablePrefix" option +; in the modelsim.ini +; EnableSVCoverpointExprVariable = 0 + +; Specify the override for the prefix used in forming the variable names +; which represent the Coverpoint expressions. This is used in conjunction with +; "EnableSVCoverpointExprVariable" option of the modelsim.ini +; The default prefix is "expr". +; The variable name is +; variable name => <prefix>_<coverpoint name> +; SVCoverpointExprVariablePrefix = expr + +; Override for the default value of the SystemVerilog covergroup, +; coverpoint, and cross option.goal (defined to be 100 in the LRM). +; NOTE: It does not override specific assignments in SystemVerilog +; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal" +; in the [vsim] section can override this value. +; SVCovergroupGoalDefault = 100 + +; Override for the default value of the SystemVerilog covergroup, +; coverpoint, and cross type_option.goal (defined to be 100 in the LRM) +; NOTE: It does not override specific assignments in SystemVerilog +; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal" +; in the [vsim] section can override this value. +; SVCovergroupTypeGoalDefault = 100 + +; Specify the override for the default value of "strobe" option for the +; Covergroup Type. This is a compile time option which forces "strobe" to +; a user specified default value and supersedes SystemVerilog specified +; default value of '0'(zero). NOTE: This can be overriden by a runtime +; modelsim.ini variable "SVCovergroupStrobe" in the [vsim] section. +; SVCovergroupStrobeDefault = 0 + +; Specify the override for the default value of "per_instance" option for the +; Covergroup variables. This is a compile time option which forces "per_instance" +; to a user specified default value and supersedes SystemVerilog specified +; default value of '0'(zero). +; SVCovergroupPerInstanceDefault = 0 + +; Specify the override for the default value of "get_inst_coverage" option for the +; Covergroup variables. This is a compile time option which forces +; "get_inst_coverage" to a user specified default value and supersedes +; SystemVerilog specified default value of '0'(zero). +; SVCovergroupGetInstCoverageDefault = 0 + +; +; A space separated list of resource libraries that contain precompiled +; packages. The behavior is identical to using the "-L" switch. +; +; LibrarySearchPath = <path/lib> [<path/lib> ...] +LibrarySearchPath = mtiAvm mtiRnm mtiOvm mtiUvm mtiUPF infact + +; The behavior is identical to the "-mixedansiports" switch. Default is off. +; MixedAnsiPorts = 1 + +; Enable SystemVerilog 3.1a $typeof() function. Default is off. +; EnableTypeOf = 1 + +; Only allow lower case pragmas. Default is disabled. +; AcceptLowerCasePragmaOnly = 1 + +; Set the maximum depth permitted for a recursive include file nesting. +; IncludeRecursionDepthMax = 5 + +; Turn ON detection of FSMs having single bit current state variable. +; FsmSingle = 1 + +; Turn off reset state transitions in FSM. +; FsmResetTrans = 0 + +; Turn off detections of FSMs having x-assignment. +; FsmXAssign = 0 + +; Turn ON detection of FSM Implicit Transitions. +; FsmImplicitTrans = 1 + +; List of file suffixes which will be read as SystemVerilog. White space +; in extensions can be specified with a back-slash: "\ ". Back-slashes +; can be specified with two consecutive back-slashes: "\\"; +; SvFileSuffixes = sv svp svh + +; This setting is the same as the vlog -sv command line switch. +; Enables SystemVerilog features and keywords when true (1). +; When false (0), the rules of IEEE Std 1364-2005 are followed and +; SystemVerilog keywords are ignored. +; Svlog = 0 + +; Prints attribute placed upon SV packages during package import +; when true (1). The attribute will be ignored when this +; entry is false (0). The attribute name is "mti_design_element_load_message". +; The value of this attribute is a string literal. +; Default is true (1). +; PrintSVPackageLoadingAttribute = 1 + +; Do not show immediate assertions with constant expressions in +; GUI/reports/UCDB etc. By default immediate assertions with constant +; expressions are shown in GUI/reports/UCDB etc. This does not affect +; evaluation of immediate assertions. +; ShowConstantImmediateAsserts = 0 + +; Controls if untyped parameters that are initialized with values greater +; than 2147483647 are mapped to generics of type INTEGER or ignored. +; If mapped to VHDL Integers, values greater than 2147483647 +; are mapped to negative values. +; Default is to map these parameter to generic of type INTEGER +; ForceUnsignedToVHDLInteger = 1 + +; Enable AMS wreal (wired real) extensions. Default is 0. +; WrealType = 1 + +; Controls SystemVerilog Language Extensions. These options enable +; some non-LRM compliant behavior. +; SvExtensions = [+|-]<extension>[,[+|-]<extension>*] + +; Generate symbols debugging database in only some special cases to save on +; the number of files in the library. For other design-units, this database is +; generated on-demand in vsim. +; Default is to to generate debugging database for all design-units. +; SmartDbgSym = 1 + +; Controls how $unit library entries are named. Valid options are: +; "file" (generate name based on the first file on the command line) +; "du" (generate name based on first design unit following an item +; found in $unit scope) +; CUAutoName = file + +; Enable or disable automatic creation of missing libraries. +; Default is 1 (enabled) +; CreateLib = 1 + +[sccom] +; Enable use of SCV include files and library. Default is off. +; UseScv = 1 + +; Add C++ compiler options to the sccom command line by using this variable. +; CppOptions = -g + +; Use custom C++ compiler located at this path rather than the default path. +; The path should point directly at a compiler executable. +; CppPath = /usr/bin/g++ + +; Specify the compiler version from the list of support GNU compilers. +; examples 4.7.4, 5.3.0, 7.4.0 +; CppInstall = 7.4.0 + +; Enable verbose messages from sccom. Default is off. +; SccomVerbose = 1 + +; sccom logfile. Default is no logfile. +; SccomLogfile = sccom.log + +; Enable use of SC_MS include files and library. Default is off. +; UseScMs = 1 + +; Use SystemC-2.2 instead of the default SystemC-2.3. Default is off. +; Sc22Mode = 1 + +; Enable compiler statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list,kb] +; Add '-' to disable specific statistics. Default is [time,cmd,msg]. +; Stats = time,cmd,msg + +; Enable or disable automatic creation of missing libraries. +; Default is 1 (enabled) +; CreateLib = 1 + +; Enable use of UVMC library. Default is off. +; UseUvmc = 1 + +[vopt] +; Turn on code coverage in vopt. Default is off. +; Coverage = sbceft + +; enable or disable param saving in UCDB. +; CoverageSaveParam = 0 + +; Control compiler optimizations that are allowed when +; code coverage is on. Refer to the comment for this in the [vlog] area. +; CoverOpt = 3 + +; Controls set of CoverConstructs that are being considered for Coverage +; Collection. +; Some of Valid options are: default,set1,set2 +; Covermode = default + +; Override all PA VOPT and VSIM commands to run simulation in Non-PA mode. +; NonPAmode = 1 + +; Controls set of HDL cover constructs that would be considered(or not considered) +; for Coverage Collection. (Default corresponds to covermode default). +; Some of Valid options are: "ca", "citf", "cifl", "tcint", "fsmqs". +; Coverconstruct = noca,nocitf,nofsmtf,nofsmds,noctes,nocicl,nocprc,nocfl,nofsmup,nocifl,nocpm,notcint,nocpkg,nocsva + +; Increase or decrease the maximum number of rows allowed in a UDP table +; implementing a VHDL condition coverage or expression coverage expression. +; More rows leads to a longer compile time, but more expressions covered. +; CoverMaxUDPRows = 192 + +; Increase or decrease the maximum number of input patterns that are present +; in FEC table. This leads to a longer compile time with more expressions +; covered with FEC metric. +; CoverMaxFECRows = 192 + +; Enable Multi Bit Expression Coverage in a Design, If design has expression with +; multi bit operands, this option enables its Expression Coverage. +; The default value is 0. +; CoverFecMultiBit = 1 + +; Increase or decrease the limit on the size of expressions and conditions +; considered for expression and condition coverages. Higher FecUdpEffort leads +; to higher compile, optimize and simulation time, but more expressions and +; conditions are considered for coverage in the design. FecUdpEffort can +; be set to a number ranging from 1 (low) to 3 (high), defined as: +; 1 - (low) Only small expressions and conditions considered for coverage. +; 2 - (medium) Bigger expressions and conditions considered for coverage. +; 3 - (high) Very large expressions and conditions considered for coverage. +; The default setting is 1 (low). +; FecUdpEffort = 1 + +; Enable code coverage reporting of code that has been optimized away. +; The default is not to report. +; CoverReportCancelled = 1 + +; Enable deglitching of code coverage in combinatorial, non-clocked, processes. +; Default is no deglitching. +; CoverDeglitchOn = 1 + +; Enable compiler statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list,kb] +; Add '-' to disable specific statistics. Default is [time,cmd,msg]. +; Stats = time,cmd,msg + +; Control the code coverage deglitching period. A period of 0, eliminates delta +; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a +; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". +; CoverDeglitchPeriod = 0 + +; Do not show immediate assertions with constant expressions in +; GUI/reports/UCDB etc. By default immediate assertions with constant +; expressions are shown in GUI/reports/UCDB etc. This does not affect +; evaluation of immediate assertions. +; ShowConstantImmediateAsserts = 0 + +; Set the maximum number of iterations permitted for a generate loop. +; Restricting this permits the implementation to recognize infinite +; generate loops. +; GenerateLoopIterationMax = 100000 + +; Set the maximum depth permitted for a recursive generate instantiation. +; Restricting this permits the implementation to recognize infinite +; recursions. +; GenerateRecursionDepthMax = 200 + +; Set the number of processes created during the code generation phase. +; By default a heuristic is used to set this value. This may be set to 0 +; to disable this feature completely. +; ParallelJobs = 0 + +; Controls SystemVerilog Language Extensions. These options enable +; some non-LRM compliant behavior. +; SvExtensions = [+|-]<extension>[,[+|-]<extension>*] + +; Load the specified shared objects with the RTLD_GLOBAL flag. +; This gives global visibility to all symbols in the shared objects, +; meaning that subsequently loaded shared objects can bind to symbols +; in the global shared objects. The list of shared objects should +; be whitespace delimited. This option is not supported on the +; Windows or AIX platforms. +; GlobalSharedObjectList = example1.so example2.so example3.so + +; Disable SystemVerilog elaboration system task messages +; IgnoreSVAInfo = 1 +; IgnoreSVAWarning = 1 +; IgnoreSVAError = 1 +; IgnoreSVAFatal = 1 + +; Enable or disable automatic creation of missing libraries. +; Default is 1 (enabled) +; CreateLib = 1 + +[vsim] +; vopt flow +; Set to turn on automatic optimization of a design. +; Default is on +VoptFlow = 1 + +; Simulator resolution +; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. +Resolution = ns + +; Disable certain code coverage exclusions automatically. +; Assertions and FSM are exluded from the code coverage by default +; Set AutoExclusionsDisable = fsm to enable code coverage for fsm +; Set AutoExclusionsDisable = assertions to enable code coverage for assertions +; Set AutoExclusionsDisable = all to enable code coverage for all the automatic exclusions +; Or specify comma or space separated list +;AutoExclusionsDisable = fsm,assertions + +; User time unit for run commands +; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the +; unit specified for Resolution. For example, if Resolution is 100ps, +; then UserTimeUnit defaults to ps. +; Should generally be set to default. +UserTimeUnit = default + +; Default run length +RunLength = 10 us + +; Maximum iterations that can be run without advancing simulation time +IterationLimit = 10000000 + +; Specify libraries to be searched for precompiled modules +; LibrarySearchPath = <path/lib> [<path/lib> ...] + +; Set XPROP assertion fail limit. Default is 5. +; Any positive integer, -1 for infinity. +; XpropAssertionLimit = 5 + +; Control PSL and Verilog Assume directives during simulation +; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts +; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts +; SimulateAssumeDirectives = 1 + +; Control the simulation of PSL and SVA +; These switches can be overridden by the vsim command line switches: +; -psl, -nopsl, -sva, -nosva. +; Set SimulatePSL = 0 to disable PSL simulation +; Set SimulatePSL = 1 to enable PSL simulation (default) +; SimulatePSL = 1 +; Set SimulateSVA = 0 to disable SVA simulation +; Set SimulateSVA = 1 to enable concurrent SVA simulation (default) +; SimulateSVA = 1 + +; Control SVA and VHDL immediate assertion directives during simulation +; Set SimulateImmedAsserts = 0 to disable simulation of immediate asserts +; Set SimulateImmedAsserts = 1 to enable simulation of immediate asserts +; SimulateImmedAsserts = 1 + +; License feature mappings for Verilog and VHDL +; qhsimvh Single language VHDL license +; qhsimvl Single language Verilog license +; msimhdlsim Language neutral license for either Verilog or VHDL +; msimhdlmix Second language only, language neutral license for either +; Verilog or VHDL +; +; Directives to license manager can be set either as single value or as +; space separated multi-values: +; vhdl Immediately checkout and hold a VHDL license (i.e., one of +; qhsimvh, msimhdlsim, or msimhdlmix) +; vlog Immediately checkout and hold a Verilog license (i.e., one of +; qhsimvl, msimhdlsim, or msimhdlmix) +; plus Immediately checkout and hold a VHDL license and a Verilog license +; noqueue Do not wait in the license queue when a license is not available +; viewsim Try for viewer license but accept simulator license(s) instead +; of queuing for viewer license (PE ONLY) +; noviewer Disable checkout of msimviewer license feature (PE ONLY) +; noslvhdl Disable checkout of qhsimvh license feature +; noslvlog Disable checkout of qhsimvl license feature +; nomix Disable checkout of msimhdlmix license feature +; nolnl Disable checkout of msimhdlsim license feature +; mixedonly Disable checkout of qhsimvh and qhsimvl license features +; lnlonly Disable checkout of qhsimvh,qhsimvl, and msimhdlmix license features +; +; Examples (remove ";" comment character to activate licensing directives): +; Single directive: +; License = plus +; Multi-directive (Note: space delimited directives): +; License = noqueue plus + +; Severity level of a VHDL assertion message or of a SystemVerilog severity system task +; which will cause a running simulation to stop. +; VHDL assertions and SystemVerilog severity system task that occur with the +; given severity or higher will cause a running simulation to stop. +; This value is ignored during elaboration. +; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal +BreakOnAssertion = 3 + +; Severity level of a tool message which will cause a running simulation to +; stop. This value is ignored during elaboration. Default is to not break. +; 0 = Note 1 = Warning 2 = Error 3 = Fatal +;BreakOnMessage = 2 + +; The class debug feature enables more visibility and tracking of class instances +; during simulation. By default this feature is disabled (0). To enable this +; feature set ClassDebug to 1. +; ClassDebug = 1 + +; Message Format conversion specifications: +; %S - Severity Level of message/assertion +; %R - Text of message +; %T - Time of message +; %D - Delta value (iteration number) of Time +; %K - Kind of path: Instance/Region/Signal/Process/Foreign Process/Unknown/Protected +; %i - Instance/Region/Signal pathname with Process name (if available) +; %I - shorthand for one of these: +; " %K: %i" +; " %K: %i File: %F" (when path is not Process or Signal) +; except that the %i in this case does not report the Process name +; %O - Process name +; %P - Instance/Region path without leaf process +; %F - File name +; %L - Line number; if assertion message, then line number of assertion or, if +; assertion is in a subprogram, line from which the call is made +; %u - Design unit name in form library.primary +; %U - Design unit name in form library.primary(secondary) +; %% - The '%' character itself +; +; If specific format for Severity Level is defined, use that format. +; Else, for a message that occurs during elaboration: +; -- Failure/Fatal message in VHDL region that is not a Process, and in +; certain non-VHDL regions, uses MessageFormatBreakLine; +; -- Failure/Fatal message otherwise uses MessageFormatBreak; +; -- Note/Warning/Error message uses MessageFormat. +; Else, for a message that occurs during runtime and triggers a breakpoint because +; of the BreakOnAssertion setting: +; -- if in a VHDL region that is not a Process, uses MessageFormatBreakLine; +; -- otherwise uses MessageFormatBreak. +; Else (a runtime message that does not trigger a breakpoint) uses MessageFormat. +; +; MessageFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n" +; MessageFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n" +; MessageFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormatBreakLine = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F Line: %L\n" +; MessageFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" + +; Error File - alternate file for storing error messages +; ErrorFile = error.log + +; Simulation Breakpoint messages +; This flag controls the display of function names when reporting the location +; where the simulator stops because of a breakpoint or fatal error. +; Example with function name: # Break in Process ctr at counter.vhd line 44 +; Example without function name: # Break at counter.vhd line 44 +; Default value is 1. +ShowFunctions = 1 + +; Default radix for all windows and commands. +; Radix may be one of: symbolic, ascii, binary, octal, decimal, hex, unsigned +; Flags may be one of: enumnumeric, showbase, wreal +DefaultRadix = hexadecimal +DefaultRadixFlags = showbase +; Set to 1 for make the signal_force VHDL and Verilog functions use the +; default radix when processing the force value. Prior to 10.2 signal_force +; used the default radix, now it always uses symbolic unless value explicitly indicates base +;SignalForceFunctionUseDefaultRadix = 0 + +; VSIM Startup command +; Startup = do startup.do + +; VSIM Shutdown file +; Filename to save u/i formats and configurations. +; ShutdownFile = restart.do +; To explicitly disable auto save: +; ShutdownFile = --disable-auto-save + +; Run simulator in batch mode as if -batch were specified on the command line if none of -c, -gui, or -i specified. +; Simulator runs in interactive mode as if -i were specified if this option is 0. Default is 0. +; BatchMode = 1 + +; File for saving command transcript when -batch option used +; This option is ignored when -c, -gui, or -i options are used or if BatchMode above is zero +; default is unset so command transcript only goes to stdout for better performance +; BatchTranscriptFile = transcript + +; File for saving command transcript, this option is ignored when -batch option is used +TranscriptFile = transcript + +; Transcript file long line wrapping mode(s) +; mode == 0 :: no wrapping, line recorded as is +; mode == 1 :: wrap at first whitespace after WSColumn +; or at Column. +; mode == 2 :: wrap as above, but add continuation +; character ('\') at end of each wrapped line +; +; WrapMode = 0 +; WrapColumn = 30000 +; WrapWSColumn = 27000 + +; File for saving command history +; CommandHistory = cmdhist.log + +; Specify whether paths in simulator commands should be described +; in VHDL or Verilog format. +; For VHDL, PathSeparator = / +; For Verilog, PathSeparator = . +; Must not be the same character as DatasetSeparator. +PathSeparator = / + +; Specify the dataset separator for fully rooted contexts. +; The default is ':'. For example: sim:/top +; Must not be the same character as PathSeparator. +DatasetSeparator = : + +; Specify a unique path separator for the Signal Spy set of functions. +; The default will be to use the PathSeparator variable. +; Must not be the same character as DatasetSeparator. +; SignalSpyPathSeparator = / + +; Used to control parsing of HDL identifiers input to the tool. +; This includes CLI commands, vsim/vopt/vlog/vcom options, +; string arguments to FLI/VPI/DPI calls, etc. +; If set to 1, accept either Verilog escaped Id syntax or +; VHDL extended id syntax, regardless of source language. +; If set to 0, the syntax of the source language must be used. +; Each identifier in a hierarchical name may need different syntax, +; e.g. "/top/\vhdl*ext*id\/middle/\vlog*ext*id /bottom" or +; "top.\vhdl*ext*id\.middle.\vlog*ext*id .bottom" +; GenerousIdentifierParsing = 1 + +; Disable VHDL assertion messages +; IgnoreNote = 1 +; IgnoreWarning = 1 +; IgnoreError = 1 +; IgnoreFailure = 1 + +; Disable SystemVerilog assertion messages +; IgnoreSVAInfo = 1 +; IgnoreSVAWarning = 1 +; IgnoreSVAError = 1 +; IgnoreSVAFatal = 1 + +; Do not print any additional information from Severity System tasks. +; Only the message provided by the user is printed along with severity +; information. +; SVAPrintOnlyUserMessage = 1; + +; Default force kind. May be freeze, drive, deposit, or default +; or in other terms, fixed, wired, or charged. +; A value of "default" will use the signal kind to determine the +; force kind, drive for resolved signals, freeze for unresolved signals +; DefaultForceKind = freeze + +; Control the iteration of events when a VHDL signal is forced to a value +; This flag can be set to honour the signal update event in next iteration, +; the default is to update and propagate in the same iteration. +; ForceSigNextIter = 1 + +; Enable simulation statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list,kb,eor] +; Add '-' to disable specific statistics. Default is [time,cmd,msg]. +; Stats = time,cmd,msg + +; If zero, open files when elaborated; otherwise, open files on +; first read or write. Default is 0. +; DelayFileOpen = 1 + +; Control VHDL files opened for write. +; 0 = Buffered, 1 = Unbuffered +UnbufferedOutput = 0 + +; Control the number of VHDL files open concurrently. +; This number should always be less than the current ulimit +; setting for max file descriptors. +; 0 = unlimited +ConcurrentFileLimit = 40 + +; If nonzero, close files as soon as there is either an explicit call to +; file_close, or when the file variable's scope is closed. When zero, a +; file opened in append mode is not closed in case it is immediately +; reopened in append mode; otherwise, the file will be closed at the +; point it is reopened. +; AppendClose = 1 + +; Control the number of hierarchical regions displayed as +; part of a signal name shown in the Wave window. +; A value of zero tells VSIM to display the full name. +; The default is 0. +; WaveSignalNameWidth = 0 + +; Turn off warnings when changing VHDL constants and generics +; Default is 1 to generate warning messages +; WarnConstantChange = 0 + +; Turn off warnings from accelerated versions of the std_logic_arith, +; std_logic_unsigned, and std_logic_signed packages. +; StdArithNoWarnings = 1 + +; Turn off warnings from accelerated versions of the IEEE numeric_std +; and numeric_bit packages. +; NumericStdNoWarnings = 1 + +; Use old-style (pre-6.6) VHDL FOR GENERATE statement iteration names +; in the design hierarchy. +; This style is controlled by the value of the GenerateFormat +; value described next. Default is to use new-style names, which +; comprise the generate statement label, '(', the value of the generate +; parameter, and a closing ')'. +; Set this to 1 to use old-style names. +; OldVhdlForGenNames = 1 + +; Control the format of the old-style VHDL FOR generate statement region +; name for each iteration. Do not quote the value. +; The format string here must contain the conversion codes %s and %d, +; in that order, and no other conversion codes. The %s represents +; the generate statement label; the %d represents the generate parameter value +; at a particular iteration (this is the position number if the generate parameter +; is of an enumeration type). Embedded whitespace is allowed (but discouraged); +; leading and trailing whitespace is ignored. +; Application of the format must result in a unique region name over all +; loop iterations for a particular immediately enclosing scope so that name +; lookup can function properly. The default is %s__%d. +; GenerateFormat = %s__%d + +; Enable more efficient logging of VHDL Variables. +; Logging VHDL variables without this enabled, while possible, is very +; inefficient. Enabling this will provide a more efficient logging methodology +; at the expense of more memory usage. By default this feature is disabled (0). +; To enabled this feature, set this variable to 1. +; VhdlVariableLogging = 1 + +; Enable logging of VHDL access type variables and their designated objects. +; This setting will allow both variables of an access type ("access variables") +; and their designated objects ("access objects") to be logged. Logging a +; variable of an access type will automatically also cause the designated +; object(s) of that variable to be logged as the simulation progresses. +; Further, enabling this allows access objects to be logged by name. By default +; this feature is disabled (0). To enable this feature, set this variable to 1. +; Enabling this will automatically enable the VhdlVariableLogging feature also. +; AccessObjDebug = 1 + +; Make each VHDL package in a PDU has its own separate copy of the package instead +; of sharing the package between PDUs. The default is to share packages. +; To ensure that each PDU has its own set of packages, set this variable to 1. +; VhdlSeparatePduPackage = 1 + +; Specify whether checkpoint files should be compressed. +; The default is 1 (compressed). +; CheckpointCompressMode = 0 + +; Specify gcc compiler used in the compilation of automatically generated DPI exportwrapper. +; Use custom gcc compiler located at this path rather than the default path. +; The path should point directly at a compiler executable. +; DpiCppPath = <your-gcc-installation>/bin/gcc +; +; Specify the compiler version from the list of support GNU compilers. +; examples 4.7.4, 5.3.0, 7.4.0 +; DpiCppInstall = 7.4.0 + +; Specify whether to enable SystemVerilog DPI "out-of-the-blue" calls. +; The term "out-of-the-blue" refers to SystemVerilog export function calls +; made from C functions that don't have the proper context setup +; (as is the case when running under "DPI-C" import functions). +; When this is enabled, one can call a DPI export function +; (but not task) from any C code. +; the setting of this variable can be one of the following values: +; 0 : dpioutoftheblue call is disabled (default) +; 1 : dpioutoftheblue call is enabled, but export call debug support is not available. +; 2 : dpioutoftheblue call is enabled, and limited export call debug support is available. +; DpiOutOfTheBlue = 1 + +; Specify whether continuous assignments are run before other normal priority +; processes scheduled in the same iteration. This event ordering minimizes race +; differences between optimized and non-optimized designs, and is the default +; behavior beginning with the 6.5 release. For pre-6.5 event ordering, set +; ImmediateContinuousAssign to 0. +; The default is 1 (enabled). +; ImmediateContinuousAssign = 0 + +; List of dynamically loaded objects for Verilog PLI applications +; Veriuser = veriuser.sl + +; Which default VPI object model should the tool conform to? +; The 1364 modes are Verilog-only, for backwards compatibility with older +; libraries, and SystemVerilog objects are not available in these modes. +; +; In the absence of a user-specified default, the tool default is the +; latest available LRM behavior. +; Options for PliCompatDefault are: +; VPI_COMPATIBILITY_VERSION_1364v1995 +; VPI_COMPATIBILITY_VERSION_1364v2001 +; VPI_COMPATIBILITY_VERSION_1364v2005 +; VPI_COMPATIBILITY_VERSION_1800v2005 +; VPI_COMPATIBILITY_VERSION_1800v2008 +; +; Synonyms for each string are also recognized: +; VPI_COMPATIBILITY_VERSION_1364v1995 (1995, 95, 1364v1995, 1364V1995, VL1995) +; VPI_COMPATIBILITY_VERSION_1364v2001 (2001, 01, 1364v2001, 1364V2001, VL2001) +; VPI_COMPATIBILITY_VERSION_1364v2005 (1364v2005, 1364V2005, VL2005) +; VPI_COMPATIBILITY_VERSION_1800v2005 (2005, 05, 1800v2005, 1800V2005, SV2005) +; VPI_COMPATIBILITY_VERSION_1800v2008 (2008, 08, 1800v2008, 1800V2008, SV2008) + + +; PliCompatDefault = VPI_COMPATIBILITY_VERSION_1800v2005 + +; Specify whether the Verilog system task $fopen or vpi_mcd_open() +; will create directories that do not exist when opening the file +; in "a" or "w" mode. +; The default is 0 (do not create non-existent directories) +; CreateDirForFileAccess = 1 + +; Specify default options for the restart command. Options can be one +; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions +; DefaultRestartOptions = -force + + +; Specify default UVM-aware debug options if the vsim -uvmcontrol switch is not used. +; Valid options include: all, none, verbose, disable, struct, reseed, msglog, trlog, certe. +; Options can be enabled by just adding the name, or disabled by prefixing the option with a "-". +; The list of options must be delimited by commas, without spaces or tabs. +; +; Some examples +; To turn on all available UVM-aware debug features: +; UVMControl = all +; To turn on the struct window, mesage logging, and transaction logging: +; UVMControl = struct,msglog,trlog +; To turn on all options except certe: +; UVMControl = all,-certe +; To completely disable all UVM-aware debug functionality: +; UVMControl = disable + +; Specify the WildcardFilter setting. +; A space separated list of object types to be excluded when performing +; wildcard matches with log, wave, etc commands. The default value for this variable is: +; "Variable Constant Generic Parameter SpecParam Memory Assertion Cover Endpoint ScVariable CellInternal ImmediateAssert VHDLFile" +; See "Using the WildcardFilter Preference Variable" in the documentation for +; details on how to use this variable and for descriptions of the filter types. +WildcardFilter = Variable Constant Generic Parameter SpecParam Memory Assertion Cover Endpoint ScVariable CellInternal ImmediateAssert VHDLFile + +; Specify the WildcardSizeThreshold setting. +; This integer setting specifies the size at which objects will be excluded when +; performing wildcard matches with log, wave, etc commands. Objects of size equal +; to or greater than the WildcardSizeThreshold will be filtered out from the wildcard +; matches. The size is a simple calculation of number of bits or items in the object. +; The default value is 8k (8192). Setting this value to 0 will disable the checking +; of object size against this threshold and allow all objects of any size to be logged. +WildcardSizeThreshold = 8192 + +; Specify whether warning messages are output when objects are filtered out due to the +; WildcardSizeThreshold. The default is 0 (no messages generated). +WildcardSizeThresholdVerbose = 0 + +; Turn on (1) or off (0) WLF file compression. +; The default is 1 (compress WLF file). +; WLFCompress = 0 + +; Specify whether to save all design hierarchy (1) in the WLF file +; or only regions containing logged signals (0). +; The default is 0 (save only regions with logged signals). +; WLFSaveAllRegions = 1 + +; WLF file time limit. Limit WLF file by time, as closely as possible, +; to the specified amount of simulation time. When the limit is exceeded +; the earliest times get truncated from the file. +; If both time and size limits are specified the most restrictive is used. +; UserTimeUnits are used if time units are not specified. +; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} +; WLFTimeLimit = 0 + +; WLF file size limit. Limit WLF file size, as closely as possible, +; to the specified number of megabytes. If both time and size limits +; are specified then the most restrictive is used. +; The default is 0 (no limit). +; WLFSizeLimit = 1000 + +; Specify whether or not a WLF file should be deleted when the +; simulation ends. A value of 1 will cause the WLF file to be deleted. +; The default is 0 (do not delete WLF file when simulation ends). +; WLFDeleteOnQuit = 1 + +; Specify whether or not a WLF file should be optimized during +; simulation. If set to 0, the WLF file will not be optimized. +; The default is 1, optimize the WLF file. +; WLFOptimize = 0 + +; Specify the name of the WLF file. +; The default is vsim.wlf +; WLFFilename = vsim.wlf + +; Specify whether to lock the WLF file. +; Locking the file prevents other invocations of ModelSim/Questa tools from +; inadvertently overwriting the WLF file. +; The default is 1, lock the WLF file. +; WLFFileLock = 0 + +; Specify the update interval for the WLF file in live simulation. +; The interval is given in seconds. +; The value is the smallest interval between WLF file updates. The WLF file +; will be flushed (updated) after (at least) the interval has elapsed, ensuring +; that the data is correct when viewed from a separate viewer. +; A value of 0 means that no updating will occur. +; The default value is 10 seconds. +; WLFUpdateInterval = 10 + +; Specify the WLF cache size limit for WLF files. +; The value is given in megabytes. A value of 0 turns off the cache. +; On non-Windows platforms the default WLFCacheSize setting is 2000 (megabytes). +; On Windows, the default value is 1000 (megabytes) to help to avoid filling +; process memory. +; WLFSimCacheSize allows a different cache size to be set for a live simulation +; WLF file, independent of post-simulation WLF file viewing. If WLFSimCacheSize +; is not set, it defaults to the WLFCacheSize value. +; WLFCacheSize = 2000 +; WLFSimCacheSize = 500 + +; Specify the WLF file event collapse mode. +; 0 = Preserve all events and event order. (same as -wlfnocollapse) +; 1 = Only record values of logged objects at the end of a simulator iteration. +; (same as -wlfcollapsedelta) +; 2 = Only record values of logged objects at the end of a simulator time step. +; (same as -wlfcollapsetime) +; The default is 1. +; WLFCollapseMode = 0 + +; Specify whether WLF file logging can use threads on multi-processor machines. +; If 0, no threads will be used; if 1, threads will be used if the system has +; more than one processor. +; WLFUseThreads = 1 + +; Specify the size of objects that will trigger "large object" messages +; at log/wave/list time. The size calculation of the object is the same as that +; used by the WildcardSizeThreshold. The default LargeObjectSize size is 500,000. +; Setting LargeObjectSize to 0 will disable these messages. +; LargeObjectSize = 500000 + +; Specify the depth of stack frames returned by $stacktrace([level]). +; This depth will be picked up when the optional 'level' argument +; is not specified or its value is not a positive integer. +; StackTraceDepth = 100 + +; Turn on/off undebuggable SystemC type warnings. Default is on. +; ShowUndebuggableScTypeWarning = 0 + +; Turn on/off unassociated SystemC name warnings. Default is off. +; ShowUnassociatedScNameWarning = 1 + +; Turn on/off SystemC IEEE 1666 deprecation warnings. Default is off. +; ScShowIeeeDeprecationWarnings = 1 + +; Turn on/off the check for multiple drivers on a SystemC sc_signal. Default is off. +; For SystemC-2.3.2 the valid values are 0,1 and 2 +; 0 = SC_SIGNAL_WRITE_CHECK_DISABLE_ +; 1 = SC_SIGNAL_WRITE_CHECK_DEFAULT_ +; 2 = SC_SIGNAL_WRITE_CHECK_CONFLICT_ +; For SystemC-2.2 the valid values are 0 and 1 +; 0 = DISABLE +; 1 = ENABLE +; ScEnableScSignalWriteCheck = 1 + +; Set SystemC default time unit. +; Set to fs, ps, ns, us, ms, or sec with optional +; prefix of 1, 10, or 100. The default is 1 ns. +; The ScTimeUnit value is honored if it is coarser than Resolution. +; If ScTimeUnit is finer than Resolution, it is set to the value +; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns, +; then the default time unit will be 1 ns. However if Resolution +; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns. +ScTimeUnit = ns + +; Set SystemC sc_main stack size. The stack size is set as an integer +; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or +; Gb(Giga-byte). Default is 10 Mb. The stack size for sc_main depends +; on the amount of data on the sc_main() stack and the memory required +; to succesfully execute the longest function call chain of sc_main(). +ScMainStackSize = 10 Mb + +; Set SystemC thread stack size. The stack size is set as an integer +; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or +; Gb(Giga-byte). The stack size for sc_thread depends +; on the amount of data on the sc_thread stack and the memory required +; to succesfully execute the thread. +; ScStackSize = 1 Mb + +; Turn on/off execution of remainder of sc_main upon quitting the current +; simulation session. If the cumulative length of sc_main() in terms of +; simulation time units is less than the length of the current simulation +; run upon quit or restart, sc_main() will be in the middle of execution. +; This switch gives the option to execute the remainder of sc_main upon +; quitting simulation. The drawback of not running sc_main till the end +; is memory leaks for objects created by sc_main. If on, the remainder of +; sc_main will be executed ignoring all delays. This may cause the simulator +; to crash if the code in sc_main is dependent on some simulation state. +; Default is on. +ScMainFinishOnQuit = 1 + +; Enable calling of the DPI export taks/functions from the +; SystemC start_of_simulation() callback. +; The default is off. +; EnableDpiSosCb = 1 + + +; Set the SCV relationship name that will be used to identify phase +; relations. If the name given to a transactor relation matches this +; name, the transactions involved will be treated as phase transactions +ScvPhaseRelationName = mti_phase + +; Customize the vsim kernel shutdown behavior at the end of the simulation. +; Some common causes of the end of simulation are $finish (implicit or explicit), +; sc_stop(), tf_dofinish(), and assertion failures. +; This should be set to "ask", "exit", or "stop". The default is "ask". +; "ask" -- In batch mode, the vsim kernel will abruptly exit. +; In GUI mode, a dialog box will pop up and ask for user confirmation +; whether or not to quit the simulation. +; "stop" -- Cause the simulation to stay loaded in memory. This can make some +; post-simulation tasks easier. +; "exit" -- The simulation will abruptly exit without asking for any confirmation. +; "final" -- Run SystemVerilog final blocks then behave as "stop". +; Note: This variable can be overridden with the vsim "-onfinish" command line switch. +OnFinish = ask + +; Print pending deferred assertion messages. +; Deferred assertion messages may be scheduled after the $finish in the same +; time step. Deferred assertions scheduled to print after the $finish are +; printed before exiting with severity level NOTE since it's not known whether +; the assertion is still valid due to being printed in the active region +; instead of the reactive region where they are normally printed. +; OnFinishPendingAssert = 1; + +; Print "simstats" result. Default is 0. +; 0 == do not print simstats +; 1 == print at end of simulation +; 2 == print at end of each run command and end of simulation +; PrintSimStats = 1 + +; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages +; AssertFile = assert.log + +; Enable assertion counts. Default is off. +; AssertionCounts = 1 + +; Run simulator in assertion debug mode. Default is off. +; AssertionDebug = 1 + +; Turn on/off PSL/SVA/VHDL assertion enable. Default is on. +; AssertionEnable = 0 + +; Set PSL/SVA/VHDL concurrent assertion fail limit. Default is -1. +; Any positive integer, -1 for infinity. +; AssertionLimit = 1 + +; Turn on/off concurrent assertion pass log. Default is off. +; Assertion pass logging is only enabled when assertion is browseable +; and assertion debug is enabled. +; AssertionPassLog = 1 + +; Turn on/off PSL concurrent assertion fail log. Default is on. +; The flag does not affect SVA +; AssertionFailLog = 0 + +; Turn on/off SVA concurrent assertion local var printing in -assertdebug mode. Default is on. +; AssertionFailLocalVarLog = 0 + +; Set action type for PSL/SVA concurrent assertion fail action. Default is continue. +; 0 = Continue 1 = Break 2 = Exit +; AssertionFailAction = 1 + +; Enable the active thread monitor in the waveform display when assertion debug is enabled. +; AssertionActiveThreadMonitor = 1 + +; Control how many waveform rows will be used for displaying the active threads. Default is 5. +; AssertionActiveThreadMonitorLimit = 5 + +; Assertion thread limit after which assertion would be killed/switched off. +; The default is -1 (unlimited). If the number of threads for an assertion go +; beyond this limit, the assertion would be either switched off or killed. This +; limit applies to only assert directives. +;AssertionThreadLimit = -1 + +; Action to be taken once the assertion thread limit is reached. Default +; is kill. It can have a value of off or kill. In case of kill, all the existing +; threads are terminated and no new attempts are started. In case of off, the +; existing attempts keep on evaluating but no new attempts are started. This +; variable applies to only assert directives. +;AssertionThreadLimitAction = kill + +; Cover thread limit after which cover would be killed/switched off. +; The default is -1 (unlimited). If the number of threads for a cover go +; beyond this limit, the cover would be either switched off or killed. This +; limit applies to only cover directives. +;CoverThreadLimit = -1 + +; Action to be taken once the cover thread limit is reached. Default +; is kill. It can have a value of off or kill. In case of kill, all the existing +; threads are terminated and no new attempts are started. In case of off, the +; existing attempts keep on evaluating but no new attempts are started. This +; variable applies to only cover directives. +;CoverThreadLimitAction = kill + + +; By default immediate assertions do not participate in Assertion Coverage calculations +; unless they are executed. This switch causes all immediate assertions in the design +; to participate in Assertion Coverage calculations, whether attempted or not. +; UnattemptedImmediateAssertions = 0 + +; By default immediate covers participate in Coverage calculations +; whether they are attempted or not. This switch causes all unattempted +; immediate covers in the design to stop participating in Coverage +; calculations. +; UnattemptedImmediateCovers = 0 + +; By default pass action block is not executed for assertions on vacuous +; success. The following variable is provided to enable execution of +; pass action block on vacuous success. The following variable is only effective +; if the user does not disable pass action block execution by using either +; system tasks or CLI. Also there is a performance penalty for enabling +; the following variable. +;AssertionEnableVacuousPassActionBlock = 1 + +; As per strict 1850-2005 PSL LRM, an always property can either pass +; or fail. However, by default, Questa reports multiple passes and +; multiple fails on top always/never property (always/never operator +; is the top operator under Verification Directive). The reason +; being that Questa reports passes and fails on per attempt of the +; top always/never property. Use the following flag to instruct +; Questa to strictly follow LRM. With this flag, all assert/never +; directives will start an attempt once at start of simulation. +; The attempt can either fail, match or match vacuously. +; For e.g. if always is the top operator under assert, the always will +; keep on checking the property at every clock. If the property under +; always fails, the directive will be considered failed and no more +; checking will be done for that directive. A top always property, +; if it does not fail, will show a pass at end of simulation. +; The default value is '0' (i.e. zero is off). For example: +; PslOneAttempt = 1 + +; Specify the number of clock ticks to represent infinite clock ticks. +; This affects eventually!, until! and until_!. If at End of Simulation +; (EOS) an active strong-property has not clocked this number of +; clock ticks then neither pass or fail (vacuous match) is returned +; else respective fail/pass is returned. The default value is '0' (zero) +; which effectively does not check for clock tick condition. For example: +; PslInfinityThreshold = 5000 + +; Control how many thread start times will be preserved for ATV viewing for a given assertion +; instance. Default is -1 (ALL). +; ATVStartTimeKeepCount = -1 + +; Turn on/off code coverage +; CodeCoverage = 0 + +; This option applies to condition and expression coverage UDP tables. It +; has no effect unless UDP is enabled for coverage with vcom/vlog/vopt -coverudp. +; If this option is used and a match occurs in more than one row in the UDP table, +; none of the counts for all matching rows is incremented. By default, counts are +; incremented for all matching rows. +; CoverCountAll = 1 + +; Turn off automatic inclusion of VHDL integers in toggle coverage. Default +; is to include them. +; ToggleNoIntegers = 1 + +; Set the maximum number of values that are collected for toggle coverage of +; VHDL integers. Default is 100; +; ToggleMaxIntValues = 100 + +; Set the maximum number of values that are collected for toggle coverage of +; Verilog real. Default is 100; +; ToggleMaxRealValues = 100 + +; Turn on automatic inclusion of Verilog integers in toggle coverage, except +; for enumeration types. Default is to include them. +; ToggleVlogIntegers = 0 + +; Turn on automatic inclusion of Verilog real type in toggle coverage, except +; for shortreal types. Default is to not include them. +; ToggleVlogReal = 1 + +; Turn on automatic inclusion of Verilog fixed-size unpacked arrays, VHDL multi-d arrays +; and VHDL arrays-of-arrays in toggle coverage. +; Default is to not include them. +; ToggleFixedSizeArray = 1 + +; Increase or decrease the maximum size of Verilog unpacked fixed-size arrays, +; VHDL multi-d arrays and VHDL arrays-of-arrays that are included for toggle coverage. +; This leads to a longer simulation time with bigger arrays covered with toggle coverage. +; Default is 1024. +; ToggleMaxFixedSizeArray = 1024 + +; Treat Verilog multi-dimensional packed vectors and packed structures as equivalently sized +; one-dimensional packed vectors for toggle coverage. Default is 0. +; TogglePackedAsVec = 0 + +; Treat Verilog enumerated types as equivalently sized one-dimensional packed vectors for +; toggle coverage. Default is 0. +; ToggleVlogEnumBits = 0 + +; Turn off automatic inclusion of VHDL records in toggle coverage. +; Default is to include them. +; ToggleVHDLRecords = 0 + +; Limit the widths of registers automatically tracked for toggle coverage. Default is 128. +; For unlimited width, set to 0. +; ToggleWidthLimit = 128 + +; Limit the counts that are tracked for toggle coverage. When all edges for a bit have +; reached this count, further activity on the bit is ignored. Default is 1. +; For unlimited counts, set to 0. +; ToggleCountLimit = 1 + +; Change the mode of extended toggle coverage. Default is 3. Valid modes are 1, 2 and 3. +; Following is the toggle coverage calculation criteria based on extended toggle mode: +; Mode 1: 0L->1H & 1H->0L & any one 'Z' transition (to/from 'Z'). +; Mode 2: 0L->1H & 1H->0L & one transition to 'Z' & one transition from 'Z'. +; Mode 3: 0L->1H & 1H->0L & all 'Z' transitions. +; ExtendedToggleMode = 3 + +; Enable toggle statistics collection only for ports. Default is 0. +; TogglePortsOnly = 1 + +; Limit the counts that are tracked for Focussed Expression Coverage. When a bin has +; reached this count, further tracking of the input patterns linked to it is ignored. +; Default is 1. For unlimited counts, set to 0. +; NOTE: Changing this value from its default value may affect simulation performance. +; FecCountLimit = 1 + +; Limit the counts that are tracked for UDP Coverage. When a bin has +; reached this count, further tracking of the input patterns linked to it is ignored. +; Default is 1. For unlimited counts, set to 0. +; NOTE: Changing this value from its default value may affect simulation performance. +; UdpCountLimit = 1 + +; Control toggle coverage deglitching period. A period of 0, eliminates delta +; cycle glitches. This is the default. The value of ToggleDeglitchPeriod needs to be either +; 0 or a time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". +; ToggleDeglitchPeriod = 10.0ps + +; Turn on/off all PSL/SVA cover directive enables. Default is on. +; CoverEnable = 0 + +; Turn on/off PSL/SVA cover log. Default is off "0". +; CoverLog = 1 + +; Set "at_least" value for all PSL/SVA cover directives. Default is 1. +; CoverAtLeast = 2 + +; Set "limit" value for all PSL/SVA cover directives. Default is -1. +; Any positive integer, -1 for infinity. +; CoverLimit = 1 + +; Specify the coverage database filename. +; Default is "" (i.e. database is NOT automatically saved on close). +; UCDBFilename = vsim.ucdb + +; Specify the maximum limit for the number of Cross (bin) products reported +; in XML and UCDB report against a Cross. A warning is issued if the limit +; is crossed. Default is zero. vsim switch -cvgmaxrptrhscross can override this +; setting. +; MaxReportRhsSVCrossProducts = 1000 + +; Specify the override for the "auto_bin_max" option for the Covergroups. +; If not specified then value from Covergroup "option" is used. +; SVCoverpointAutoBinMax = 64 + +; Specify the override for the value of "cross_num_print_missing" +; option for the Cross in Covergroups. If not specified then value +; specified in the "option.cross_num_print_missing" is used. This +; is a runtime option. NOTE: This overrides any "cross_num_print_missing" +; value specified by user in source file and any SVCrossNumPrintMissingDefault +; specified in modelsim.ini. +; SVCrossNumPrintMissing = 0 + +; Specify whether to use the value of "cross_num_print_missing" +; option in report and GUI for the Cross in Covergroups. If not specified then +; cross_num_print_missing is ignored for creating reports and displaying +; covergroups in GUI. Default is 0, which means ignore "cross_num_print_missing". +; UseSVCrossNumPrintMissing = 0 + +; Specify the threshold of Coverpoint wildcard bin value range size, above which +; a warning will be triggered. The default is 4K -- 12 wildcard bits. +; SVCoverpointWildCardBinValueSizeWarn = 4096 + +; Specify the override for the value of "strobe" option for the +; Covergroup Type. If not specified then value in "type_option.strobe" +; will be used. This is runtime option which forces "strobe" to +; user specified value and supersedes user specified values in the +; SystemVerilog Code. NOTE: This also overrides the compile time +; default value override specified using "SVCovergroupStrobeDefault" +; SVCovergroupStrobe = 0 + +; Override for explicit assignments in source code to "option.goal" of +; SystemVerilog covergroup, coverpoint, and cross. It also overrides the +; default value of "option.goal" (defined to be 100 in the SystemVerilog +; LRM) and the value of modelsim.ini variable "SVCovergroupGoalDefault". +; SVCovergroupGoal = 100 + +; Override for explicit assignments in source code to "type_option.goal" of +; SystemVerilog covergroup, coverpoint, and cross. It also overrides the +; default value of "type_option.goal" (defined to be 100 in the SystemVerilog +; LRM) and the value of modelsim.ini variable "SVCovergroupTypeGoalDefault". +; SVCovergroupTypeGoal = 100 + +; Enforce the 6.3 behavior of covergroup get_coverage() and get_inst_coverage() +; builtin functions, and report. This setting changes the default values of +; option.get_inst_coverage and type_option.merge_instances to ensure the 6.3 +; behavior if explicit assignments are not made on option.get_inst_coverage and +; type_option.merge_instances by the user. There are two vsim command line +; options, -cvg63 and -nocvg63 to override this setting from vsim command line. +; The default value of this variable from release 6.6 onwards is 0. This default +; drives compliance with the clarified behavior in the IEEE 1800-2009 standard. +; SVCovergroup63Compatibility = 0 + +; Enforce the default behavior of covergroup get_coverage() builtin function, GUI +; and report. This variable sets the default value of type_option.merge_instances. +; There are two vsim command line options, -cvgmergeinstances and +; -nocvgmergeinstances to override this setting from vsim command line. +; The default value of this variable, -1 (don't care), allows the tool to determine +; the effective value, based on factors related to capacity and optimization. +; The type_option.merge_instances appears in the GUI and coverage reports as either +; auto(1) or auto(0), depending on whether the effective value was determined to +; be a 1 or a 0. +; SVCovergroupMergeInstancesDefault = -1 + +; Enable or disable generation of more detailed information about the sampling +; of covergroup, cross, and coverpoints. It provides the details of the number +; of times the covergroup instance and type were sampled, as well as details +; about why covergroup, cross and coverpoint were not covered. A non-zero value +; is to enable this feature. 0 is to disable this feature. Default is 0 +; SVCovergroupSampleInfo = 0 + +; Specify the maximum number of Coverpoint bins in whole design for +; all Covergroups. +; MaxSVCoverpointBinsDesign = 2147483648 + +; Specify maximum number of Coverpoint bins in any instance of a Covergroup, default is 2^10 bins +; MaxSVCoverpointBinsInst = 1048576 + +; Specify the maximum number of Cross bins in whole design for +; all Covergroups. +; MaxSVCrossBinsDesign = 2147483648 + +; Specify maximum number of Cross bins in any instance of a Covergroup, default is 2^16 bins +; MaxSVCrossBinsInst = 67108864 + +; Specify whether vsim will collect the coverage data of zero-weight coverage items or not. +; By default, this variable is set 0, in which case option.no_collect setting will take effect. +; If this variable is set to 1, all zero-weight coverage items will not be saved. +; Note that the usage of vsim switch -cvgzwnocollect, if present, will override the setting +; of this variable. +; CvgZWNoCollect = 1 + +; Specify a space delimited list of double quoted TCL style +; regular expressions which will be matched against the text of all messages. +; If any regular expression is found to be contained within any message, the +; status for that message will not be propagated to the UCDB TESTSTATUS. +; If no match is detected, then the status will be propagated to the +; UCDB TESTSTATUS. More than one such regular expression text is allowed, +; and each message text is compared for each regular expression in the list. +; UCDBTestStatusMessageFilter = "Done with Test Bench" "Ignore .* message" + +; Set weight for all PSL/SVA cover directives. Default is 1. +; CoverWeight = 2 + +; Check vsim plusargs. Default is 0 (off). +; 0 = Don't check plusargs +; 1 = Warning on unrecognized plusarg +; 2 = Error and exit on unrecognized plusarg +; CheckPlusargs = 1 + +; Load the specified shared objects with the RTLD_GLOBAL flag. +; This gives global visibility to all symbols in the shared objects, +; meaning that subsequently loaded shared objects can bind to symbols +; in the global shared objects. The list of shared objects should +; be whitespace delimited. This option is not supported on the +; Windows or AIX platforms. +; GlobalSharedObjectList = example1.so example2.so example3.so + +; Generate the stub definitions for the undefined symbols in the shared libraries being +; loaded in the simulation. When this flow is turned on, the undefined symbols will not +; prevent vsim from loading. Calling undefined symbols at runtime will cause fatal error. +; The valid arguments are: on, off, verbose. +; on : turn on the automatic generation of stub definitions. +; off: turn off the flow. The undefined symbols will trigger an immediate load failure. +; verbose: Turn on the flow and report the undefined symbols for each shared library. +; NOTE: This variable can be overriden with vsim switch "-undefsyms". +; The default is on. +; +; UndefSyms = off + +; Enable the support for checkpointing foreign C/C++ libraries. +; The valid arguments are: 0, 1, 2 +; 0: off (default) +; 1: on (manually save/restore user shared library data) +; 2: auto (automatically save/restore user shared library data) +; This option is not supported on the Windows platforms. +; +; AllowCheckpointCpp = 2 + +; Initial seed for the random number generator of the root thread (SystemVerilog). +; NOTE: This variable can be overridden with the vsim "-sv_seed" command line switch. +; The default value is 0. +; Sv_Seed = 0 + +; Specify the solver "engine" that vsim will select for constrained random +; generation. +; Valid values are: +; "auto" - automatically select the best engine for the current +; constraint scenario +; "bdd" - evaluate all constraint scenarios using the BDD solver engine +; "act" - evaluate all constraint scenarios using the ACT solver engine +; While the BDD solver engine is generally efficient with constraint scenarios +; involving bitwise logical relationships, the ACT solver engine can exhibit +; superior performance with constraint scenarios involving large numbers of +; random variables related via arithmetic operators (+, *, etc). +; NOTE: This variable can be overridden with the vsim "-solveengine" command +; line switch. +; The default value is "auto". +; SolveEngine = auto + +; Specify the maximum size that a random dynamic array or queue may be resized +; to by the solver. If the solver attempts to resize a dynamic array or queue +; to a size greater than the specified limit, the solver will abort with an error. +; The default value is 10000. The maximum value is 10000000. A value of 0 is +; equivalent to specifying the maximum value. +; SolveArrayResizeMax = 10000 + +; Specify error message severity when randomize() and randomize(null) failures +; are detected. +; +; Integer value up to two digits are allowed with each digit having the following legal values: +; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal +; +; 1) When a value with two digits is used, the digit at tenth place (leftmost digit) represents +; the severtity setting for normal randomize() calls. The digit at ones place (rightmost digit) +; represents the setting for randomize(null) calls. +; +; 2) When a single digit value is used, the setting is applied to both normal randomize() call +; and randomize(null) call. +; +; Example: Fatal error for randomize() failures and NO error for randomize(null) failures +; -solvefailseverity=40 +; +; NOTE: SolveFailSeverity can affect the behavior of SolveFailDebug. When SolveFailDebug is +; enabled, a constraint contradiction report will be displayed for randomize() calls that +; have a message severity >= warning (i.e. constraint contradiction reports will not be +; generated for randomize() calls having a "no error" severity level) +; +; NOTE: This variable can be overridden with the vsim "-solvefailseverity" command +; line switch. +; +; The default is 1 (warning). +; SolveFailSeverity = 1 + +; Error message severity for suppressible errors that are detected in a +; solve/before constraint. +; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal +; NOTE: This variable can be overridden with the vsim "-solvebeforeerrorseverity" +; command line switch. +; The default is 3 (failure). +; SolveBeforeErrorSeverity = 3 + +; Error message severity for suppressible errors that are related to +; solve engine capacity limits +; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal +; NOTE: This variable can be overridden with the vsim "-solveengineerrorseverity" +; command line switch. +; The default is 3 (failure). +; SolveEngineErrorSeverity = 3 + +; Enable/disable constraint conflicts on randomize() failure +; Valid values: +; 0 - disable solvefaildebug +; 1 - basic debug (no performance penalty) +; 2 - enhanced debug (runtime performance penalty) +; +; NOTE: SolveFailSeverity can affect the behavior of SolveFailDebug. When SolveFailDebug is +; enabled, a constraint contradiction report will be displayed for randomize() calls that +; have a message severity >= warning (i.e. constraint contradiction reports will not be +; generated for randomize() calls having a "no error" severity level) +; +; NOTE: This variable can be overridden with the vsim "-solvefaildebug" command +; line switch. +; +; The default is 1 (basic debug). +; SolveFailDebug = 1 + +; Upon encountering a randomize() failure, generate a simplified testcase that +; will reproduce the failure. Optionally output the testcase to a file. +; Testcases for 'no-solution' failures will only be produced if SolveFailDebug +; is enabled (see above). +; NOTE: This variable can be overridden with the vsim "-solvefailtestcase" +; command line switch. +; The default is OFF (do not generate a testcase). To enable testcase +; generation, uncomment this variable. To redirect testcase generation to a +; file, specify the name of the output file. +; SolveFailTestcase = + +; Specify solver timeout threshold (in seconds). randomize() will fail if the +; CPU time required to evaluate any randset exceeds the specified timeout. +; The default value is 500. A value of 0 will disable timeout failures. +; SolveTimeout = 500 + +; Specify the alternative behavior during solver replay. Must be used when combined with -solvereplay switch. +; SolveReplayOpt=[+|-]<opt>[,[+|-]<opt>]*" +' Valid <opt> settings: +; validate : toggle the checking of value changes of non-random variables involved in randomize(). (default is off)" +; SolveReplayOpt=validate + +; Switch to specify options that control the behavior of the solver profiler.. +; Valid options are: +; cputime - use CPU time instead of elapsed time (wall time) to measure performance data (default is off) +; randsets - enable detailed profiling of randsets (default is off) +; testgen - generate testcases for profiled randsets (only when randsets option is enabled) (default is off) +; SolverFProf = [+|-]<option>[,[+|-]<option>*] + +; Specify the maximum size of the solution graph generated by the BDD solver. +; This value can be used to force the BDD solver to abort the evaluation of a +; complex constraint scenario that cannot be evaluated with finite memory. +; This value is specified in 1000s of nodes. +; The default value is 10000. A value of 0 indicates no limit. +; SolveGraphMaxSize = 10000 + +; Specify the maximum number of evaluations that may be performed on the +; solution graph by the BDD solver. This value can be used to force the BDD +; solver to abort the evaluation of a complex constraint scenario that cannot +; be evaluated in finite time. This value is specified in 10000s of evaluations. +; The default value is 10000. A value of 0 indicates no limit. +; SolveGraphMaxEval = 10000 + +; Specify random sequence compatiblity with a prior release. This +; option is used to get the same random sequences during simulation as +; as a prior release. Only prior releases with the same major version +; as the current release are allowed. +; NOTE: Only those random sequence changes due to solver optimizations are +; reverted by this variable. Random sequence changes due to solver bugfixes +; cannot be un-done. +; NOTE: This variable can be overridden with the vsim "-solverev" command +; line switch. +; Default value set to "" (no compatibility). +; SolveRev = + +; Environment variable expansion of command line arguments has been depricated +; in favor shell level expansion. Universal environment variable expansion +; inside -f files is support and continued support for MGC Location Maps provide +; alternative methods for handling flexible pathnames. +; The following line may be uncommented and the value set to 1 to re-enable this +; deprecated behavior. The default value is 0. +; DeprecatedEnvironmentVariableExpansion = 0 + +; Specify the memory threshold for the System Verilog garbage collector. +; The value is the number of megabytes of class objects that must accumulate +; before the garbage collector is run. +; The GCThreshold setting is used when class debug mode is disabled to allow +; less frequent garbage collection and better simulation performance. +; The GCThresholdClassDebug setting is used when class debug mode is enabled +; to allow for more frequent garbage collection. +; GCThreshold = 100 +; GCThresholdClassDebug = 5 + +; Turn on/off collapsing of bus ports in VCD dumpports output +DumpportsCollapse = 1 + +; Location of Multi-Level Verification Component (MVC) installation. +; The default location is the product installation directory. +MvcHome = $QUESTA_MVC_HOME + +; Location of InFact installation. The default is $MODEL_TECH/../../infact +; +; InFactHome = $MODEL_TECH/../../infact + +; Initialize SystemVerilog enums using the base type's default value +; instead of the leftmost value. +; EnumBaseInit = 1 + +; Suppress file type registration. +; SuppressFileTypeReg = 1 + +; Enable/disable non-LRM compliant SystemVerilog language extensions. +; Valid extensions are: +; altdpiheader - Alternative style function signature generated in DPI header", +; cfce - generate an error if $cast fails as a function +; cfmt - C like formatting for specifiers with '#' prefix ('%#x', '%#h') +; dfsp - sets default format specifier as %p, if no format specifier is given for unpacked array in $display and related systasks +; expdfmt - enable format string extensions for $display/$sformatf +; extscan - support values greater than 32 bit for string builtin methods (atohex, atobin, atooct, atoi) +; fmtcap - prints capital hex digits with %X/%H in display calls +; iddp - ignore DPI disable protocol check +; lfmt - zero-pad data if '0' prefixes width in format specifier (e.g. "%04h") +; noexptc - ignore DPI export type name overloading check +; realrand - support randomize() with real variables and constraints (Default) +; SvExtensions = [+|-]<extension>[,[+|-]<extension>*] + +; Enable/disable non-LRM compliant SystemVerilog constrained-random language extensions. +; Valid extensions are: +; arraymode - consider rand_mode of unpacked array field independently from its elements +; deepcheck - allow randomize(null) to recursively consider constraints from member rand class handles (Default) +; funcback - enable function backtracking (ACT only) +; genmodseedfix - enable LRM-compliant seeding of module/interface instances under for-generate blocks (Default) +; impvecindex - inject constraints on random indices of 2-state vectors +; nodist - interpret 'dist' constraint as 'inside' (ACT only) +; noorder - ignore solve/before ordering constraints (ACT only) +; pathseed - enable unique seeding of module instances based on hierarchical path name +; prerandfirst - execute all pre_randomize() functions before evaluating any constraints +; promotedist - promote priority of 'dist' constraint if LHS has no solve/before +; purecheck - suppress pre_randomize() and post_randomize() calls for randomize(null) +; randindex - allow random index in constraint (Default) +; randstruct - consider all fields of unpacked structs as 'rand' +; skew - skew randomize results (ACT only) +; strictstab - strict random stability +; SvRandExtensions = [+|-]<extension>[,[+|-]<extension>*] + +; Controls the formatting of '%p' and '%P' conversion specification, used in $display +; and similar system tasks. +; 1. SVPrettyPrintFlags=I<n><S|T> use <n> spaces(S) or tabs(T) per indentation level. +; The 'I' flag when present causes relevant data types to be expanded and indented into +; a more readable format. +; (e.g. SVPrettyPrintFlags=I4S will cause 4 spaces to be used per indentation level). +; 2. SVPrettyPrintFlags=L<numLines> limits the output to <numLines> lines. +; (e.g. SVPrettyPrintFlags=L20 will limit the output to 20 lines). +; 3. SVPrettyPrintFlags=C<numChars> limits the output to <numChars> characters. +; (e.g. SVPrettyPrintFlags=C256 will limit the output to 256 characters). +; 4. SVPrettyPrintFlags=F<numFields> limits the output to <numFields> of relevant datatypes +; (e.g. SVPrettyPrintFlags=F4 will limit the output to 4 fields of a structure). +; 5. SVPrettyPrintFlags=E<numElements> limits the output to <numElements> of relevant datatypes +; (e.g. SVPrettyPrintFlags=E50 will limit the output to 50 elements of an array). +; 6. SVPrettyPrintFlags=D<depth> suppresses the output of sub-elements below <depth>. +; (e.g. SVPrettyPrintFlags=D5 will suppresses the output of sub elements below a depth of 5). +; 7. SVPrettyPrintFlags=R<specifier> shows the output of specifier %p as per the specifed radix. +; It changes the output in $display and similar systasks. It does not affect formatted output functions ($displayh etc)). +; (e.g. SVPrettyPrintFlags=Rb will show the output of %p specifier in binary format. +; 8. Items 1-7 above can be combined as a comma separated list. +; (e.g. SVPrettyPrintFlags=I4S,L20,C256,F4,E50,D5,Rb) +; SVPrettyPrintFlags=I4S + +[lmc] +; The simulator's interface to Logic Modeling's SmartModel SWIFT software +libsm = $MODEL_TECH/libsm.sl +; The simulator's interface to Logic Modeling's SmartModel SWIFT software (Windows NT) +; libsm = $MODEL_TECH/libsm.dll +; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700) +; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl +; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000) +; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o +; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris) +; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so +; Logic Modeling's SmartModel SWIFT software (Windows NT) +; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll +; Logic Modeling's SmartModel SWIFT software (non-Enterprise versions of Linux) +; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so +; Logic Modeling's SmartModel SWIFT software (Enterprise versions of Linux) +; libswift = $LMC_HOME/lib/linux.lib/libswift.so + +; The simulator's interface to Logic Modeling's hardware modeler SFI software +libhm = $MODEL_TECH/libhm.sl +; The simulator's interface to Logic Modeling's hardware modeler SFI software (Windows NT) +; libhm = $MODEL_TECH/libhm.dll +; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700) +; libsfi = <sfi_dir>/lib/hp700/libsfi.sl +; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000) +; libsfi = <sfi_dir>/lib/rs6000/libsfi.a +; Logic Modeling's hardware modeler SFI software (Sun4 Solaris) +; libsfi = <sfi_dir>/lib/sun4.solaris/libsfi.so +; Logic Modeling's hardware modeler SFI software (Windows NT) +; libsfi = <sfi_dir>/lib/pcnt/lm_sfi.dll +; Logic Modeling's hardware modeler SFI software (Linux) +; libsfi = <sfi_dir>/lib/linux/libsfi.so + +[msg_system] +; Change a message severity or suppress a message. +; The format is: <msg directive> = <msg number>[,<msg number>...] +; suppress can be used to achieve +nowarn<CODE> functionality +; The format is: suppress = <CODE>,<msg number>,[<CODE>,<msg number>,...] +; Examples: +suppress = 8780 ;an explanation can be had by running: verror 8780 +;suppress = 12110 ; +; note = 3009 +; warning = 3033 +; error = 3010,3016 +; fatal = 3016,3033 +; suppress = 3009,3016,3601 +; suppress = 3009,CNNODP,3601,TFMPC +; suppress = 8683,8684 +; The command verror <msg number> can be used to get the complete +; description of a message. + +; Control transcripting of Verilog display system task messages and +; PLI/FLI print function call messages. The system tasks include +; $display[bho], $strobe[bho], $monitor[bho], and $write[bho]. They +; also include the analogous file I/O tasks that write to STDOUT +; (i.e. $fwrite or $fdisplay). The PLI/FLI calls include io_printf, +; vpi_printf, mti_PrintMessage, and mti_PrintFormatted. The default +; is to have messages appear only in the transcript. The other +; settings are to send messages to the wlf file only (messages that +; are recorded in the wlf file can be viewed in the MsgViewer) or +; to both the transcript and the wlf file. The valid values are +; tran {transcript only (default)} +; wlf {wlf file only} +; both {transcript and wlf file} +; displaymsgmode = tran + +; Control transcripting of elaboration/runtime messages not +; addressed by the displaymsgmode setting. The default is to +; have messages appear only in the transcript. The other settings +; are to send messages to the wlf file only (messages that are +; recorded in the wlf file can be viewed in the MsgViewer) or to both +; the transcript and the wlf file. The valid values are +; tran {transcript only (default)} +; wlf {wlf file only} +; both {transcript and wlf file} +; msgmode = tran + +; Controls number of displays of a particluar message +; default value is 5 +; MsgLimitCount = 5 + +[utils] +; Default Library Type (while creating a library with "vlib") +; 0 - legacy library using subdirectories for design units +; 2 - flat library +; DefaultLibType = 2 + +; Flat Library Page Size (while creating a library with "vlib") +; Set the size in bytes for flat library file pages. Libraries containing +; very large files may benefit from a larger value. +; FlatLibPageSize = 8192 + +; Flat Library Page Cleanup Percentage (while creating a library with "vlib") +; Set the percentage of total pages deleted before library cleanup can occur. +; This setting is applied together with FlatLibPageDeleteThreshold. +; FlatLibPageDeletePercentage = 50 + +; Flat Library Page Cleanup Threshold (while creating a library with "vlib") +; Set the number of pages deleted before library cleanup can occur. +; This setting is applied together with FlatLibPageDeletePercentage. +; FlatLibPageDeleteThreshold = 1000 + +[Project] +** Warning: ; Warning -- Do not edit the project properties directly. +; Property names are dynamic in nature and property +; values have special syntax. Changing property data directly +; can result in a corrupt MPF file. All project properties +; can be modified through project window dialogs. +Project_Version = 6 +Project_DefaultLib = work +Project_SortMethod = unused +Project_Files_Count = 25 +Project_File_0 = /build/PrivateIsland/pi-betsy/src/ml_engine.v +Project_File_P_0 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1764815559 cover_fsm 0 cover_branch 0 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +define+SIMULATION=1 compile_order 23 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_1 = /build/PrivateIsland/pi-betsy/src/sync_fifo.v +Project_File_P_1 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 last_compile 1751563207 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - 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vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 10 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_14 = /build/PrivateIsland/pi-betsy/src/drop_fifo.v +Project_File_P_14 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 last_compile 1752290708 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 4 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_15 = /build/PrivateIsland/pi-betsy/src/ipv4_tx_c.v +Project_File_P_15 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1764824572 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 22 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_16 = /build/PrivateIsland/pi-betsy/src/mdio.v +Project_File_P_16 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 last_compile 1751563043 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 11 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_17 = /build/PrivateIsland/pi-betsy/src/cam.v +Project_File_P_17 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 last_compile 1752619650 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_18 = /build/PrivateIsland/pi-betsy/src/switch.v +Project_File_P_18 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1763443024 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +define+PHY2_PRESENT=1 compile_order 16 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_19 = /build/PrivateIsland/pi-betsy/src/udp_rx.v +Project_File_P_19 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 last_compile 1751563703 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 18 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_20 = /build/PrivateIsland/pi-betsy/manufacturer/altera/cyclone10_lp/src/betsy.v +Project_File_P_20 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1764813509 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +define+SIMULATION=1 compile_to work vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_21 = /build/PrivateIsland/pi-betsy/src/mdio_cont.v +Project_File_P_21 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 last_compile 1753843952 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 12 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_22 = /build/PrivateIsland/pi-betsy/src/ipv4_rx.v +Project_File_P_22 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 last_compile 1753844953 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 8 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_23 = /build/PrivateIsland/pi-betsy/src/pkt_filter.v +Project_File_P_23 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 last_compile 1751563149 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 14 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_24 = /build/PrivateIsland/pi-betsy/manufacturer/altera/cyclone10_lp/sim/src/tb.sv +Project_File_P_24 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1763615031 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 20 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_Sim_Count = 0 +Project_Folder_Count = 0 +Echo_Compile_Output = 1 +Save_Compile_Report = 1 +Project_Opt_Count = 0 +ForceSoftPaths = 0 +ProjectStatusDelay = 5000 +VERILOG_DoubleClick = Edit +VERILOG_CustomDoubleClick = +SYSTEMVERILOG_DoubleClick = Edit +SYSTEMVERILOG_CustomDoubleClick = +VHDL_DoubleClick = Edit +VHDL_CustomDoubleClick = +PSL_DoubleClick = Edit +PSL_CustomDoubleClick = +TEXT_DoubleClick = Edit +TEXT_CustomDoubleClick = +SYSTEMC_DoubleClick = Edit +SYSTEMC_CustomDoubleClick = +TCL_DoubleClick = Edit +TCL_CustomDoubleClick = +MACRO_DoubleClick = Edit +MACRO_CustomDoubleClick = +VCD_DoubleClick = Edit +VCD_CustomDoubleClick = +SDF_DoubleClick = Edit +SDF_CustomDoubleClick = +XML_DoubleClick = Edit +XML_CustomDoubleClick = +LOGFILE_DoubleClick = Edit +LOGFILE_CustomDoubleClick = +UCDB_DoubleClick = Edit +UCDB_CustomDoubleClick = +TDB_DoubleClick = Edit +TDB_CustomDoubleClick = +UPF_DoubleClick = Edit +UPF_CustomDoubleClick = +PCF_DoubleClick = Edit +PCF_CustomDoubleClick = +PROJECT_DoubleClick = Edit +PROJECT_CustomDoubleClick = +VRM_DoubleClick = Edit +VRM_CustomDoubleClick = +DEBUGDATABASE_DoubleClick = Edit +DEBUGDATABASE_CustomDoubleClick = +DEBUGARCHIVE_DoubleClick = Edit +DEBUGARCHIVE_CustomDoubleClick = +Project_Major_Version = 2025 +Project_Minor_Version = 2 diff --git a/manufacturer/altera/cyclone10_lp/sim/lin/modelsim.ini b/manufacturer/altera/cyclone10_lp/sim/lin/modelsim.ini new file mode 100644 index 0000000..61316b0 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/sim/lin/modelsim.ini @@ -0,0 +1,2220 @@ +; vsim modelsim.ini file +[Version] +INIVersion = "QA Baseline: 2021.1 Beta - 4536908" + +; Copyright 1991-2020 Mentor Graphics Corporation +; +; All Rights Reserved. +; +; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF +; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. +; + +[Library] +others = $MODEL_TECH/../modelsim.ini +; +; VITAL concerns: +; +; The library ieee contains (among other packages) the packages of the +; VITAL 2000 standard. When a design uses VITAL 2000 exclusively, it should use +; the physical library ieee (recommended), or use the physical library +; vital2000, but not both. The design can use logical library ieee and/or +; vital2000 as long as each of these maps to the same physical library, either +; ieee or vital2000. +; +; A design using the 1995 version of the VITAL packages, whether or not +; it also uses the 2000 version of the VITAL packages, must have logical library +; name ieee mapped to physical library vital1995. (A design cannot use library +; vital1995 directly because some packages in this library use logical name ieee +; when referring to the other packages in the library.) The design source +; should use logical name ieee when referring to any packages there except the +; VITAL 2000 packages. Any VITAL 2000 present in the design must use logical +; name vital2000 (mapped to physical library vital2000) to refer to those +; packages. +; ieee = $MODEL_TECH/../vital1995 +; +; For compatiblity with previous releases, logical library name vital2000 maps +; to library vital2000 (a different library than library ieee, containing the +; same packages). +; A design should not reference VITAL from both the ieee library and the +; vital2000 library because the vital packages are effectively different. +; A design that references both the ieee and vital2000 libraries must have +; both logical names ieee and vital2000 mapped to the same library, either of +; these: +; $MODEL_TECH/../ieee +; $MODEL_TECH/../vital2000 +; + +; added mapping for ADMS + +;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers // Source files only for this release +;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release +;mvc_lib = $MODEL_TECH/../mvc_lib + +; Altera Primitive libraries +; +; VHDL Section +; +; +; Verilog Section +; + + +; Automatically perform logical->physical mapping for physical libraries that +; appear in -L/-Lf options with filesystem path delimiters (e.g. '.' or '/'). +; The tail of the filesystem path name is chosen as the logical library name. +; For example, in the command "vopt -L ./path/to/lib1 -o opttop top", +; vopt automatically performs the mapping "lib1 -> ./path/to/lib1". +; See the User Manual for more details. +; +; AutoLibMapping = 0 + +work = ./libraries/work/ +work_lib = ./libraries/work/ +ram_2port_2050 = ./libraries/ram_2port_2050 +dpram_2kx9 = ./libraries/dpram_2kx9 +altera_common_sv_packages = ./libraries/altera_common_sv_packages +altera_xcvr_atx_pll_a10_191 = ./libraries/altera_xcvr_atx_pll_a10_191 +gige_pll_atx = ./libraries/gige_pll_atx +altera_xcvr_fpll_a10_191 = ./libraries/altera_xcvr_fpll_a10_191 +gige_pll_fract = ./libraries/gige_pll_fract +altera_xcvr_reset_control_1911 = ./libraries/altera_xcvr_reset_control_1911 +gige_reset_cont = ./libraries/gige_reset_cont +altera_xcvr_native_a10_1911 = ./libraries/altera_xcvr_native_a10_1911 +gige_xcvr = ./libraries/gige_xcvr +altera_int_osc_1910 = ./libraries/altera_int_osc_1910 +internal_osc = ./libraries/internal_osc +param_ram = ./libraries/param_ram +sgmii_xcvr = ./libraries/sgmii_xcvr +altera_temp_sense_1910 = ./libraries/altera_temp_sense_1910 +temp_sensor = ./libraries/temp_sensor +[DefineOptionset] +; Define optionset entries for the various compilers, vmake, and vsim. +; These option sets can be used with the "-optionset <optionsetname>" syntax. +; i.e. +; vlog -optionset COMPILEDEBUG top.sv +; vsim -optionset UVMDEBUG my_top +; +; Following are some useful examples. + +; define a vsim optionset for uvm debugging +UVMDEBUG = -uvmcontrol=all -msgmode both -displaymsgmode both -classdebug -onfinish stop + +; define a vopt optionset for debugging +VOPTDEBUG = +acc -debugdb + +[encryption] +; For vencrypt and vhencrypt. + +; Controls whether to encrypt whole files by ignoring all protect directives +; (except "viewport" and "interface_viewport") that are present in the input. +; The default is 0, use embedded protect directives to control the encryption. +; Set this to 1 to encrypt whole files by ignoring embedded protect directives. +; wholefile = 0 + +; Sets the data_method to use for the symmetric session key. +; The session key is a symmetric key that is randomly generated for each +; protected region (envelope) and is the heart of all encryption. This is used +; to set the length of the session key to generate and use when encrypting the +; HDL text. Supported values are aes128, aes192, and aes256. +; data_method = aes128 + +; The following 2 are for specifying an IEEE Std. 1735 Version 2 (V2) encryption +; "recipe" comprising an optional common block, at least one tool block (which +; contains the key public key), and the text to be encrypted. The common block +; and any of the tool blocks may contain rights in the form of the "control" +; directive. The text to be encrypted is specified either by setting +; "wholefile" to 1 or by embedding protect "begin" and "end" directives in +; the input HDL files. + +; Common recipe specification file. This file is optional. Its presence will +; require at least one "toolblock" to be specified. +; Directives such as "author" "author_info" and "data_method", +; as well as the common block license specification, go in this file. +; common = <file name> + +; Tool block specification recipe(s). Public key file with optional tool block +; file name. May be multiply-defined; at least one tool block is required if +; a recipe is being specified. +; Key file is a file name with no extension (.deprecated or .active will be +; supplied by the encryption tool). +; Rights file name is optional. +; toolblock = <key file name>[,<rights file name>]{:<key file name>[,<rights file name>]} + +; Location of directory containing recipe files. +; The default location is in the product installation directory. +; keyring = $MODEL_TECH/../keyring + +; Enable encryption statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list] +; Add '-' to disable specific statistics. Default is [cmd,msg]. +Stats = cmd,msg + +[vcom] +; VHDL93 variable selects language version as the default. +; Default is VHDL-2002. +; Value of 0 or 1987 for VHDL-1987. +; Value of 1 or 1993 for VHDL-1993. +; Default or value of 2 or 2002 for VHDL-2002. +; Value of 3 or 2008 for VHDL-2008 +; Value of 4 or ams99 for VHDL-AMS-1999 +; Value of 5 or ams07 for VHDL-AMS-2007 +VHDL93 = 2002 + +; Ignore VHDL-2008 declaration of REAL_VECTOR in package STANDARD. Default is off. +; ignoreStandardRealVector = 1 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn off unbound-component warnings. Default is on. +; Show_Warning1 = 0 + +; Turn off process-without-a-wait-statement warnings. Default is on. +; Show_Warning2 = 0 + +; Turn off null-range warnings. Default is on. +; Show_Warning3 = 0 + +; Turn off no-space-in-time-literal warnings. Default is on. +; Show_Warning4 = 0 + +; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. +; Show_Warning5 = 0 + +; Turn off optimization for IEEE std_logic_1164 package. Default is on. +; Optimize_1164 = 0 + +; Enable compiler statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list] +; Add '-' to disable specific statistics. Default is [time,cmd,msg]. +; Stats = time,cmd,msg + +; Turn on resolving of ambiguous function overloading in favor of the +; "explicit" function declaration (not the one automatically created by +; the compiler for each type declaration). Default is off. +; The .ini file has Explicit enabled so that std_logic_signed/unsigned +; will match the behavior of synthesis tools. +Explicit = 1 + +; Turn off acceleration of the VITAL packages. Default is to accelerate. +; NoVital = 1 + +; Turn off VITAL compliance checking. Default is checking on. +; NoVitalCheck = 1 + +; Ignore VITAL compliance checking errors. Default is to not ignore. +; IgnoreVitalErrors = 1 + +; Turn off VITAL compliance checking warnings. Default is to show warnings. +; Show_VitalChecksWarnings = 0 + +; Turn off PSL assertion warning messages. Default is to show warnings. +; Show_PslChecksWarnings = 0 + +; Enable parsing of embedded PSL assertions. Default is enabled. +; EmbeddedPsl = 0 + +; Keep silent about case statement static warnings. +; Default is to give a warning. +; NoCaseStaticError = 1 + +; Keep silent about warnings caused by aggregates that are not locally static. +; Default is to give a warning. +; NoOthersStaticError = 1 + +; Treat as errors: +; case statement static warnings +; warnings caused by aggregates that are not locally static +; Overrides NoCaseStaticError, NoOthersStaticError settings. +; PedanticErrors = 1 + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on some limited synthesis rule compliance checking. Checks only: +; -- signals used (read) by a process must be in the sensitivity list +; CheckSynthesis = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +; Require the user to specify a configuration for all bindings, +; and do not generate a compile time default binding for the +; component. This will result in an elaboration error of +; 'component not bound' if the user fails to do so. Avoids the rare +; issue of a false dependency upon the unused default binding. +; RequireConfigForAllDefaultBinding = 1 + +; Perform default binding at compile time. +; Default is to do default binding at load time. +; BindAtCompile = 1; + +; Inhibit range checking on subscripts of arrays. Range checking on +; scalars defined with subtypes is inhibited by default. +; NoIndexCheck = 1 + +; Inhibit range checks on all (implicit and explicit) assignments to +; scalar objects defined with subtypes. +; NoRangeCheck = 1 + +; Set the prefix to be honored for synthesis/coverage pragma recognition. +; Default is "". +; AddPragmaPrefix = "" + +; Ignore synthesis and coverage pragmas with this prefix. +; Default is "". +; IgnorePragmaPrefix = "" + +; Turn on code coverage in VHDL design units. Default is off. +; Coverage = sbceft + +; Turn off code coverage in VHDL subprograms. Default is on. +; CoverSub = 0 + +; Automatically exclude VHDL case statement OTHERS choice branches. +; This includes OTHERS choices in selected signal assigment statements. +; Default is to not exclude. +; CoverExcludeDefault = 1 + +; Control compiler and VOPT optimizations that are allowed when +; code coverage is on. Refer to the comment for this in the [vlog] area. +; CoverOpt = 3 + +; Turn on or off clkOpt optimization for code coverage. Default is on. +; CoverClkOpt = 1 + +; Turn on or off clkOpt optimization builtins for code coverage. Default is on. +; CoverClkOptBuiltins = 0 + +; Inform code coverage optimizations to respect VHDL 'H' and 'L' +; values on signals in conditions and expressions, and to not automatically +; convert them to '1' and '0'. Default is to not convert. +; CoverRespectHandL = 0 + +; Increase or decrease the maximum number of rows allowed in a UDP table +; implementing a VHDL condition coverage or expression coverage expression. +; More rows leads to a longer compile time, but more expressions covered. +; CoverMaxUDPRows = 192 + +; Increase or decrease the maximum number of input patterns that are present +; in FEC table. This leads to a longer compile time with more expressions +; covered with FEC metric. +; CoverMaxFECRows = 192 + +; Increase or decrease the limit on the size of expressions and conditions +; considered for expression and condition coverages. Higher FecUdpEffort leads +; to higher compile, optimize and simulation time, but more expressions and +; conditions are considered for coverage in the design. FecUdpEffort can +; be set to a number ranging from 1 (low) to 3 (high), defined as: +; 1 - (low) Only small expressions and conditions considered for coverage. +; 2 - (medium) Bigger expressions and conditions considered for coverage. +; 3 - (high) Very large expressions and conditions considered for coverage. +; The default setting is 1 (low). +; FecUdpEffort = 1 + +; Enable or disable Focused Expression Coverage analysis for conditions and +; expressions. Focused Expression Coverage data is provided by default when +; expression and/or condition coverage is active. +; CoverFEC = 0 + +; Enable or disable UDP Coverage analysis for conditions and expressions. +; UDP Coverage data is disabled by default when expression and/or condition +; coverage is active. +; CoverUDP = 1 + +; Enable or disable Rapid Expression Coverage mode for conditions and expressions. +; Disabling this would convert non-masking conditions in FEC tables to matching +; input patterns. +; CoverREC = 1 + +; Enable or disable bit-blasting multi-bit operands of reduction prefix expressions +; for expression/condition coverage. +; NOTE: Enabling this may have a negative impact on simulation performance. +; CoverExpandReductionPrefix = 0 + +; Enable or disable short circuit evaluation of conditions and expressions when +; condition or expression coverage is active. Short circuit evaluation is enabled +; by default. +; CoverShortCircuit = 0 + +; Enable code coverage reporting of code that has been optimized away. +; The default is not to report. +; CoverReportCancelled = 1 + +; Enable deglitching of code coverage in combinatorial, non-clocked, processes. +; Default is no deglitching. +; CoverDeglitchOn = 1 + +; Control the code coverage deglitching period. A period of 0, eliminates delta +; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a +; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". +; CoverDeglitchPeriod = 0 + +; Use this directory for compiler temporary files instead of "work/_temp" +; CompilerTempDir = /tmp + +; Set this to cause the compilers to force data to be committed to disk +; when the files are closed. +; SyncCompilerFiles = 1 + +; Add VHDL-AMS declarations to package STANDARD +; Default is not to add +; AmsStandard = 1 + +; Range and length checking will be performed on array indices and discrete +; ranges, and when violations are found within subprograms, errors will be +; reported. Default is to issue warnings for violations, because subprograms +; may not be invoked. +; NoDeferSubpgmCheck = 0 + +; Turn ON detection of FSMs having single bit current state variable. +; FsmSingle = 1 + +; Turn off reset state transitions in FSM. +; FsmResetTrans = 0 + +; Turn ON detection of FSM Implicit Transitions. +; FsmImplicitTrans = 1 + +; Controls whether or not to show immediate assertions with constant expressions +; in GUI/report/UCDB etc. By default, immediate assertions with constant +; expressions are shown in GUI/report/UCDB etc. This does not affect +; evaluation of immediate assertions. +; ShowConstantImmediateAsserts = 0 + +; Controls how VHDL basic identifiers are stored with the design unit. +; Does not make the language case-sensitive, affects only how declarations +; declared with basic identifiers have their names stored and printed +; (in the GUI, examine, etc.). +; Default is to preserve the case as originally depicted in the VHDL source. +; Value of 0 indicates to change all basic identifiers to lower case. +; PreserveCase = 0 + +; For Configuration Declarations, controls the effect that USE clauses have +; on visibility inside the configuration items being configured. If 1 +; (the default), then use pre-10.0 behavior. If 0, then for stricter LRM-compliance, +; extend the visibility of objects made visible through USE clauses into nested +; component configurations. +; OldVHDLConfigurationVisibility = 0 + +; Allows VHDL configuration declarations to be in a different library from +; the corresponding configured entity. Default is to not allow this for +; stricter LRM-compliance. +; SeparateConfigLibrary = 1; + +; Determine how mode OUT subprogram parameters of type array and record are treated. +; If 0 (the default), then only VHDL 2008 will do this initialization. +; If 1, always initialize the mode OUT parameter to its default value. +; If 2, do not initialize the mode OUT out parameter. +; Note that prior to release 10.1, all language versions did not initialize mode +; OUT array and record type parameters, unless overridden here via this mechanism. +; In release 10.1 and later, only files compiled with VHDL 2008 will cause this +; initialization, unless overridden here. +; InitOutCompositeParam = 0 + +; Generate symbols debugging database in only some special cases to save on +; the number of files in the library. For other design-units, this database is +; generated on-demand in vsim. +; Default is to to generate debugging database for all design-units. +; SmartDbgSym = 1 + +; Enable or disable automatic creation of missing libraries. +; Default is 1 (enabled) +; CreateLib = 1 + +; Describe compilation options according to matching file patterns. +; File pattern * matches all printing characters other than '/'. +; File pattern **/x matches all paths containing file/directory x. +; File pattern x/** matches all paths beginning at directory x. +; FileOptMap = (**/*.vhd => -2008); + +; Describe library targets of compilation according to matching file patterns. +; LibMap = (**/*.vhd => work); + +[vlog] +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on Verilog hazard checking (order-dependent accessing of global vars). +; Default is off. +; Hazard = 1 + +; Turn on converting regular Verilog identifiers to uppercase. Allows case +; insensitivity for module names. Default is no conversion. +; UpCase = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn on bad option warning. Default is off. +; Show_BadOptionWarning = 1 + +; Revert back to IEEE 1364-1995 syntax, default is 0 (off). +; vlog95compat = 1 + +; Turn off PSL warning messages. Default is to show warnings. +; Show_PslChecksWarnings = 0 + +; Enable parsing of embedded PSL assertions. Default is enabled. +; EmbeddedPsl = 0 + +; Enable compiler statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list,kb] +; Add '-' to disable specific statistics. Default is [time,cmd,msg]. +; Stats = time,cmd,msg + +; Set the threshold for automatically identifying sparse Verilog memories. +; A memory with total size in bytes equal to or more than the sparse memory +; threshold gets marked as sparse automatically, unless specified otherwise +; in source code or by the +nosparse commandline option of vlog or vopt. +; The default is 1M. (i.e. memories with total size equal +; to or greater than 1Mb are marked as sparse) +; SparseMemThreshold = 1048576 + +; Set the prefix to be honored for synthesis and coverage pragma recognition. +; Default is "". +; AddPragmaPrefix = "" + +; Ignore synthesis and coverage pragmas with this prefix. +; Default is "". +; IgnorePragmaPrefix = "" + +; Set the option to treat all files specified in a vlog invocation as a +; single compilation unit. The default value is set to 0 which will treat +; each file as a separate compilation unit as specified in the P1800 draft standard. +; MultiFileCompilationUnit = 1 + +; Turn on code coverage in Verilog design units. Default is off. +; Coverage = sbceft + +; Automatically exclude Verilog case statement default branches. +; Default is to not automatically exclude defaults. +; CoverExcludeDefault = 1 + +; Increase or decrease the maximum number of rows allowed in a UDP table +; implementing a VHDL condition coverage or expression coverage expression. +; More rows leads to a longer compile time, but more expressions covered. +; CoverMaxUDPRows = 192 + +; Increase or decrease the maximum number of input patterns that are present +; in FEC table. This leads to a longer compile time with more expressions +; covered with FEC metric. +; CoverMaxFECRows = 192 + +; Enable Multi Bit Expression Coverage in a Design, If design has expression with +; multi bit operands, this option enables its Expression Coverage. +; The default value is 0. +; CoverFecMultiBit = 1 + +; Increase or decrease the limit on the size of expressions and conditions +; considered for expression and condition coverages. Higher FecUdpEffort leads +; to higher compile, optimize and simulation time, but more expressions and +; conditions are considered for coverage in the design. FecUdpEffort can +; be set to a number ranging from 1 (low) to 3 (high), defined as: +; 1 - (low) Only small expressions and conditions considered for coverage. +; 2 - (medium) Bigger expressions and conditions considered for coverage. +; 3 - (high) Very large expressions and conditions considered for coverage. +; The default setting is 1 (low). +; FecUdpEffort = 1 + +; Enable or disable Focused Expression Coverage analysis for conditions and +; expressions. Focused Expression Coverage data is provided by default when +; expression and/or condition coverage is active. +; CoverFEC = 0 + +; Enable or disable UDP Coverage analysis for conditions and expressions. +; UDP Coverage data is disabled by default when expression and/or condition +; coverage is active. +; CoverUDP = 1 + +; Enable or disable Rapid Expression Coverage mode for conditions and expressions. +; Disabling this would convert non-masking conditions in FEC tables to matching +; input patterns. +; CoverREC = 1 + +; Enable or disable bit-blasting multi-bit operands of reduction prefix expressions +; for expression/condition coverage. +; NOTE: Enabling this may have a negative impact on simulation performance. +; CoverExpandReductionPrefix = 0 + +; Enable or disable short circuit evaluation of conditions and expressions when +; condition or expression coverage is active. Short circuit evaluation is enabled +; by default. +; CoverShortCircuit = 0 + +; Enable deglitching of code coverage in combinatorial, non-clocked, processes. +; Default is no deglitching. +; CoverDeglitchOn = 1 + +; Control the code coverage deglitching period. A period of 0, eliminates delta +; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a +; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". +; CoverDeglitchPeriod = 0 + +; Turn on code coverage in VLOG `celldefine modules, modules containing +; specify blocks, and modules included using vlog -v and -y. Default is off. +; CoverCells = 1 + +; Enable code coverage reporting of code that has been optimized away. +; The default is not to report. +; CoverReportCancelled = 1 + +; Control compiler and VOPT optimizations that are allowed when +; code coverage is on. This is a number from 0 to 5, with the following +; meanings (the default is 3): +; 5 -- All allowable optimizations are on. +; 4 -- Turn off removing unreferenced code. +; 3 -- Turn off process, always block and if statement merging. +; 2 -- Turn off expression optimization, converting primitives +; to continuous assignments, VHDL subprogram inlining. +; and VHDL clkOpt (converting FF's to builtins). +; 1 -- Turn off continuous assignment optimizations and clock suppression. +; 0 -- Turn off Verilog module inlining and VHDL arch inlining. +; HOWEVER, if fsm coverage is turned on, optimizations will be forced to +; level 3, with also turning off converting primitives to continuous assigns. +; CoverOpt = 3 + +; Specify the override for the default value of "cross_num_print_missing" +; option for the Cross in Covergroups. If not specified then LRM default +; value of 0 (zero) is used. This is a compile time option. +; SVCrossNumPrintMissingDefault = 0 + +; Setting following to 1 would cause creation of variables which +; would represent the value of Coverpoint expressions. This is used +; in conjunction with "SVCoverpointExprVariablePrefix" option +; in the modelsim.ini +; EnableSVCoverpointExprVariable = 0 + +; Specify the override for the prefix used in forming the variable names +; which represent the Coverpoint expressions. This is used in conjunction with +; "EnableSVCoverpointExprVariable" option of the modelsim.ini +; The default prefix is "expr". +; The variable name is +; variable name => <prefix>_<coverpoint name> +; SVCoverpointExprVariablePrefix = expr + +; Override for the default value of the SystemVerilog covergroup, +; coverpoint, and cross option.goal (defined to be 100 in the LRM). +; NOTE: It does not override specific assignments in SystemVerilog +; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal" +; in the [vsim] section can override this value. +; SVCovergroupGoalDefault = 100 + +; Override for the default value of the SystemVerilog covergroup, +; coverpoint, and cross type_option.goal (defined to be 100 in the LRM) +; NOTE: It does not override specific assignments in SystemVerilog +; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal" +; in the [vsim] section can override this value. +; SVCovergroupTypeGoalDefault = 100 + +; Specify the override for the default value of "strobe" option for the +; Covergroup Type. This is a compile time option which forces "strobe" to +; a user specified default value and supersedes SystemVerilog specified +; default value of '0'(zero). NOTE: This can be overriden by a runtime +; modelsim.ini variable "SVCovergroupStrobe" in the [vsim] section. +; SVCovergroupStrobeDefault = 0 + +; Specify the override for the default value of "per_instance" option for the +; Covergroup variables. This is a compile time option which forces "per_instance" +; to a user specified default value and supersedes SystemVerilog specified +; default value of '0'(zero). +; SVCovergroupPerInstanceDefault = 0 + +; Specify the override for the default value of "get_inst_coverage" option for the +; Covergroup variables. This is a compile time option which forces +; "get_inst_coverage" to a user specified default value and supersedes +; SystemVerilog specified default value of '0'(zero). +; SVCovergroupGetInstCoverageDefault = 0 + +; +; A space separated list of resource libraries that contain precompiled +; packages. The behavior is identical to using the "-L" switch. +; +; LibrarySearchPath = <path/lib> [<path/lib> ...] +LibrarySearchPath = mtiAvm mtiRnm mtiOvm mtiUvm mtiUPF infact + +; The behavior is identical to the "-mixedansiports" switch. Default is off. +; MixedAnsiPorts = 1 + +; Enable SystemVerilog 3.1a $typeof() function. Default is off. +; EnableTypeOf = 1 + +; Only allow lower case pragmas. Default is disabled. +; AcceptLowerCasePragmaOnly = 1 + +; Set the maximum depth permitted for a recursive include file nesting. +; IncludeRecursionDepthMax = 5 + +; Turn ON detection of FSMs having single bit current state variable. +; FsmSingle = 1 + +; Turn off reset state transitions in FSM. +; FsmResetTrans = 0 + +; Turn off detections of FSMs having x-assignment. +; FsmXAssign = 0 + +; Turn ON detection of FSM Implicit Transitions. +; FsmImplicitTrans = 1 + +; List of file suffixes which will be read as SystemVerilog. White space +; in extensions can be specified with a back-slash: "\ ". Back-slashes +; can be specified with two consecutive back-slashes: "\\"; +; SvFileSuffixes = sv svp svh + +; This setting is the same as the vlog -sv command line switch. +; Enables SystemVerilog features and keywords when true (1). +; When false (0), the rules of IEEE Std 1364-2005 are followed and +; SystemVerilog keywords are ignored. +; Svlog = 0 + +; Prints attribute placed upon SV packages during package import +; when true (1). The attribute will be ignored when this +; entry is false (0). The attribute name is "mti_design_element_load_message". +; The value of this attribute is a string literal. +; Default is true (1). +; PrintSVPackageLoadingAttribute = 1 + +; Do not show immediate assertions with constant expressions in +; GUI/reports/UCDB etc. By default immediate assertions with constant +; expressions are shown in GUI/reports/UCDB etc. This does not affect +; evaluation of immediate assertions. +; ShowConstantImmediateAsserts = 0 + +; Controls if untyped parameters that are initialized with values greater +; than 2147483647 are mapped to generics of type INTEGER or ignored. +; If mapped to VHDL Integers, values greater than 2147483647 +; are mapped to negative values. +; Default is to map these parameter to generic of type INTEGER +; ForceUnsignedToVHDLInteger = 1 + +; Enable AMS wreal (wired real) extensions. Default is 0. +; WrealType = 1 + +; Controls SystemVerilog Language Extensions. These options enable +; some non-LRM compliant behavior. +; SvExtensions = [+|-]<extension>[,[+|-]<extension>*] + +; Generate symbols debugging database in only some special cases to save on +; the number of files in the library. For other design-units, this database is +; generated on-demand in vsim. +; Default is to to generate debugging database for all design-units. +; SmartDbgSym = 1 + +; Controls how $unit library entries are named. Valid options are: +; "file" (generate name based on the first file on the command line) +; "du" (generate name based on first design unit following an item +; found in $unit scope) +; CUAutoName = file + +; Enable or disable automatic creation of missing libraries. +; Default is 1 (enabled) +; CreateLib = 1 + +[sccom] +; Enable use of SCV include files and library. Default is off. +; UseScv = 1 + +; Add C++ compiler options to the sccom command line by using this variable. +; CppOptions = -g + +; Use custom C++ compiler located at this path rather than the default path. +; The path should point directly at a compiler executable. +; CppPath = /usr/bin/g++ + +; Specify the compiler version from the list of support GNU compilers. +; examples 4.7.4, 5.3.0, 7.4.0 +; CppInstall = 7.4.0 + +; Enable verbose messages from sccom. Default is off. +; SccomVerbose = 1 + +; sccom logfile. Default is no logfile. +; SccomLogfile = sccom.log + +; Enable use of SC_MS include files and library. Default is off. +; UseScMs = 1 + +; Use SystemC-2.2 instead of the default SystemC-2.3. Default is off. +; Sc22Mode = 1 + +; Enable compiler statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list,kb] +; Add '-' to disable specific statistics. Default is [time,cmd,msg]. +; Stats = time,cmd,msg + +; Enable or disable automatic creation of missing libraries. +; Default is 1 (enabled) +; CreateLib = 1 + +; Enable use of UVMC library. Default is off. +; UseUvmc = 1 + +[vopt] +; Turn on code coverage in vopt. Default is off. +; Coverage = sbceft + +; enable or disable param saving in UCDB. +; CoverageSaveParam = 0 + +; Control compiler optimizations that are allowed when +; code coverage is on. Refer to the comment for this in the [vlog] area. +; CoverOpt = 3 + +; Controls set of CoverConstructs that are being considered for Coverage +; Collection. +; Some of Valid options are: default,set1,set2 +; Covermode = default + +; Override all PA VOPT and VSIM commands to run simulation in Non-PA mode. +; NonPAmode = 1 + +; Controls set of HDL cover constructs that would be considered(or not considered) +; for Coverage Collection. (Default corresponds to covermode default). +; Some of Valid options are: "ca", "citf", "cifl", "tcint", "fsmqs". +; Coverconstruct = noca,nocitf,nofsmtf,nofsmds,noctes,nocicl,nocprc,nocfl,nofsmup,nocifl,nocpm,notcint,nocpkg,nocsva + +; Increase or decrease the maximum number of rows allowed in a UDP table +; implementing a VHDL condition coverage or expression coverage expression. +; More rows leads to a longer compile time, but more expressions covered. +; CoverMaxUDPRows = 192 + +; Increase or decrease the maximum number of input patterns that are present +; in FEC table. This leads to a longer compile time with more expressions +; covered with FEC metric. +; CoverMaxFECRows = 192 + +; Enable Multi Bit Expression Coverage in a Design, If design has expression with +; multi bit operands, this option enables its Expression Coverage. +; The default value is 0. +; CoverFecMultiBit = 1 + +; Increase or decrease the limit on the size of expressions and conditions +; considered for expression and condition coverages. Higher FecUdpEffort leads +; to higher compile, optimize and simulation time, but more expressions and +; conditions are considered for coverage in the design. FecUdpEffort can +; be set to a number ranging from 1 (low) to 3 (high), defined as: +; 1 - (low) Only small expressions and conditions considered for coverage. +; 2 - (medium) Bigger expressions and conditions considered for coverage. +; 3 - (high) Very large expressions and conditions considered for coverage. +; The default setting is 1 (low). +; FecUdpEffort = 1 + +; Enable code coverage reporting of code that has been optimized away. +; The default is not to report. +; CoverReportCancelled = 1 + +; Enable deglitching of code coverage in combinatorial, non-clocked, processes. +; Default is no deglitching. +; CoverDeglitchOn = 1 + +; Enable compiler statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list,kb] +; Add '-' to disable specific statistics. Default is [time,cmd,msg]. +; Stats = time,cmd,msg + +; Control the code coverage deglitching period. A period of 0, eliminates delta +; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a +; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". +; CoverDeglitchPeriod = 0 + +; Do not show immediate assertions with constant expressions in +; GUI/reports/UCDB etc. By default immediate assertions with constant +; expressions are shown in GUI/reports/UCDB etc. This does not affect +; evaluation of immediate assertions. +; ShowConstantImmediateAsserts = 0 + +; Set the maximum number of iterations permitted for a generate loop. +; Restricting this permits the implementation to recognize infinite +; generate loops. +; GenerateLoopIterationMax = 100000 + +; Set the maximum depth permitted for a recursive generate instantiation. +; Restricting this permits the implementation to recognize infinite +; recursions. +; GenerateRecursionDepthMax = 200 + +; Set the number of processes created during the code generation phase. +; By default a heuristic is used to set this value. This may be set to 0 +; to disable this feature completely. +; ParallelJobs = 0 + +; Controls SystemVerilog Language Extensions. These options enable +; some non-LRM compliant behavior. +; SvExtensions = [+|-]<extension>[,[+|-]<extension>*] + +; Load the specified shared objects with the RTLD_GLOBAL flag. +; This gives global visibility to all symbols in the shared objects, +; meaning that subsequently loaded shared objects can bind to symbols +; in the global shared objects. The list of shared objects should +; be whitespace delimited. This option is not supported on the +; Windows or AIX platforms. +; GlobalSharedObjectList = example1.so example2.so example3.so + +; Disable SystemVerilog elaboration system task messages +; IgnoreSVAInfo = 1 +; IgnoreSVAWarning = 1 +; IgnoreSVAError = 1 +; IgnoreSVAFatal = 1 + +; Enable or disable automatic creation of missing libraries. +; Default is 1 (enabled) +; CreateLib = 1 + +[vsim] +; vopt flow +; Set to turn on automatic optimization of a design. +; Default is on +VoptFlow = 1 + +; Simulator resolution +; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. +Resolution = ns + +; Disable certain code coverage exclusions automatically. +; Assertions and FSM are exluded from the code coverage by default +; Set AutoExclusionsDisable = fsm to enable code coverage for fsm +; Set AutoExclusionsDisable = assertions to enable code coverage for assertions +; Set AutoExclusionsDisable = all to enable code coverage for all the automatic exclusions +; Or specify comma or space separated list +;AutoExclusionsDisable = fsm,assertions + +; User time unit for run commands +; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the +; unit specified for Resolution. For example, if Resolution is 100ps, +; then UserTimeUnit defaults to ps. +; Should generally be set to default. +UserTimeUnit = default + +; Default run length +RunLength = 100 + +; Maximum iterations that can be run without advancing simulation time +IterationLimit = 10000000 + +; Specify libraries to be searched for precompiled modules +; LibrarySearchPath = <path/lib> [<path/lib> ...] + +; Set XPROP assertion fail limit. Default is 5. +; Any positive integer, -1 for infinity. +; XpropAssertionLimit = 5 + +; Control PSL and Verilog Assume directives during simulation +; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts +; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts +; SimulateAssumeDirectives = 1 + +; Control the simulation of PSL and SVA +; These switches can be overridden by the vsim command line switches: +; -psl, -nopsl, -sva, -nosva. +; Set SimulatePSL = 0 to disable PSL simulation +; Set SimulatePSL = 1 to enable PSL simulation (default) +; SimulatePSL = 1 +; Set SimulateSVA = 0 to disable SVA simulation +; Set SimulateSVA = 1 to enable concurrent SVA simulation (default) +; SimulateSVA = 1 + +; Control SVA and VHDL immediate assertion directives during simulation +; Set SimulateImmedAsserts = 0 to disable simulation of immediate asserts +; Set SimulateImmedAsserts = 1 to enable simulation of immediate asserts +; SimulateImmedAsserts = 1 + +; License feature mappings for Verilog and VHDL +; qhsimvh Single language VHDL license +; qhsimvl Single language Verilog license +; msimhdlsim Language neutral license for either Verilog or VHDL +; msimhdlmix Second language only, language neutral license for either +; Verilog or VHDL +; +; Directives to license manager can be set either as single value or as +; space separated multi-values: +; vhdl Immediately checkout and hold a VHDL license (i.e., one of +; qhsimvh, msimhdlsim, or msimhdlmix) +; vlog Immediately checkout and hold a Verilog license (i.e., one of +; qhsimvl, msimhdlsim, or msimhdlmix) +; plus Immediately checkout and hold a VHDL license and a Verilog license +; noqueue Do not wait in the license queue when a license is not available +; viewsim Try for viewer license but accept simulator license(s) instead +; of queuing for viewer license (PE ONLY) +; noviewer Disable checkout of msimviewer license feature (PE ONLY) +; noslvhdl Disable checkout of qhsimvh license feature +; noslvlog Disable checkout of qhsimvl license feature +; nomix Disable checkout of msimhdlmix license feature +; nolnl Disable checkout of msimhdlsim license feature +; mixedonly Disable checkout of qhsimvh and qhsimvl license features +; lnlonly Disable checkout of qhsimvh,qhsimvl, and msimhdlmix license features +; +; Examples (remove ";" comment character to activate licensing directives): +; Single directive: +; License = plus +; Multi-directive (Note: space delimited directives): +; License = noqueue plus + +; Severity level of a VHDL assertion message or of a SystemVerilog severity system task +; which will cause a running simulation to stop. +; VHDL assertions and SystemVerilog severity system task that occur with the +; given severity or higher will cause a running simulation to stop. +; This value is ignored during elaboration. +; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal +BreakOnAssertion = 3 + +; Severity level of a tool message which will cause a running simulation to +; stop. This value is ignored during elaboration. Default is to not break. +; 0 = Note 1 = Warning 2 = Error 3 = Fatal +;BreakOnMessage = 2 + +; The class debug feature enables more visibility and tracking of class instances +; during simulation. By default this feature is disabled (0). To enable this +; feature set ClassDebug to 1. +; ClassDebug = 1 + +; Message Format conversion specifications: +; %S - Severity Level of message/assertion +; %R - Text of message +; %T - Time of message +; %D - Delta value (iteration number) of Time +; %K - Kind of path: Instance/Region/Signal/Process/Foreign Process/Unknown/Protected +; %i - Instance/Region/Signal pathname with Process name (if available) +; %I - shorthand for one of these: +; " %K: %i" +; " %K: %i File: %F" (when path is not Process or Signal) +; except that the %i in this case does not report the Process name +; %O - Process name +; %P - Instance/Region path without leaf process +; %F - File name +; %L - Line number; if assertion message, then line number of assertion or, if +; assertion is in a subprogram, line from which the call is made +; %u - Design unit name in form library.primary +; %U - Design unit name in form library.primary(secondary) +; %% - The '%' character itself +; +; If specific format for Severity Level is defined, use that format. +; Else, for a message that occurs during elaboration: +; -- Failure/Fatal message in VHDL region that is not a Process, and in +; certain non-VHDL regions, uses MessageFormatBreakLine; +; -- Failure/Fatal message otherwise uses MessageFormatBreak; +; -- Note/Warning/Error message uses MessageFormat. +; Else, for a message that occurs during runtime and triggers a breakpoint because +; of the BreakOnAssertion setting: +; -- if in a VHDL region that is not a Process, uses MessageFormatBreakLine; +; -- otherwise uses MessageFormatBreak. +; Else (a runtime message that does not trigger a breakpoint) uses MessageFormat. +; +; MessageFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n" +; MessageFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n" +; MessageFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormatBreakLine = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F Line: %L\n" +; MessageFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" + +; Error File - alternate file for storing error messages +; ErrorFile = error.log + +; Simulation Breakpoint messages +; This flag controls the display of function names when reporting the location +; where the simulator stops because of a breakpoint or fatal error. +; Example with function name: # Break in Process ctr at counter.vhd line 44 +; Example without function name: # Break at counter.vhd line 44 +; Default value is 1. +ShowFunctions = 1 + +; Default radix for all windows and commands. +; Radix may be one of: symbolic, ascii, binary, octal, decimal, hex, unsigned +; Flags may be one of: enumnumeric, showbase, wreal +DefaultRadix = hexadecimal +DefaultRadixFlags = showbase +; Set to 1 for make the signal_force VHDL and Verilog functions use the +; default radix when processing the force value. Prior to 10.2 signal_force +; used the default radix, now it always uses symbolic unless value explicitly indicates base +;SignalForceFunctionUseDefaultRadix = 0 + +; VSIM Startup command +; Startup = do startup.do + +; VSIM Shutdown file +; Filename to save u/i formats and configurations. +; ShutdownFile = restart.do +; To explicitly disable auto save: +; ShutdownFile = --disable-auto-save + +; Run simulator in batch mode as if -batch were specified on the command line if none of -c, -gui, or -i specified. +; Simulator runs in interactive mode as if -i were specified if this option is 0. Default is 0. +; BatchMode = 1 + +; File for saving command transcript when -batch option used +; This option is ignored when -c, -gui, or -i options are used or if BatchMode above is zero +; default is unset so command transcript only goes to stdout for better performance +; BatchTranscriptFile = transcript + +; File for saving command transcript, this option is ignored when -batch option is used +TranscriptFile = transcript + +; Transcript file long line wrapping mode(s) +; mode == 0 :: no wrapping, line recorded as is +; mode == 1 :: wrap at first whitespace after WSColumn +; or at Column. +; mode == 2 :: wrap as above, but add continuation +; character ('\') at end of each wrapped line +; +; WrapMode = 0 +; WrapColumn = 30000 +; WrapWSColumn = 27000 + +; File for saving command history +; CommandHistory = cmdhist.log + +; Specify whether paths in simulator commands should be described +; in VHDL or Verilog format. +; For VHDL, PathSeparator = / +; For Verilog, PathSeparator = . +; Must not be the same character as DatasetSeparator. +PathSeparator = / + +; Specify the dataset separator for fully rooted contexts. +; The default is ':'. For example: sim:/top +; Must not be the same character as PathSeparator. +DatasetSeparator = : + +; Specify a unique path separator for the Signal Spy set of functions. +; The default will be to use the PathSeparator variable. +; Must not be the same character as DatasetSeparator. +; SignalSpyPathSeparator = / + +; Used to control parsing of HDL identifiers input to the tool. +; This includes CLI commands, vsim/vopt/vlog/vcom options, +; string arguments to FLI/VPI/DPI calls, etc. +; If set to 1, accept either Verilog escaped Id syntax or +; VHDL extended id syntax, regardless of source language. +; If set to 0, the syntax of the source language must be used. +; Each identifier in a hierarchical name may need different syntax, +; e.g. "/top/\vhdl*ext*id\/middle/\vlog*ext*id /bottom" or +; "top.\vhdl*ext*id\.middle.\vlog*ext*id .bottom" +; GenerousIdentifierParsing = 1 + +; Disable VHDL assertion messages +; IgnoreNote = 1 +; IgnoreWarning = 1 +; IgnoreError = 1 +; IgnoreFailure = 1 + +; Disable SystemVerilog assertion messages +; IgnoreSVAInfo = 1 +; IgnoreSVAWarning = 1 +; IgnoreSVAError = 1 +; IgnoreSVAFatal = 1 + +; Do not print any additional information from Severity System tasks. +; Only the message provided by the user is printed along with severity +; information. +; SVAPrintOnlyUserMessage = 1; + +; Default force kind. May be freeze, drive, deposit, or default +; or in other terms, fixed, wired, or charged. +; A value of "default" will use the signal kind to determine the +; force kind, drive for resolved signals, freeze for unresolved signals +; DefaultForceKind = freeze + +; Control the iteration of events when a VHDL signal is forced to a value +; This flag can be set to honour the signal update event in next iteration, +; the default is to update and propagate in the same iteration. +; ForceSigNextIter = 1 + +; Enable simulation statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list,kb,eor] +; Add '-' to disable specific statistics. Default is [time,cmd,msg]. +; Stats = time,cmd,msg + +; If zero, open files when elaborated; otherwise, open files on +; first read or write. Default is 0. +; DelayFileOpen = 1 + +; Control VHDL files opened for write. +; 0 = Buffered, 1 = Unbuffered +UnbufferedOutput = 0 + +; Control the number of VHDL files open concurrently. +; This number should always be less than the current ulimit +; setting for max file descriptors. +; 0 = unlimited +ConcurrentFileLimit = 40 + +; If nonzero, close files as soon as there is either an explicit call to +; file_close, or when the file variable's scope is closed. When zero, a +; file opened in append mode is not closed in case it is immediately +; reopened in append mode; otherwise, the file will be closed at the +; point it is reopened. +; AppendClose = 1 + +; Control the number of hierarchical regions displayed as +; part of a signal name shown in the Wave window. +; A value of zero tells VSIM to display the full name. +; The default is 0. +; WaveSignalNameWidth = 0 + +; Turn off warnings when changing VHDL constants and generics +; Default is 1 to generate warning messages +; WarnConstantChange = 0 + +; Turn off warnings from accelerated versions of the std_logic_arith, +; std_logic_unsigned, and std_logic_signed packages. +; StdArithNoWarnings = 1 + +; Turn off warnings from accelerated versions of the IEEE numeric_std +; and numeric_bit packages. +; NumericStdNoWarnings = 1 + +; Use old-style (pre-6.6) VHDL FOR GENERATE statement iteration names +; in the design hierarchy. +; This style is controlled by the value of the GenerateFormat +; value described next. Default is to use new-style names, which +; comprise the generate statement label, '(', the value of the generate +; parameter, and a closing ')'. +; Set this to 1 to use old-style names. +; OldVhdlForGenNames = 1 + +; Control the format of the old-style VHDL FOR generate statement region +; name for each iteration. Do not quote the value. +; The format string here must contain the conversion codes %s and %d, +; in that order, and no other conversion codes. The %s represents +; the generate statement label; the %d represents the generate parameter value +; at a particular iteration (this is the position number if the generate parameter +; is of an enumeration type). Embedded whitespace is allowed (but discouraged); +; leading and trailing whitespace is ignored. +; Application of the format must result in a unique region name over all +; loop iterations for a particular immediately enclosing scope so that name +; lookup can function properly. The default is %s__%d. +; GenerateFormat = %s__%d + +; Enable more efficient logging of VHDL Variables. +; Logging VHDL variables without this enabled, while possible, is very +; inefficient. Enabling this will provide a more efficient logging methodology +; at the expense of more memory usage. By default this feature is disabled (0). +; To enabled this feature, set this variable to 1. +; VhdlVariableLogging = 1 + +; Enable logging of VHDL access type variables and their designated objects. +; This setting will allow both variables of an access type ("access variables") +; and their designated objects ("access objects") to be logged. Logging a +; variable of an access type will automatically also cause the designated +; object(s) of that variable to be logged as the simulation progresses. +; Further, enabling this allows access objects to be logged by name. By default +; this feature is disabled (0). To enable this feature, set this variable to 1. +; Enabling this will automatically enable the VhdlVariableLogging feature also. +; AccessObjDebug = 1 + +; Make each VHDL package in a PDU has its own separate copy of the package instead +; of sharing the package between PDUs. The default is to share packages. +; To ensure that each PDU has its own set of packages, set this variable to 1. +; VhdlSeparatePduPackage = 1 + +; Specify whether checkpoint files should be compressed. +; The default is 1 (compressed). +; CheckpointCompressMode = 0 + +; Specify gcc compiler used in the compilation of automatically generated DPI exportwrapper. +; Use custom gcc compiler located at this path rather than the default path. +; The path should point directly at a compiler executable. +; DpiCppPath = <your-gcc-installation>/bin/gcc +; +; Specify the compiler version from the list of support GNU compilers. +; examples 4.7.4, 5.3.0, 7.4.0 +; DpiCppInstall = 7.4.0 + +; Specify whether to enable SystemVerilog DPI "out-of-the-blue" calls. +; The term "out-of-the-blue" refers to SystemVerilog export function calls +; made from C functions that don't have the proper context setup +; (as is the case when running under "DPI-C" import functions). +; When this is enabled, one can call a DPI export function +; (but not task) from any C code. +; the setting of this variable can be one of the following values: +; 0 : dpioutoftheblue call is disabled (default) +; 1 : dpioutoftheblue call is enabled, but export call debug support is not available. +; 2 : dpioutoftheblue call is enabled, and limited export call debug support is available. +; DpiOutOfTheBlue = 1 + +; Specify whether continuous assignments are run before other normal priority +; processes scheduled in the same iteration. This event ordering minimizes race +; differences between optimized and non-optimized designs, and is the default +; behavior beginning with the 6.5 release. For pre-6.5 event ordering, set +; ImmediateContinuousAssign to 0. +; The default is 1 (enabled). +; ImmediateContinuousAssign = 0 + +; List of dynamically loaded objects for Verilog PLI applications +; Veriuser = veriuser.sl + +; Which default VPI object model should the tool conform to? +; The 1364 modes are Verilog-only, for backwards compatibility with older +; libraries, and SystemVerilog objects are not available in these modes. +; +; In the absence of a user-specified default, the tool default is the +; latest available LRM behavior. +; Options for PliCompatDefault are: +; VPI_COMPATIBILITY_VERSION_1364v1995 +; VPI_COMPATIBILITY_VERSION_1364v2001 +; VPI_COMPATIBILITY_VERSION_1364v2005 +; VPI_COMPATIBILITY_VERSION_1800v2005 +; VPI_COMPATIBILITY_VERSION_1800v2008 +; +; Synonyms for each string are also recognized: +; VPI_COMPATIBILITY_VERSION_1364v1995 (1995, 95, 1364v1995, 1364V1995, VL1995) +; VPI_COMPATIBILITY_VERSION_1364v2001 (2001, 01, 1364v2001, 1364V2001, VL2001) +; VPI_COMPATIBILITY_VERSION_1364v2005 (1364v2005, 1364V2005, VL2005) +; VPI_COMPATIBILITY_VERSION_1800v2005 (2005, 05, 1800v2005, 1800V2005, SV2005) +; VPI_COMPATIBILITY_VERSION_1800v2008 (2008, 08, 1800v2008, 1800V2008, SV2008) + + +; PliCompatDefault = VPI_COMPATIBILITY_VERSION_1800v2005 + +; Specify whether the Verilog system task $fopen or vpi_mcd_open() +; will create directories that do not exist when opening the file +; in "a" or "w" mode. +; The default is 0 (do not create non-existent directories) +; CreateDirForFileAccess = 1 + +; Specify default options for the restart command. Options can be one +; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions +; DefaultRestartOptions = -force + + +; Specify default UVM-aware debug options if the vsim -uvmcontrol switch is not used. +; Valid options include: all, none, verbose, disable, struct, reseed, msglog, trlog, certe. +; Options can be enabled by just adding the name, or disabled by prefixing the option with a "-". +; The list of options must be delimited by commas, without spaces or tabs. +; +; Some examples +; To turn on all available UVM-aware debug features: +; UVMControl = all +; To turn on the struct window, mesage logging, and transaction logging: +; UVMControl = struct,msglog,trlog +; To turn on all options except certe: +; UVMControl = all,-certe +; To completely disable all UVM-aware debug functionality: +; UVMControl = disable + +; Specify the WildcardFilter setting. +; A space separated list of object types to be excluded when performing +; wildcard matches with log, wave, etc commands. The default value for this variable is: +; "Variable Constant Generic Parameter SpecParam Memory Assertion Cover Endpoint ScVariable CellInternal ImmediateAssert VHDLFile" +; See "Using the WildcardFilter Preference Variable" in the documentation for +; details on how to use this variable and for descriptions of the filter types. +WildcardFilter = Variable Constant Generic Parameter SpecParam Memory Assertion Cover Endpoint ScVariable CellInternal ImmediateAssert VHDLFile + +; Specify the WildcardSizeThreshold setting. +; This integer setting specifies the size at which objects will be excluded when +; performing wildcard matches with log, wave, etc commands. Objects of size equal +; to or greater than the WildcardSizeThreshold will be filtered out from the wildcard +; matches. The size is a simple calculation of number of bits or items in the object. +; The default value is 8k (8192). Setting this value to 0 will disable the checking +; of object size against this threshold and allow all objects of any size to be logged. +WildcardSizeThreshold = 8192 + +; Specify whether warning messages are output when objects are filtered out due to the +; WildcardSizeThreshold. The default is 0 (no messages generated). +WildcardSizeThresholdVerbose = 0 + +; Turn on (1) or off (0) WLF file compression. +; The default is 1 (compress WLF file). +; WLFCompress = 0 + +; Specify whether to save all design hierarchy (1) in the WLF file +; or only regions containing logged signals (0). +; The default is 0 (save only regions with logged signals). +; WLFSaveAllRegions = 1 + +; WLF file time limit. Limit WLF file by time, as closely as possible, +; to the specified amount of simulation time. When the limit is exceeded +; the earliest times get truncated from the file. +; If both time and size limits are specified the most restrictive is used. +; UserTimeUnits are used if time units are not specified. +; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} +; WLFTimeLimit = 0 + +; WLF file size limit. Limit WLF file size, as closely as possible, +; to the specified number of megabytes. If both time and size limits +; are specified then the most restrictive is used. +; The default is 0 (no limit). +; WLFSizeLimit = 1000 + +; Specify whether or not a WLF file should be deleted when the +; simulation ends. A value of 1 will cause the WLF file to be deleted. +; The default is 0 (do not delete WLF file when simulation ends). +; WLFDeleteOnQuit = 1 + +; Specify whether or not a WLF file should be optimized during +; simulation. If set to 0, the WLF file will not be optimized. +; The default is 1, optimize the WLF file. +; WLFOptimize = 0 + +; Specify the name of the WLF file. +; The default is vsim.wlf +; WLFFilename = vsim.wlf + +; Specify whether to lock the WLF file. +; Locking the file prevents other invocations of ModelSim/Questa tools from +; inadvertently overwriting the WLF file. +; The default is 1, lock the WLF file. +; WLFFileLock = 0 + +; Specify the update interval for the WLF file in live simulation. +; The interval is given in seconds. +; The value is the smallest interval between WLF file updates. The WLF file +; will be flushed (updated) after (at least) the interval has elapsed, ensuring +; that the data is correct when viewed from a separate viewer. +; A value of 0 means that no updating will occur. +; The default value is 10 seconds. +; WLFUpdateInterval = 10 + +; Specify the WLF cache size limit for WLF files. +; The value is given in megabytes. A value of 0 turns off the cache. +; On non-Windows platforms the default WLFCacheSize setting is 2000 (megabytes). +; On Windows, the default value is 1000 (megabytes) to help to avoid filling +; process memory. +; WLFSimCacheSize allows a different cache size to be set for a live simulation +; WLF file, independent of post-simulation WLF file viewing. If WLFSimCacheSize +; is not set, it defaults to the WLFCacheSize value. +; WLFCacheSize = 2000 +; WLFSimCacheSize = 500 + +; Specify the WLF file event collapse mode. +; 0 = Preserve all events and event order. (same as -wlfnocollapse) +; 1 = Only record values of logged objects at the end of a simulator iteration. +; (same as -wlfcollapsedelta) +; 2 = Only record values of logged objects at the end of a simulator time step. +; (same as -wlfcollapsetime) +; The default is 1. +; WLFCollapseMode = 0 + +; Specify whether WLF file logging can use threads on multi-processor machines. +; If 0, no threads will be used; if 1, threads will be used if the system has +; more than one processor. +; WLFUseThreads = 1 + +; Specify the size of objects that will trigger "large object" messages +; at log/wave/list time. The size calculation of the object is the same as that +; used by the WildcardSizeThreshold. The default LargeObjectSize size is 500,000. +; Setting LargeObjectSize to 0 will disable these messages. +; LargeObjectSize = 500000 + +; Specify the depth of stack frames returned by $stacktrace([level]). +; This depth will be picked up when the optional 'level' argument +; is not specified or its value is not a positive integer. +; StackTraceDepth = 100 + +; Turn on/off undebuggable SystemC type warnings. Default is on. +; ShowUndebuggableScTypeWarning = 0 + +; Turn on/off unassociated SystemC name warnings. Default is off. +; ShowUnassociatedScNameWarning = 1 + +; Turn on/off SystemC IEEE 1666 deprecation warnings. Default is off. +; ScShowIeeeDeprecationWarnings = 1 + +; Turn on/off the check for multiple drivers on a SystemC sc_signal. Default is off. +; For SystemC-2.3.2 the valid values are 0,1 and 2 +; 0 = SC_SIGNAL_WRITE_CHECK_DISABLE_ +; 1 = SC_SIGNAL_WRITE_CHECK_DEFAULT_ +; 2 = SC_SIGNAL_WRITE_CHECK_CONFLICT_ +; For SystemC-2.2 the valid values are 0 and 1 +; 0 = DISABLE +; 1 = ENABLE +; ScEnableScSignalWriteCheck = 1 + +; Set SystemC default time unit. +; Set to fs, ps, ns, us, ms, or sec with optional +; prefix of 1, 10, or 100. The default is 1 ns. +; The ScTimeUnit value is honored if it is coarser than Resolution. +; If ScTimeUnit is finer than Resolution, it is set to the value +; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns, +; then the default time unit will be 1 ns. However if Resolution +; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns. +ScTimeUnit = ns + +; Set SystemC sc_main stack size. The stack size is set as an integer +; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or +; Gb(Giga-byte). Default is 10 Mb. The stack size for sc_main depends +; on the amount of data on the sc_main() stack and the memory required +; to succesfully execute the longest function call chain of sc_main(). +ScMainStackSize = 10 Mb + +; Set SystemC thread stack size. The stack size is set as an integer +; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or +; Gb(Giga-byte). The stack size for sc_thread depends +; on the amount of data on the sc_thread stack and the memory required +; to succesfully execute the thread. +; ScStackSize = 1 Mb + +; Turn on/off execution of remainder of sc_main upon quitting the current +; simulation session. If the cumulative length of sc_main() in terms of +; simulation time units is less than the length of the current simulation +; run upon quit or restart, sc_main() will be in the middle of execution. +; This switch gives the option to execute the remainder of sc_main upon +; quitting simulation. The drawback of not running sc_main till the end +; is memory leaks for objects created by sc_main. If on, the remainder of +; sc_main will be executed ignoring all delays. This may cause the simulator +; to crash if the code in sc_main is dependent on some simulation state. +; Default is on. +ScMainFinishOnQuit = 1 + +; Enable calling of the DPI export taks/functions from the +; SystemC start_of_simulation() callback. +; The default is off. +; EnableDpiSosCb = 1 + + +; Set the SCV relationship name that will be used to identify phase +; relations. If the name given to a transactor relation matches this +; name, the transactions involved will be treated as phase transactions +ScvPhaseRelationName = mti_phase + +; Customize the vsim kernel shutdown behavior at the end of the simulation. +; Some common causes of the end of simulation are $finish (implicit or explicit), +; sc_stop(), tf_dofinish(), and assertion failures. +; This should be set to "ask", "exit", or "stop". The default is "ask". +; "ask" -- In batch mode, the vsim kernel will abruptly exit. +; In GUI mode, a dialog box will pop up and ask for user confirmation +; whether or not to quit the simulation. +; "stop" -- Cause the simulation to stay loaded in memory. This can make some +; post-simulation tasks easier. +; "exit" -- The simulation will abruptly exit without asking for any confirmation. +; "final" -- Run SystemVerilog final blocks then behave as "stop". +; Note: This variable can be overridden with the vsim "-onfinish" command line switch. +OnFinish = ask + +; Print pending deferred assertion messages. +; Deferred assertion messages may be scheduled after the $finish in the same +; time step. Deferred assertions scheduled to print after the $finish are +; printed before exiting with severity level NOTE since it's not known whether +; the assertion is still valid due to being printed in the active region +; instead of the reactive region where they are normally printed. +; OnFinishPendingAssert = 1; + +; Print "simstats" result. Default is 0. +; 0 == do not print simstats +; 1 == print at end of simulation +; 2 == print at end of each run command and end of simulation +; PrintSimStats = 1 + +; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages +; AssertFile = assert.log + +; Enable assertion counts. Default is off. +; AssertionCounts = 1 + +; Run simulator in assertion debug mode. Default is off. +; AssertionDebug = 1 + +; Turn on/off PSL/SVA/VHDL assertion enable. Default is on. +; AssertionEnable = 0 + +; Set PSL/SVA/VHDL concurrent assertion fail limit. Default is -1. +; Any positive integer, -1 for infinity. +; AssertionLimit = 1 + +; Turn on/off concurrent assertion pass log. Default is off. +; Assertion pass logging is only enabled when assertion is browseable +; and assertion debug is enabled. +; AssertionPassLog = 1 + +; Turn on/off PSL concurrent assertion fail log. Default is on. +; The flag does not affect SVA +; AssertionFailLog = 0 + +; Turn on/off SVA concurrent assertion local var printing in -assertdebug mode. Default is on. +; AssertionFailLocalVarLog = 0 + +; Set action type for PSL/SVA concurrent assertion fail action. Default is continue. +; 0 = Continue 1 = Break 2 = Exit +; AssertionFailAction = 1 + +; Enable the active thread monitor in the waveform display when assertion debug is enabled. +; AssertionActiveThreadMonitor = 1 + +; Control how many waveform rows will be used for displaying the active threads. Default is 5. +; AssertionActiveThreadMonitorLimit = 5 + +; Assertion thread limit after which assertion would be killed/switched off. +; The default is -1 (unlimited). If the number of threads for an assertion go +; beyond this limit, the assertion would be either switched off or killed. This +; limit applies to only assert directives. +;AssertionThreadLimit = -1 + +; Action to be taken once the assertion thread limit is reached. Default +; is kill. It can have a value of off or kill. In case of kill, all the existing +; threads are terminated and no new attempts are started. In case of off, the +; existing attempts keep on evaluating but no new attempts are started. This +; variable applies to only assert directives. +;AssertionThreadLimitAction = kill + +; Cover thread limit after which cover would be killed/switched off. +; The default is -1 (unlimited). If the number of threads for a cover go +; beyond this limit, the cover would be either switched off or killed. This +; limit applies to only cover directives. +;CoverThreadLimit = -1 + +; Action to be taken once the cover thread limit is reached. Default +; is kill. It can have a value of off or kill. In case of kill, all the existing +; threads are terminated and no new attempts are started. In case of off, the +; existing attempts keep on evaluating but no new attempts are started. This +; variable applies to only cover directives. +;CoverThreadLimitAction = kill + + +; By default immediate assertions do not participate in Assertion Coverage calculations +; unless they are executed. This switch causes all immediate assertions in the design +; to participate in Assertion Coverage calculations, whether attempted or not. +; UnattemptedImmediateAssertions = 0 + +; By default immediate covers participate in Coverage calculations +; whether they are attempted or not. This switch causes all unattempted +; immediate covers in the design to stop participating in Coverage +; calculations. +; UnattemptedImmediateCovers = 0 + +; By default pass action block is not executed for assertions on vacuous +; success. The following variable is provided to enable execution of +; pass action block on vacuous success. The following variable is only effective +; if the user does not disable pass action block execution by using either +; system tasks or CLI. Also there is a performance penalty for enabling +; the following variable. +;AssertionEnableVacuousPassActionBlock = 1 + +; As per strict 1850-2005 PSL LRM, an always property can either pass +; or fail. However, by default, Questa reports multiple passes and +; multiple fails on top always/never property (always/never operator +; is the top operator under Verification Directive). The reason +; being that Questa reports passes and fails on per attempt of the +; top always/never property. Use the following flag to instruct +; Questa to strictly follow LRM. With this flag, all assert/never +; directives will start an attempt once at start of simulation. +; The attempt can either fail, match or match vacuously. +; For e.g. if always is the top operator under assert, the always will +; keep on checking the property at every clock. If the property under +; always fails, the directive will be considered failed and no more +; checking will be done for that directive. A top always property, +; if it does not fail, will show a pass at end of simulation. +; The default value is '0' (i.e. zero is off). For example: +; PslOneAttempt = 1 + +; Specify the number of clock ticks to represent infinite clock ticks. +; This affects eventually!, until! and until_!. If at End of Simulation +; (EOS) an active strong-property has not clocked this number of +; clock ticks then neither pass or fail (vacuous match) is returned +; else respective fail/pass is returned. The default value is '0' (zero) +; which effectively does not check for clock tick condition. For example: +; PslInfinityThreshold = 5000 + +; Control how many thread start times will be preserved for ATV viewing for a given assertion +; instance. Default is -1 (ALL). +; ATVStartTimeKeepCount = -1 + +; Turn on/off code coverage +; CodeCoverage = 0 + +; This option applies to condition and expression coverage UDP tables. It +; has no effect unless UDP is enabled for coverage with vcom/vlog/vopt -coverudp. +; If this option is used and a match occurs in more than one row in the UDP table, +; none of the counts for all matching rows is incremented. By default, counts are +; incremented for all matching rows. +; CoverCountAll = 1 + +; Turn off automatic inclusion of VHDL integers in toggle coverage. Default +; is to include them. +; ToggleNoIntegers = 1 + +; Set the maximum number of values that are collected for toggle coverage of +; VHDL integers. Default is 100; +; ToggleMaxIntValues = 100 + +; Set the maximum number of values that are collected for toggle coverage of +; Verilog real. Default is 100; +; ToggleMaxRealValues = 100 + +; Turn on automatic inclusion of Verilog integers in toggle coverage, except +; for enumeration types. Default is to include them. +; ToggleVlogIntegers = 0 + +; Turn on automatic inclusion of Verilog real type in toggle coverage, except +; for shortreal types. Default is to not include them. +; ToggleVlogReal = 1 + +; Turn on automatic inclusion of Verilog fixed-size unpacked arrays, VHDL multi-d arrays +; and VHDL arrays-of-arrays in toggle coverage. +; Default is to not include them. +; ToggleFixedSizeArray = 1 + +; Increase or decrease the maximum size of Verilog unpacked fixed-size arrays, +; VHDL multi-d arrays and VHDL arrays-of-arrays that are included for toggle coverage. +; This leads to a longer simulation time with bigger arrays covered with toggle coverage. +; Default is 1024. +; ToggleMaxFixedSizeArray = 1024 + +; Treat Verilog multi-dimensional packed vectors and packed structures as equivalently sized +; one-dimensional packed vectors for toggle coverage. Default is 0. +; TogglePackedAsVec = 0 + +; Treat Verilog enumerated types as equivalently sized one-dimensional packed vectors for +; toggle coverage. Default is 0. +; ToggleVlogEnumBits = 0 + +; Turn off automatic inclusion of VHDL records in toggle coverage. +; Default is to include them. +; ToggleVHDLRecords = 0 + +; Limit the widths of registers automatically tracked for toggle coverage. Default is 128. +; For unlimited width, set to 0. +; ToggleWidthLimit = 128 + +; Limit the counts that are tracked for toggle coverage. When all edges for a bit have +; reached this count, further activity on the bit is ignored. Default is 1. +; For unlimited counts, set to 0. +; ToggleCountLimit = 1 + +; Change the mode of extended toggle coverage. Default is 3. Valid modes are 1, 2 and 3. +; Following is the toggle coverage calculation criteria based on extended toggle mode: +; Mode 1: 0L->1H & 1H->0L & any one 'Z' transition (to/from 'Z'). +; Mode 2: 0L->1H & 1H->0L & one transition to 'Z' & one transition from 'Z'. +; Mode 3: 0L->1H & 1H->0L & all 'Z' transitions. +; ExtendedToggleMode = 3 + +; Enable toggle statistics collection only for ports. Default is 0. +; TogglePortsOnly = 1 + +; Limit the counts that are tracked for Focussed Expression Coverage. When a bin has +; reached this count, further tracking of the input patterns linked to it is ignored. +; Default is 1. For unlimited counts, set to 0. +; NOTE: Changing this value from its default value may affect simulation performance. +; FecCountLimit = 1 + +; Limit the counts that are tracked for UDP Coverage. When a bin has +; reached this count, further tracking of the input patterns linked to it is ignored. +; Default is 1. For unlimited counts, set to 0. +; NOTE: Changing this value from its default value may affect simulation performance. +; UdpCountLimit = 1 + +; Control toggle coverage deglitching period. A period of 0, eliminates delta +; cycle glitches. This is the default. The value of ToggleDeglitchPeriod needs to be either +; 0 or a time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". +; ToggleDeglitchPeriod = 10.0ps + +; Turn on/off all PSL/SVA cover directive enables. Default is on. +; CoverEnable = 0 + +; Turn on/off PSL/SVA cover log. Default is off "0". +; CoverLog = 1 + +; Set "at_least" value for all PSL/SVA cover directives. Default is 1. +; CoverAtLeast = 2 + +; Set "limit" value for all PSL/SVA cover directives. Default is -1. +; Any positive integer, -1 for infinity. +; CoverLimit = 1 + +; Specify the coverage database filename. +; Default is "" (i.e. database is NOT automatically saved on close). +; UCDBFilename = vsim.ucdb + +; Specify the maximum limit for the number of Cross (bin) products reported +; in XML and UCDB report against a Cross. A warning is issued if the limit +; is crossed. Default is zero. vsim switch -cvgmaxrptrhscross can override this +; setting. +; MaxReportRhsSVCrossProducts = 1000 + +; Specify the override for the "auto_bin_max" option for the Covergroups. +; If not specified then value from Covergroup "option" is used. +; SVCoverpointAutoBinMax = 64 + +; Specify the override for the value of "cross_num_print_missing" +; option for the Cross in Covergroups. If not specified then value +; specified in the "option.cross_num_print_missing" is used. This +; is a runtime option. NOTE: This overrides any "cross_num_print_missing" +; value specified by user in source file and any SVCrossNumPrintMissingDefault +; specified in modelsim.ini. +; SVCrossNumPrintMissing = 0 + +; Specify whether to use the value of "cross_num_print_missing" +; option in report and GUI for the Cross in Covergroups. If not specified then +; cross_num_print_missing is ignored for creating reports and displaying +; covergroups in GUI. Default is 0, which means ignore "cross_num_print_missing". +; UseSVCrossNumPrintMissing = 0 + +; Specify the threshold of Coverpoint wildcard bin value range size, above which +; a warning will be triggered. The default is 4K -- 12 wildcard bits. +; SVCoverpointWildCardBinValueSizeWarn = 4096 + +; Specify the override for the value of "strobe" option for the +; Covergroup Type. If not specified then value in "type_option.strobe" +; will be used. This is runtime option which forces "strobe" to +; user specified value and supersedes user specified values in the +; SystemVerilog Code. NOTE: This also overrides the compile time +; default value override specified using "SVCovergroupStrobeDefault" +; SVCovergroupStrobe = 0 + +; Override for explicit assignments in source code to "option.goal" of +; SystemVerilog covergroup, coverpoint, and cross. It also overrides the +; default value of "option.goal" (defined to be 100 in the SystemVerilog +; LRM) and the value of modelsim.ini variable "SVCovergroupGoalDefault". +; SVCovergroupGoal = 100 + +; Override for explicit assignments in source code to "type_option.goal" of +; SystemVerilog covergroup, coverpoint, and cross. It also overrides the +; default value of "type_option.goal" (defined to be 100 in the SystemVerilog +; LRM) and the value of modelsim.ini variable "SVCovergroupTypeGoalDefault". +; SVCovergroupTypeGoal = 100 + +; Enforce the 6.3 behavior of covergroup get_coverage() and get_inst_coverage() +; builtin functions, and report. This setting changes the default values of +; option.get_inst_coverage and type_option.merge_instances to ensure the 6.3 +; behavior if explicit assignments are not made on option.get_inst_coverage and +; type_option.merge_instances by the user. There are two vsim command line +; options, -cvg63 and -nocvg63 to override this setting from vsim command line. +; The default value of this variable from release 6.6 onwards is 0. This default +; drives compliance with the clarified behavior in the IEEE 1800-2009 standard. +; SVCovergroup63Compatibility = 0 + +; Enforce the default behavior of covergroup get_coverage() builtin function, GUI +; and report. This variable sets the default value of type_option.merge_instances. +; There are two vsim command line options, -cvgmergeinstances and +; -nocvgmergeinstances to override this setting from vsim command line. +; The default value of this variable, -1 (don't care), allows the tool to determine +; the effective value, based on factors related to capacity and optimization. +; The type_option.merge_instances appears in the GUI and coverage reports as either +; auto(1) or auto(0), depending on whether the effective value was determined to +; be a 1 or a 0. +; SVCovergroupMergeInstancesDefault = -1 + +; Enable or disable generation of more detailed information about the sampling +; of covergroup, cross, and coverpoints. It provides the details of the number +; of times the covergroup instance and type were sampled, as well as details +; about why covergroup, cross and coverpoint were not covered. A non-zero value +; is to enable this feature. 0 is to disable this feature. Default is 0 +; SVCovergroupSampleInfo = 0 + +; Specify the maximum number of Coverpoint bins in whole design for +; all Covergroups. +; MaxSVCoverpointBinsDesign = 2147483648 + +; Specify maximum number of Coverpoint bins in any instance of a Covergroup, default is 2^10 bins +; MaxSVCoverpointBinsInst = 1048576 + +; Specify the maximum number of Cross bins in whole design for +; all Covergroups. +; MaxSVCrossBinsDesign = 2147483648 + +; Specify maximum number of Cross bins in any instance of a Covergroup, default is 2^16 bins +; MaxSVCrossBinsInst = 67108864 + +; Specify whether vsim will collect the coverage data of zero-weight coverage items or not. +; By default, this variable is set 0, in which case option.no_collect setting will take effect. +; If this variable is set to 1, all zero-weight coverage items will not be saved. +; Note that the usage of vsim switch -cvgzwnocollect, if present, will override the setting +; of this variable. +; CvgZWNoCollect = 1 + +; Specify a space delimited list of double quoted TCL style +; regular expressions which will be matched against the text of all messages. +; If any regular expression is found to be contained within any message, the +; status for that message will not be propagated to the UCDB TESTSTATUS. +; If no match is detected, then the status will be propagated to the +; UCDB TESTSTATUS. More than one such regular expression text is allowed, +; and each message text is compared for each regular expression in the list. +; UCDBTestStatusMessageFilter = "Done with Test Bench" "Ignore .* message" + +; Set weight for all PSL/SVA cover directives. Default is 1. +; CoverWeight = 2 + +; Check vsim plusargs. Default is 0 (off). +; 0 = Don't check plusargs +; 1 = Warning on unrecognized plusarg +; 2 = Error and exit on unrecognized plusarg +; CheckPlusargs = 1 + +; Load the specified shared objects with the RTLD_GLOBAL flag. +; This gives global visibility to all symbols in the shared objects, +; meaning that subsequently loaded shared objects can bind to symbols +; in the global shared objects. The list of shared objects should +; be whitespace delimited. This option is not supported on the +; Windows or AIX platforms. +; GlobalSharedObjectList = example1.so example2.so example3.so + +; Generate the stub definitions for the undefined symbols in the shared libraries being +; loaded in the simulation. When this flow is turned on, the undefined symbols will not +; prevent vsim from loading. Calling undefined symbols at runtime will cause fatal error. +; The valid arguments are: on, off, verbose. +; on : turn on the automatic generation of stub definitions. +; off: turn off the flow. The undefined symbols will trigger an immediate load failure. +; verbose: Turn on the flow and report the undefined symbols for each shared library. +; NOTE: This variable can be overriden with vsim switch "-undefsyms". +; The default is on. +; +; UndefSyms = off + +; Enable the support for checkpointing foreign C/C++ libraries. +; The valid arguments are: 0, 1, 2 +; 0: off (default) +; 1: on (manually save/restore user shared library data) +; 2: auto (automatically save/restore user shared library data) +; This option is not supported on the Windows platforms. +; +; AllowCheckpointCpp = 2 + +; Initial seed for the random number generator of the root thread (SystemVerilog). +; NOTE: This variable can be overridden with the vsim "-sv_seed" command line switch. +; The default value is 0. +; Sv_Seed = 0 + +; Specify the solver "engine" that vsim will select for constrained random +; generation. +; Valid values are: +; "auto" - automatically select the best engine for the current +; constraint scenario +; "bdd" - evaluate all constraint scenarios using the BDD solver engine +; "act" - evaluate all constraint scenarios using the ACT solver engine +; While the BDD solver engine is generally efficient with constraint scenarios +; involving bitwise logical relationships, the ACT solver engine can exhibit +; superior performance with constraint scenarios involving large numbers of +; random variables related via arithmetic operators (+, *, etc). +; NOTE: This variable can be overridden with the vsim "-solveengine" command +; line switch. +; The default value is "auto". +; SolveEngine = auto + +; Specify the maximum size that a random dynamic array or queue may be resized +; to by the solver. If the solver attempts to resize a dynamic array or queue +; to a size greater than the specified limit, the solver will abort with an error. +; The default value is 10000. The maximum value is 10000000. A value of 0 is +; equivalent to specifying the maximum value. +; SolveArrayResizeMax = 10000 + +; Specify error message severity when randomize() and randomize(null) failures +; are detected. +; +; Integer value up to two digits are allowed with each digit having the following legal values: +; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal +; +; 1) When a value with two digits is used, the digit at tenth place (leftmost digit) represents +; the severtity setting for normal randomize() calls. The digit at ones place (rightmost digit) +; represents the setting for randomize(null) calls. +; +; 2) When a single digit value is used, the setting is applied to both normal randomize() call +; and randomize(null) call. +; +; Example: Fatal error for randomize() failures and NO error for randomize(null) failures +; -solvefailseverity=40 +; +; NOTE: SolveFailSeverity can affect the behavior of SolveFailDebug. When SolveFailDebug is +; enabled, a constraint contradiction report will be displayed for randomize() calls that +; have a message severity >= warning (i.e. constraint contradiction reports will not be +; generated for randomize() calls having a "no error" severity level) +; +; NOTE: This variable can be overridden with the vsim "-solvefailseverity" command +; line switch. +; +; The default is 1 (warning). +; SolveFailSeverity = 1 + +; Error message severity for suppressible errors that are detected in a +; solve/before constraint. +; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal +; NOTE: This variable can be overridden with the vsim "-solvebeforeerrorseverity" +; command line switch. +; The default is 3 (failure). +; SolveBeforeErrorSeverity = 3 + +; Error message severity for suppressible errors that are related to +; solve engine capacity limits +; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal +; NOTE: This variable can be overridden with the vsim "-solveengineerrorseverity" +; command line switch. +; The default is 3 (failure). +; SolveEngineErrorSeverity = 3 + +; Enable/disable constraint conflicts on randomize() failure +; Valid values: +; 0 - disable solvefaildebug +; 1 - basic debug (no performance penalty) +; 2 - enhanced debug (runtime performance penalty) +; +; NOTE: SolveFailSeverity can affect the behavior of SolveFailDebug. When SolveFailDebug is +; enabled, a constraint contradiction report will be displayed for randomize() calls that +; have a message severity >= warning (i.e. constraint contradiction reports will not be +; generated for randomize() calls having a "no error" severity level) +; +; NOTE: This variable can be overridden with the vsim "-solvefaildebug" command +; line switch. +; +; The default is 1 (basic debug). +; SolveFailDebug = 1 + +; Upon encountering a randomize() failure, generate a simplified testcase that +; will reproduce the failure. Optionally output the testcase to a file. +; Testcases for 'no-solution' failures will only be produced if SolveFailDebug +; is enabled (see above). +; NOTE: This variable can be overridden with the vsim "-solvefailtestcase" +; command line switch. +; The default is OFF (do not generate a testcase). To enable testcase +; generation, uncomment this variable. To redirect testcase generation to a +; file, specify the name of the output file. +; SolveFailTestcase = + +; Specify solver timeout threshold (in seconds). randomize() will fail if the +; CPU time required to evaluate any randset exceeds the specified timeout. +; The default value is 500. A value of 0 will disable timeout failures. +; SolveTimeout = 500 + +; Specify the alternative behavior during solver replay. Must be used when combined with -solvereplay switch. +; SolveReplayOpt=[+|-]<opt>[,[+|-]<opt>]*" +' Valid <opt> settings: +; validate : toggle the checking of value changes of non-random variables involved in randomize(). (default is off)" +; SolveReplayOpt=validate + +; Switch to specify options that control the behavior of the solver profiler.. +; Valid options are: +; cputime - use CPU time instead of elapsed time (wall time) to measure performance data (default is off) +; randsets - enable detailed profiling of randsets (default is off) +; testgen - generate testcases for profiled randsets (only when randsets option is enabled) (default is off) +; SolverFProf = [+|-]<option>[,[+|-]<option>*] + +; Specify the maximum size of the solution graph generated by the BDD solver. +; This value can be used to force the BDD solver to abort the evaluation of a +; complex constraint scenario that cannot be evaluated with finite memory. +; This value is specified in 1000s of nodes. +; The default value is 10000. A value of 0 indicates no limit. +; SolveGraphMaxSize = 10000 + +; Specify the maximum number of evaluations that may be performed on the +; solution graph by the BDD solver. This value can be used to force the BDD +; solver to abort the evaluation of a complex constraint scenario that cannot +; be evaluated in finite time. This value is specified in 10000s of evaluations. +; The default value is 10000. A value of 0 indicates no limit. +; SolveGraphMaxEval = 10000 + +; Specify random sequence compatiblity with a prior release. This +; option is used to get the same random sequences during simulation as +; as a prior release. Only prior releases with the same major version +; as the current release are allowed. +; NOTE: Only those random sequence changes due to solver optimizations are +; reverted by this variable. Random sequence changes due to solver bugfixes +; cannot be un-done. +; NOTE: This variable can be overridden with the vsim "-solverev" command +; line switch. +; Default value set to "" (no compatibility). +; SolveRev = + +; Environment variable expansion of command line arguments has been depricated +; in favor shell level expansion. Universal environment variable expansion +; inside -f files is support and continued support for MGC Location Maps provide +; alternative methods for handling flexible pathnames. +; The following line may be uncommented and the value set to 1 to re-enable this +; deprecated behavior. The default value is 0. +; DeprecatedEnvironmentVariableExpansion = 0 + +; Specify the memory threshold for the System Verilog garbage collector. +; The value is the number of megabytes of class objects that must accumulate +; before the garbage collector is run. +; The GCThreshold setting is used when class debug mode is disabled to allow +; less frequent garbage collection and better simulation performance. +; The GCThresholdClassDebug setting is used when class debug mode is enabled +; to allow for more frequent garbage collection. +; GCThreshold = 100 +; GCThresholdClassDebug = 5 + +; Turn on/off collapsing of bus ports in VCD dumpports output +DumpportsCollapse = 1 + +; Location of Multi-Level Verification Component (MVC) installation. +; The default location is the product installation directory. +MvcHome = $QUESTA_MVC_HOME + +; Location of InFact installation. The default is $MODEL_TECH/../../infact +; +; InFactHome = $MODEL_TECH/../../infact + +; Initialize SystemVerilog enums using the base type's default value +; instead of the leftmost value. +; EnumBaseInit = 1 + +; Suppress file type registration. +; SuppressFileTypeReg = 1 + +; Enable/disable non-LRM compliant SystemVerilog language extensions. +; Valid extensions are: +; altdpiheader - Alternative style function signature generated in DPI header", +; cfce - generate an error if $cast fails as a function +; cfmt - C like formatting for specifiers with '#' prefix ('%#x', '%#h') +; dfsp - sets default format specifier as %p, if no format specifier is given for unpacked array in $display and related systasks +; expdfmt - enable format string extensions for $display/$sformatf +; extscan - support values greater than 32 bit for string builtin methods (atohex, atobin, atooct, atoi) +; fmtcap - prints capital hex digits with %X/%H in display calls +; iddp - ignore DPI disable protocol check +; lfmt - zero-pad data if '0' prefixes width in format specifier (e.g. "%04h") +; noexptc - ignore DPI export type name overloading check +; realrand - support randomize() with real variables and constraints (Default) +; SvExtensions = [+|-]<extension>[,[+|-]<extension>*] + +; Enable/disable non-LRM compliant SystemVerilog constrained-random language extensions. +; Valid extensions are: +; arraymode - consider rand_mode of unpacked array field independently from its elements +; deepcheck - allow randomize(null) to recursively consider constraints from member rand class handles (Default) +; funcback - enable function backtracking (ACT only) +; genmodseedfix - enable LRM-compliant seeding of module/interface instances under for-generate blocks (Default) +; impvecindex - inject constraints on random indices of 2-state vectors +; nodist - interpret 'dist' constraint as 'inside' (ACT only) +; noorder - ignore solve/before ordering constraints (ACT only) +; pathseed - enable unique seeding of module instances based on hierarchical path name +; prerandfirst - execute all pre_randomize() functions before evaluating any constraints +; promotedist - promote priority of 'dist' constraint if LHS has no solve/before +; purecheck - suppress pre_randomize() and post_randomize() calls for randomize(null) +; randindex - allow random index in constraint (Default) +; randstruct - consider all fields of unpacked structs as 'rand' +; skew - skew randomize results (ACT only) +; strictstab - strict random stability +; SvRandExtensions = [+|-]<extension>[,[+|-]<extension>*] + +; Controls the formatting of '%p' and '%P' conversion specification, used in $display +; and similar system tasks. +; 1. SVPrettyPrintFlags=I<n><S|T> use <n> spaces(S) or tabs(T) per indentation level. +; The 'I' flag when present causes relevant data types to be expanded and indented into +; a more readable format. +; (e.g. SVPrettyPrintFlags=I4S will cause 4 spaces to be used per indentation level). +; 2. SVPrettyPrintFlags=L<numLines> limits the output to <numLines> lines. +; (e.g. SVPrettyPrintFlags=L20 will limit the output to 20 lines). +; 3. SVPrettyPrintFlags=C<numChars> limits the output to <numChars> characters. +; (e.g. SVPrettyPrintFlags=C256 will limit the output to 256 characters). +; 4. SVPrettyPrintFlags=F<numFields> limits the output to <numFields> of relevant datatypes +; (e.g. SVPrettyPrintFlags=F4 will limit the output to 4 fields of a structure). +; 5. SVPrettyPrintFlags=E<numElements> limits the output to <numElements> of relevant datatypes +; (e.g. SVPrettyPrintFlags=E50 will limit the output to 50 elements of an array). +; 6. SVPrettyPrintFlags=D<depth> suppresses the output of sub-elements below <depth>. +; (e.g. SVPrettyPrintFlags=D5 will suppresses the output of sub elements below a depth of 5). +; 7. SVPrettyPrintFlags=R<specifier> shows the output of specifier %p as per the specifed radix. +; It changes the output in $display and similar systasks. It does not affect formatted output functions ($displayh etc)). +; (e.g. SVPrettyPrintFlags=Rb will show the output of %p specifier in binary format. +; 8. Items 1-7 above can be combined as a comma separated list. +; (e.g. SVPrettyPrintFlags=I4S,L20,C256,F4,E50,D5,Rb) +; SVPrettyPrintFlags=I4S + +[lmc] +; The simulator's interface to Logic Modeling's SmartModel SWIFT software +libsm = $MODEL_TECH/libsm.sl +; The simulator's interface to Logic Modeling's SmartModel SWIFT software (Windows NT) +; libsm = $MODEL_TECH/libsm.dll +; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700) +; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl +; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000) +; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o +; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris) +; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so +; Logic Modeling's SmartModel SWIFT software (Windows NT) +; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll +; Logic Modeling's SmartModel SWIFT software (non-Enterprise versions of Linux) +; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so +; Logic Modeling's SmartModel SWIFT software (Enterprise versions of Linux) +; libswift = $LMC_HOME/lib/linux.lib/libswift.so + +; The simulator's interface to Logic Modeling's hardware modeler SFI software +libhm = $MODEL_TECH/libhm.sl +; The simulator's interface to Logic Modeling's hardware modeler SFI software (Windows NT) +; libhm = $MODEL_TECH/libhm.dll +; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700) +; libsfi = <sfi_dir>/lib/hp700/libsfi.sl +; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000) +; libsfi = <sfi_dir>/lib/rs6000/libsfi.a +; Logic Modeling's hardware modeler SFI software (Sun4 Solaris) +; libsfi = <sfi_dir>/lib/sun4.solaris/libsfi.so +; Logic Modeling's hardware modeler SFI software (Windows NT) +; libsfi = <sfi_dir>/lib/pcnt/lm_sfi.dll +; Logic Modeling's hardware modeler SFI software (Linux) +; libsfi = <sfi_dir>/lib/linux/libsfi.so + +[msg_system] +; Change a message severity or suppress a message. +; The format is: <msg directive> = <msg number>[,<msg number>...] +; suppress can be used to achieve +nowarn<CODE> functionality +; The format is: suppress = <CODE>,<msg number>,[<CODE>,<msg number>,...] +; Examples: +suppress = 8780 ;an explanation can be had by running: verror 8780 +;suppress = 12110 ; +; note = 3009 +; warning = 3033 +; error = 3010,3016 +; fatal = 3016,3033 +; suppress = 3009,3016,3601 +; suppress = 3009,CNNODP,3601,TFMPC +; suppress = 8683,8684 +; The command verror <msg number> can be used to get the complete +; description of a message. + +; Control transcripting of Verilog display system task messages and +; PLI/FLI print function call messages. The system tasks include +; $display[bho], $strobe[bho], $monitor[bho], and $write[bho]. They +; also include the analogous file I/O tasks that write to STDOUT +; (i.e. $fwrite or $fdisplay). The PLI/FLI calls include io_printf, +; vpi_printf, mti_PrintMessage, and mti_PrintFormatted. The default +; is to have messages appear only in the transcript. The other +; settings are to send messages to the wlf file only (messages that +; are recorded in the wlf file can be viewed in the MsgViewer) or +; to both the transcript and the wlf file. The valid values are +; tran {transcript only (default)} +; wlf {wlf file only} +; both {transcript and wlf file} +; displaymsgmode = tran + +; Control transcripting of elaboration/runtime messages not +; addressed by the displaymsgmode setting. The default is to +; have messages appear only in the transcript. The other settings +; are to send messages to the wlf file only (messages that are +; recorded in the wlf file can be viewed in the MsgViewer) or to both +; the transcript and the wlf file. The valid values are +; tran {transcript only (default)} +; wlf {wlf file only} +; both {transcript and wlf file} +; msgmode = tran + +; Controls number of displays of a particluar message +; default value is 5 +; MsgLimitCount = 5 + +[utils] +; Default Library Type (while creating a library with "vlib") +; 0 - legacy library using subdirectories for design units +; 2 - flat library +; DefaultLibType = 2 + +; Flat Library Page Size (while creating a library with "vlib") +; Set the size in bytes for flat library file pages. Libraries containing +; very large files may benefit from a larger value. +; FlatLibPageSize = 8192 + +; Flat Library Page Cleanup Percentage (while creating a library with "vlib") +; Set the percentage of total pages deleted before library cleanup can occur. +; This setting is applied together with FlatLibPageDeleteThreshold. +; FlatLibPageDeletePercentage = 50 + +; Flat Library Page Cleanup Threshold (while creating a library with "vlib") +; Set the number of pages deleted before library cleanup can occur. +; This setting is applied together with FlatLibPageDeletePercentage. +; FlatLibPageDeleteThreshold = 1000 + diff --git a/manufacturer/altera/cyclone10_lp/sim/lin/wave.do b/manufacturer/altera/cyclone10_lp/sim/lin/wave.do new file mode 100644 index 0000000..65535fe --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/sim/lin/wave.do @@ -0,0 +1,307 @@ +onerror {resume} +quietly virtual signal -install /tb/dut { (context /tb/dut )&{mac_sel ,mac_addr }} data_sel +quietly virtual signal -install /tb/dut { (context /tb/dut )&{mac_addr , mac_sel , mle_sel , hf_ptrs_sel , hf_rx_sel , hf_tx_sel }} data_sel001 +quietly virtual signal -install /tb/dut { (context /tb/dut )&{mac_addr[0] , mac_addr[1] , mac_sel , mle_sel , hf_ptrs_sel , hf_rx_sel , hf_tx_sel }} data_sel002 +quietly virtual signal -install /tb/dut { (concat_range (0 to 6) )( (context /tb/dut )&{mac_addr , mac_sel , mle_sel , hf_ptrs_sel , hf_rx_sel , hf_tx_sel } )} data_sel003 +quietly WaveActivateNextPane {} 0 +add wave -noupdate /tb/rstn +add wave -noupdate /tb/clk_125 +add wave -noupdate /tb/pclk +add wave -noupdate /tb/clk_25 +add wave -noupdate /tb/clk_phy +add wave -noupdate /tb/clk_phyx2 +add wave -noupdate /tb/phy0_rx_clk +add wave -noupdate /tb/phy0_rx_ctl +add wave -noupdate /tb/phy0_rx_d +add wave -noupdate /tb/phy1_rx_clk +add wave -noupdate /tb/phy1_rx_ctl +add wave -noupdate /tb/phy1_rx_d +add wave -noupdate /tb/phy2_rx_clk +add wave -noupdate /tb/phy2_rx_ctl +add wave -noupdate /tb/phy2_rx_d +add wave -noupdate /tb/phy0_mdc +add wave -noupdate /tb/phy0_mdio +add wave -noupdate /tb/phy0_resetn +add wave -noupdate /tb/phy0_intn +add wave -noupdate /tb/phy1_mdc +add wave -noupdate /tb/phy1_mdio +add wave -noupdate /tb/phy1_resetn +add wave -noupdate /tb/phy1_intn +add wave -noupdate /tb/phy_up +add wave -noupdate /tb/rx0_data_cnt +add wave -noupdate /tb/rx0_d +add wave -noupdate /tb/rx1_d +add wave -noupdate /tb/rx2_d +add wave -noupdate /tb/rx1_data_cnt +add wave -noupdate /tb/rx2_data_cnt +add wave -noupdate /tb/phy0_tx_clk +add wave -noupdate /tb/phy0_tx_ctl +add wave -noupdate /tb/phy0_tx_d +add wave -noupdate /tb/phy1_tx_clk +add wave -noupdate /tb/phy1_tx_ctl +add wave -noupdate /tb/phy1_tx_d +add wave -noupdate /tb/phy2_tx_clk +add wave -noupdate /tb/phy2_tx_ctl +add wave -noupdate /tb/phy2_tx_d +add wave -noupdate -divider Top +add wave -noupdate /tb/dut/rstn +add wave -noupdate /tb/dut/sys_rstn +add wave -noupdate /tb/dut/clk_i +add wave -noupdate /tb/dut/pll_locked +add wave -noupdate /tb/clk_25 +add wave -noupdate /tb/clk_125 +add wave -noupdate /tb/dut/phy0_clk +add wave -noupdate /tb/dut/phy1_clk +add wave -noupdate /tb/dut/cont_clk +add wave -noupdate /tb/dut/sys_rstn +add wave -noupdate /tb/dut/phy_resetn +add wave -noupdate /tb/dut/phy0_rstn +add wave -noupdate /tb/dut/phy1_rstn +add wave -noupdate /tb/clk_phy +add wave -noupdate /tb/clk_phyx2 +add wave -noupdate {/tb/dut/phy_up[0]} +add wave -noupdate /tb/phy0_rx_clk +add wave -noupdate /tb/dut/rgmi_rx_0/datain +add wave -noupdate /tb/dut/rgmi_rx_0/inclock +add wave -noupdate /tb/dut/rgmi_rx_0/dataout_h +add wave -noupdate /tb/dut/rgmi_rx_0/dataout_l +add wave -noupdate /tb/dut/rx0_ctl_m1 +add wave -noupdate /tb/dut/rx0_d_m1 +add wave -noupdate /tb/dut/rx0_ctl_m2 +add wave -noupdate /tb/dut/rx0_d_m2 +add wave -noupdate /tb/dut/tx0_ctl +add wave -noupdate /tb/dut/tx0_d +add wave -noupdate /tb/dut/tx1_ctl +add wave -noupdate /tb/dut/tx1_d +add wave -noupdate /tb/dut/mle_d_0 +add wave -noupdate /tb/dut/mle_d_1 +add wave -noupdate /tb/dut/mle_d_2 +add wave -noupdate /tb/dut/mle_d_3 +add wave -noupdate /tb/dut/mle_d_i +add wave -noupdate /tb/clk_125 +add wave -noupdate /tb/dut/mle_evt_start +add wave -noupdate /tb/dut/mle_evt_active +add wave -noupdate -color Yellow /tb/dut/mle_enable +add wave -noupdate /tb/dut/mle_empty +add wave -noupdate /tb/dut/mle_fifo_d_o +add wave -noupdate /tb/dut/mle_fifo_empty +add wave -noupdate /tb/dut/mle_fifo_re +add wave -noupdate /tb/dut/mle_oe +add wave -noupdate /tb/dut/mle_we +add wave -noupdate /tb/dut/data_sel003 +add wave -noupdate /tb/dut/mac_addr +add wave -noupdate /tb/dut/mac_sel +add wave -noupdate /tb/dut/mle_sel +add wave -noupdate /tb/dut/hf_ptrs_sel +add wave -noupdate /tb/dut/hf_rx_sel +add wave -noupdate /tb/dut/hf_tx_sel +add wave -noupdate /tb/dut/mac_0_d_o +add wave -noupdate /tb/dut/mac_1_d_o +add wave -noupdate /tb/dut/mac_2_d_o +add wave -noupdate /tb/dut/mle_d_o +add wave -noupdate /tb/dut/hfifo_d_o +add wave -noupdate /tb/dut/mem_d_i +add wave -noupdate -divider {MAC 0} +add wave -noupdate /tb/dut/mac_0/rx_clk +add wave -noupdate /tb/dut/mac_0/phy_up +add wave -noupdate /tb/dut/mac_0/rx_sop +add wave -noupdate -color Yellow /tb/dut/mac_0/rx_eop +add wave -noupdate /tb/dut/mac_0/rx_state +add wave -noupdate /tb/dut/mac_0/rx_packet_complete +add wave -noupdate /tb/dut/mac_0/rx_wr_done +add wave -noupdate /tb/dut/mac_0/rx_keep +add wave -noupdate /tb/dut/mac_0/rx_l3_proto +add wave -noupdate /tb/dut/mac_0/rx_pkt_length +add wave -noupdate /tb/dut/mac_0/rx_ctl +add wave -noupdate /tb/dut/mac_0/rx_d +add wave -noupdate /tb/dut/mac_0/rx_ctl_m1 +add wave -noupdate /tb/dut/mac_0/rx_d_m1 +add wave -noupdate /tb/dut/mac_0/rx_line_up_cnt +add wave -noupdate /tb/dut/mac_0/mle_if_cnt +add wave -noupdate /tb/dut/mac_0/mle_if_d_o +add wave -noupdate /tb/dut/mac_0/mle_if_empty +add wave -noupdate /tb/dut/mac_0/mle_if_enable +add wave -noupdate /tb/dut/mac_0/mle_if_we +add wave -noupdate /tb/dut/mac_0/mle_if_oe +add wave -noupdate -divider HFIFO +add wave -noupdate /tb/dut/micro_fifo_0/rx_fifo_int +add wave -noupdate /tb/dut/micro_fifo_0/rx_fifo_int_acked +add wave -noupdate /tb/dut/micro_fifo_0/rx_wr_ptr +add wave -noupdate /tb/dut/micro_fifo_0/rx_wr_ptr_latched +add wave -noupdate /tb/dut/micro_fifo_0/dpram_rx/rstn +add wave -noupdate /tb/dut/micro_fifo_0/dpram_rx/a_clk +add wave -noupdate /tb/dut/micro_fifo_0/dpram_rx/a_clk_e +add wave -noupdate /tb/dut/micro_fifo_0/dpram_rx/a_we +add wave -noupdate /tb/dut/micro_fifo_0/dpram_rx/a_oe +add wave -noupdate /tb/dut/micro_fifo_0/dpram_rx/a_addr +add wave -noupdate /tb/dut/micro_fifo_0/dpram_rx/a_din +add wave -noupdate /tb/dut/micro_fifo_0/dpram_rx/a_dout +add wave -noupdate /tb/dut/micro_fifo_0/dpram_rx/b_clk +add wave -noupdate /tb/dut/micro_fifo_0/dpram_rx/b_clk_e +add wave -noupdate /tb/dut/micro_fifo_0/dpram_rx/b_we +add wave -noupdate /tb/dut/micro_fifo_0/dpram_rx/b_oe +add wave -noupdate /tb/dut/micro_fifo_0/dpram_rx/b_addr +add wave -noupdate /tb/dut/micro_fifo_0/dpram_rx/b_din +add wave -noupdate /tb/dut/micro_fifo_0/dpram_rx/b_dout +add wave -noupdate -divider Controller +add wave -noupdate /tb/dut/controller_0/clk +add wave -noupdate /tb/dut/controller_0/rx_msg_captured +add wave -noupdate /tb/dut/controller_0/rx_msg_cnt +add wave -noupdate /tb/dut/controller_0/msg_addr +add wave -noupdate /tb/dut/controller_0/msg_addr_ro +add wave -noupdate /tb/dut/controller_0/msg_addr_valid +add wave -noupdate /tb/dut/controller_0/msg_data +add wave -noupdate /tb/dut/controller_0/msg_error +add wave -noupdate /tb/dut/controller_0/msg_response +add wave -noupdate /tb/dut/controller_0/msg_token +add wave -noupdate /tb/dut/controller_0/msg_type +add wave -noupdate /tb/dut/controller_0/cont_msg +add wave -noupdate /tb/dut/controller_0/cont_state +add wave -noupdate /tb/dut/controller_0/rx_rd_active +add wave -noupdate /tb/dut/controller_0/rx_wr_ptr +add wave -noupdate /tb/dut/controller_0/rx_rd_ptr +add wave -noupdate /tb/dut/controller_0/mem_state +add wave -noupdate /tb/dut/controller_0/mem_addr +add wave -noupdate /tb/dut/controller_0/mem_cmd +add wave -noupdate /tb/dut/controller_0/mem_d_i +add wave -noupdate /tb/dut/controller_0/mem_d_o +add wave -noupdate /tb/dut/controller_0/mem_oe +add wave -noupdate /tb/dut/controller_0/mem_tgt_ready +add wave -noupdate /tb/dut/controller_0/mem_tgt_ready_m1 +add wave -noupdate /tb/dut/controller_0/mem_tgt_ready_m2 +add wave -noupdate /tb/dut/controller_0/mem_we +add wave -noupdate /tb/dut/controller_0/mle_sel +add wave -noupdate -divider {MAC 1} +add wave -noupdate /tb/dut/mac_1/mle_if_cnt +add wave -noupdate /tb/dut/mac_1/mle_if_d_o +add wave -noupdate /tb/dut/mac_1/mle_if_empty +add wave -noupdate /tb/dut/mac_1/mle_if_enable +add wave -noupdate /tb/dut/mac_1/mle_if_oe +add wave -noupdate /tb/dut/mac_1/mle_if_we +add wave -noupdate /tb/dut/mac_1/rx_ctl +add wave -noupdate /tb/dut/mac_1/rx_d +add wave -noupdate -divider {MAC 2} +add wave -noupdate /tb/dut/mac_2/mle_if_cnt +add wave -noupdate /tb/dut/mac_2/mle_if_d_o +add wave -noupdate /tb/dut/mac_2/mle_if_empty +add wave -noupdate /tb/dut/mac_2/mle_if_enable +add wave -noupdate /tb/dut/mac_2/mle_if_oe +add wave -noupdate /tb/dut/mac_2/mle_if_we +add wave -noupdate /tb/dut/mac_2/rx_ctl +add wave -noupdate /tb/dut/mac_2/rx_d +add wave -noupdate -divider {ML ENGINE 0} +add wave -noupdate /tb/dut/ml_engine_0/rstn +add wave -noupdate /tb/dut/ml_engine_0/clk +add wave -noupdate /tb/dut/ml_engine_0/mle_enable +add wave -noupdate -radix decimal /tb/dut/ml_engine_0/evt_counter +add wave -noupdate /tb/dut/ml_engine_0/evt_start +add wave -noupdate /tb/dut/ml_engine_0/evt_active +add wave -noupdate -color Yellow /tb/dut/ml_engine_0/mle_0_state +add wave -noupdate /tb/dut/ml_engine_0/enable_logic_active +add wave -noupdate /tb/dut/ml_engine_0/enable +add wave -noupdate /tb/dut/ml_engine_0/empty +add wave -noupdate /tb/dut/ml_engine_0/empty_m1 +add wave -noupdate /tb/dut/ml_engine_0/we +add wave -noupdate /tb/dut/ml_engine_0/wr_block0 +add wave -noupdate /tb/dut/ml_engine_0/wr_ptr0 +add wave -noupdate /tb/dut/ml_engine_0/wr_addr0 +add wave -noupdate /tb/dut/mle_oe +add wave -noupdate /tb/dut/ml_engine_0/cnt0 +add wave -noupdate /tb/dut/ml_engine_0/clk +add wave -noupdate /tb/dut/ml_engine_0/we1 +add wave -noupdate /tb/dut/ml_engine_0/d_out_avail +add wave -noupdate /tb/dut/ml_engine_0/evt_delay_out +add wave -noupdate /tb/dut/ml_engine_0/rd_block1 +add wave -noupdate /tb/dut/ml_engine_0/rd_ptr1 +add wave -noupdate /tb/dut/ml_engine_0/rd_addr1 +add wave -noupdate /tb/dut/ml_engine_0/fifo_d_o +add wave -noupdate /tb/dut/ml_engine_0/fifo_d_out_flag +add wave -noupdate /tb/dut/ml_engine_0/fifo_d_out_flag_m1 +add wave -noupdate /tb/dut/ml_engine_0/fifo_empty +add wave -noupdate /tb/dut/ml_engine_0/fifo_re +add wave -noupdate -divider {DPRAM Inpt} +add wave -noupdate /tb/dut/ml_engine_0/dpram_s0/rstn +add wave -noupdate /tb/dut/ml_engine_0/dpram_s0/a_clk +add wave -noupdate /tb/dut/ml_engine_0/dpram_s0/a_clk_e +add wave -noupdate /tb/dut/ml_engine_0/dpram_s0/a_we +add wave -noupdate /tb/dut/ml_engine_0/dpram_s0/a_oe +add wave -noupdate /tb/dut/ml_engine_0/dpram_s0/a_addr +add wave -noupdate /tb/dut/ml_engine_0/dpram_s0/a_din +add wave -noupdate /tb/dut/ml_engine_0/dpram_s0/a_dout +add wave -noupdate /tb/dut/ml_engine_0/dpram_s0/b_clk +add wave -noupdate /tb/dut/ml_engine_0/dpram_s0/b_clk_e +add wave -noupdate /tb/dut/ml_engine_0/dpram_s0/b_we +add wave -noupdate /tb/dut/ml_engine_0/dpram_s0/b_oe +add wave -noupdate /tb/dut/ml_engine_0/dpram_s0/b_addr +add wave -noupdate /tb/dut/ml_engine_0/dpram_s0/b_din +add wave -noupdate /tb/dut/ml_engine_0/dpram_s0/b_dout +add wave -noupdate -divider DIRECT_OUTPUT +add wave -noupdate /tb/dut/ml_engine_0/rd_addr0 +add wave -noupdate /tb/dut/ml_engine_0/d_s0_o +add wave -noupdate /tb/dut/ml_engine_0/rd_oe0 +add wave -noupdate -divider {ML ENGINE OUTPUT} +add wave -noupdate /tb/dut/ml_engine_0/evt_delay_out +add wave -noupdate /tb/dut/ml_engine_0/rd_addr1 +add wave -noupdate /tb/dut/ml_engine_0/rd_block1 +add wave -noupdate /tb/dut/ml_engine_0/rd_ptr1 +add wave -noupdate /tb/dut/ml_engine_0/fifo_d_out_flag +add wave -noupdate /tb/dut/ml_engine_0/fifo_d_out_flag_m1 +add wave -noupdate /tb/dut/ml_engine_0/fifo_empty +add wave -noupdate /tb/dut/ml_engine_0/fifo_re +add wave -noupdate /tb/dut/ml_engine_0/fifo_d_o +add wave -noupdate -divider {SWITCH 0} +add wave -noupdate /tb/dut/switch_0/clk +add wave -noupdate /tb/dut/switch_0/phy_up +add wave -noupdate /tb/dut/switch_0/rx_d_01 +add wave -noupdate /tb/dut/switch_0/rx_d_0u +add wave -noupdate /tb/dut/switch_0/rx0_byte_cnt +add wave -noupdate /tb/dut/switch_0/rx_fifo_empty_0u +add wave -noupdate /tb/dut/switch_0/rx_fifo_empty_01 +add wave -noupdate /tb/dut/switch_0/rx_fifo_empty_u0 +add wave -noupdate /tb/dut/switch_0/rx_fifo_re_01 +add wave -noupdate /tb/dut/switch_0/rx_fifo_re_0u +add wave -noupdate {/tb/dut/switch_0/tx_f[0]} +add wave -noupdate {/tb/dut/switch_0/tx_fifo_empty[0]} +add wave -noupdate {/tb/dut/switch_0/tx_f[1]} +add wave -noupdate {/tb/dut/switch_0/tx_fifo_empty[1]} +add wave -noupdate /tb/dut/switch_0/tx_mode0 +add wave -noupdate /tb/dut/switch_0/tx0_byte_cnt +add wave -noupdate /tb/dut/switch_0/tx0_src_sel +add wave -noupdate -divider {MAC 0 TX} +add wave -noupdate /tb/dut/mac_0/tx_clk +add wave -noupdate /tb/dut/mac_0/tx_byte_cnt_i +add wave -noupdate /tb/dut/mac_0/tx_fifo_empty +add wave -noupdate /tb/dut/mac_0/tx_fifo_re +add wave -noupdate /tb/dut/mac_0/tx_state +add wave -noupdate /tb/dut/mac_0/tx_cnt +add wave -noupdate /tb/dut/mac_0/tx_mode +add wave -noupdate /tb/dut/mac_0/tx_src_sel +add wave -noupdate /tb/dut/mac_0/tx_fifo_d +add wave -noupdate /tb/dut/mac_0/tx_fifo_d_m1 +add wave -noupdate /tb/dut/mac_0/tx_fifo_d_m2 +add wave -noupdate /tb/dut/mac_0/tx_pkt_cnt +add wave -noupdate /tb/dut/mac_0/tx_mle_fifo_d +add wave -noupdate /tb/dut/mac_0/tx_mle_fifo_empty +add wave -noupdate /tb/dut/mac_0/tx_mode +add wave -noupdate /tb/dut/mac_0/tx_sop +add wave -noupdate -radix unsigned /tb/dut/mac_0/tx_cnt +add wave -noupdate /tb/dut/mac_0/tx_ctl +add wave -noupdate /tb/dut/mac_0/tx_d +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {5416031 ps} 0} +quietly wave cursor active 1 +configure wave -namecolwidth 233 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ps +update +WaveRestoreZoom {5433405 ps} {5630040 ps} diff --git a/manufacturer/altera/cyclone10_lp/sim/sim.do b/manufacturer/altera/cyclone10_lp/sim/sim.do new file mode 100644 index 0000000..60d9627 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/sim/sim.do @@ -0,0 +1,4 @@ +vsim -voptargs="+acc" -i -l msim_transcript work.tb -L work -L rtl_work \ +-L lpm_ver -L sgate_ver -L altera_ver -L altera_mf_ver -L altera_lnsim_ver \ +-L altera_ver -L altera_mf_ver -L cyclone10lp_ver + diff --git a/manufacturer/altera/cyclone10_lp/sim/src/tb.sv b/manufacturer/altera/cyclone10_lp/sim/src/tb.sv new file mode 100644 index 0000000..9b6b3a2 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/sim/src/tb.sv @@ -0,0 +1,359 @@ +/* + * tb.sv + * + * Copyright (C) 2025 Private Island Networks Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * function: test bench for Betsy + * + * Notes: + * + * RX data is from the TB to the DUT + * TX data is from the DUT to the TB + * + */ + +`timescale 1ns / 1ps + +//`define TEST_ETOE +`define ML_ENGINE +//`define TEST_CONTROLLER + +`define INCLUDED +`include "../../../../../src/rgmii_params.v" +`include "../../../../../src/ethernet_params.v" +`undef INCLUDED + +module tb; + + parameter NUM_PHYS = 3; + + // System clocks + parameter PERIOD_CLK_25 = 40; // 25 MHz + parameter PERIOD_CLK_125 = 8; // 125 MHz + parameter PERIOD_CLK_250 = 4; // 250 MHz to support RGMII DDR + + localparam IDLE_SHIFT = 4; // Used to multiple the specified # of idle clocks + +`ifdef ML_ENGINE + localparam RX0_CLK_CNT_START = 'd400; + localparam RX1_CLK_CNT_START = 'd4000_0000; + localparam RX2_CLK_CNT_START = 'd4000_0000; +`else + localparam RX0_CLK_CNT_START = 'd400; + localparam RX1_CLK_CNT_START = 'd400; + localparam RX2_CLK_CNT_START = 'd400; +`endif + + + // FPGA I/O + reg rstn; + reg clk_125, clk_25, clk_phy, clk_phyx2; + wire phy0_rx_clk, phy1_rx_clk, phy2_rx_clk; + reg phy0_rx_ctl, phy1_rx_ctl, phy2_rx_ctl; + reg [3:0] phy0_rx_d, phy1_rx_d, phy2_rx_d; + wire phy0_tx_clk, phy1_tx_clk, phy2_tx_clk; + wire phy0_tx_ctl, phy1_tx_ctl, phy2_tx_ctl; + wire [3:0] phy0_tx_d, phy1_tx_d, phy2_tx_d; + wire phy0_mdc, phy0_mdio, phy0_resetn, phy0_intn; + wire phy1_mdc, phy1_mdio, phy1_resetn, phy1_intn; + wire phy2_mdc, phy2_mdio, phy2_resetn, phy2_intn; + wire [2:0] led; + + // sim only I/O + wire pclk; + wire pll_lock; + wire [2:0] phy_up; + + betsy dut( + .rstn(rstn), + .clk_i(clk_25), + .phy0_clk(clk_25), + .phy1_clk(), + + // Sim Only + .pll_locked_o(pll_lock), + .pclk_o(pclk), + .phy_up_o(phy_up), + + .phy0_rstn(phy0_resetn), + .phy0_rx_clk(phy0_rx_clk), + .phy0_rx_ctl(phy0_rx_ctl), + .phy0_rx_d(phy0_rx_d), + .phy0_tx_clk(phy0_tx_clk), + .phy0_tx_ctl(phy0_tx_ctl), + .phy0_tx_d(phy0_tx_d), + .phy0_mdc(phy0_mdc), + .phy0_mdio(phy0_mdio), + .phy0_intn(phy0_intn), + + .phy1_rstn(phy1_resetn), + .phy1_rx_clk(phy1_rx_clk), + .phy1_rx_ctl(phy1_rx_ctl), + .phy1_rx_d(phy1_rx_d), + .phy1_tx_clk(phy1_tx_clk), + .phy1_tx_ctl(phy1_tx_ctl), + .phy1_tx_d(phy1_tx_d), + .phy1_mdc(phy1_mdc), + .phy1_mdio(phy1_mdio), + .phy1_intn(phy1_intn), + + .phy2_rstn(phy2_resetn), + .phy2_rx_clk(phy2_rx_clk), + .phy2_rx_ctl(phy2_rx_ctl), + .phy2_rx_d(phy2_rx_d), + .phy2_tx_clk(phy2_tx_clk), + .phy2_tx_ctl(phy2_tx_ctl), + .phy2_tx_d(phy2_tx_d), + .phy2_mdc(phy2_mdc), + .phy2_mdio(phy2_mdio), + .phy2_intn(phy2_intn), + + .flash_clk(), + .flash_dqs(), + .flash_seln(), + .flash_d(), + + .fpga_led(led) + + ); + + + reg [23:0] rx_clk_cnt; + reg [23:0] rx0_clk_cnt_start, rx1_clk_cnt_start, rx2_clk_cnt_start; + reg [13:0] rx0_idle_cnt, rx1_idle_cnt, rx2_idle_cnt; + reg [13:0] rx0_data_cnt, rx1_data_cnt, rx2_data_cnt; + reg rx0_last_byte, rx1_last_byte, rx2_last_byte; + reg [8:0] rx0_d[0:16383]; // 2**14 + reg [8:0] rx1_d[0:16383]; // + reg [8:0] rx2_d[0:16383]; // + + +`ifdef ML_ENGINE + initial begin + $readmemh("../data/cont_mle_w.dat",rx0_d); + $display("[%0t ns] ==INFO== Load memory from file for rx0: %0s.", $time, "cont_mle_w.dat"); + end +`endif + +`ifdef TEST_ETOE + initial begin + $readmemh("../data/etoe0.dat",rx0_d); + $display("[%0t ns] ==INFO== Load memory from file for rx0: %0s.", $time, "etoe0.dat"); + $readmemh("../data/etoe1.dat",rx1_d); + $display("[%0t ns] ==INFO== Load memory from file for rx1: %0s.", $time, "etoe1.dat"); + $readmemh("../data/etoe2.dat",rx2_d); + $display("[%0t ns] ==INFO== Load memory from file for rx2: %0s.", $time, "etoe2.dat"); + end +`endif + +`ifdef TEST_CONTROLLER + initial begin + $readmemh("../data/cont_query.dat",rx0_d); + $display("[%0t ns] ==INFO== Load memory from file for rx0: %0s.", $time, "cont_query.dat"); + end +`endif + + + initial begin + rstn = 1'b0; + clk_25 = 1'b0; + clk_125 = 1'b0; + clk_phy = 0; + clk_phyx2 = 0; + #25 rstn = 1'b1; + end + + // Clocks + always + #(PERIOD_CLK_125/2) clk_125 = ~clk_125; + + always + #(PERIOD_CLK_25/2) clk_25 = ~clk_25; + + always + #(PERIOD_CLK_125/2) clk_phy = ~clk_phy; + + always + #(PERIOD_CLK_250/2) clk_phyx2 = ~clk_phyx2; + + + assign #2 phy0_rx_clk = ~clk_phy; // 2.0 ns of delay + assign #2 phy1_rx_clk = ~clk_phy; + assign #2 phy2_rx_clk = ~clk_phy; + + // DDR count. Use bit 0 to indicate rising edge + always @(posedge clk_phyx2, negedge rstn) + if (!rstn) + rx_clk_cnt <= 24'd0; + else + rx_clk_cnt <= rx_clk_cnt + 1'b1; + + // PHY0 + always @(posedge clk_phy, negedge rstn) + if (!rstn) + rx0_idle_cnt <= 14'd0; + else if (rx0_d[rx0_data_cnt][8]) + rx0_idle_cnt <= rx0_d[rx0_data_cnt+1][7:0] << IDLE_SHIFT; + + always @(posedge clk_phy, negedge rstn) + if (!rstn) + rx0_clk_cnt_start <= RX0_CLK_CNT_START; + else if (rx0_d[rx0_data_cnt][8]) + rx0_clk_cnt_start <= rx_clk_cnt + (rx0_d[rx0_data_cnt+1][7:0] << IDLE_SHIFT) + 1'b1; + + always @(negedge clk_phyx2, negedge rstn) + if (!rstn) + rx0_last_byte <= 1'b0; + else if (rx0_d[rx0_data_cnt][8] && rx_clk_cnt[0]) + rx0_last_byte <= 1'b1; + else + rx0_last_byte <= 1'b0; + + always @(negedge clk_phyx2, negedge rstn) + if (!rstn) begin + phy0_rx_ctl <= 1'b0; + phy0_rx_d <= 4'hD; + rx0_data_cnt <= 24'd0; + end + else if (rx_clk_cnt >= rx0_clk_cnt_start && !rx0_last_byte) begin + if (!rx_clk_cnt[0]) begin + phy0_rx_ctl <= 1'b1; + phy0_rx_d <= rx0_d[rx0_data_cnt][3:0]; + end + else begin + phy0_rx_ctl <= 1'b1; + phy0_rx_d <= rx0_d[rx0_data_cnt][7:4]; + rx0_data_cnt <= rx0_data_cnt + 1'b1; + end + end + else if (rx0_last_byte) begin + phy0_rx_ctl <= 1'b0; + phy0_rx_d <= 4'hD; + rx0_data_cnt <= rx0_data_cnt + 1'b1; + end + else begin + phy0_rx_ctl <= 1'b0; + phy0_rx_d <= 4'hD; + end + + + // PHY1 + + // rx1_idle_cnt: when flag is set, update idle count + always @(posedge clk_phy, negedge rstn) + if (!rstn) + rx1_idle_cnt <= 14'd0; + else if (rx1_d[rx1_data_cnt][8]) + rx1_idle_cnt <= rx1_d[rx1_data_cnt+1][7:0] << IDLE_SHIFT; + + // rx1_clk_cnt_start: + always @(posedge clk_phy, negedge rstn) + if (!rstn) + rx1_clk_cnt_start <= RX1_CLK_CNT_START; + else if (rx1_d[rx1_data_cnt][8]) + rx1_clk_cnt_start <= rx_clk_cnt + (rx1_d[rx1_data_cnt+1][7:0] << IDLE_SHIFT) + 1'b1; + + + always @(negedge clk_phyx2, negedge rstn) + if (!rstn) + rx1_last_byte <= 1'b0; + else if (rx1_d[rx1_data_cnt][8] && rx_clk_cnt[0]) + rx1_last_byte <= 1'b1; + else + rx1_last_byte <= 1'b0; + + always @(negedge clk_phyx2, negedge rstn) + if (!rstn) begin + phy1_rx_ctl <= 1'b0; + phy1_rx_d <= 4'hD; + rx1_data_cnt <= 24'd0; + end + else if (rx_clk_cnt >= rx1_clk_cnt_start && !rx1_last_byte) begin + if (!rx_clk_cnt[0]) begin + phy1_rx_ctl <= 1'b1; + phy1_rx_d <= rx1_d[rx1_data_cnt][3:0]; + end + else begin + phy1_rx_ctl <= 1'b1; + phy1_rx_d <= rx1_d[rx1_data_cnt][7:4]; + rx1_data_cnt <= rx1_data_cnt + 1'b1; + end + end + else if (rx1_last_byte) begin + phy1_rx_ctl <= 1'b0; + phy1_rx_d <= 4'hD; + rx1_data_cnt <= rx1_data_cnt + 1'b1; + end + else begin + phy1_rx_ctl <= 1'b0; + phy1_rx_d <= 4'hD; + end + + // PHY2 + + // rx1_idle_cnt: when flag is set, update idle count + always @(posedge clk_phy, negedge rstn) + if (!rstn) + rx2_idle_cnt <= 14'd0; + else if (rx2_d[rx2_data_cnt][8]) + rx2_idle_cnt <= rx2_d[rx2_data_cnt+1][7:0] << IDLE_SHIFT; + + always @(posedge clk_phy, negedge rstn) + if (!rstn) + rx2_clk_cnt_start <= RX2_CLK_CNT_START; + else if (rx2_d[rx2_data_cnt][8]) + rx2_clk_cnt_start <= rx_clk_cnt + (rx2_d[rx2_data_cnt+1][7:0] << IDLE_SHIFT) + 1'b1; + + // + always @(negedge clk_phyx2, negedge rstn) + if (!rstn) + rx2_last_byte <= 1'b0; + else if (rx2_d[rx2_data_cnt][8] && rx_clk_cnt[0]) + rx2_last_byte <= 1'b1; + else + rx2_last_byte <= 1'b0; + + + always @(negedge clk_phyx2, negedge rstn) + if (!rstn) begin + phy2_rx_ctl <= 1'b0; + phy2_rx_d <= 4'hD; + rx2_data_cnt <= 24'd0; + end + else if (rx_clk_cnt >= rx2_clk_cnt_start && !rx2_last_byte) begin + if (!rx_clk_cnt[0]) begin + phy2_rx_ctl <= 1'b1; + phy2_rx_d <= rx2_d[rx2_data_cnt][3:0]; + end + else begin + phy2_rx_ctl <= 1'b1; + phy2_rx_d <= rx2_d[rx2_data_cnt][7:4]; + rx2_data_cnt <= rx2_data_cnt + 1'b1; + end + end + else if (rx2_last_byte) begin + phy2_rx_ctl <= 1'b0; + phy2_rx_d <= 4'hD; + rx2_data_cnt <= rx2_data_cnt + 1'b1; + end + else begin + phy2_rx_ctl <= 1'b0; + phy2_rx_d <= 4'hD; + end + + +endmodule + + diff --git a/manufacturer/altera/cyclone10_lp/sim/wav/wave.do b/manufacturer/altera/cyclone10_lp/sim/wav/wave.do new file mode 100644 index 0000000..b64b7d5 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/sim/wav/wave.do @@ -0,0 +1,294 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /tb/rstn +add wave -noupdate /tb/clk_125 +add wave -noupdate /tb/pclk +add wave -noupdate /tb/clk_25 +add wave -noupdate /tb/clk_phy +add wave -noupdate /tb/clk_phyx2 +add wave -noupdate /tb/rx_cnt +add wave -noupdate /tb/phy0_rx_clk +add wave -noupdate /tb/phy0_rx_ctl +add wave -noupdate /tb/phy0_rx_d +add wave -noupdate /tb/phy1_rx_clk +add wave -noupdate /tb/phy1_rx_ctl +add wave -noupdate /tb/phy1_rx_d +add wave -noupdate /tb/phy2_rx_clk +add wave -noupdate /tb/phy2_rx_ctl +add wave -noupdate /tb/phy2_rx_d +add wave -noupdate /tb/phy0_mdc +add wave -noupdate /tb/phy0_mdio +add wave -noupdate /tb/phy0_resetn +add wave -noupdate /tb/phy0_intn +add wave -noupdate /tb/phy1_mdc +add wave -noupdate /tb/phy1_mdio +add wave -noupdate /tb/phy1_resetn +add wave -noupdate /tb/phy1_intn +add wave -noupdate /tb/phy_up +add wave -noupdate /tb/word_sync_active +add wave -noupdate /tb/rx_cnt +add wave -noupdate /tb/rx0_f +add wave -noupdate /tb/rx0_f_reg +add wave -noupdate /tb/rx0_data_cnt +add wave -noupdate /tb/rx0_data_interval +add wave -noupdate /tb/rx0_d +add wave -noupdate /tb/rx1_d +add wave -noupdate /tb/rx2_d +add wave -noupdate /tb/rx0_packets +add wave -noupdate /tb/rx0_packet_active +add wave -noupdate /tb/rx1_data_cnt +add wave -noupdate /tb/rx1 +add wave -noupdate /tb/rx2_data_cnt +add wave -noupdate /tb/phy0_tx_clk +add wave -noupdate /tb/phy0_tx_ctl +add wave -noupdate /tb/phy0_tx_d +add wave -noupdate /tb/phy1_tx_clk +add wave -noupdate /tb/phy1_tx_ctl +add wave -noupdate /tb/phy1_tx_d +add wave -noupdate /tb/phy2_tx_clk +add wave -noupdate /tb/phy2_tx_ctl +add wave -noupdate /tb/phy2_tx_d +add wave -noupdate -divider Top +add wave -noupdate /tb/dut/rstn +add wave -noupdate /tb/dut/sys_rstn +add wave -noupdate /tb/dut/clk_i +add wave -noupdate /tb/dut/pll_locked +add wave -noupdate /tb/clk_25 +add wave -noupdate /tb/clk_125 +add wave -noupdate /tb/dut/phy0_clk +add wave -noupdate /tb/dut/phy1_clk +add wave -noupdate /tb/dut/cont_clk +add wave -noupdate /tb/dut/sys_rstn +add wave -noupdate /tb/dut/phy_resetn +add wave -noupdate /tb/dut/phy0_rstn +add wave -noupdate /tb/dut/phy1_rstn +add wave -noupdate /tb/rx_cnt +add wave -noupdate /tb/clk_phy +add wave -noupdate /tb/clk_phyx2 +add wave -noupdate {/tb/dut/phy_up[0]} +add wave -noupdate /tb/phy0_rx_clk +add wave -noupdate /tb/dut/rgmi_rx_0/datain +add wave -noupdate /tb/dut/rgmi_rx_0/inclock +add wave -noupdate /tb/dut/rgmi_rx_0/dataout_h +add wave -noupdate /tb/dut/rgmi_rx_0/dataout_l +add wave -noupdate /tb/dut/rx0_ctl +add wave -noupdate /tb/dut/rx0_d +add wave -noupdate /tb/dut/rx0_ctl_m1 +add wave -noupdate /tb/dut/rx0_d_m1 +add wave -noupdate /tb/dut/rx0_ctl_m2 +add wave -noupdate /tb/dut/rx0_d_m2 +add wave -noupdate /tb/dut/tx0_ctl +add wave -noupdate /tb/dut/tx0_d +add wave -noupdate /tb/dut/tx1_ctl +add wave -noupdate /tb/dut/tx1_d +add wave -noupdate -divider {SWITCH 0} +add wave -noupdate /tb/dut/switch_0/clk +add wave -noupdate /tb/dut/switch_0/phy_up +add wave -noupdate /tb/dut/switch_0/rx_d_01 +add wave -noupdate /tb/dut/switch_0/rx_d_0u +add wave -noupdate /tb/dut/switch_0/rx0_byte_cnt +add wave -noupdate /tb/dut/switch_0/rx_fifo_empty_0u +add wave -noupdate /tb/dut/switch_0/rx_fifo_empty_01 +add wave -noupdate /tb/dut/switch_0/rx_fifo_empty_u0 +add wave -noupdate /tb/dut/switch_0/rx_fifo_re_01 +add wave -noupdate /tb/dut/switch_0/rx_fifo_re_0u +add wave -noupdate {/tb/dut/switch_0/tx_f[0]} +add wave -noupdate {/tb/dut/switch_0/tx_fifo_empty[0]} +add wave -noupdate {/tb/dut/switch_0/tx_f[1]} +add wave -noupdate {/tb/dut/switch_0/tx_fifo_empty[1]} +add wave -noupdate /tb/dut/switch_0/tx_mode0 +add wave -noupdate /tb/dut/switch_0/tx0_byte_cnt +add wave -noupdate /tb/dut/switch_0/tx0_src_sel +add wave -noupdate -divider {MAC 0} +add wave -noupdate /tb/dut/mac_0/rx_clk +add wave -noupdate /tb/dut/mac_0/rx_sop +add wave -noupdate /tb/dut/mac_0/rx_state +add wave -noupdate /tb/dut/mac_0/rx_packet_complete +add wave -noupdate /tb/dut/mac_0/rx_wr_done +add wave -noupdate /tb/dut/mac_0/rx_keep +add wave -noupdate /tb/dut/mac_0/rx_l3_proto +add wave -noupdate /tb/dut/mac_0/rx_pkt_length +add wave -noupdate /tb/dut/mac_0/rx_ctl +add wave -noupdate /tb/dut/mac_0/rx_d +add wave -noupdate /tb/dut/mac_0/rx_ctl_m1 +add wave -noupdate /tb/dut/mac_0/rx_d_m1 +add wave -noupdate /tb/dut/mac_0/rx_line_up_cnt +add wave -noupdate /tb/dut/mac_0/phy_up +add wave -noupdate /tb/dut/mac_0/tx_clk +add wave -noupdate /tb/dut/mac_0/dpr_ad +add wave -noupdate /tb/dut/mac_0/dpr_ce +add wave -noupdate /tb/dut/mac_0/dpr_di +add wave -noupdate /tb/dut/mac_0/dpr_di_reg +add wave -noupdate /tb/dut/mac_0/dpr_do +add wave -noupdate /tb/dut/mac_0/dpr_we +add wave -noupdate /tb/dut/mac_0/tx_sample +add wave -noupdate /tb/dut/mac_0/tx_sample_re +add wave -noupdate /tb/dut/mac_0/tx_active +add wave -noupdate /tb/dut/mac_0/tx_byte_cnt +add wave -noupdate /tb/dut/mac_0/tx_byte_cnt_i +add wave -noupdate /tb/dut/mac_0/tx_src_sel +add wave -noupdate /tb/dut/mac_0/tx_mode +add wave -noupdate /tb/dut/mac_0/tx_state +add wave -noupdate /tb/dut/mac_0/tx_last_byte +add wave -noupdate /tb/dut/mac_0/tx_fifo_d +add wave -noupdate /tb/dut/mac_0/tx_fifo_d_m1 +add wave -noupdate /tb/dut/mac_0/tx_fifo_empty +add wave -noupdate /tb/dut/mac_0/tx_fifo_re +add wave -noupdate /tb/dut/mac_0/tx_f_pkt +add wave -noupdate /tb/dut/mac_0/tx_sop +add wave -noupdate /tb/dut/mac_0/tx_eop +add wave -noupdate /tb/dut/mac_0/tx_ctl +add wave -noupdate /tb/dut/mac_0/tx_d +add wave -noupdate /tb/dut/mac_0/tx_f +add wave -noupdate /tb/dut/mac_0/tx_ctl_idle +add wave -noupdate /tb/dut/mac_0/tx_d_idle +add wave -noupdate /tb/dut/mac_0/tx_ctl_pkt +add wave -noupdate /tb/dut/mac_0/tx_data_pkt +add wave -noupdate -divider {IP RX 0 U} +add wave -noupdate /tb/dut/ipv4_rx_c_0/clk +add wave -noupdate /tb/dut/ipv4_rx_c_0/rx_state +add wave -noupdate /tb/dut/ipv4_rx_c_0/pkt_complete +add wave -noupdate /tb/dut/ipv4_rx_c_0/pkt_start +add wave -noupdate /tb/dut/ipv4_rx_c_0/protocol +add wave -noupdate /tb/dut/ipv4_rx_c_0/rx_byte_cnt +add wave -noupdate /tb/dut/ipv4_rx_c_0/rx_data_m1 +add wave -noupdate /tb/dut/ipv4_rx_c_0/rx_data_m2 +add wave -noupdate /tb/dut/ipv4_rx_c_0/rx_data_m3 +add wave -noupdate /tb/dut/ipv4_rx_c_0/rx_data_m4 +add wave -noupdate -radix unsigned /tb/dut/ipv4_rx_c_0/rx_pkt_length +add wave -noupdate -divider {UDP RX 0 U} +add wave -noupdate /tb/dut/udp_rx_c_0/rx_state +add wave -noupdate /tb/dut/udp_rx_c_0/pkt_complete +add wave -noupdate /tb/dut/udp_rx_c_0/pkt_start +add wave -noupdate /tb/dut/udp_rx_c_0/rx_byte_cnt +add wave -noupdate /tb/dut/udp_rx_c_0/rx_data_m1 +add wave -noupdate /tb/dut/udp_rx_c_0/rx_data_m2 +add wave -noupdate /tb/dut/udp_rx_c_0/rx_data_m3 +add wave -noupdate /tb/dut/udp_rx_c_0/rx_data_m4 +add wave -noupdate -divider {DROP FIFO 0 U} +add wave -noupdate /tb/dut/drop_fifo_0u/active +add wave -noupdate /tb/dut/drop_fifo_0u/passthrough +add wave -noupdate /tb/dut/drop_fifo_0u/phy_up +add wave -noupdate /tb/dut/drop_fifo_0u/rx_clk +add wave -noupdate /tb/dut/drop_fifo_0u/we_in +add wave -noupdate /tb/dut/drop_fifo_0u/wr_ptr0 +add wave -noupdate /tb/dut/drop_fifo_0u/wr_ptr1 +add wave -noupdate /tb/dut/drop_fifo_0u/d_in +add wave -noupdate /tb/dut/drop_fifo_0u/tx_clk +add wave -noupdate /tb/dut/drop_fifo_0u/we_out +add wave -noupdate /tb/dut/drop_fifo_0u/d_out_internal +add wave -noupdate /tb/dut/drop_fifo_0u/d_out +add wave -noupdate /tb/dut/drop_fifo_0u/df_bytes +add wave -noupdate /tb/dut/drop_fifo_0u/enable +add wave -noupdate /tb/dut/drop_fifo_0u/fifo_empty +add wave -noupdate /tb/dut/drop_fifo_0u/keep +add wave -noupdate /tb/dut/drop_fifo_0u/kept +add wave -noupdate /tb/dut/drop_fifo_0u/rd_ptr +add wave -noupdate /tb/dut/drop_fifo_0u/read_run +add wave -noupdate /tb/dut/drop_fifo_0u/read_run_m1 +add wave -noupdate /tb/dut/drop_fifo_0u/read_run_m2 +add wave -noupdate /tb/dut/drop_fifo_0u/rx_error +add wave -noupdate /tb/dut/drop_fifo_0u/wr_done +add wave -noupdate -divider {SYNC FIFO 0U} +add wave -noupdate /tb/dut/sync_fifo_rx_0u/active +add wave -noupdate /tb/dut/sync_fifo_rx_0u/almost_full +add wave -noupdate /tb/dut/sync_fifo_rx_0u/clk +add wave -noupdate /tb/dut/sync_fifo_rx_0u/we +add wave -noupdate /tb/dut/sync_fifo_rx_0u/wr_bytes_available +add wave -noupdate /tb/dut/sync_fifo_rx_0u/wr_ptr +add wave -noupdate /tb/dut/sync_fifo_rx_0u/d_in +add wave -noupdate /tb/dut/sync_fifo_rx_0u/d_out +add wave -noupdate /tb/dut/sync_fifo_rx_0u/empty +add wave -noupdate /tb/dut/sync_fifo_rx_0u/rd_ptr +add wave -noupdate /tb/dut/sync_fifo_rx_0u/re +add wave -noupdate /tb/dut/sync_fifo_rx_0u/reset_ptrs +add wave -noupdate -divider {Half FIFO} +add wave -noupdate /tb/dut/micro_fifo_0/dpram_addr +add wave -noupdate /tb/dut/micro_fifo_0/dpram_din +add wave -noupdate /tb/dut/micro_fifo_0/dpram_dout +add wave -noupdate /tb/dut/micro_fifo_0/dpram_oe +add wave -noupdate /tb/dut/micro_fifo_0/dpram_ptrs_sel +add wave -noupdate /tb/dut/micro_fifo_0/dpram_rx_dout +add wave -noupdate /tb/dut/micro_fifo_0/dpram_rx_enable +add wave -noupdate /tb/dut/micro_fifo_0/dpram_rx_sel +add wave -noupdate /tb/dut/micro_fifo_0/dpram_tx_dout +add wave -noupdate /tb/dut/micro_fifo_0/dpram_tx_enable +add wave -noupdate /tb/dut/micro_fifo_0/dpram_tx_sel +add wave -noupdate /tb/dut/micro_fifo_0/dpram_we +add wave -noupdate /tb/dut/micro_fifo_0/fifo_clk +add wave -noupdate /tb/dut/micro_fifo_0/fifo_d_out +add wave -noupdate /tb/dut/micro_fifo_0/fifo_int +add wave -noupdate /tb/dut/micro_fifo_0/fifo_int_acked +add wave -noupdate /tb/dut/micro_fifo_0/fifo_re +add wave -noupdate /tb/dut/micro_fifo_0/fifo_we +add wave -noupdate /tb/dut/micro_fifo_0/fifo_we_m1 +add wave -noupdate /tb/dut/micro_fifo_0/reset_ptrs +add wave -noupdate /tb/dut/micro_fifo_0/rx_byte_cnt +add wave -noupdate /tb/dut/micro_fifo_0/rx_empty +add wave -noupdate /tb/dut/micro_fifo_0/rx_rd_ptr +add wave -noupdate /tb/dut/micro_fifo_0/rx_wr_ptr +add wave -noupdate /tb/dut/micro_fifo_0/tx_mode +add wave -noupdate /tb/dut/micro_fifo_0/tx_rd_ptr +add wave -noupdate /tb/dut/micro_fifo_0/tx_wr_ptr +add wave -noupdate /tb/dut/micro_fifo_0/tx_wr_ptr_latched +add wave -noupdate /tb/dut/micro_fifo_0/fifo_d_in +add wave -noupdate /tb/dut/micro_fifo_0/uc_clk +add wave -noupdate -divider Controller +add wave -noupdate /tb/dut/controller_0/clk +add wave -noupdate /tb/dut/controller_0/cont_state +add wave -noupdate /tb/dut/controller_0/cmd_ack +add wave -noupdate /tb/dut/controller_0/cmd_addr +add wave -noupdate /tb/dut/controller_0/cmd_addr_ro +add wave -noupdate /tb/dut/controller_0/cmd_addr_valid +add wave -noupdate /tb/dut/controller_0/cmd_data +add wave -noupdate /tb/dut/controller_0/cmd_error +add wave -noupdate /tb/dut/controller_0/cmd_id +add wave -noupdate /tb/dut/controller_0/cmd_response +add wave -noupdate /tb/dut/controller_0/cmd_size +add wave -noupdate /tb/dut/controller_0/cmd_type +add wave -noupdate /tb/dut/controller_0/hf_ptrs_sel +add wave -noupdate /tb/dut/controller_0/hf_rx_sel +add wave -noupdate /tb/dut/controller_0/hf_tx_sel +add wave -noupdate /tb/dut/controller_0/hf_ptrs_sel +add wave -noupdate /tb/dut/controller_0/hf_rx_sel +add wave -noupdate /tb/dut/controller_0/hf_tx_sel +add wave -noupdate /tb/dut/controller_0/mdio_we +add wave -noupdate /tb/dut/controller_0/mem_addr +add wave -noupdate /tb/dut/controller_0/mem_d_i +add wave -noupdate /tb/dut/controller_0/mem_d_o +add wave -noupdate /tb/dut/controller_0/mem_state +add wave -noupdate /tb/dut/controller_0/mem_we +add wave -noupdate /tb/dut/controller_0/mem_oe +add wave -noupdate /tb/dut/controller_0/rx_cmd +add wave -noupdate /tb/dut/controller_0/rx_cnt +add wave -noupdate /tb/dut/controller_0/rx_fifo_int +add wave -noupdate /tb/dut/controller_0/rx_fifo_int_acked +add wave -noupdate /tb/dut/controller_0/rx_fifo_int_m1 +add wave -noupdate /tb/dut/controller_0/rx_fifo_int_m2 +add wave -noupdate /tb/dut/controller_0/rx_rd_active +add wave -noupdate /tb/dut/controller_0/rx_wr_ptr +add wave -noupdate /tb/dut/controller_0/rx_rd_ptr +add wave -noupdate /tb/dut/controller_0/tx_cnt +add wave -noupdate /tb/dut/controller_0/tx_fifo_empty +add wave -noupdate /tb/dut/controller_0/tx_pkt_cnt +add wave -noupdate /tb/dut/controller_0/tx_wr_active +add wave -noupdate /tb/dut/controller_0/tx_wr_ptr +add wave -noupdate /tb/dut/controller_0/mem_event_handling +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {3188000 ps} 0} +quietly wave cursor active 1 +configure wave -namecolwidth 199 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ps +update +WaveRestoreZoom {3173619 ps} {4640839 ps} diff --git a/manufacturer/altera/cyclone10_lp/sim/wav/wave_cont.do b/manufacturer/altera/cyclone10_lp/sim/wav/wave_cont.do new file mode 100644 index 0000000..674ee29 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/sim/wav/wave_cont.do @@ -0,0 +1,367 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /tb/rstn +add wave -noupdate /tb/clk_125 +add wave -noupdate /tb/clk_25 +add wave -noupdate /tb/clk_phy +add wave -noupdate /tb/clk_phyx2 +add wave -noupdate /tb/pll_lock +add wave -noupdate /tb/phy_up +add wave -noupdate /tb/pclk +add wave -noupdate -radix unsigned /tb/rx0_data_cnt +add wave -noupdate /tb/rx0_idle_cnt +add wave -noupdate /tb/rx0_last_byte +add wave -noupdate -radix hexadecimal /tb/rx_clk_cnt +add wave -noupdate /tb/phy0_rx_clk +add wave -noupdate /tb/phy0_rx_ctl +add wave -noupdate /tb/phy0_rx_d +add wave -noupdate /tb/phy1_rx_clk +add wave -noupdate /tb/phy1_rx_ctl +add wave -noupdate /tb/phy1_rx_d +add wave -noupdate /tb/phy2_rx_clk +add wave -noupdate /tb/phy2_rx_ctl +add wave -noupdate /tb/phy2_rx_d +add wave -noupdate /tb/phy0_tx_clk +add wave -noupdate /tb/phy0_tx_ctl +add wave -noupdate /tb/phy0_tx_d +add wave -noupdate /tb/phy1_tx_clk +add wave -noupdate /tb/phy1_tx_ctl +add wave -noupdate /tb/phy1_tx_d +add wave -noupdate /tb/phy2_tx_clk +add wave -noupdate /tb/phy2_tx_ctl +add wave -noupdate /tb/phy2_tx_d +add wave -noupdate -divider {RGMII RX 0} +add wave -noupdate /tb/dut/rgmi_rx_0/inclock +add wave -noupdate /tb/dut/rgmi_rx_0/datain +add wave -noupdate /tb/dut/rgmi_rx_0/dataout_h +add wave -noupdate /tb/dut/rgmi_rx_0/dataout_l +add wave -noupdate -divider Top +add wave -noupdate /tb/dut/rstn +add wave -noupdate /tb/dut/sys_rstn +add wave -noupdate /tb/dut/clk_i +add wave -noupdate /tb/dut/pll_locked +add wave -noupdate /tb/clk_25 +add wave -noupdate /tb/clk_125 +add wave -noupdate /tb/dut/phy0_clk +add wave -noupdate /tb/dut/phy1_clk +add wave -noupdate /tb/dut/cont_clk +add wave -noupdate /tb/dut/sys_rstn +add wave -noupdate /tb/dut/phy_resetn +add wave -noupdate /tb/dut/phy0_rstn +add wave -noupdate /tb/dut/phy1_rstn +add wave -noupdate /tb/clk_phy +add wave -noupdate /tb/clk_phyx2 +add wave -noupdate {/tb/dut/phy_up[0]} +add wave -noupdate /tb/phy0_rx_clk +add wave -noupdate /tb/dut/rgmi_rx_0/datain +add wave -noupdate /tb/dut/rgmi_rx_0/inclock +add wave -noupdate /tb/dut/rgmi_rx_0/dataout_h +add wave -noupdate /tb/dut/rgmi_rx_0/dataout_l +add wave -noupdate /tb/dut/rx0_ctl_m1 +add wave -noupdate /tb/dut/rx0_d_m1 +add wave -noupdate /tb/dut/rx0_ctl_m2 +add wave -noupdate /tb/dut/rx0_d_m2 +add wave -noupdate /tb/dut/tx0_ctl +add wave -noupdate /tb/dut/tx0_d +add wave -noupdate /tb/dut/tx1_ctl +add wave -noupdate /tb/dut/tx1_d +add wave -noupdate -divider {MAC 0 RX} +add wave -noupdate /tb/dut/mac_0/rx_clk +add wave -noupdate /tb/dut/mac_0/rx_sop +add wave -noupdate /tb/dut/mac_0/rx_ctl_m1 +add wave -noupdate /tb/dut/mac_0/rx_d_m1 +add wave -noupdate /tb/dut/mac_0/fcs_rx_init +add wave -noupdate /tb/dut/mac_0/fcs_rx_enable +add wave -noupdate /tb/dut/mac_0/fcs_rx_addr +add wave -noupdate /tb/dut/mac_0/fcs_rx_addr_e +add wave -noupdate /tb/dut/mac_0/fcs_rx_din +add wave -noupdate /tb/dut/mac_0/fcs_rx_dout +add wave -noupdate /tb/dut/mac_0/fcs_rx_error +add wave -noupdate /tb/dut/mac_0/rx_state +add wave -noupdate -radix unsigned /tb/dut/mac_0/rx_byte_cnt +add wave -noupdate -radix unsigned /tb/dut/mac_0/rx_pkt_length +add wave -noupdate /tb/dut/mac_0/rx_l3_proto +add wave -noupdate /tb/dut/mac_0/rx_packet_complete +add wave -noupdate /tb/dut/mac_0/rx_wr_done +add wave -noupdate /tb/dut/mac_0/rx_keep +add wave -noupdate /tb/dut/mac_0/rx_ctl +add wave -noupdate /tb/dut/mac_0/rx_d +add wave -noupdate /tb/dut/mac_0/rx_ctl_m1 +add wave -noupdate /tb/dut/mac_0/rx_d_m1 +add wave -noupdate /tb/dut/mac_0/rx_line_up_cnt +add wave -noupdate /tb/dut/mac_0/phy_up +add wave -noupdate -divider {IP RX 0 U} +add wave -noupdate /tb/dut/ipv4_rx_c_0/clk +add wave -noupdate /tb/dut/ipv4_rx_c_0/rx_state +add wave -noupdate /tb/dut/ipv4_rx_c_0/pkt_complete +add wave -noupdate /tb/dut/ipv4_rx_c_0/pkt_start +add wave -noupdate /tb/dut/ipv4_rx_c_0/protocol +add wave -noupdate /tb/dut/ipv4_rx_c_0/rx_byte_cnt +add wave -noupdate /tb/dut/ipv4_rx_c_0/rx_data_m1 +add wave -noupdate /tb/dut/ipv4_rx_c_0/rx_data_m2 +add wave -noupdate /tb/dut/ipv4_rx_c_0/rx_data_m3 +add wave -noupdate /tb/dut/ipv4_rx_c_0/rx_data_m4 +add wave -noupdate -radix unsigned /tb/dut/ipv4_rx_c_0/rx_pkt_length +add wave -noupdate /tb/dut/ipv4_rx_c_0/ip_addr_match +add wave -noupdate -divider {UDP RX 0 U} +add wave -noupdate /tb/dut/udp_rx_c_0/rx_state +add wave -noupdate /tb/dut/udp_rx_c_0/pkt_complete +add wave -noupdate /tb/dut/udp_rx_c_0/pkt_start +add wave -noupdate /tb/dut/udp_rx_c_0/rx_byte_cnt +add wave -noupdate /tb/dut/udp_rx_c_0/rx_data_m1 +add wave -noupdate /tb/dut/udp_rx_c_0/rx_data_m2 +add wave -noupdate /tb/dut/udp_rx_c_0/rx_data_m3 +add wave -noupdate /tb/dut/udp_rx_c_0/rx_data_m4 +add wave -noupdate /tb/dut/udp_rx_c_0/udp_port_match +add wave -noupdate -divider {DROP FIFO 0 U} +add wave -noupdate /tb/dut/drop_fifo_0u/phy_up +add wave -noupdate /tb/dut/drop_fifo_0u/rx_clk +add wave -noupdate /tb/dut/drop_fifo_0u/passthrough +add wave -noupdate /tb/dut/drop_fifo_0u/enable +add wave -noupdate /tb/dut/drop_fifo_0u/keep +add wave -noupdate /tb/dut/drop_fifo_0u/kept +add wave -noupdate /tb/dut/drop_fifo_0u/we_in +add wave -noupdate /tb/dut/drop_fifo_0u/d_in +add wave -noupdate /tb/dut/drop_fifo_0u/wr_ptr0 +add wave -noupdate /tb/dut/drop_fifo_0u/wr_ptr1 +add wave -noupdate /tb/dut/drop_fifo_0u/wr_done +add wave -noupdate /tb/dut/drop_fifo_0u/wr_done_m1 +add wave -noupdate /tb/dut/drop_fifo_0u/wr_done_m2 +add wave -noupdate /tb/dut/drop_fifo_0u/wr_done_m3 +add wave -noupdate /tb/dut/drop_fifo_0u/rx_error +add wave -noupdate /tb/dut/drop_fifo_0u/rx_idle +add wave -noupdate /tb/dut/drop_fifo_0u/rx_idle_m1 +add wave -noupdate /tb/dut/drop_fifo_0u/rx_idle_m2 +add wave -noupdate /tb/dut/drop_fifo_0u/tx_clk +add wave -noupdate /tb/dut/drop_fifo_0u/we_out +add wave -noupdate /tb/dut/drop_fifo_0u/fifo_empty +add wave -noupdate /tb/dut/drop_fifo_0u/read_run +add wave -noupdate /tb/dut/drop_fifo_0u/read_run_m1 +add wave -noupdate /tb/dut/drop_fifo_0u/read_run_m2 +add wave -noupdate /tb/dut/drop_fifo_0u/rd_ptr +add wave -noupdate /tb/dut/drop_fifo_0u/d_out_internal +add wave -noupdate /tb/dut/drop_fifo_0u/d_out +add wave -noupdate /tb/dut/drop_fifo_0u/active +add wave -noupdate /tb/dut/drop_fifo_0u/df_bytes +add wave -noupdate -divider {SYNC FIFO 0U} +add wave -noupdate /tb/dut/sync_fifo_rx_0u/reset_ptrs +add wave -noupdate /tb/dut/sync_fifo_rx_0u/active +add wave -noupdate /tb/dut/sync_fifo_rx_0u/almost_full +add wave -noupdate /tb/dut/sync_fifo_rx_0u/clk +add wave -noupdate /tb/dut/sync_fifo_rx_0u/we +add wave -noupdate /tb/dut/sync_fifo_rx_0u/wr_bytes_available +add wave -noupdate /tb/dut/sync_fifo_rx_0u/wr_ptr +add wave -noupdate /tb/dut/sync_fifo_rx_0u/d_in +add wave -noupdate /tb/dut/sync_fifo_rx_0u/empty +add wave -noupdate /tb/dut/sync_fifo_rx_0u/re +add wave -noupdate /tb/dut/sync_fifo_rx_0u/rd_ptr +add wave -noupdate /tb/dut/sync_fifo_rx_0u/d_out +add wave -noupdate -divider {SWITCH 0} +add wave -noupdate /tb/dut/switch_0/clk +add wave -noupdate /tb/dut/switch_0/phy_up +add wave -noupdate /tb/dut/switch_0/rx_d_01 +add wave -noupdate /tb/dut/switch_0/rx_d_0u +add wave -noupdate /tb/dut/switch_0/rx0_byte_cnt +add wave -noupdate /tb/dut/switch_0/rx_fifo_empty_0u +add wave -noupdate /tb/dut/switch_0/rx_fifo_empty_01 +add wave -noupdate /tb/dut/switch_0/rx_fifo_empty_u0 +add wave -noupdate /tb/dut/switch_0/rx_fifo_re_01 +add wave -noupdate /tb/dut/switch_0/rx_fifo_re_0u +add wave -noupdate {/tb/dut/switch_0/tx_f[0]} +add wave -noupdate {/tb/dut/switch_0/tx_fifo_empty[0]} +add wave -noupdate {/tb/dut/switch_0/tx_f[1]} +add wave -noupdate {/tb/dut/switch_0/tx_fifo_empty[1]} +add wave -noupdate /tb/dut/switch_0/tx_mode0 +add wave -noupdate /tb/dut/switch_0/tx0_byte_cnt +add wave -noupdate /tb/dut/switch_0/tx0_src_sel +add wave -noupdate -divider {Half FIFO} +add wave -noupdate /tb/dut/micro_fifo_0/dpram_addr +add wave -noupdate /tb/dut/micro_fifo_0/dpram_din +add wave -noupdate /tb/dut/micro_fifo_0/dpram_dout +add wave -noupdate /tb/dut/micro_fifo_0/dpram_oe +add wave -noupdate /tb/dut/micro_fifo_0/dpram_ptrs_sel +add wave -noupdate /tb/dut/micro_fifo_0/dpram_rx_dout +add wave -noupdate /tb/dut/micro_fifo_0/dpram_rx_sel +add wave -noupdate /tb/dut/micro_fifo_0/dpram_tx_dout +add wave -noupdate /tb/dut/micro_fifo_0/dpram_tx_sel +add wave -noupdate /tb/dut/micro_fifo_0/dpram_we +add wave -noupdate /tb/dut/micro_fifo_0/fifo_clk +add wave -noupdate /tb/dut/micro_fifo_0/fifo_d_out +add wave -noupdate /tb/dut/micro_fifo_0/fifo_re +add wave -noupdate /tb/dut/micro_fifo_0/fifo_we +add wave -noupdate /tb/dut/micro_fifo_0/fifo_we_m1 +add wave -noupdate /tb/dut/micro_fifo_0/reset_ptrs +add wave -noupdate /tb/dut/micro_fifo_0/rx_wr_ptr +add wave -noupdate /tb/dut/micro_fifo_0/rx_wr_ptr_latched +add wave -noupdate /tb/dut/micro_fifo_0/fifo_d_in +add wave -noupdate /tb/dut/micro_fifo_0/tx_rd_ptr +add wave -noupdate /tb/dut/micro_fifo_0/tx_wr_ptr +add wave -noupdate /tb/dut/micro_fifo_0/tx_wr_ptr_latched +add wave -noupdate /tb/dut/micro_fifo_0/uc_clk +add wave -noupdate -divider Controller +add wave -noupdate /tb/dut/controller_0/clk +add wave -noupdate /tb/dut/controller_0/rx_fifo_int +add wave -noupdate /tb/dut/controller_0/rx_fifo_int_m1 +add wave -noupdate /tb/dut/controller_0/rx_fifo_int_m2 +add wave -noupdate /tb/dut/controller_0/rx_fifo_int_acked +add wave -noupdate /tb/dut/controller_0/tx_fifo_empty +add wave -noupdate /tb/dut/controller_0/mac_sel +add wave -noupdate /tb/dut/controller_0/mac_addr +add wave -noupdate /tb/dut/controller_0/pkt_filter_addr +add wave -noupdate /tb/dut/controller_0/pkt_filter_sel +add wave -noupdate /tb/dut/controller_0/hf_ptrs_sel +add wave -noupdate /tb/dut/controller_0/hf_rx_sel +add wave -noupdate /tb/dut/controller_0/hf_tx_sel +add wave -noupdate -color Yellow /tb/dut/controller_0/rx_msg_captured +add wave -noupdate /tb/dut/controller_0/rx_msg_cnt +add wave -noupdate /tb/dut/controller_0/rx_rd_active +add wave -noupdate /tb/dut/controller_0/rx_wr_ptr +add wave -noupdate /tb/dut/controller_0/rx_rd_ptr +add wave -noupdate -color gold /tb/dut/controller_0/cont_state +add wave -noupdate /tb/dut/controller_0/cont_msg +add wave -noupdate /tb/dut/controller_0/msg_type +add wave -noupdate /tb/dut/controller_0/msg_token +add wave -noupdate /tb/dut/controller_0/msg_addr +add wave -noupdate /tb/dut/controller_0/msg_addr_valid +add wave -noupdate /tb/dut/controller_0/msg_addr_ro +add wave -noupdate /tb/dut/controller_0/msg_data +add wave -noupdate /tb/dut/controller_0/msg_error +add wave -noupdate /tb/dut/controller_0/msg_response +add wave -noupdate /tb/dut/controller_0/clk +add wave -noupdate /tb/dut/controller_0/mem_cmd +add wave -noupdate /tb/dut/controller_0/mem_tgt_ready +add wave -noupdate /tb/dut/controller_0/mem_oe +add wave -noupdate -color Gold /tb/dut/controller_0/mem_state +add wave -noupdate /tb/dut/controller_0/mem_we +add wave -noupdate /tb/dut/controller_0/mem_addr +add wave -noupdate /tb/dut/controller_0/mem_d_o +add wave -noupdate /tb/dut/controller_0/mem_d_i +add wave -noupdate /tb/dut/controller_0/rx_cnt +add wave -noupdate /tb/dut/controller_0/tx_cnt +add wave -noupdate /tb/dut/controller_0/tx_wr_active +add wave -noupdate /tb/dut/controller_0/tx_wr_ptr +add wave -noupdate -divider {PKT FILTER 01} +add wave -noupdate /tb/dut/pkt_filter_01/clk +add wave -noupdate /tb/dut/pkt_filter_01/addr +add wave -noupdate /tb/dut/pkt_filter_01/block +add wave -noupdate /tb/dut/pkt_filter_01/d_i +add wave -noupdate /tb/dut/pkt_filter_01/d_o +add wave -noupdate /tb/dut/pkt_filter_01/DATAW +add wave -noupdate /tb/dut/pkt_filter_01/DEPTH +add wave -noupdate /tb/dut/pkt_filter_01/invert +add wave -noupdate /tb/dut/pkt_filter_01/keep +add wave -noupdate /tb/dut/pkt_filter_01/match +add wave -noupdate /tb/dut/pkt_filter_01/new_frame +add wave -noupdate /tb/dut/pkt_filter_01/prgclk +add wave -noupdate /tb/dut/pkt_filter_01/rx_d_m1 +add wave -noupdate /tb/dut/pkt_filter_01/rx_d_m2 +add wave -noupdate /tb/dut/pkt_filter_01/rx_d_m3 +add wave -noupdate /tb/dut/pkt_filter_01/rx_d_m4 +add wave -noupdate /tb/dut/pkt_filter_01/sel +add wave -noupdate /tb/dut/pkt_filter_01/trigger +add wave -noupdate /tb/dut/pkt_filter_01/trigger_m1 +add wave -noupdate /tb/dut/pkt_filter_01/we +add wave -noupdate /tb/dut/pkt_filter_01/cam_0/clk +add wave -noupdate /tb/dut/pkt_filter_01/cam_0/prgclk +add wave -noupdate /tb/dut/pkt_filter_01/cam_0/addr +add wave -noupdate /tb/dut/pkt_filter_01/cam_0/we +add wave -noupdate /tb/dut/pkt_filter_01/cam_0/d_i +add wave -noupdate /tb/dut/pkt_filter_01/cam_0/content +add wave -noupdate /tb/dut/pkt_filter_01/cam_0/d_o +add wave -noupdate /tb/dut/pkt_filter_01/cam_0/DATAW +add wave -noupdate /tb/dut/pkt_filter_01/cam_0/DEPTH +add wave -noupdate /tb/dut/pkt_filter_01/cam_0/i +add wave -noupdate /tb/dut/pkt_filter_01/cam_0/j +add wave -noupdate /tb/dut/pkt_filter_01/cam_0/match +add wave -noupdate /tb/dut/pkt_filter_01/cam_0/search +add wave -noupdate /tb/dut/pkt_filter_01/cam_0/search_address +add wave -noupdate /tb/dut/pkt_filter_01/cam_0/sel +add wave -noupdate /tb/dut/pkt_filter_01/cam_0/valid +add wave -noupdate -divider {IPV4 TX C} +add wave -noupdate /tb/dut/ipv4_tx_c_0/clk +add wave -noupdate /tb/dut/ipv4_tx_c_0/rstn +add wave -noupdate /tb/dut/ipv4_tx_c_0/phy_up +add wave -noupdate /tb/dut/ipv4_tx_c_0/tx_mode +add wave -noupdate /tb/dut/ipv4_tx_c_0/tx_src_sel +add wave -noupdate /tb/dut/ipv4_tx_c_0/byte_cnt_i +add wave -noupdate -radix decimal /tb/dut/ipv4_tx_c_0/tx_cnt +add wave -noupdate /tb/dut/ipv4_tx_c_0/ipv4_cksum +add wave -noupdate {/tb/dut/ipv4_tx_c_0/gpio[1]} +add wave -noupdate {/tb/dut/ipv4_tx_c_0/gpio[0]} +add wave -noupdate /tb/dut/ipv4_tx_c_0/fifo_re_i +add wave -noupdate /tb/dut/ipv4_tx_c_0/fifo_empty_o +add wave -noupdate /tb/dut/ipv4_tx_c_0/fifo_d_o +add wave -noupdate -divider {MAC Cont I/F} +add wave -noupdate /tb/dut/mac_0/cont_addr +add wave -noupdate /tb/dut/mac_0/cont_clk +add wave -noupdate /tb/dut/mac_0/cont_d_i +add wave -noupdate /tb/dut/mac_0/cont_d_o +add wave -noupdate /tb/dut/mac_0/cont_sel +add wave -noupdate /tb/dut/mac_0/cont_we +add wave -noupdate /tb/dut/mac_0/tx_pkt_cnt +add wave -noupdate /tb/dut/mac_0/rx_pkt_cnt +add wave -noupdate -divider {MAC 0 TX} +add wave -noupdate /tb/dut/mac_0/tx_byte_cnt_i +add wave -noupdate /tb/dut/mac_0/dpr_ad +add wave -noupdate /tb/dut/mac_0/dpr_ce +add wave -noupdate /tb/dut/mac_0/dpr_di +add wave -noupdate /tb/dut/mac_0/dpr_di_reg +add wave -noupdate /tb/dut/mac_0/dpr_di_reg_m1 +add wave -noupdate /tb/dut/mac_0/tx_alt_fifo_empty +add wave -noupdate /tb/dut/mac_0/tx_alt_fifo_d +add wave -noupdate /tb/dut/mac_0/tx_fifo_d +add wave -noupdate /tb/dut/mac_0/tx_fifo_d_m1 +add wave -noupdate /tb/dut/mac_0/tx_fifo_d_m2 +add wave -noupdate /tb/dut/mac_0/tx_ctl_pkt +add wave -noupdate /tb/dut/mac_0/tx_data_pkt +add wave -noupdate /tb/dut/mac_0/fcs_tx_dout +add wave -noupdate /tb/dut/mac_0/dpr_do +add wave -noupdate /tb/dut/mac_0/dpr_we +add wave -noupdate /tb/dut/mac_0/tx_sample +add wave -noupdate /tb/dut/mac_0/tx_sample_re +add wave -noupdate /tb/dut/mac_0/tx_active +add wave -noupdate /tb/dut/mac_0/tx_clk +add wave -noupdate /tb/dut/mac_0/tx_src_sel +add wave -noupdate /tb/dut/mac_0/tx_mode +add wave -noupdate /tb/dut/mac_0/tx_state +add wave -noupdate /tb/dut/mac_0/tx_fifo_re +add wave -noupdate /tb/dut/mac_0/tx_last_byte +add wave -noupdate /tb/dut/mac_0/tx_finished +add wave -noupdate /tb/dut/mac_0/tx_fifo_empty +add wave -noupdate /tb/dut/mac_0/tx_f_pkt +add wave -noupdate /tb/dut/mac_0/tx_sop +add wave -noupdate /tb/dut/mac_0/tx_eop +add wave -noupdate /tb/dut/mac_0/tx_clk +add wave -noupdate /tb/dut/mac_0/tx_f +add wave -noupdate /tb/dut/mac_0/tx_ctl +add wave -noupdate /tb/dut/mac_0/tx_d +add wave -noupdate /tb/dut/mac_0/tx_state +add wave -noupdate /tb/dut/phy0_tx_clk +add wave -noupdate /tb/dut/phy0_tx_ctl +add wave -noupdate /tb/dut/phy0_tx_d +add wave -noupdate /tb/dut/mac_0/tx_ctl_idle +add wave -noupdate /tb/dut/mac_0/tx_d_idle +add wave -noupdate /tb/dut/mac_0/fcs_tx_init +add wave -noupdate /tb/dut/mac_0/fcs_tx_enable +add wave -noupdate /tb/dut/mac_0/fcs_tx_dout +add wave -noupdate /tb/dut/mac_0/fcs_tx_addr +add wave -noupdate /tb/dut/mac_0/fcs_tx_addr_e +add wave -noupdate /tb/dut/mac_0/fcs_tx_din +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {4535401 ps} 0} +quietly wave cursor active 1 +configure wave -namecolwidth 257 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ps +update +WaveRestoreZoom {4476359 ps} {4592044 ps} diff --git a/manufacturer/altera/cyclone10_lp/sim/wav/wave_cont_fcs.do b/manufacturer/altera/cyclone10_lp/sim/wav/wave_cont_fcs.do new file mode 100644 index 0000000..c08d61c --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/sim/wav/wave_cont_fcs.do @@ -0,0 +1,325 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /tb/rstn +add wave -noupdate /tb/clk_125 +add wave -noupdate /tb/pclk +add wave -noupdate /tb/clk_25 +add wave -noupdate /tb/clk_phy +add wave -noupdate /tb/clk_phyx2 +add wave -noupdate /tb/rx_cnt +add wave -noupdate /tb/phy0_rx_clk +add wave -noupdate /tb/phy0_rx_ctl +add wave -noupdate /tb/phy0_rx_d +add wave -noupdate /tb/phy1_rx_clk +add wave -noupdate /tb/phy1_rx_ctl +add wave -noupdate /tb/phy1_rx_d +add wave -noupdate /tb/phy2_rx_clk +add wave -noupdate /tb/phy2_rx_ctl +add wave -noupdate /tb/phy2_rx_d +add wave -noupdate /tb/phy0_mdc +add wave -noupdate /tb/phy0_mdio +add wave -noupdate /tb/phy0_resetn +add wave -noupdate /tb/phy0_intn +add wave -noupdate /tb/phy1_mdc +add wave -noupdate /tb/phy1_mdio +add wave -noupdate /tb/phy1_resetn +add wave -noupdate /tb/phy1_intn +add wave -noupdate /tb/phy_up +add wave -noupdate /tb/word_sync_active +add wave -noupdate /tb/rx_cnt +add wave -noupdate /tb/rx0_f +add wave -noupdate /tb/rx0_f_reg +add wave -noupdate /tb/rx0_data_cnt +add wave -noupdate /tb/rx0_data_interval +add wave -noupdate /tb/rx0_d +add wave -noupdate /tb/rx1_d +add wave -noupdate /tb/rx2_d +add wave -noupdate /tb/rx0_packets +add wave -noupdate /tb/rx0_packet_active +add wave -noupdate /tb/rx1_data_cnt +add wave -noupdate /tb/rx1 +add wave -noupdate /tb/rx2_data_cnt +add wave -noupdate /tb/phy0_tx_clk +add wave -noupdate /tb/phy0_tx_ctl +add wave -noupdate /tb/phy0_tx_d +add wave -noupdate /tb/phy1_tx_clk +add wave -noupdate /tb/phy1_tx_ctl +add wave -noupdate /tb/phy1_tx_d +add wave -noupdate /tb/phy2_tx_clk +add wave -noupdate /tb/phy2_tx_ctl +add wave -noupdate /tb/phy2_tx_d +add wave -noupdate -divider Top +add wave -noupdate /tb/dut/rstn +add wave -noupdate /tb/dut/sys_rstn +add wave -noupdate /tb/dut/clk_i +add wave -noupdate /tb/dut/pll_locked +add wave -noupdate /tb/clk_25 +add wave -noupdate /tb/clk_125 +add wave -noupdate /tb/dut/phy0_clk +add wave -noupdate /tb/dut/phy1_clk +add wave -noupdate /tb/dut/cont_clk +add wave -noupdate /tb/dut/sys_rstn +add wave -noupdate /tb/dut/phy_resetn +add wave -noupdate /tb/dut/phy0_rstn +add wave -noupdate /tb/dut/phy1_rstn +add wave -noupdate /tb/rx_cnt +add wave -noupdate /tb/clk_phy +add wave -noupdate /tb/clk_phyx2 +add wave -noupdate {/tb/dut/phy_up[0]} +add wave -noupdate /tb/phy0_rx_clk +add wave -noupdate /tb/dut/rgmi_rx_0/datain +add wave -noupdate /tb/dut/rgmi_rx_0/inclock +add wave -noupdate /tb/dut/rgmi_rx_0/dataout_h +add wave -noupdate /tb/dut/rgmi_rx_0/dataout_l +add wave -noupdate /tb/dut/rx0_ctl_m1 +add wave -noupdate /tb/dut/rx0_d_m1 +add wave -noupdate /tb/dut/rx0_ctl_m2 +add wave -noupdate /tb/dut/rx0_d_m2 +add wave -noupdate /tb/dut/tx0_ctl +add wave -noupdate /tb/dut/tx0_d +add wave -noupdate /tb/dut/tx1_ctl +add wave -noupdate /tb/dut/tx1_d +add wave -noupdate -divider {SWITCH 0} +add wave -noupdate /tb/dut/switch_0/clk +add wave -noupdate /tb/dut/switch_0/phy_up +add wave -noupdate /tb/dut/switch_0/rx_d_01 +add wave -noupdate /tb/dut/switch_0/rx_d_0u +add wave -noupdate /tb/dut/switch_0/rx0_byte_cnt +add wave -noupdate /tb/dut/switch_0/rx_fifo_empty_0u +add wave -noupdate /tb/dut/switch_0/rx_fifo_empty_01 +add wave -noupdate /tb/dut/switch_0/rx_fifo_empty_u0 +add wave -noupdate /tb/dut/switch_0/rx_fifo_re_01 +add wave -noupdate /tb/dut/switch_0/rx_fifo_re_0u +add wave -noupdate {/tb/dut/switch_0/tx_f[0]} +add wave -noupdate {/tb/dut/switch_0/tx_fifo_empty[0]} +add wave -noupdate {/tb/dut/switch_0/tx_f[1]} +add wave -noupdate {/tb/dut/switch_0/tx_fifo_empty[1]} +add wave -noupdate /tb/dut/switch_0/tx_mode0 +add wave -noupdate /tb/dut/switch_0/tx0_byte_cnt +add wave -noupdate /tb/dut/switch_0/tx0_src_sel +add wave -noupdate -divider {MAC 0 FCS RX} +add wave -noupdate /tb/dut/fcs_rx_0/clk +add wave -noupdate /tb/dut/fcs_rx_0/init +add wave -noupdate /tb/dut/fcs_rx_0/enable +add wave -noupdate /tb/dut/fcs_rx_0/addr +add wave -noupdate /tb/dut/mac_0/rx_d_m1 +add wave -noupdate /tb/dut/fcs_rx_0/din +add wave -noupdate /tb/dut/fcs_rx_0/dout +add wave -noupdate /tb/dut/fcs_rx_0/d +add wave -noupdate /tb/dut/fcs_rx_0/crc +add wave -noupdate -divider {MAC 0} +add wave -noupdate /tb/dut/mac_0/rx_clk +add wave -noupdate /tb/dut/mac_0/rx_sop +add wave -noupdate /tb/dut/mac_0/rx_d_m1 +add wave -noupdate /tb/dut/mac_0/fcs_rx_init +add wave -noupdate /tb/dut/mac_0/fcs_rx_enable +add wave -noupdate /tb/dut/mac_0/fcs_rx_addr +add wave -noupdate /tb/dut/mac_0/fcs_rx_addr_e +add wave -noupdate /tb/dut/mac_0/fcs_rx_din +add wave -noupdate /tb/dut/mac_0/fcs_rx_dout +add wave -noupdate /tb/dut/mac_0/fcs_rx_error +add wave -noupdate /tb/dut/mac_0/rx_state +add wave -noupdate -radix unsigned /tb/dut/mac_0/rx_byte_cnt +add wave -noupdate -radix unsigned /tb/dut/mac_0/rx_pkt_length +add wave -noupdate /tb/dut/mac_0/rx_l3_proto +add wave -noupdate /tb/dut/mac_0/rx_packet_complete +add wave -noupdate /tb/dut/mac_0/rx_wr_done +add wave -noupdate /tb/dut/mac_0/rx_keep +add wave -noupdate /tb/dut/mac_0/rx_ctl +add wave -noupdate /tb/dut/mac_0/rx_d +add wave -noupdate /tb/dut/mac_0/rx_ctl_m1 +add wave -noupdate /tb/dut/mac_0/rx_d_m1 +add wave -noupdate /tb/dut/mac_0/rx_line_up_cnt +add wave -noupdate /tb/dut/mac_0/phy_up +add wave -noupdate /tb/dut/mac_0/dpr_ad +add wave -noupdate /tb/dut/mac_0/dpr_ce +add wave -noupdate /tb/dut/mac_0/dpr_di +add wave -noupdate /tb/dut/mac_0/dpr_di_reg +add wave -noupdate /tb/dut/mac_0/dpr_do +add wave -noupdate /tb/dut/mac_0/dpr_we +add wave -noupdate /tb/dut/mac_0/tx_sample +add wave -noupdate /tb/dut/mac_0/tx_sample_re +add wave -noupdate /tb/dut/mac_0/tx_active +add wave -noupdate /tb/dut/mac_0/tx_byte_cnt +add wave -noupdate /tb/dut/mac_0/tx_byte_cnt_i +add wave -noupdate /tb/dut/mac_0/tx_clk +add wave -noupdate /tb/dut/mac_0/tx_src_sel +add wave -noupdate /tb/dut/mac_0/tx_mode +add wave -noupdate /tb/dut/mac_0/tx_state +add wave -noupdate /tb/dut/mac_0/tx_fifo_re +add wave -noupdate /tb/dut/mac_0/tx_last_byte +add wave -noupdate /tb/dut/mac_0/tx_finished +add wave -noupdate /tb/dut/mac_0/tx_fifo_d +add wave -noupdate /tb/dut/mac_0/tx_fifo_d_m1 +add wave -noupdate /tb/dut/mac_0/tx_fifo_empty +add wave -noupdate /tb/dut/mac_0/tx_f_pkt +add wave -noupdate /tb/dut/mac_0/tx_sop +add wave -noupdate /tb/dut/mac_0/tx_eop +add wave -noupdate /tb/dut/mac_0/tx_clk +add wave -noupdate /tb/dut/mac_0/tx_ctl +add wave -noupdate /tb/dut/mac_0/tx_d +add wave -noupdate /tb/dut/mac_0/tx_f +add wave -noupdate /tb/dut/mac_0/tx_ipv4_cksum +add wave -noupdate /tb/dut/mac_0/tx_ipv4_length +add wave -noupdate /tb/dut/phy0_tx_clk +add wave -noupdate /tb/dut/phy0_tx_ctl +add wave -noupdate /tb/dut/phy0_tx_d +add wave -noupdate /tb/dut/mac_0/tx_ctl_idle +add wave -noupdate /tb/dut/mac_0/tx_d_idle +add wave -noupdate /tb/dut/mac_0/tx_ctl_pkt +add wave -noupdate /tb/dut/mac_0/tx_data_pkt +add wave -noupdate /tb/dut/mac_0/fcs_tx_init +add wave -noupdate /tb/dut/mac_0/fcs_tx_enable +add wave -noupdate /tb/dut/mac_0/fcs_tx_dout +add wave -noupdate /tb/dut/mac_0/fcs_tx_addr +add wave -noupdate /tb/dut/mac_0/fcs_tx_addr_e +add wave -noupdate /tb/dut/mac_0/fcs_tx_din +add wave -noupdate -divider {IP RX 0 U} +add wave -noupdate /tb/dut/ipv4_rx_c_0/clk +add wave -noupdate /tb/dut/ipv4_rx_c_0/rx_state +add wave -noupdate /tb/dut/ipv4_rx_c_0/pkt_complete +add wave -noupdate /tb/dut/ipv4_rx_c_0/pkt_start +add wave -noupdate /tb/dut/ipv4_rx_c_0/protocol +add wave -noupdate /tb/dut/ipv4_rx_c_0/rx_byte_cnt +add wave -noupdate /tb/dut/ipv4_rx_c_0/rx_data_m1 +add wave -noupdate /tb/dut/ipv4_rx_c_0/rx_data_m2 +add wave -noupdate /tb/dut/ipv4_rx_c_0/rx_data_m3 +add wave -noupdate /tb/dut/ipv4_rx_c_0/rx_data_m4 +add wave -noupdate -radix unsigned /tb/dut/ipv4_rx_c_0/rx_pkt_length +add wave -noupdate -divider {UDP RX 0 U} +add wave -noupdate /tb/dut/udp_rx_c_0/rx_state +add wave -noupdate /tb/dut/udp_rx_c_0/pkt_complete +add wave -noupdate /tb/dut/udp_rx_c_0/pkt_start +add wave -noupdate /tb/dut/udp_rx_c_0/rx_byte_cnt +add wave -noupdate /tb/dut/udp_rx_c_0/rx_data_m1 +add wave -noupdate /tb/dut/udp_rx_c_0/rx_data_m2 +add wave -noupdate /tb/dut/udp_rx_c_0/rx_data_m3 +add wave -noupdate /tb/dut/udp_rx_c_0/rx_data_m4 +add wave -noupdate -divider {DROP FIFO 0 U} +add wave -noupdate /tb/dut/drop_fifo_0u/phy_up +add wave -noupdate /tb/dut/drop_fifo_0u/active +add wave -noupdate /tb/dut/drop_fifo_0u/passthrough +add wave -noupdate /tb/dut/drop_fifo_0u/enable +add wave -noupdate /tb/dut/drop_fifo_0u/keep +add wave -noupdate /tb/dut/drop_fifo_0u/kept +add wave -noupdate /tb/dut/drop_fifo_0u/df_bytes +add wave -noupdate /tb/dut/drop_fifo_0u/rx_clk +add wave -noupdate /tb/dut/drop_fifo_0u/we_in +add wave -noupdate /tb/dut/drop_fifo_0u/wr_done +add wave -noupdate /tb/dut/drop_fifo_0u/wr_done_m1 +add wave -noupdate /tb/dut/drop_fifo_0u/wr_done_m2 +add wave -noupdate /tb/dut/drop_fifo_0u/wr_ptr0 +add wave -noupdate /tb/dut/drop_fifo_0u/wr_ptr1 +add wave -noupdate /tb/dut/drop_fifo_0u/d_in +add wave -noupdate /tb/dut/drop_fifo_0u/tx_clk +add wave -noupdate /tb/dut/drop_fifo_0u/we_out +add wave -noupdate /tb/dut/drop_fifo_0u/fifo_empty +add wave -noupdate /tb/dut/drop_fifo_0u/read_run +add wave -noupdate /tb/dut/drop_fifo_0u/read_run_m1 +add wave -noupdate /tb/dut/drop_fifo_0u/read_run_m2 +add wave -noupdate /tb/dut/drop_fifo_0u/rd_ptr +add wave -noupdate /tb/dut/drop_fifo_0u/d_out_internal +add wave -noupdate /tb/dut/drop_fifo_0u/d_out +add wave -noupdate -divider {SYNC FIFO 0U} +add wave -noupdate /tb/dut/sync_fifo_rx_0u/active +add wave -noupdate /tb/dut/sync_fifo_rx_0u/almost_full +add wave -noupdate /tb/dut/sync_fifo_rx_0u/clk +add wave -noupdate /tb/dut/sync_fifo_rx_0u/we +add wave -noupdate /tb/dut/sync_fifo_rx_0u/wr_bytes_available +add wave -noupdate /tb/dut/sync_fifo_rx_0u/wr_ptr +add wave -noupdate /tb/dut/sync_fifo_rx_0u/d_in +add wave -noupdate /tb/dut/sync_fifo_rx_0u/d_out +add wave -noupdate /tb/dut/sync_fifo_rx_0u/empty +add wave -noupdate /tb/dut/sync_fifo_rx_0u/rd_ptr +add wave -noupdate /tb/dut/sync_fifo_rx_0u/re +add wave -noupdate /tb/dut/sync_fifo_rx_0u/reset_ptrs +add wave -noupdate -divider {Half FIFO} +add wave -noupdate /tb/dut/micro_fifo_0/dpram_addr +add wave -noupdate /tb/dut/micro_fifo_0/dpram_din +add wave -noupdate /tb/dut/micro_fifo_0/dpram_dout +add wave -noupdate /tb/dut/micro_fifo_0/dpram_oe +add wave -noupdate /tb/dut/micro_fifo_0/dpram_ptrs_sel +add wave -noupdate /tb/dut/micro_fifo_0/dpram_rx_dout +add wave -noupdate /tb/dut/micro_fifo_0/dpram_rx_enable +add wave -noupdate /tb/dut/micro_fifo_0/dpram_rx_sel +add wave -noupdate /tb/dut/micro_fifo_0/dpram_tx_dout +add wave -noupdate /tb/dut/micro_fifo_0/dpram_tx_enable +add wave -noupdate /tb/dut/micro_fifo_0/dpram_tx_sel +add wave -noupdate /tb/dut/micro_fifo_0/dpram_we +add wave -noupdate /tb/dut/micro_fifo_0/fifo_clk +add wave -noupdate /tb/dut/micro_fifo_0/fifo_d_out +add wave -noupdate /tb/dut/micro_fifo_0/fifo_int +add wave -noupdate /tb/dut/micro_fifo_0/fifo_int_acked +add wave -noupdate /tb/dut/micro_fifo_0/fifo_re +add wave -noupdate /tb/dut/micro_fifo_0/fifo_we +add wave -noupdate /tb/dut/micro_fifo_0/fifo_we_m1 +add wave -noupdate /tb/dut/micro_fifo_0/reset_ptrs +add wave -noupdate /tb/dut/micro_fifo_0/rx_byte_cnt +add wave -noupdate /tb/dut/micro_fifo_0/rx_empty +add wave -noupdate /tb/dut/micro_fifo_0/rx_rd_ptr +add wave -noupdate /tb/dut/micro_fifo_0/rx_wr_ptr +add wave -noupdate /tb/dut/micro_fifo_0/tx_mode +add wave -noupdate /tb/dut/micro_fifo_0/tx_rd_ptr +add wave -noupdate /tb/dut/micro_fifo_0/tx_wr_ptr +add wave -noupdate /tb/dut/micro_fifo_0/tx_wr_ptr_latched +add wave -noupdate /tb/dut/micro_fifo_0/fifo_d_in +add wave -noupdate /tb/dut/micro_fifo_0/uc_clk +add wave -noupdate -divider Controller +add wave -noupdate /tb/dut/controller_0/clk +add wave -noupdate /tb/dut/controller_0/cont_state +add wave -noupdate /tb/dut/controller_0/cmd_ack +add wave -noupdate /tb/dut/controller_0/cmd_addr +add wave -noupdate /tb/dut/controller_0/cmd_addr_ro +add wave -noupdate /tb/dut/controller_0/cmd_addr_valid +add wave -noupdate /tb/dut/controller_0/cmd_data +add wave -noupdate /tb/dut/controller_0/cmd_error +add wave -noupdate /tb/dut/controller_0/cmd_id +add wave -noupdate /tb/dut/controller_0/cmd_response +add wave -noupdate /tb/dut/controller_0/cmd_size +add wave -noupdate /tb/dut/controller_0/cmd_type +add wave -noupdate /tb/dut/controller_0/hf_ptrs_sel +add wave -noupdate /tb/dut/controller_0/hf_rx_sel +add wave -noupdate /tb/dut/controller_0/hf_tx_sel +add wave -noupdate /tb/dut/controller_0/hf_ptrs_sel +add wave -noupdate /tb/dut/controller_0/hf_rx_sel +add wave -noupdate /tb/dut/controller_0/hf_tx_sel +add wave -noupdate /tb/dut/controller_0/mdio_we +add wave -noupdate /tb/dut/controller_0/mem_addr +add wave -noupdate /tb/dut/controller_0/mem_d_i +add wave -noupdate /tb/dut/controller_0/mem_d_o +add wave -noupdate /tb/dut/controller_0/mem_state +add wave -noupdate /tb/dut/controller_0/mem_we +add wave -noupdate /tb/dut/controller_0/mem_oe +add wave -noupdate /tb/dut/controller_0/rx_cmd +add wave -noupdate /tb/dut/controller_0/rx_cnt +add wave -noupdate /tb/dut/controller_0/rx_fifo_int +add wave -noupdate /tb/dut/controller_0/rx_fifo_int_acked +add wave -noupdate /tb/dut/controller_0/rx_fifo_int_m1 +add wave -noupdate /tb/dut/controller_0/rx_fifo_int_m2 +add wave -noupdate /tb/dut/controller_0/rx_rd_active +add wave -noupdate /tb/dut/controller_0/rx_wr_ptr +add wave -noupdate /tb/dut/controller_0/rx_rd_ptr +add wave -noupdate /tb/dut/controller_0/tx_cnt +add wave -noupdate /tb/dut/controller_0/tx_fifo_empty +add wave -noupdate /tb/dut/controller_0/tx_pkt_cnt +add wave -noupdate /tb/dut/controller_0/tx_wr_active +add wave -noupdate /tb/dut/controller_0/tx_wr_ptr +add wave -noupdate /tb/dut/controller_0/mem_event_handling +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {1606000 ps} 0} +quietly wave cursor active 1 +configure wave -namecolwidth 199 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ps +update +WaveRestoreZoom {0 ps} {5250 ns} diff --git a/manufacturer/altera/cyclone10_lp/sim/wav/wave_etoe.do b/manufacturer/altera/cyclone10_lp/sim/wav/wave_etoe.do new file mode 100644 index 0000000..7459b26 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/sim/wav/wave_etoe.do @@ -0,0 +1,152 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /tb/rstn +add wave -noupdate /tb/clk_125 +add wave -noupdate /tb/clk_25 +add wave -noupdate /tb/clk_phy +add wave -noupdate /tb/clk_phyx2 +add wave -noupdate /tb/pll_lock +add wave -noupdate /tb/phy_up +add wave -noupdate /tb/pclk +add wave -noupdate -radix unsigned /tb/rx0_data_cnt +add wave -noupdate /tb/rx0_last_byte +add wave -noupdate /tb/rx0_idle_cnt +add wave -noupdate -radix hexadecimal /tb/rx_clk_cnt +add wave -noupdate /tb/phy0_tx_clk +add wave -noupdate /tb/phy0_tx_ctl +add wave -noupdate /tb/phy0_tx_d +add wave -noupdate /tb/phy0_rx_clk +add wave -noupdate /tb/phy0_rx_ctl +add wave -noupdate /tb/phy0_rx_d +add wave -noupdate /tb/phy1_rx_clk +add wave -noupdate /tb/phy1_rx_ctl +add wave -noupdate /tb/phy1_rx_d +add wave -noupdate /tb/phy1_tx_clk +add wave -noupdate /tb/phy1_tx_ctl +add wave -noupdate /tb/phy1_tx_d +add wave -noupdate -divider Top +add wave -noupdate /tb/dut/rstn +add wave -noupdate /tb/dut/sys_rstn +add wave -noupdate /tb/dut/clk_i +add wave -noupdate /tb/dut/pll_locked +add wave -noupdate /tb/clk_25 +add wave -noupdate /tb/clk_125 +add wave -noupdate /tb/dut/phy0_clk +add wave -noupdate /tb/dut/phy1_clk +add wave -noupdate {/tb/dut/phy_up[0]} +add wave -noupdate -divider {MAC 0} +add wave -noupdate /tb/dut/mac_0/rx_ctl +add wave -noupdate /tb/dut/mac_0/rx_d +add wave -noupdate /tb/dut/mac_0/tx_ctl +add wave -noupdate /tb/dut/mac_0/tx_d +add wave -noupdate -divider {MAC 1} +add wave -noupdate /tb/dut/mac_1/rx_ctl +add wave -noupdate /tb/dut/mac_1/rx_d +add wave -noupdate /tb/dut/mac_1/tx_ctl +add wave -noupdate /tb/dut/mac_1/tx_d +add wave -noupdate -divider {MAC 2} +add wave -noupdate /tb/dut/mac_2/rx_ctl +add wave -noupdate /tb/dut/mac_2/rx_d +add wave -noupdate /tb/dut/mac_2/tx_ctl +add wave -noupdate /tb/dut/mac_2/tx_d +add wave -noupdate -divider {SWITCH 0} +add wave -noupdate /tb/dut/switch_0/clk +add wave -noupdate /tb/dut/switch_0/phy_up +add wave -noupdate /tb/dut/switch_0/rx_d_01 +add wave -noupdate /tb/dut/switch_0/rx_d_0u +add wave -noupdate /tb/dut/switch_0/rx0_byte_cnt +add wave -noupdate /tb/dut/switch_0/rx_fifo_empty_0u +add wave -noupdate /tb/dut/switch_0/rx_fifo_empty_01 +add wave -noupdate /tb/dut/switch_0/rx_fifo_empty_u0 +add wave -noupdate /tb/dut/switch_0/rx_fifo_re_01 +add wave -noupdate /tb/dut/switch_0/rx_fifo_re_0u +add wave -noupdate {/tb/dut/switch_0/tx_f[0]} +add wave -noupdate {/tb/dut/switch_0/tx_fifo_empty[0]} +add wave -noupdate {/tb/dut/switch_0/tx_f[1]} +add wave -noupdate {/tb/dut/switch_0/tx_fifo_empty[1]} +add wave -noupdate /tb/dut/switch_0/tx_mode0 +add wave -noupdate /tb/dut/switch_0/tx0_byte_cnt +add wave -noupdate /tb/dut/switch_0/tx0_src_sel +add wave -noupdate -divider {MAC 0} +add wave -noupdate /tb/dut/mac_0/rx_clk +add wave -noupdate /tb/dut/mac_0/rx_sop +add wave -noupdate /tb/dut/mac_0/rx_ctl_m1 +add wave -noupdate /tb/dut/mac_0/rx_d_m1 +add wave -noupdate /tb/dut/mac_0/fcs_rx_init +add wave -noupdate /tb/dut/mac_0/fcs_rx_enable +add wave -noupdate /tb/dut/mac_0/fcs_rx_addr +add wave -noupdate /tb/dut/mac_0/fcs_rx_addr_e +add wave -noupdate /tb/dut/mac_0/fcs_rx_din +add wave -noupdate /tb/dut/mac_0/fcs_rx_dout +add wave -noupdate /tb/dut/mac_0/fcs_rx_error +add wave -noupdate /tb/dut/mac_0/rx_state +add wave -noupdate -radix unsigned /tb/dut/mac_0/rx_byte_cnt +add wave -noupdate -radix unsigned /tb/dut/mac_0/rx_pkt_length +add wave -noupdate /tb/dut/mac_0/rx_l3_proto +add wave -noupdate /tb/dut/mac_0/rx_packet_complete +add wave -noupdate /tb/dut/mac_0/rx_wr_done +add wave -noupdate /tb/dut/mac_0/rx_keep +add wave -noupdate /tb/dut/mac_0/rx_ctl +add wave -noupdate /tb/dut/mac_0/rx_d +add wave -noupdate /tb/dut/mac_0/rx_ctl_m1 +add wave -noupdate /tb/dut/mac_0/rx_d_m1 +add wave -noupdate /tb/dut/mac_0/rx_line_up_cnt +add wave -noupdate /tb/dut/mac_0/phy_up +add wave -noupdate /tb/dut/mac_0/dpr_ad +add wave -noupdate /tb/dut/mac_0/dpr_ce +add wave -noupdate /tb/dut/mac_0/dpr_di +add wave -noupdate /tb/dut/mac_0/dpr_di_reg +add wave -noupdate /tb/dut/mac_0/dpr_do +add wave -noupdate /tb/dut/mac_0/dpr_we +add wave -noupdate /tb/dut/mac_0/tx_sample +add wave -noupdate /tb/dut/mac_0/tx_sample_re +add wave -noupdate /tb/dut/mac_0/tx_active +add wave -noupdate /tb/dut/mac_0/tx_byte_cnt_i +add wave -noupdate /tb/dut/mac_0/tx_clk +add wave -noupdate /tb/dut/mac_0/tx_src_sel +add wave -noupdate /tb/dut/mac_0/tx_mode +add wave -noupdate /tb/dut/mac_0/tx_state +add wave -noupdate /tb/dut/mac_0/tx_fifo_re +add wave -noupdate /tb/dut/mac_0/tx_last_byte +add wave -noupdate /tb/dut/mac_0/tx_finished +add wave -noupdate /tb/dut/mac_0/tx_fifo_d +add wave -noupdate /tb/dut/mac_0/tx_fifo_d_m1 +add wave -noupdate /tb/dut/mac_0/tx_fifo_empty +add wave -noupdate /tb/dut/mac_0/tx_f_pkt +add wave -noupdate /tb/dut/mac_0/tx_sop +add wave -noupdate /tb/dut/mac_0/tx_eop +add wave -noupdate /tb/dut/mac_0/tx_clk +add wave -noupdate /tb/dut/mac_0/tx_ctl +add wave -noupdate /tb/dut/mac_0/tx_d +add wave -noupdate /tb/dut/mac_0/tx_f +add wave -noupdate /tb/dut/phy0_tx_clk +add wave -noupdate /tb/dut/phy0_tx_ctl +add wave -noupdate /tb/dut/phy0_tx_d +add wave -noupdate /tb/dut/mac_0/tx_ctl_idle +add wave -noupdate /tb/dut/mac_0/tx_d_idle +add wave -noupdate /tb/dut/mac_0/tx_ctl_pkt +add wave -noupdate /tb/dut/mac_0/tx_data_pkt +add wave -noupdate /tb/dut/mac_0/fcs_tx_init +add wave -noupdate /tb/dut/mac_0/fcs_tx_enable +add wave -noupdate /tb/dut/mac_0/fcs_tx_dout +add wave -noupdate /tb/dut/mac_0/fcs_tx_addr +add wave -noupdate /tb/dut/mac_0/fcs_tx_addr_e +add wave -noupdate /tb/dut/mac_0/fcs_tx_din +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {652000 ps} 0} +quietly wave cursor active 1 +configure wave -namecolwidth 257 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ps +update +WaveRestoreZoom {0 ps} {10500 ns} diff --git a/manufacturer/altera/cyclone10_lp/sim/wav/wave_ml_engine.do b/manufacturer/altera/cyclone10_lp/sim/wav/wave_ml_engine.do new file mode 100644 index 0000000..a0e1480 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/sim/wav/wave_ml_engine.do @@ -0,0 +1,206 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /tb/rstn +add wave -noupdate /tb/clk_125 +add wave -noupdate /tb/pclk +add wave -noupdate /tb/clk_25 +add wave -noupdate /tb/clk_phy +add wave -noupdate /tb/clk_phyx2 +add wave -noupdate /tb/phy0_rx_clk +add wave -noupdate /tb/phy0_rx_ctl +add wave -noupdate /tb/phy0_rx_d +add wave -noupdate /tb/phy1_rx_clk +add wave -noupdate /tb/phy1_rx_ctl +add wave -noupdate /tb/phy1_rx_d +add wave -noupdate /tb/phy2_rx_clk +add wave -noupdate /tb/phy2_rx_ctl +add wave -noupdate /tb/phy2_rx_d +add wave -noupdate /tb/phy0_mdc +add wave -noupdate /tb/phy0_mdio +add wave -noupdate /tb/phy0_resetn +add wave -noupdate /tb/phy0_intn +add wave -noupdate /tb/phy1_mdc +add wave -noupdate /tb/phy1_mdio +add wave -noupdate /tb/phy1_resetn +add wave -noupdate /tb/phy1_intn +add wave -noupdate /tb/phy_up +add wave -noupdate /tb/rx0_data_cnt +add wave -noupdate /tb/rx0_d +add wave -noupdate /tb/rx1_d +add wave -noupdate /tb/rx2_d +add wave -noupdate /tb/rx1_data_cnt +add wave -noupdate /tb/rx2_data_cnt +add wave -noupdate /tb/phy0_tx_clk +add wave -noupdate /tb/phy0_tx_ctl +add wave -noupdate /tb/phy0_tx_d +add wave -noupdate /tb/phy1_tx_clk +add wave -noupdate /tb/phy1_tx_ctl +add wave -noupdate /tb/phy1_tx_d +add wave -noupdate /tb/phy2_tx_clk +add wave -noupdate /tb/phy2_tx_ctl +add wave -noupdate /tb/phy2_tx_d +add wave -noupdate -divider Top +add wave -noupdate /tb/dut/rstn +add wave -noupdate /tb/dut/sys_rstn +add wave -noupdate /tb/dut/clk_i +add wave -noupdate /tb/dut/pll_locked +add wave -noupdate /tb/clk_25 +add wave -noupdate /tb/clk_125 +add wave -noupdate /tb/dut/phy0_clk +add wave -noupdate /tb/dut/phy1_clk +add wave -noupdate /tb/dut/cont_clk +add wave -noupdate /tb/dut/sys_rstn +add wave -noupdate /tb/dut/phy_resetn +add wave -noupdate /tb/dut/phy0_rstn +add wave -noupdate /tb/dut/phy1_rstn +add wave -noupdate /tb/clk_phy +add wave -noupdate /tb/clk_phyx2 +add wave -noupdate {/tb/dut/phy_up[0]} +add wave -noupdate /tb/phy0_rx_clk +add wave -noupdate /tb/dut/rgmi_rx_0/datain +add wave -noupdate /tb/dut/rgmi_rx_0/inclock +add wave -noupdate /tb/dut/rgmi_rx_0/dataout_h +add wave -noupdate /tb/dut/rgmi_rx_0/dataout_l +add wave -noupdate /tb/dut/rx0_ctl_m1 +add wave -noupdate /tb/dut/rx0_d_m1 +add wave -noupdate /tb/dut/rx0_ctl_m2 +add wave -noupdate /tb/dut/rx0_d_m2 +add wave -noupdate /tb/dut/tx0_ctl +add wave -noupdate /tb/dut/tx0_d +add wave -noupdate /tb/dut/tx1_ctl +add wave -noupdate /tb/dut/tx1_d +add wave -noupdate /tb/dut/mle_d_0 +add wave -noupdate /tb/dut/mle_d_1 +add wave -noupdate /tb/dut/mle_d_2 +add wave -noupdate /tb/dut/mle_d_3 +add wave -noupdate /tb/dut/mle_d_i +add wave -noupdate /tb/dut/mle_d_o +add wave -noupdate /tb/dut/mle_empty +add wave -noupdate /tb/dut/mle_enable +add wave -noupdate /tb/dut/mle_event_start +add wave -noupdate /tb/dut/mle_event_stop +add wave -noupdate /tb/dut/mle_fifo_d_o +add wave -noupdate /tb/dut/mle_fifo_empty +add wave -noupdate /tb/dut/mle_fifo_re +add wave -noupdate /tb/dut/mle_oe +add wave -noupdate /tb/dut/mle_sel +add wave -noupdate /tb/dut/mle_we +add wave -noupdate -divider {MAC 0} +add wave -noupdate /tb/dut/mac_0/rx_clk +add wave -noupdate /tb/dut/mac_0/phy_up +add wave -noupdate /tb/dut/mac_0/rx_sop +add wave -noupdate /tb/dut/mac_0/rx_state +add wave -noupdate /tb/dut/mac_0/rx_packet_complete +add wave -noupdate /tb/dut/mac_0/rx_wr_done +add wave -noupdate /tb/dut/mac_0/rx_keep +add wave -noupdate /tb/dut/mac_0/rx_l3_proto +add wave -noupdate /tb/dut/mac_0/rx_pkt_length +add wave -noupdate /tb/dut/mac_0/rx_ctl +add wave -noupdate /tb/dut/mac_0/rx_d +add wave -noupdate /tb/dut/mac_0/rx_ctl_m1 +add wave -noupdate /tb/dut/mac_0/rx_d_m1 +add wave -noupdate /tb/dut/mac_0/rx_line_up_cnt +add wave -noupdate /tb/dut/mac_0/mle_if_cnt +add wave -noupdate /tb/dut/mac_0/mle_if_d_o +add wave -noupdate /tb/dut/mac_0/mle_if_empty +add wave -noupdate /tb/dut/mac_0/mle_if_enable +add wave -noupdate /tb/dut/mac_0/mle_if_we +add wave -noupdate /tb/dut/mac_0/mle_if_oe +add wave -noupdate -divider {ML ENGINE STAGE 0} +add wave -noupdate /tb/dut/ml_engine_0/rstn +add wave -noupdate /tb/dut/ml_engine_0/clk +add wave -noupdate -radix decimal /tb/dut/ml_engine_0/evt_counter +add wave -noupdate /tb/dut/ml_engine_0/evt_start +add wave -noupdate /tb/dut/ml_engine_0/evt_stop +add wave -noupdate /tb/dut/ml_engine_0/evt_active +add wave -noupdate /tb/dut/ml_engine_0/enable_logic_active +add wave -noupdate /tb/dut/ml_engine_0/enable +add wave -noupdate /tb/dut/ml_engine_0/empty +add wave -noupdate /tb/dut/ml_engine_0/empty_m1 +add wave -noupdate /tb/dut/ml_engine_0/mle_0_state +add wave -noupdate /tb/dut/ml_engine_0/we +add wave -noupdate /tb/dut/ml_engine_0/wr_block0 +add wave -noupdate /tb/dut/ml_engine_0/wr_ptr0 +add wave -noupdate /tb/dut/ml_engine_0/wr_addr0 +add wave -noupdate /tb/dut/mle_oe +add wave -noupdate /tb/dut/ml_engine_0/cnt0 +add wave -noupdate -divider {DPRAM STAGE 0} +add wave -noupdate /tb/dut/ml_engine_0/dpram_s0/rstn +add wave -noupdate /tb/dut/ml_engine_0/dpram_s0/a_clk +add wave -noupdate /tb/dut/ml_engine_0/dpram_s0/a_clk_e +add wave -noupdate /tb/dut/ml_engine_0/dpram_s0/a_we +add wave -noupdate /tb/dut/ml_engine_0/dpram_s0/a_oe +add wave -noupdate /tb/dut/ml_engine_0/dpram_s0/a_addr +add wave -noupdate /tb/dut/ml_engine_0/dpram_s0/a_din +add wave -noupdate /tb/dut/ml_engine_0/dpram_s0/a_dout +add wave -noupdate /tb/dut/ml_engine_0/dpram_s0/b_clk +add wave -noupdate /tb/dut/ml_engine_0/dpram_s0/b_clk_e +add wave -noupdate /tb/dut/ml_engine_0/dpram_s0/b_we +add wave -noupdate /tb/dut/ml_engine_0/dpram_s0/b_oe +add wave -noupdate /tb/dut/ml_engine_0/dpram_s0/b_addr +add wave -noupdate /tb/dut/ml_engine_0/dpram_s0/b_din +add wave -noupdate /tb/dut/ml_engine_0/dpram_s0/b_dout +add wave -noupdate -divider {ML ENGINE OUTPUT} +add wave -noupdate /tb/dut/ml_engine_0/wr_addr1 +add wave -noupdate /tb/dut/ml_engine_0/wr_block1 +add wave -noupdate /tb/dut/ml_engine_0/wr_ptr1 +add wave -noupdate /tb/dut/ml_engine_0/rd_addr1 +add wave -noupdate /tb/dut/ml_engine_0/rd_block1 +add wave -noupdate /tb/dut/ml_engine_0/rd_ptr1 +add wave -noupdate /tb/dut/ml_engine_0/fifo_empty +add wave -noupdate /tb/dut/ml_engine_0/fifo_re +add wave -noupdate /tb/dut/ml_engine_0/fifo_d_o +add wave -noupdate /tb/dut/ml_engine_0/fifo_d_out_flag +add wave -noupdate /tb/dut/ml_engine_0/fifo_d_out_flag_m1 +add wave -noupdate -divider {DPRAM STAGE 1} +add wave -noupdate /tb/dut/ml_engine_0/dpram_s1/rstn +add wave -noupdate /tb/dut/ml_engine_0/dpram_s1/a_clk +add wave -noupdate /tb/dut/ml_engine_0/dpram_s1/a_clk_e +add wave -noupdate /tb/dut/ml_engine_0/dpram_s1/a_we +add wave -noupdate /tb/dut/ml_engine_0/dpram_s1/a_oe +add wave -noupdate /tb/dut/ml_engine_0/dpram_s1/a_addr +add wave -noupdate /tb/dut/ml_engine_0/dpram_s1/a_din +add wave -noupdate /tb/dut/ml_engine_0/dpram_s1/a_dout +add wave -noupdate /tb/dut/ml_engine_0/dpram_s1/b_clk +add wave -noupdate /tb/dut/ml_engine_0/dpram_s1/b_clk_e +add wave -noupdate /tb/dut/ml_engine_0/dpram_s1/b_we +add wave -noupdate /tb/dut/ml_engine_0/dpram_s1/b_oe +add wave -noupdate /tb/dut/ml_engine_0/dpram_s1/b_addr +add wave -noupdate /tb/dut/ml_engine_0/dpram_s1/b_din +add wave -noupdate /tb/dut/ml_engine_0/dpram_s1/b_dout +add wave -noupdate -divider {SWITCH 0} +add wave -noupdate /tb/dut/switch_0/clk +add wave -noupdate /tb/dut/switch_0/phy_up +add wave -noupdate /tb/dut/switch_0/rx_d_01 +add wave -noupdate /tb/dut/switch_0/rx_d_0u +add wave -noupdate /tb/dut/switch_0/rx0_byte_cnt +add wave -noupdate /tb/dut/switch_0/rx_fifo_empty_0u +add wave -noupdate /tb/dut/switch_0/rx_fifo_empty_01 +add wave -noupdate /tb/dut/switch_0/rx_fifo_empty_u0 +add wave -noupdate /tb/dut/switch_0/rx_fifo_re_01 +add wave -noupdate /tb/dut/switch_0/rx_fifo_re_0u +add wave -noupdate {/tb/dut/switch_0/tx_f[0]} +add wave -noupdate {/tb/dut/switch_0/tx_fifo_empty[0]} +add wave -noupdate {/tb/dut/switch_0/tx_f[1]} +add wave -noupdate {/tb/dut/switch_0/tx_fifo_empty[1]} +add wave -noupdate /tb/dut/switch_0/tx_mode0 +add wave -noupdate /tb/dut/switch_0/tx0_byte_cnt +add wave -noupdate /tb/dut/switch_0/tx0_src_sel +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {1546837 ps} 0} +quietly wave cursor active 1 +configure wave -namecolwidth 315 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ps +update +WaveRestoreZoom {0 ps} {6885108 ps} diff --git a/manufacturer/altera/cyclone10_lp/sim/wav/wave_ml_engine_direct.do b/manufacturer/altera/cyclone10_lp/sim/wav/wave_ml_engine_direct.do new file mode 100644 index 0000000..6c56e8e --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/sim/wav/wave_ml_engine_direct.do @@ -0,0 +1,306 @@ +onerror {resume} +quietly virtual signal -install /tb/dut { (context /tb/dut )&{mac_sel ,mac_addr }} data_sel +quietly virtual signal -install /tb/dut { (context /tb/dut )&{mac_addr , mac_sel , mle_sel , hf_ptrs_sel , hf_rx_sel , hf_tx_sel }} data_sel001 +quietly virtual signal -install /tb/dut { (context /tb/dut )&{mac_addr[0] , mac_addr[1] , mac_sel , mle_sel , hf_ptrs_sel , hf_rx_sel , hf_tx_sel }} data_sel002 +quietly virtual signal -install /tb/dut { (concat_range (0 to 6) )( (context /tb/dut )&{mac_addr , mac_sel , mle_sel , hf_ptrs_sel , hf_rx_sel , hf_tx_sel } )} data_sel003 +quietly WaveActivateNextPane {} 0 +add wave -noupdate /tb/rstn +add wave -noupdate /tb/clk_125 +add wave -noupdate /tb/pclk +add wave -noupdate /tb/clk_25 +add wave -noupdate /tb/clk_phy +add wave -noupdate /tb/clk_phyx2 +add wave -noupdate /tb/phy0_rx_clk +add wave -noupdate /tb/phy0_rx_ctl +add wave -noupdate /tb/phy0_rx_d +add wave -noupdate /tb/phy1_rx_clk +add wave -noupdate /tb/phy1_rx_ctl +add wave -noupdate /tb/phy1_rx_d +add wave -noupdate /tb/phy2_rx_clk +add wave -noupdate /tb/phy2_rx_ctl +add wave -noupdate /tb/phy2_rx_d +add wave -noupdate /tb/phy0_mdc +add wave -noupdate /tb/phy0_mdio +add wave -noupdate /tb/phy0_resetn +add wave -noupdate /tb/phy0_intn +add wave -noupdate /tb/phy1_mdc +add wave -noupdate /tb/phy1_mdio +add wave -noupdate /tb/phy1_resetn +add wave -noupdate /tb/phy1_intn +add wave -noupdate /tb/phy_up +add wave -noupdate /tb/rx0_data_cnt +add wave -noupdate /tb/rx0_d +add wave -noupdate /tb/rx1_d +add wave -noupdate /tb/rx2_d +add wave -noupdate /tb/rx1_data_cnt +add wave -noupdate /tb/rx2_data_cnt +add wave -noupdate /tb/phy0_tx_clk +add wave -noupdate /tb/phy0_tx_ctl +add wave -noupdate /tb/phy0_tx_d +add wave -noupdate /tb/phy1_tx_clk +add wave -noupdate /tb/phy1_tx_ctl +add wave -noupdate /tb/phy1_tx_d +add wave -noupdate /tb/phy2_tx_clk +add wave -noupdate /tb/phy2_tx_ctl +add wave -noupdate /tb/phy2_tx_d +add wave -noupdate -divider Top +add wave -noupdate /tb/dut/rstn +add wave -noupdate /tb/dut/sys_rstn +add wave -noupdate /tb/dut/clk_i +add wave -noupdate /tb/dut/pll_locked +add wave -noupdate /tb/clk_25 +add wave -noupdate /tb/clk_125 +add wave -noupdate /tb/dut/phy0_clk +add wave -noupdate /tb/dut/phy1_clk +add wave -noupdate /tb/dut/cont_clk +add wave -noupdate /tb/dut/sys_rstn +add wave -noupdate /tb/dut/phy_resetn +add wave -noupdate /tb/dut/phy0_rstn +add wave -noupdate /tb/dut/phy1_rstn +add wave -noupdate /tb/clk_phy +add wave -noupdate /tb/clk_phyx2 +add wave -noupdate {/tb/dut/phy_up[0]} +add wave -noupdate /tb/phy0_rx_clk +add wave -noupdate /tb/dut/rgmi_rx_0/datain +add wave -noupdate /tb/dut/rgmi_rx_0/inclock +add wave -noupdate /tb/dut/rgmi_rx_0/dataout_h +add wave -noupdate /tb/dut/rgmi_rx_0/dataout_l +add wave -noupdate /tb/dut/rx0_ctl_m1 +add wave -noupdate /tb/dut/rx0_d_m1 +add wave -noupdate /tb/dut/rx0_ctl_m2 +add wave -noupdate /tb/dut/rx0_d_m2 +add wave -noupdate /tb/dut/tx0_ctl +add wave -noupdate /tb/dut/tx0_d +add wave -noupdate /tb/dut/tx1_ctl +add wave -noupdate /tb/dut/tx1_d +add wave -noupdate /tb/dut/mle_d_0 +add wave -noupdate /tb/dut/mle_d_1 +add wave -noupdate /tb/dut/mle_d_2 +add wave -noupdate /tb/dut/mle_d_3 +add wave -noupdate /tb/dut/mle_d_i +add wave -noupdate /tb/clk_125 +add wave -noupdate /tb/dut/mle_evt_start +add wave -noupdate /tb/dut/mle_evt_active +add wave -noupdate -color Yellow /tb/dut/mle_enable +add wave -noupdate /tb/dut/mle_empty +add wave -noupdate /tb/dut/mle_fifo_d_o +add wave -noupdate /tb/dut/mle_fifo_empty +add wave -noupdate /tb/dut/mle_fifo_re +add wave -noupdate /tb/dut/mle_oe +add wave -noupdate /tb/dut/mle_we +add wave -noupdate /tb/dut/data_sel003 +add wave -noupdate /tb/dut/mac_addr +add wave -noupdate /tb/dut/mac_sel +add wave -noupdate /tb/dut/mle_sel +add wave -noupdate /tb/dut/hf_ptrs_sel +add wave -noupdate /tb/dut/hf_rx_sel +add wave -noupdate /tb/dut/hf_tx_sel +add wave -noupdate /tb/dut/mac_0_d_o +add wave -noupdate /tb/dut/mac_1_d_o +add wave -noupdate /tb/dut/mac_2_d_o +add wave -noupdate /tb/dut/mle_d_o +add wave -noupdate /tb/dut/hfifo_d_o +add wave -noupdate /tb/dut/mem_d_i +add wave -noupdate -divider {MAC 0} +add wave -noupdate /tb/dut/mac_0/rx_clk +add wave -noupdate /tb/dut/mac_0/phy_up +add wave -noupdate /tb/dut/mac_0/rx_sop +add wave -noupdate -color Yellow /tb/dut/mac_0/rx_eop +add wave -noupdate /tb/dut/mac_0/rx_state +add wave -noupdate /tb/dut/mac_0/rx_packet_complete +add wave -noupdate /tb/dut/mac_0/rx_wr_done +add wave -noupdate /tb/dut/mac_0/rx_keep +add wave -noupdate /tb/dut/mac_0/rx_l3_proto +add wave -noupdate /tb/dut/mac_0/rx_pkt_length +add wave -noupdate /tb/dut/mac_0/rx_ctl +add wave -noupdate /tb/dut/mac_0/rx_d +add wave -noupdate /tb/dut/mac_0/rx_ctl_m1 +add wave -noupdate /tb/dut/mac_0/rx_d_m1 +add wave -noupdate /tb/dut/mac_0/rx_line_up_cnt +add wave -noupdate /tb/dut/mac_0/mle_if_cnt +add wave -noupdate /tb/dut/mac_0/mle_if_d_o +add wave -noupdate /tb/dut/mac_0/mle_if_empty +add wave -noupdate /tb/dut/mac_0/mle_if_enable +add wave -noupdate /tb/dut/mac_0/mle_if_we +add wave -noupdate /tb/dut/mac_0/mle_if_oe +add wave -noupdate -divider HFIFO +add wave -noupdate /tb/dut/micro_fifo_0/rx_fifo_int +add wave -noupdate /tb/dut/micro_fifo_0/rx_fifo_int_acked +add wave -noupdate /tb/dut/micro_fifo_0/rx_wr_ptr +add wave -noupdate /tb/dut/micro_fifo_0/rx_wr_ptr_latched +add wave -noupdate /tb/dut/micro_fifo_0/dpram_rx/rstn +add wave -noupdate /tb/dut/micro_fifo_0/dpram_rx/a_clk +add wave -noupdate /tb/dut/micro_fifo_0/dpram_rx/a_clk_e +add wave -noupdate /tb/dut/micro_fifo_0/dpram_rx/a_we +add wave -noupdate /tb/dut/micro_fifo_0/dpram_rx/a_oe +add wave -noupdate /tb/dut/micro_fifo_0/dpram_rx/a_addr +add wave -noupdate /tb/dut/micro_fifo_0/dpram_rx/a_din +add wave -noupdate /tb/dut/micro_fifo_0/dpram_rx/a_dout +add wave -noupdate /tb/dut/micro_fifo_0/dpram_rx/b_clk +add wave -noupdate /tb/dut/micro_fifo_0/dpram_rx/b_clk_e +add wave -noupdate /tb/dut/micro_fifo_0/dpram_rx/b_we +add wave -noupdate /tb/dut/micro_fifo_0/dpram_rx/b_oe +add wave -noupdate /tb/dut/micro_fifo_0/dpram_rx/b_addr +add wave -noupdate /tb/dut/micro_fifo_0/dpram_rx/b_din +add wave -noupdate /tb/dut/micro_fifo_0/dpram_rx/b_dout +add wave -noupdate -divider Controller +add wave -noupdate /tb/dut/controller_0/clk +add wave -noupdate /tb/dut/controller_0/rx_msg_captured +add wave -noupdate /tb/dut/controller_0/rx_msg_cnt +add wave -noupdate /tb/dut/controller_0/msg_addr +add wave -noupdate /tb/dut/controller_0/msg_addr_ro +add wave -noupdate /tb/dut/controller_0/msg_addr_valid +add wave -noupdate /tb/dut/controller_0/msg_data +add wave -noupdate /tb/dut/controller_0/msg_error +add wave -noupdate /tb/dut/controller_0/msg_response +add wave -noupdate /tb/dut/controller_0/msg_token +add wave -noupdate /tb/dut/controller_0/msg_type +add wave -noupdate /tb/dut/controller_0/cont_msg +add wave -noupdate /tb/dut/controller_0/cont_state +add wave -noupdate /tb/dut/controller_0/rx_rd_active +add wave -noupdate /tb/dut/controller_0/rx_wr_ptr +add wave -noupdate /tb/dut/controller_0/rx_rd_ptr +add wave -noupdate /tb/dut/controller_0/mem_state +add wave -noupdate /tb/dut/controller_0/mem_addr +add wave -noupdate /tb/dut/controller_0/mem_cmd +add wave -noupdate /tb/dut/controller_0/mem_d_i +add wave -noupdate /tb/dut/controller_0/mem_d_o +add wave -noupdate /tb/dut/controller_0/mem_oe +add wave -noupdate /tb/dut/controller_0/mem_tgt_ready +add wave -noupdate /tb/dut/controller_0/mem_tgt_ready_m1 +add wave -noupdate /tb/dut/controller_0/mem_tgt_ready_m2 +add wave -noupdate /tb/dut/controller_0/mem_we +add wave -noupdate /tb/dut/controller_0/mle_sel +add wave -noupdate -divider {MAC 1} +add wave -noupdate /tb/dut/mac_1/mle_if_cnt +add wave -noupdate /tb/dut/mac_1/mle_if_d_o +add wave -noupdate /tb/dut/mac_1/mle_if_empty +add wave -noupdate /tb/dut/mac_1/mle_if_enable +add wave -noupdate /tb/dut/mac_1/mle_if_oe +add wave -noupdate /tb/dut/mac_1/mle_if_we +add wave -noupdate /tb/dut/mac_1/rx_ctl +add wave -noupdate /tb/dut/mac_1/rx_d +add wave -noupdate -divider {MAC 2} +add wave -noupdate /tb/dut/mac_2/mle_if_cnt +add wave -noupdate /tb/dut/mac_2/mle_if_d_o +add wave -noupdate /tb/dut/mac_2/mle_if_empty +add wave -noupdate /tb/dut/mac_2/mle_if_enable +add wave -noupdate /tb/dut/mac_2/mle_if_oe +add wave -noupdate /tb/dut/mac_2/mle_if_we +add wave -noupdate /tb/dut/mac_2/rx_ctl +add wave -noupdate /tb/dut/mac_2/rx_d +add wave -noupdate -divider {ML ENGINE 0} +add wave -noupdate /tb/dut/ml_engine_0/rstn +add wave -noupdate /tb/dut/ml_engine_0/clk +add wave -noupdate /tb/dut/ml_engine_0/mle_enable +add wave -noupdate -radix decimal /tb/dut/ml_engine_0/evt_counter +add wave -noupdate /tb/dut/ml_engine_0/evt_start +add wave -noupdate /tb/dut/ml_engine_0/evt_active +add wave -noupdate -color Yellow /tb/dut/ml_engine_0/mle_0_state +add wave -noupdate -radix ascii /tb/dut/ml_engine_0/mle_0_state_str +add wave -noupdate /tb/dut/ml_engine_0/enable_logic_active +add wave -noupdate /tb/dut/ml_engine_0/enable +add wave -noupdate /tb/dut/ml_engine_0/empty +add wave -noupdate /tb/dut/ml_engine_0/empty_m1 +add wave -noupdate /tb/dut/ml_engine_0/we +add wave -noupdate /tb/dut/ml_engine_0/wr_block0 +add wave -noupdate /tb/dut/ml_engine_0/wr_ptr0 +add wave -noupdate /tb/dut/ml_engine_0/wr_addr0 +add wave -noupdate /tb/dut/mle_oe +add wave -noupdate /tb/dut/ml_engine_0/cnt0 +add wave -noupdate /tb/dut/ml_engine_0/clk +add wave -noupdate /tb/dut/ml_engine_0/we1 +add wave -noupdate /tb/dut/ml_engine_0/d_out_avail +add wave -noupdate /tb/dut/ml_engine_0/evt_delay_out +add wave -noupdate /tb/dut/ml_engine_0/rd_block1 +add wave -noupdate /tb/dut/ml_engine_0/rd_ptr1 +add wave -noupdate /tb/dut/ml_engine_0/rd_addr1 +add wave -noupdate /tb/dut/ml_engine_0/fifo_d_o +add wave -noupdate /tb/dut/ml_engine_0/fifo_d_out_flag +add wave -noupdate /tb/dut/ml_engine_0/fifo_empty +add wave -noupdate /tb/dut/ml_engine_0/fifo_re +add wave -noupdate -divider {DPRAM Inpt} +add wave -noupdate /tb/dut/ml_engine_0/dpram_s0/rstn +add wave -noupdate /tb/dut/ml_engine_0/dpram_s0/a_clk +add wave -noupdate /tb/dut/ml_engine_0/dpram_s0/a_clk_e +add wave -noupdate /tb/dut/ml_engine_0/dpram_s0/a_we +add wave -noupdate /tb/dut/ml_engine_0/dpram_s0/a_oe +add wave -noupdate /tb/dut/ml_engine_0/dpram_s0/a_addr +add wave -noupdate /tb/dut/ml_engine_0/dpram_s0/a_din +add wave -noupdate /tb/dut/ml_engine_0/dpram_s0/a_dout +add wave -noupdate /tb/dut/ml_engine_0/dpram_s0/b_clk +add wave -noupdate /tb/dut/ml_engine_0/dpram_s0/b_clk_e +add wave -noupdate /tb/dut/ml_engine_0/dpram_s0/b_we +add wave -noupdate /tb/dut/ml_engine_0/dpram_s0/b_oe +add wave -noupdate /tb/dut/ml_engine_0/dpram_s0/b_addr +add wave -noupdate /tb/dut/ml_engine_0/dpram_s0/b_din +add wave -noupdate /tb/dut/ml_engine_0/dpram_s0/b_dout +add wave -noupdate -divider DIRECT_OUTPUT +add wave -noupdate /tb/dut/ml_engine_0/rd_addr0 +add wave -noupdate /tb/dut/ml_engine_0/d_s0_o +add wave -noupdate /tb/dut/ml_engine_0/rd_oe0 +add wave -noupdate -divider {ML ENGINE OUTPUT} +add wave -noupdate /tb/dut/ml_engine_0/evt_delay_out +add wave -noupdate /tb/dut/ml_engine_0/rd_addr1 +add wave -noupdate /tb/dut/ml_engine_0/rd_block1 +add wave -noupdate /tb/dut/ml_engine_0/rd_ptr1 +add wave -noupdate /tb/dut/ml_engine_0/fifo_d_out_flag +add wave -noupdate /tb/dut/ml_engine_0/fifo_empty +add wave -noupdate /tb/dut/ml_engine_0/fifo_re +add wave -noupdate /tb/dut/ml_engine_0/fifo_d_o +add wave -noupdate -divider {SWITCH 0} +add wave -noupdate /tb/dut/switch_0/clk +add wave -noupdate /tb/dut/switch_0/phy_up +add wave -noupdate /tb/dut/switch_0/rx_d_01 +add wave -noupdate /tb/dut/switch_0/rx_d_0u +add wave -noupdate /tb/dut/switch_0/rx0_byte_cnt +add wave -noupdate /tb/dut/switch_0/rx_fifo_empty_0u +add wave -noupdate /tb/dut/switch_0/rx_fifo_empty_01 +add wave -noupdate /tb/dut/switch_0/rx_fifo_empty_u0 +add wave -noupdate /tb/dut/switch_0/rx_fifo_re_01 +add wave -noupdate /tb/dut/switch_0/rx_fifo_re_0u +add wave -noupdate {/tb/dut/switch_0/tx_f[0]} +add wave -noupdate {/tb/dut/switch_0/tx_fifo_empty[0]} +add wave -noupdate {/tb/dut/switch_0/tx_f[1]} +add wave -noupdate {/tb/dut/switch_0/tx_fifo_empty[1]} +add wave -noupdate /tb/dut/switch_0/tx_mode0 +add wave -noupdate /tb/dut/switch_0/tx0_byte_cnt +add wave -noupdate /tb/dut/switch_0/tx0_src_sel +add wave -noupdate -divider {MAC 0 TX} +add wave -noupdate /tb/dut/mac_0/tx_clk +add wave -noupdate /tb/dut/mac_0/tx_byte_cnt_i +add wave -noupdate /tb/dut/mac_0/tx_fifo_empty +add wave -noupdate /tb/dut/mac_0/tx_fifo_re +add wave -noupdate /tb/dut/mac_0/tx_state +add wave -noupdate /tb/dut/mac_0/tx_cnt +add wave -noupdate /tb/dut/mac_0/tx_mode +add wave -noupdate /tb/dut/mac_0/tx_src_sel +add wave -noupdate /tb/dut/mac_0/tx_fifo_d +add wave -noupdate /tb/dut/mac_0/tx_fifo_d_m1 +add wave -noupdate /tb/dut/mac_0/tx_fifo_d_m2 +add wave -noupdate /tb/dut/mac_0/tx_pkt_cnt +add wave -noupdate /tb/dut/mac_0/tx_mle_fifo_d +add wave -noupdate /tb/dut/mac_0/tx_mle_fifo_empty +add wave -noupdate /tb/dut/mac_0/tx_mode +add wave -noupdate /tb/dut/mac_0/tx_sop +add wave -noupdate -radix unsigned /tb/dut/mac_0/tx_cnt +add wave -noupdate /tb/dut/mac_0/tx_ctl +add wave -noupdate /tb/dut/mac_0/tx_d +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {5416031 ps} 0} +quietly wave cursor active 1 +configure wave -namecolwidth 233 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ps +update +WaveRestoreZoom {4633158 ps} {4712031 ps} diff --git a/manufacturer/altera/cyclone10_lp/sim/win/betsy.mpf b/manufacturer/altera/cyclone10_lp/sim/win/betsy.mpf new file mode 100644 index 0000000..af316f2 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/sim/win/betsy.mpf @@ -0,0 +1,2342 @@ +; vsim modelsim.ini file +[Version] +INIVersion = "2024.3" + +; Unpublished work. Copyright 2024 Siemens +; +; This material contains trade secrets or otherwise confidential information +; owned by Siemens Industry Software Inc. or its affiliates (collectively, +; "SISW"), or its licensors. Access to and use of this information is strictly +; limited as set forth in the Customer's applicable agreements with SISW. +; +; This material may not be copied, distributed, or otherwise disclosed outside +; of the Customer's facilities without the express written permission of SISW, +; and may not be used in any way not expressly authorized by SISW. +; + +[Library] +others = $MODEL_TECH/../modelsim.ini +; +; VITAL concerns: +; +; The library ieee contains (among other packages) the packages of the +; VITAL 2000 standard. When a design uses VITAL 2000 exclusively, it should use +; the physical library ieee (recommended), or use the physical library +; vital2000, but not both. The design can use logical library ieee and/or +; vital2000 as long as each of these maps to the same physical library, either +; ieee or vital2000. +; +; A design using the 1995 version of the VITAL packages, whether or not +; it also uses the 2000 version of the VITAL packages, must have logical library +; name ieee mapped to physical library vital1995. (A design cannot use library +; vital1995 directly because some packages in this library use logical name ieee +; when referring to the other packages in the library.) The design source +; should use logical name ieee when referring to any packages there except the +; VITAL 2000 packages. Any VITAL 2000 present in the design must use logical +; name vital2000 (mapped to physical library vital2000) to refer to those +; packages. +; ieee = $MODEL_TECH/../vital1995 +; +; For compatiblity with previous releases, logical library name vital2000 maps +; to library vital2000 (a different library than library ieee, containing the +; same packages). +; A design should not reference VITAL from both the ieee library and the +; vital2000 library because the vital packages are effectively different. +; A design that references both the ieee and vital2000 libraries must have +; both logical names ieee and vital2000 mapped to the same library, either of +; these: +; $MODEL_TECH/../ieee +; $MODEL_TECH/../vital2000 +; + +; added mapping for ADMS + +;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers // Source files only for this release +;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release +;mvc_lib = $MODEL_TECH/../mvc_lib + +; Altera Primitive libraries +; +; VHDL Section +; +; +; Verilog Section +; + +; Automatically perform logical->physical mapping for physical libraries that +; appear in -L/-Lf options with filesystem path delimiters (e.g. '.' or '/'). +; The tail of the filesystem path name is chosen as the logical library name. +; For example, in the command "vopt -L ./path/to/lib1 -o opttop top", +; vopt automatically performs the mapping "lib1 -> ./path/to/lib1". +; See the User Manual for more details. +; +; AutoLibMapping = 0 + +work = rtl_work +[BC_COMPAT] +; Start of Backward Compatibility Section +; The Variables in this section are dedicated for the Backward Compatibility feature +; Set desired release version for backward compatibility, note that currently this only supports 2023.1 +;BC_ReleaseCompat = 2023.1 +;BC_XClass = <activate/deactivate> +; End of Backward Compatibility Section + +[DefineOptionset] +; Define optionset entries for the various compilers, vmake, and vsim. +; These option sets can be used with the "-optionset <optionsetname>" syntax. +; i.e. +; vlog -optionset COMPILEDEBUG top.sv +; vsim -optionset UVMDEBUG my_top +; +; Following are some useful examples. + +; define a vsim optionset for uvm debugging +UVMDEBUG = -uvmcontrol=all -msgmode both -displaymsgmode both -classdebug -onfinish stop + +; define a vopt optionset for debugging +VOPTDEBUG = +acc -debugdb + +[encryption] +; For vencrypt and vhencrypt. + +; Controls whether to encrypt whole files by ignoring all protect directives +; (except "viewport" and "interface_viewport") that are present in the input. +; The default is 0, use embedded protect directives to control the encryption. +; Set this to 1 to encrypt whole files by ignoring embedded protect directives. +; wholefile = 0 + +; Sets the data_method to use for the symmetric session key. +; The session key is a symmetric key that is randomly generated for each +; protected region (envelope) and is the heart of all encryption. This is used +; to set the length of the session key to generate and use when encrypting the +; HDL text. Supported values are aes128, aes192, and aes256. +; data_method = aes128 + +; The following 2 are for specifying an IEEE Std. 1735 Version 2 (V2) encryption +; "recipe" comprising an optional common block, at least one tool block (which +; contains the key public key), and the text to be encrypted. The common block +; and any of the tool blocks may contain rights in the form of the "control" +; directive. The text to be encrypted is specified either by setting +; "wholefile" to 1 or by embedding protect "begin" and "end" directives in +; the input HDL files. + +; Common recipe specification file. This file is optional. Its presence will +; require at least one "toolblock" to be specified. +; Directives such as "author" "author_info" and "data_method", +; as well as the common block license specification, go in this file. +; common = <file name> + +; Tool block specification recipe(s). Public key file with optional tool block +; file name. May be multiply-defined; at least one tool block is required if +; a recipe is being specified. +; Key file is a file name with no extension (.deprecated or .active will be +; supplied by the encryption tool). +; Rights file name is optional. +; toolblock = <key file name>[,<rights file name>]{:<key file name>[,<rights file name>]} + +; Location of directory containing recipe files. +; The default location is in the product installation directory. +; keyring = $MODEL_TECH/../keyring + +; Enable encryption statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list] +; Add '-' to disable specific statistics. Default is [cmd,msg]. +Stats = cmd,msg + +[vcom] +; VHDL93 variable selects language version as the default. +; Default is VHDL-2002. +; Value of 0 or 1987 for VHDL-1987. +; Value of 1 or 1993 for VHDL-1993. +; Default or value of 2 or 2002 for VHDL-2002. +; Value of 3 or 2008 for VHDL-2008 +; Value of 4 or ams99 for VHDL-AMS-1999 +; Value of 5 or ams07 for VHDL-AMS-2007 +; Value of 7 or 2019 for VHDL-2019 +VHDL93 = 2002 + +; Ignore VHDL-2008 declaration of REAL_VECTOR in package STANDARD. Default is off. +; ignoreStandardRealVector = 1 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn off unbound-component warnings. Default is on. +; Show_Warning1 = 0 + +; Turn off process-without-a-wait-statement warnings. Default is on. +; Show_Warning2 = 0 + +; Turn off null-range warnings. Default is on. +; Show_Warning3 = 0 + +; Turn off no-space-in-time-literal warnings. Default is on. +; Show_Warning4 = 0 + +; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. +; Show_Warning5 = 0 + +; Turn off optimization for IEEE std_logic_1164 package. Default is on. +; Optimize_1164 = 0 + +; Enable compiler statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list] +; Add '-' to disable specific statistics. Default is [time,cmd,msg]. +; Stats = time,cmd,msg + +; Turn on resolving of ambiguous function overloading in favor of the +; "explicit" function declaration (not the one automatically created by +; the compiler for each type declaration). Default is off. +; The .ini file has Explicit enabled so that std_logic_signed/unsigned +; will match the behavior of synthesis tools. +Explicit = 1 + +; Turn off acceleration of the VITAL packages. Default is to accelerate. +; NoVital = 1 + +; Turn off VITAL compliance checking. Default is checking on. +; NoVitalCheck = 1 + +; Ignore VITAL compliance checking errors. Default is to not ignore. +; IgnoreVitalErrors = 1 + +; Turn off VITAL compliance checking warnings. Default is to show warnings. +; Show_VitalChecksWarnings = 0 + +; Turn off PSL assertion warning messages. Default is to show warnings. +; Show_PslChecksWarnings = 0 + +; Enable parsing of embedded PSL assertions. Default is enabled. +; EmbeddedPsl = 0 + +; Keep silent about case statement static warnings. +; Default is to give a warning. +; NoCaseStaticError = 1 + +; Keep silent about warnings caused by aggregates that are not locally static. +; Default is to give a warning. +; NoOthersStaticError = 1 + +; Treat as errors: +; case statement static warnings +; warnings caused by aggregates that are not locally static +; Overrides NoCaseStaticError, NoOthersStaticError settings. +; PedanticErrors = 1 + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on some limited synthesis rule compliance checking. Checks only: +; -- signals used (read) by a process must be in the sensitivity list +; CheckSynthesis = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +; Require the user to specify a configuration for all bindings, +; and do not generate a compile time default binding for the +; component. This will result in an elaboration error of +; 'component not bound' if the user fails to do so. Avoids the rare +; issue of a false dependency upon the unused default binding. +; RequireConfigForAllDefaultBinding = 1 + +; Perform default binding at compile time. +; Default is to do default binding at load time. +; BindAtCompile = 1; + +; Inhibit range checking on subscripts of arrays. Range checking on +; scalars defined with subtypes is inhibited by default. +; NoIndexCheck = 1 + +; Inhibit range checks on all (implicit and explicit) assignments to +; scalar objects defined with subtypes. +; NoRangeCheck = 1 + +; Set the prefix to be honored for synthesis/coverage pragma recognition. +; Default is "". +; AddPragmaPrefix = "" + +; Ignore synthesis and coverage pragmas with this prefix. +; Default is "". +; IgnorePragmaPrefix = "" + +; Turn on code coverage in VHDL design units. Default is off. +; Coverage = sbceft + +; Turn off code coverage in VHDL subprograms. Default is on. +; CoverSub = 0 + +; Automatically exclude VHDL case statement OTHERS choice branches. +; This includes OTHERS choices in selected signal assigment statements. +; Default is to not exclude. +; CoverExcludeDefault = 1 + +; Control compiler and VOPT optimizations that are allowed when +; code coverage is on. Refer to the comment for this in the [vlog] area. +; CoverOpt = 3 + +; Turn on or off clkOpt optimization for code coverage. Default is on. +; CoverClkOpt = 1 + +; Turn on or off clkOpt optimization builtins for code coverage. Default is on. +; CoverClkOptBuiltins = 0 + +; Inform code coverage optimizations to respect VHDL 'H' and 'L' +; values on signals in conditions and expressions, and to not automatically +; convert them to '1' and '0'. Default is to not convert. +; CoverRespectHandL = 0 + +; Increase or decrease the maximum number of rows allowed in a UDP table +; implementing a VHDL condition coverage or expression coverage expression. +; More rows leads to a longer compile time, but more expressions covered. +; CoverMaxUDPRows = 192 + +; Increase or decrease the maximum number of input patterns that are present +; in FEC table. This leads to a longer compile time with more expressions +; covered with FEC metric. +; CoverMaxFECRows = 192 + +; Increase or decrease the limit on the size of expressions and conditions +; considered for expression and condition coverages. Higher FecUdpEffort leads +; to higher compile, optimize and simulation time, but more expressions and +; conditions are considered for coverage in the design. FecUdpEffort can +; be set to a number ranging from 1 (low) to 3 (high), defined as: +; 1 - (low) Only small expressions and conditions considered for coverage. +; 2 - (medium) Bigger expressions and conditions considered for coverage. +; 3 - (high) Very large expressions and conditions considered for coverage. +; The default setting is 1 (low). +; FecUdpEffort = 1 + +; Enable or disable Focused Expression Coverage analysis for conditions and +; expressions. Focused Expression Coverage data is provided by default when +; expression and/or condition coverage is active. +; CoverFEC = 0 + +; Enable or disable UDP Coverage analysis for conditions and expressions. +; UDP Coverage data is disabled by default when expression and/or condition +; coverage is active. +; CoverUDP = 1 + +; Enable or disable Rapid Expression Coverage mode for conditions and expressions. +; Disabling this would convert non-masking conditions in FEC tables to matching +; input patterns. +; CoverREC = 1 + +; Enable or disable bit-blasting multi-bit operands of reduction prefix expressions +; for expression/condition coverage. +; NOTE: Enabling this may have a negative impact on simulation performance. +; CoverExpandReductionPrefix = 0 + +; Enable or disable short circuit evaluation of conditions and expressions when +; condition or expression coverage is active. Short circuit evaluation is enabled +; by default. +; CoverShortCircuit = 0 + +; Enable code coverage reporting of code that has been optimized away. +; The default is not to report. +; CoverReportCancelled = 1 + +; Enable deglitching of code coverage in combinatorial, non-clocked, processes. +; Default is no deglitching. +; CoverDeglitchOn = 1 + +; Control the code coverage deglitching period. A period of 0, eliminates delta +; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a +; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". +; CoverDeglitchPeriod = 0 + +; Use this directory for compiler temporary files instead of "work/_temp" +; CompilerTempDir = /tmp + +; Set this to cause the compilers to force data to be committed to disk +; when the files are closed. +; SyncCompilerFiles = 1 + +; Add VHDL-AMS declarations to package STANDARD +; Default is not to add +; AmsStandard = 1 + +; Range and length checking will be performed on array indices and discrete +; ranges, and when violations are found within subprograms, errors will be +; reported. Default is to issue warnings for violations, because subprograms +; may not be invoked. +; NoDeferSubpgmCheck = 0 + +; Turn ON detection of FSMs having single bit current state variable. +; FsmSingle = 1 + +; Turn off reset state transitions in FSM. +; FsmResetTrans = 0 + +; Turn ON detection of FSM Implicit Transitions. +; FsmImplicitTrans = 1 + +; Controls whether or not to show immediate assertions with constant expressions +; in GUI/report/UCDB etc. By default, immediate assertions with constant +; expressions are shown in GUI/report/UCDB etc. This does not affect +; evaluation of immediate assertions. +; ShowConstantImmediateAsserts = 0 + +; Controls how VHDL basic identifiers are stored with the design unit. +; Does not make the language case-sensitive, affects only how declarations +; declared with basic identifiers have their names stored and printed +; (in the GUI, examine, etc.). +; Default is to preserve the case as originally depicted in the VHDL source. +; Value of 0 indicates to change all basic identifiers to lower case. +; PreserveCase = 0 + +; For Configuration Declarations, controls the effect that USE clauses have +; on visibility inside the configuration items being configured. If 1 +; (the default), then use pre-10.0 behavior. If 0, then for stricter LRM-compliance, +; extend the visibility of objects made visible through USE clauses into nested +; component configurations. +; OldVHDLConfigurationVisibility = 0 + +; Allows VHDL configuration declarations to be in a different library from +; the corresponding configured entity. Default is to not allow this for +; stricter LRM-compliance. +; SeparateConfigLibrary = 1; + +; Determine how mode OUT subprogram parameters of type array and record are treated. +; If 0 (the default), then only VHDL 2008 will do this initialization. +; If 1, always initialize the mode OUT parameter to its default value. +; If 2, do not initialize the mode OUT out parameter. +; Note that prior to release 10.1, all language versions did not initialize mode +; OUT array and record type parameters, unless overridden here via this mechanism. +; In release 10.1 and later, only files compiled with VHDL 2008 will cause this +; initialization, unless overridden here. +; InitOutCompositeParam = 0 + +; Generate symbols debugging database in only some special cases to save on +; the number of files in the library. For other design-units, this database is +; generated on-demand in vsim. +; Default is to to generate debugging database for all design-units. +; SmartDbgSym = 1 + +; Enable or disable automatic creation of missing libraries. +; Default is 1 (enabled) +; CreateLib = 1 + +; Describe compilation options according to matching file patterns. +; File pattern * matches all printing characters other than '/'. +; File pattern **/x matches all paths containing file/directory x. +; File pattern x/** matches all paths beginning at directory x. +; FileOptMap = (**/*.vhd => -2008); + +; Describe library targets of compilation according to matching file patterns. +; LibMap = (**/*.vhd => work); + +; Enable or Disable Auto-order compilation. +; Default is 0 (disabled) +; Autoorder = 0 + +[vlog] +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on Verilog hazard checking (order-dependent accessing of global vars). +; Default is off. +; Hazard = 1 + +; Turn on converting regular Verilog identifiers to uppercase. Allows case +; insensitivity for module names. Default is no conversion. +; UpCase = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn on bad option warning. Default is off. +; Show_BadOptionWarning = 1 + +; Revert back to IEEE 1364-1995 syntax, default is 0 (off). +; vlog95compat = 1 + +; Turn off PSL warning messages. Default is to show warnings. +; Show_PslChecksWarnings = 0 + +; Enable parsing of embedded PSL assertions. Default is enabled. +; EmbeddedPsl = 0 + +; Enable compiler statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list,kb] +; Add '-' to disable specific statistics. Default is [time,cmd,msg]. +; Stats = time,cmd,msg + +; Check vlog plusargs. Default is 0 (off). +; The command line equivalent is -check_plusargs <number>. +; 0 = Don't check plusargs (this is the default) +; 1 = Warning on unrecognized plusarg +; 2 = Error and exit on unrecognized plusarg +; CheckPlusargs = 1 + +; Set the threshold for automatically identifying sparse Verilog memories. +; A memory with total size in bytes equal to or more than the sparse memory +; threshold gets marked as sparse automatically, unless specified otherwise +; in source code or by the +nosparse commandline option of vlog or vopt. +; The default is 1M. (i.e. memories with total size equal +; to or greater than 1Mb are marked as sparse) +; SparseMemThreshold = 1048576 + +; Set the prefix to be honored for synthesis and coverage pragma recognition. +; Default is "". +; AddPragmaPrefix = "" + +; Ignore synthesis and coverage pragmas with this prefix. +; Default is "". +; IgnorePragmaPrefix = "" + +; Set the option to treat all files specified in a vlog invocation as a +; single compilation unit. The default value is set to 0 which will treat +; each file as a separate compilation unit as specified in the P1800 draft standard. +; MultiFileCompilationUnit = 1 + +; Turn on code coverage in Verilog design units. Default is off. +; Coverage = sbceft + +; Automatically exclude Verilog case statement default branches. +; Default is to not automatically exclude defaults. +; CoverExcludeDefault = 1 + +; Increase or decrease the maximum number of rows allowed in a UDP table +; implementing a VHDL condition coverage or expression coverage expression. +; More rows leads to a longer compile time, but more expressions covered. +; CoverMaxUDPRows = 192 + +; Increase or decrease the maximum number of input patterns that are present +; in FEC table. This leads to a longer compile time with more expressions +; covered with FEC metric. +; CoverMaxFECRows = 192 + +; Enable Multi Bit Expression Coverage in a Design, If design has expression with +; multi bit operands, this option enables its Expression Coverage. +; The default value is 0. +; CoverFecMultiBit = 1 + +; Increase or decrease the limit on the size of expressions and conditions +; considered for expression and condition coverages. Higher FecUdpEffort leads +; to higher compile, optimize and simulation time, but more expressions and +; conditions are considered for coverage in the design. FecUdpEffort can +; be set to a number ranging from 1 (low) to 3 (high), defined as: +; 1 - (low) Only small expressions and conditions considered for coverage. +; 2 - (medium) Bigger expressions and conditions considered for coverage. +; 3 - (high) Very large expressions and conditions considered for coverage. +; The default setting is 1 (low). +; FecUdpEffort = 1 + +; Enable or disable Focused Expression Coverage analysis for conditions and +; expressions. Focused Expression Coverage data is provided by default when +; expression and/or condition coverage is active. +; CoverFEC = 0 + +; Enable or disable UDP Coverage analysis for conditions and expressions. +; UDP Coverage data is disabled by default when expression and/or condition +; coverage is active. +; CoverUDP = 1 + +; Enable or disable Rapid Expression Coverage mode for conditions and expressions. +; Disabling this would convert non-masking conditions in FEC tables to matching +; input patterns. +; CoverREC = 1 + +; Enable or disable bit-blasting multi-bit operands of reduction prefix expressions +; for expression/condition coverage. +; NOTE: Enabling this may have a negative impact on simulation performance. +; CoverExpandReductionPrefix = 0 + +; Enable or disable short circuit evaluation of conditions and expressions when +; condition or expression coverage is active. Short circuit evaluation is enabled +; by default. +; CoverShortCircuit = 0 + +; Enable deglitching of code coverage in combinatorial, non-clocked, processes. +; Default is no deglitching. +; CoverDeglitchOn = 1 + +; Control the code coverage deglitching period. A period of 0, eliminates delta +; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a +; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". +; CoverDeglitchPeriod = 0 + +; Turn on code coverage in VLOG `celldefine modules, modules containing +; specify blocks, and modules included using vlog -v and -y. Default is off. +; CoverCells = 1 + +; Enable code coverage reporting of code that has been optimized away. +; The default is not to report. +; CoverReportCancelled = 1 + +; Control compiler and VOPT optimizations that are allowed when +; code coverage is on. This is a number from 0 to 5, with the following +; meanings (the default is 3): +; 5 -- All allowable optimizations are on. +; 4 -- Turn off removing unreferenced code. +; 3 -- Turn off process, always block and if statement merging. +; 2 -- Turn off expression optimization, converting primitives +; to continuous assignments, VHDL subprogram inlining. +; and VHDL clkOpt (converting FF's to builtins). +; 1 -- Turn off continuous assignment optimizations and clock suppression. +; 0 -- Turn off Verilog module inlining and VHDL arch inlining. +; HOWEVER, if fsm coverage is turned on, optimizations will be forced to +; level 3, with also turning off converting primitives to continuous assigns. +; CoverOpt = 3 + +; Specify the override for the default value of "cross_num_print_missing" +; option for the Cross in Covergroups. If not specified then LRM default +; value of 0 (zero) is used. This is a compile time option. +; SVCrossNumPrintMissingDefault = 0 + +; Setting following to 1 would cause creation of variables which +; would represent the value of Coverpoint expressions. This is used +; in conjunction with "SVCoverpointExprVariablePrefix" option +; in the modelsim.ini +; EnableSVCoverpointExprVariable = 0 + +; Specify the override for the prefix used in forming the variable names +; which represent the Coverpoint expressions. This is used in conjunction with +; "EnableSVCoverpointExprVariable" option of the modelsim.ini +; The default prefix is "expr". +; The variable name is +; variable name => <prefix>_<coverpoint name> +; SVCoverpointExprVariablePrefix = expr + +; Override for the default value of the SystemVerilog covergroup, +; coverpoint, and cross option.goal (defined to be 100 in the LRM). +; NOTE: It does not override specific assignments in SystemVerilog +; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal" +; in the [vsim] section can override this value. +; SVCovergroupGoalDefault = 100 + +; Override for the default value of the SystemVerilog covergroup, +; coverpoint, and cross type_option.goal (defined to be 100 in the LRM) +; NOTE: It does not override specific assignments in SystemVerilog +; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal" +; in the [vsim] section can override this value. +; SVCovergroupTypeGoalDefault = 100 + +; Specify the override for the default value of "strobe" option for the +; Covergroup Type. This is a compile time option which forces "strobe" to +; a user specified default value and supersedes SystemVerilog specified +; default value of '0'(zero). NOTE: This can be overriden by a runtime +; modelsim.ini variable "SVCovergroupStrobe" in the [vsim] section. +; SVCovergroupStrobeDefault = 0 + +; Specify the override for the default value of "per_instance" option for the +; Covergroup variables. This is a compile time option which forces "per_instance" +; to a user specified default value and supersedes SystemVerilog specified +; default value of '0'(zero). +; SVCovergroupPerInstanceDefault = 0 + +; Specify the override for the default value of "get_inst_coverage" option for the +; Covergroup variables. This is a compile time option which forces +; "get_inst_coverage" to a user specified default value and supersedes +; SystemVerilog specified default value of '0'(zero). +; SVCovergroupGetInstCoverageDefault = 0 + +; +; A space separated list of resource libraries that contain precompiled +; packages. The behavior is identical to using the "-L" switch. +; +; LibrarySearchPath = <path/lib> [<path/lib> ...] +LibrarySearchPath = mtiAvm mtiRnm mtiOvm mtiUvm mtiUPF infact + +; The behavior is identical to the "-mixedansiports" switch. Default is off. +; MixedAnsiPorts = 1 + +; Enable SystemVerilog 3.1a $typeof() function. Default is off. +; EnableTypeOf = 1 + +; Only allow lower case pragmas. Default is disabled. +; AcceptLowerCasePragmaOnly = 1 + +; Set the maximum depth permitted for a recursive include file nesting. +; IncludeRecursionDepthMax = 5 + +; Turn ON detection of FSMs having single bit current state variable. +; FsmSingle = 1 + +; Turn off reset state transitions in FSM. +; FsmResetTrans = 0 + +; Turn off detections of FSMs having x-assignment. +; FsmXAssign = 0 + +; Turn ON detection of FSM Implicit Transitions. +; FsmImplicitTrans = 1 + +; List of file suffixes which will be read as SystemVerilog. White space +; in extensions can be specified with a back-slash: "\ ". Back-slashes +; can be specified with two consecutive back-slashes: "\\"; +; SvFileSuffixes = sv svp svh + +; This setting is the same as the vlog -sv command line switch. +; Enables SystemVerilog features and keywords when true (1). +; When false (0), the rules of IEEE Std 1364-2005 are followed and +; SystemVerilog keywords are ignored. +; Svlog = 0 + +; Prints attribute placed upon SV packages during package import +; when true (1). The attribute will be ignored when this +; entry is false (0). The attribute name is "mti_design_element_load_message". +; The value of this attribute is a string literal. +; Default is true (1). +; PrintSVPackageLoadingAttribute = 1 + +; Do not show immediate assertions with constant expressions in +; GUI/reports/UCDB etc. By default immediate assertions with constant +; expressions are shown in GUI/reports/UCDB etc. This does not affect +; evaluation of immediate assertions. +; ShowConstantImmediateAsserts = 0 + +; Controls if untyped parameters that are initialized with values greater +; than 2147483647 are mapped to generics of type INTEGER or ignored. +; If mapped to VHDL Integers, values greater than 2147483647 +; are mapped to negative values. +; Default is to map these parameter to generic of type INTEGER +; ForceUnsignedToVHDLInteger = 1 + +; Enable AMS wreal (wired real) extensions. Default is 0. +; WrealType = 1 + +; Controls SystemVerilog Language Extensions. These options enable +; some non-LRM compliant behavior. +; SvExtensions = [+|-]<extension>[,[+|-]<extension>]* + +; Generate symbols debugging database in only some special cases to save on +; the number of files in the library. For other design-units, this database is +; generated on-demand in vsim. +; Default is to to generate debugging database for all design-units. +; SmartDbgSym = 1 + +; Controls how $unit library entries are named. Valid options are: +; "file" (generate name based on the first file on the command line) +; "du" (generate name based on first design unit following an item +; found in $unit scope) +; CUAutoName = file + +; Enable or disable automatic creation of missing libraries. +; Default is 1 (enabled) +; CreateLib = 1 + +; Enable generating a warning when a module is overwritten in different vlog sessions in case +; the RTL source files are different. +; Default is 0 (disabled) +; WarnDuOverwrite = 1 + +[sccom] +; Enable use of SCV include files and library. Default is off. +; UseScv = 1 + +; Add C++ compiler options to the sccom command line by using this variable. +; CppOptions = -g + +; Use custom C++ compiler located at this path rather than the default path. +; The path should point directly at a compiler executable. +; CppPath = /usr/bin/g++ + +; Specify the compiler version from the list of support GNU compilers. +; examples 4.7.4, 5.3.0, 7.4.0 +; CppInstall = 7.4.0 + +; Enable verbose messages from sccom. Default is off. +; SccomVerbose = 1 + +; sccom logfile. Default is no logfile. +; SccomLogfile = sccom.log + +; Enable use of SC_MS include files and library. Default is off. +; UseScMs = 1 + +; Enable compiler statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list,kb] +; Add '-' to disable specific statistics. Default is [time,cmd,msg]. +; Stats = time,cmd,msg + +; Enable or disable automatic creation of missing libraries. +; Default is 1 (enabled) +; CreateLib = 1 + +; Enable use of UVMC library. Default is off. +; UseUvmc = 1 + +[vopt] +; Check vopt plusargs. Default is 0 (off). +; The command line equivalent is -check_plusargs <number>. +; 0 = Don't check plusargs (this is the default) +; 1 = Warning on unrecognized plusarg +; 2 = Error and exit on unrecognized plusarg +; CheckPlusargs = 1 + +; Turn on code coverage in vopt. Default is off. +; Coverage = sbceft + +; enable or disable param saving in UCDB. +; CoverageSaveParam = 0 + +; Control compiler optimizations that are allowed when +; code coverage is on. Refer to the comment for this in the [vlog] area. +; CoverOpt = 3 + +; Controls set of CoverConstructs that are being considered for Coverage +; Collection. +; Some of Valid options are: default,set1,set2 +; Covermode = default + +; Override all PA VOPT and VSIM commands to run simulation in Non-PA mode. +; NonPAmode = 1 + +; Controls set of HDL cover constructs that would be considered(or not considered) +; for Coverage Collection. (Default corresponds to covermode default). +; Some of Valid options are: "ca", "citf", "cifl", "tcint", "fsmqs". +; Coverconstruct = noca,nocitf,nofsmtf,nofsmds,noctes,nocicl,nocprc,nocfl,nofsmup,nocifl,nocpm,notcint,nocpkg,nocsva + +; Increase or decrease the maximum number of rows allowed in a UDP table +; implementing a VHDL condition coverage or expression coverage expression. +; More rows leads to a longer compile time, but more expressions covered. +; CoverMaxUDPRows = 192 + +; Increase or decrease the maximum number of input patterns that are present +; in FEC table. This leads to a longer compile time with more expressions +; covered with FEC metric. +; CoverMaxFECRows = 192 + +; Enable Multi Bit Expression Coverage in a Design, If design has expression with +; multi bit operands, this option enables its Expression Coverage. +; The default value is 0. +; CoverFecMultiBit = 1 + +; Increase or decrease the limit on the size of expressions and conditions +; considered for expression and condition coverages. Higher FecUdpEffort leads +; to higher compile, optimize and simulation time, but more expressions and +; conditions are considered for coverage in the design. FecUdpEffort can +; be set to a number ranging from 1 (low) to 3 (high), defined as: +; 1 - (low) Only small expressions and conditions considered for coverage. +; 2 - (medium) Bigger expressions and conditions considered for coverage. +; 3 - (high) Very large expressions and conditions considered for coverage. +; The default setting is 1 (low). +; FecUdpEffort = 1 + +; Enable code coverage reporting of code that has been optimized away. +; The default is not to report. +; CoverReportCancelled = 1 + +; Enable deglitching of code coverage in combinatorial, non-clocked, processes. +; Default is no deglitching. +; CoverDeglitchOn = 1 + +; Enable compiler statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list,kb] +; Add '-' to disable specific statistics. Default is [time,cmd,msg]. +; Stats = time,cmd,msg + +; Control the code coverage deglitching period. A period of 0, eliminates delta +; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a +; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". +; CoverDeglitchPeriod = 0 + +; Do not show immediate assertions with constant expressions in +; GUI/reports/UCDB etc. By default immediate assertions with constant +; expressions are shown in GUI/reports/UCDB etc. This does not affect +; evaluation of immediate assertions. +; ShowConstantImmediateAsserts = 0 + +; Set the maximum number of iterations permitted for a generate loop. +; Restricting this permits the implementation to recognize infinite +; generate loops. +; GenerateLoopIterationMax = 100000 + +; Set the maximum depth permitted for a recursive generate instantiation. +; Restricting this permits the implementation to recognize infinite +; recursions. +; GenerateRecursionDepthMax = 200 + +; Set the number of processes created during the code generation phase. +; By default a heuristic is used to set this value. This may be set to 0 +; to disable this feature completely. +; ParallelJobs = 0 + +; Controls SystemVerilog Language Extensions. These options enable +; some non-LRM compliant behavior. +; SvExtensions = [+|-]<extension>[,[+|-]<extension>]* + +; Load the specified shared objects with the RTLD_GLOBAL flag. +; This gives global visibility to all symbols in the shared objects, +; meaning that subsequently loaded shared objects can bind to symbols +; in the global shared objects. The list of shared objects should +; be whitespace delimited. This option is not supported on the +; Windows or AIX platforms. +; GlobalSharedObjectList = example1.so example2.so example3.so + +; Disable SystemVerilog elaboration system task messages +; IgnoreSVAInfo = 1 +; IgnoreSVAWarning = 1 +; IgnoreSVAError = 1 +; IgnoreSVAFatal = 1 + +; Enable or disable automatic creation of missing libraries. +; Default is 1 (enabled) +; CreateLib = 1 + +[vsim] +; vopt flow +; Set to turn on automatic optimization of a design. +; Default is on +VoptFlow = 1 + +; Simulator resolution +; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. +Resolution = ns + +; Disable certain code coverage exclusions automatically. +; Assertions and FSM are exluded from the code coverage by default +; Set AutoExclusionsDisable = fsm to enable code coverage for fsm +; Set AutoExclusionsDisable = assertions to enable code coverage for assertions +; Set AutoExclusionsDisable = all to enable code coverage for all the automatic exclusions +; Or specify comma or space separated list +;AutoExclusionsDisable = fsm,assertions + +; User time unit for run commands +; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the +; unit specified for Resolution. For example, if Resolution is 100ps, +; then UserTimeUnit defaults to ps. +; Should generally be set to default. +UserTimeUnit = default + +; Default run length +RunLength = 10 us + +; Maximum iterations that can be run without advancing simulation time +IterationLimit = 10000000 + +; Specify libraries to be searched for precompiled modules +; LibrarySearchPath = <path/lib> [<path/lib> ...] + +; Set XPROP assertion fail limit. Default is 5. +; Any positive integer, -1 for infinity. +; XpropAssertionLimit = 5 + +; Control PSL and Verilog Assume directives during simulation +; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts +; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts +; SimulateAssumeDirectives = 1 + +; Control the simulation of PSL and SVA +; These switches can be overridden by the vsim command line switches: +; -psl, -nopsl, -sva, -nosva. +; Set SimulatePSL = 0 to disable PSL simulation +; Set SimulatePSL = 1 to enable PSL simulation (default) +; SimulatePSL = 1 +; Set SimulateSVA = 0 to disable SVA simulation +; Set SimulateSVA = 1 to enable concurrent SVA simulation (default) +; SimulateSVA = 1 + +; Control SVA and VHDL immediate assertion directives during simulation +; Set SimulateImmedAsserts = 0 to disable simulation of immediate asserts +; Set SimulateImmedAsserts = 1 to enable simulation of immediate asserts +; SimulateImmedAsserts = 1 + +; License feature mappings for Verilog and VHDL +; qhsimvh Single language VHDL license +; qhsimvl Single language Verilog license +; msimhdlsim Language neutral license for either Verilog or VHDL +; msimhdlmix Second language only, language neutral license for either +; Verilog or VHDL +; +; Directives to license manager can be set either as single value or as +; space separated multi-values: +; vhdl Immediately checkout and hold a VHDL license (i.e., one of +; qhsimvh, msimhdlsim, or msimhdlmix) +; vlog Immediately checkout and hold a Verilog license (i.e., one of +; qhsimvl, msimhdlsim, or msimhdlmix) +; plus Immediately checkout and hold a VHDL license and a Verilog license +; noqueue Do not wait in the license queue when a license is not available +; viewsim Try for viewer license but accept simulator license(s) instead +; of queuing for viewer license (PE ONLY) +; noviewer Disable checkout of msimviewer license feature (PE ONLY) +; noslvhdl Disable checkout of qhsimvh license feature +; noslvlog Disable checkout of qhsimvl license feature +; nomix Disable checkout of msimhdlmix license feature +; nolnl Disable checkout of msimhdlsim license feature +; mixedonly Disable checkout of qhsimvh and qhsimvl license features +; lnlonly Disable checkout of qhsimvh,qhsimvl, and msimhdlmix license features +; +; Examples (remove ";" comment character to activate licensing directives): +; Single directive: +; License = plus +; Multi-directive (Note: space delimited directives): +; License = noqueue plus + +; Severity level of a VHDL assertion message or of a SystemVerilog severity system task +; which will cause a running simulation to stop. +; VHDL assertions and SystemVerilog severity system task that occur with the +; given severity or higher will cause a running simulation to stop. +; This value is ignored during elaboration. +; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal +BreakOnAssertion = 3 + +; Severity level of a tool message which will cause a running simulation to +; stop. This value is ignored during elaboration. Default is to not break. +; 0 = Note 1 = Warning 2 = Error 3 = Fatal +;BreakOnMessage = 2 + +; The class debug feature enables more visibility and tracking of class instances +; during simulation. By default this feature is disabled (0). To enable this +; feature set ClassDebug to 1. +; ClassDebug = 1 + +; Message Format conversion specifications: +; %S - Severity Level of message/assertion +; %R - Text of message +; %T - Time of message +; %D - Delta value (iteration number) of Time +; %K - Kind of path: Instance/Region/Signal/Process/Foreign Process/Unknown/Protected +; %i - Instance/Region/Signal pathname with Process name (if available) +; %I - shorthand for one of these: +; " %K: %i" +; " %K: %i File: %F" (when path is not Process or Signal) +; except that the %i in this case does not report the Process name +; %O - Process name +; %P - Instance/Region path without leaf process +; %F - File name +; %L - Line number; if assertion message, then line number of assertion or, if +; assertion is in a subprogram, line from which the call is made +; %u - Design unit name in form library.primary +; %U - Design unit name in form library.primary(secondary) +; %% - The '%' character itself +; +; If specific format for Severity Level is defined, use that format. +; Else, for a message that occurs during elaboration: +; -- Failure/Fatal message in VHDL region that is not a Process, and in +; certain non-VHDL regions, uses MessageFormatBreakLine; +; -- Failure/Fatal message otherwise uses MessageFormatBreak; +; -- Note/Warning/Error message uses MessageFormat. +; Else, for a message that occurs during runtime and triggers a breakpoint because +; of the BreakOnAssertion setting: +; -- if in a VHDL region that is not a Process, uses MessageFormatBreakLine; +; -- otherwise uses MessageFormatBreak. +; Else (a runtime message that does not trigger a breakpoint) uses MessageFormat. +; +; MessageFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n" +; MessageFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n" +; MessageFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormatBreakLine = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F Line: %L\n" +; MessageFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" + +; Error File - alternate file for storing error messages +; ErrorFile = error.log + +; Simulation Breakpoint messages +; This flag controls the display of function names when reporting the location +; where the simulator stops because of a breakpoint or fatal error. +; Example with function name: # Break in Process ctr at counter.vhd line 44 +; Example without function name: # Break at counter.vhd line 44 +; Default value is 1. +ShowFunctions = 1 + +; Default radix for all windows and commands. +; Radix may be one of: symbolic, ascii, binary, octal, decimal, hex, unsigned +; Flags may be one of: enumnumeric, showbase, wreal +DefaultRadix = hexadecimal +DefaultRadixFlags = showbase +; Set to 1 for make the signal_force VHDL and Verilog functions use the +; default radix when processing the force value. Prior to 10.2 signal_force +; used the default radix, now it always uses symbolic unless value explicitly indicates base +;SignalForceFunctionUseDefaultRadix = 0 + +; VSIM Startup command +; Startup = do startup.do + +; VSIM Shutdown file +; Filename to save u/i formats and configurations. +; ShutdownFile = restart.do +; To explicitly disable auto save: +; ShutdownFile = --disable-auto-save + +; Run simulator in batch mode as if -batch were specified on the command line if none of -c, -gui, or -i specified. +; Simulator runs in interactive mode as if -i were specified if this option is 0. Default is 0. +; BatchMode = 1 + +; File for saving command transcript when -batch option used +; This option is ignored when -c, -gui, or -i options are used or if BatchMode above is zero +; default is unset so command transcript only goes to stdout for better performance +; BatchTranscriptFile = transcript + +; File for saving command transcript, this option is ignored when -batch option is used +TranscriptFile = transcript + +; Transcript file long line wrapping mode(s) +; mode == 0 :: no wrapping, line recorded as is +; mode == 1 :: wrap at first whitespace after WSColumn +; or at Column. +; mode == 2 :: wrap as above, but add continuation +; character ('\') at end of each wrapped line +; +; WrapMode = 0 +; WrapColumn = 30000 +; WrapWSColumn = 27000 + +; File for saving command history +; CommandHistory = cmdhist.log + +; Specify whether paths in simulator commands should be described +; in VHDL or Verilog format. +; For VHDL, PathSeparator = / +; For Verilog, PathSeparator = . +; Must not be the same character as DatasetSeparator. +PathSeparator = / + +; Specify the dataset separator for fully rooted contexts. +; The default is ':'. For example: sim:/top +; Must not be the same character as PathSeparator. +DatasetSeparator = : + +; Specify a unique path separator for the Signal Spy set of functions. +; The default will be to use the PathSeparator variable. +; Must not be the same character as DatasetSeparator. +; SignalSpyPathSeparator = / + +; Used to control parsing of HDL identifiers input to the tool. +; This includes CLI commands, vsim/vopt/vlog/vcom options, +; string arguments to FLI/VPI/DPI calls, etc. +; If set to 1, accept either Verilog escaped Id syntax or +; VHDL extended id syntax, regardless of source language. +; If set to 0, the syntax of the source language must be used. +; Each identifier in a hierarchical name may need different syntax, +; e.g. "/top/\vhdl*ext*id\/middle/\vlog*ext*id /bottom" or +; "top.\vhdl*ext*id\.middle.\vlog*ext*id .bottom" +; GenerousIdentifierParsing = 1 + +; Disable VHDL assertion messages +; IgnoreNote = 1 +; IgnoreWarning = 1 +; IgnoreError = 1 +; IgnoreFailure = 1 + +; Disable SystemVerilog assertion messages +; IgnoreSVAInfo = 1 +; IgnoreSVAWarning = 1 +; IgnoreSVAError = 1 +; IgnoreSVAFatal = 1 + +; Do not print any additional information from Severity System tasks. +; Only the message provided by the user is printed along with severity +; information. +; SVAPrintOnlyUserMessage = 1; + +; Default force kind. May be freeze, drive, deposit, or default +; or in other terms, fixed, wired, or charged. +; A value of "default" will use the signal kind to determine the +; force kind, drive for resolved signals, freeze for unresolved signals +; DefaultForceKind = freeze + +; Control the iteration of events when a VHDL signal is forced to a value +; This flag can be set to honour the signal update event in next iteration, +; the default is to update and propagate in the same iteration. +; ForceSigNextIter = 1 + +; Enable simulation statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list,kb,eor] +; Add '-' to disable specific statistics. Default is [time,cmd,msg]. +; Stats = time,cmd,msg + +; If zero, open files when elaborated; otherwise, open files on +; first read or write. Default is 0. +; DelayFileOpen = 1 + +; Control VHDL files opened for write. +; 0 = Buffered, 1 = Unbuffered +UnbufferedOutput = 0 + +; Control the number of VHDL files open concurrently. +; This number should always be less than the current ulimit +; setting for max file descriptors. +; 0 = unlimited +ConcurrentFileLimit = 40 + +; If nonzero, close files as soon as there is either an explicit call to +; file_close, or when the file variable's scope is closed. When zero, a +; file opened in append mode is not closed in case it is immediately +; reopened in append mode; otherwise, the file will be closed at the +; point it is reopened. +; AppendClose = 1 + +; Control the number of hierarchical regions displayed as +; part of a signal name shown in the Wave window. +; A value of zero tells VSIM to display the full name. +; The default is 0. +; WaveSignalNameWidth = 0 + +; Turn off warnings when changing VHDL constants and generics +; Default is 1 to generate warning messages +; WarnConstantChange = 0 + +; Turn off warnings from accelerated versions of the std_logic_arith, +; std_logic_unsigned, and std_logic_signed packages. +; StdArithNoWarnings = 1 + +; Turn off warnings from accelerated versions of the IEEE numeric_std +; and numeric_bit packages. +; NumericStdNoWarnings = 1 + +; Use old-style (pre-6.6) VHDL FOR GENERATE statement iteration names +; in the design hierarchy. +; This style is controlled by the value of the GenerateFormat +; value described next. Default is to use new-style names, which +; comprise the generate statement label, '(', the value of the generate +; parameter, and a closing ')'. +; Set this to 1 to use old-style names. +; OldVhdlForGenNames = 1 + +; Control the format of the old-style VHDL FOR generate statement region +; name for each iteration. Do not quote the value. +; The format string here must contain the conversion codes %s and %d, +; in that order, and no other conversion codes. The %s represents +; the generate statement label; the %d represents the generate parameter value +; at a particular iteration (this is the position number if the generate parameter +; is of an enumeration type). Embedded whitespace is allowed (but discouraged); +; leading and trailing whitespace is ignored. +; Application of the format must result in a unique region name over all +; loop iterations for a particular immediately enclosing scope so that name +; lookup can function properly. The default is %s__%d. +; GenerateFormat = %s__%d + +; Enable more efficient logging of VHDL Variables. +; Logging VHDL variables without this enabled, while possible, is very +; inefficient. Enabling this will provide a more efficient logging methodology +; at the expense of more memory usage. By default this feature is disabled (0). +; To enabled this feature, set this variable to 1. +; VhdlVariableLogging = 1 + +; Enable logging of VHDL access type variables and their designated objects. +; This setting will allow both variables of an access type ("access variables") +; and their designated objects ("access objects") to be logged. Logging a +; variable of an access type will automatically also cause the designated +; object(s) of that variable to be logged as the simulation progresses. +; Further, enabling this allows access objects to be logged by name. By default +; this feature is disabled (0). To enable this feature, set this variable to 1. +; Enabling this will automatically enable the VhdlVariableLogging feature also. +; AccessObjDebug = 1 + +; Make each VHDL package in a PDU has its own separate copy of the package instead +; of sharing the package between PDUs. The default is to share packages. +; To ensure that each PDU has its own set of packages, set this variable to 1. +; VhdlSeparatePduPackage = 1 + +; Specify whether checkpoint files should be compressed. +; The default is 1 (compressed). +; CheckpointCompressMode = 0 + +; Specify gcc compiler used in the compilation of automatically generated DPI exportwrapper. +; Use custom gcc compiler located at this path rather than the default path. +; The path should point directly at a compiler executable. +; DpiCppPath = <your-gcc-installation>/bin/gcc +; +; Specify the compiler version from the list of support GNU compilers. +; examples 4.7.4, 5.3.0, 7.4.0 +; DpiCppInstall = 7.4.0 + +; Specify whether to enable SystemVerilog DPI "out-of-the-blue" calls. +; The term "out-of-the-blue" refers to SystemVerilog export function calls +; made from C functions that don't have the proper context setup +; (as is the case when running under "DPI-C" import functions). +; When this is enabled, one can call a DPI export function +; (but not task) from any C code. +; the setting of this variable can be one of the following values: +; 0 : dpioutoftheblue call is disabled (default) +; 1 : dpioutoftheblue call is enabled, but export call debug support is not available. +; 2 : dpioutoftheblue call is enabled, and limited export call debug support is available. +; DpiOutOfTheBlue = 1 + +; Specify whether continuous assignments are run before other normal priority +; processes scheduled in the same iteration. This event ordering minimizes race +; differences between optimized and non-optimized designs, and is the default +; behavior beginning with the 6.5 release. For pre-6.5 event ordering, set +; ImmediateContinuousAssign to 0. +; The default is 1 (enabled). +; ImmediateContinuousAssign = 0 + +; List of dynamically loaded objects for Verilog PLI applications +; Veriuser = veriuser.sl + +; Which default VPI object model should the tool conform to? +; The 1364 modes are Verilog-only, for backwards compatibility with older +; libraries, and SystemVerilog objects are not available in these modes. +; +; In the absence of a user-specified default, the tool default is the +; latest available LRM behavior. +; Options for PliCompatDefault are: +; VPI_COMPATIBILITY_VERSION_1364v1995 +; VPI_COMPATIBILITY_VERSION_1364v2001 +; VPI_COMPATIBILITY_VERSION_1364v2005 +; VPI_COMPATIBILITY_VERSION_1800v2005 +; VPI_COMPATIBILITY_VERSION_1800v2008 +; +; Synonyms for each string are also recognized: +; VPI_COMPATIBILITY_VERSION_1364v1995 (1995, 95, 1364v1995, 1364V1995, VL1995) +; VPI_COMPATIBILITY_VERSION_1364v2001 (2001, 01, 1364v2001, 1364V2001, VL2001) +; VPI_COMPATIBILITY_VERSION_1364v2005 (1364v2005, 1364V2005, VL2005) +; VPI_COMPATIBILITY_VERSION_1800v2005 (2005, 05, 1800v2005, 1800V2005, SV2005) +; VPI_COMPATIBILITY_VERSION_1800v2008 (2008, 08, 1800v2008, 1800V2008, SV2008) + + +; PliCompatDefault = VPI_COMPATIBILITY_VERSION_1800v2005 + +; Specify whether the Verilog system task $fopen or vpi_mcd_open() +; will create directories that do not exist when opening the file +; in "a" or "w" mode. +; The default is 0 (do not create non-existent directories) +; CreateDirForFileAccess = 1 + +; Specify default options for the restart command. Options can be one +; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions +; DefaultRestartOptions = -force + + +; Specify default UVM-aware debug options if the vsim -uvmcontrol switch is not used. +; Valid options include: all, none, verbose, disable, struct, reseed, msglog, trlog, certe. +; Options can be enabled by just adding the name, or disabled by prefixing the option with a "-". +; The list of options must be delimited by commas, without spaces or tabs. +; +; Some examples +; To turn on all available UVM-aware debug features: +; UVMControl = all +; To turn on the struct window, mesage logging, and transaction logging: +; UVMControl = struct,msglog,trlog +; To turn on all options except certe: +; UVMControl = all,-certe +; To completely disable all UVM-aware debug functionality: +; UVMControl = disable + +; Specify the WildcardFilter setting. +; A space separated list of object types to be excluded when performing +; wildcard matches with log, wave, etc commands. The default value for this variable is: +; "Variable Constant Generic Parameter SpecParam Memory Assertion Cover Endpoint ScVariable CellInternal ImmediateAssert VHDLFile" +; See "Using the WildcardFilter Preference Variable" in the documentation for +; details on how to use this variable and for descriptions of the filter types. +WildcardFilter = Variable Constant Generic Parameter SpecParam Memory Assertion Cover Endpoint ScVariable CellInternal ImmediateAssert VHDLFile + +; Specify the WildcardSizeThreshold setting. +; This integer setting specifies the size at which objects will be excluded when +; performing wildcard matches with log, wave, etc commands. Objects of size equal +; to or greater than the WildcardSizeThreshold will be filtered out from the wildcard +; matches. The size is a simple calculation of number of bits or items in the object. +; The default value is 8k (8192). Setting this value to 0 will disable the checking +; of object size against this threshold and allow all objects of any size to be logged. +WildcardSizeThreshold = 8192 + +; Specify whether warning messages are output when objects are filtered out due to the +; WildcardSizeThreshold. The default is 0 (no messages generated). +WildcardSizeThresholdVerbose = 0 + +; Turn on (1) or off (0) WLF file compression. +; The default is 1 (compress WLF file). +; WLFCompress = 0 + +; Specify whether to save all design hierarchy (1) in the WLF file +; or only regions containing logged signals (0). +; The default is 0 (save only regions with logged signals). +; WLFSaveAllRegions = 1 + +; WLF file time limit. Limit WLF file by time, as closely as possible, +; to the specified amount of simulation time. When the limit is exceeded +; the earliest times get truncated from the file. +; If both time and size limits are specified the most restrictive is used. +; UserTimeUnits are used if time units are not specified. +; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} +; WLFTimeLimit = 0 + +; WLF file size limit. Limit WLF file size, as closely as possible, +; to the specified number of megabytes. If both time and size limits +; are specified then the most restrictive is used. +; The default is 0 (no limit). +; WLFSizeLimit = 1000 + +; Specify whether or not a WLF file should be deleted when the +; simulation ends. A value of 1 will cause the WLF file to be deleted. +; The default is 0 (do not delete WLF file when simulation ends). +; WLFDeleteOnQuit = 1 + +; Specify whether or not a WLF file should be optimized during +; simulation. If set to 0, the WLF file will not be optimized. +; The default is 1, optimize the WLF file. +; WLFOptimize = 0 + +; Specify the name of the WLF file. +; The default is vsim.wlf +; WLFFilename = vsim.wlf + +; Specify whether to lock the WLF file. +; Locking the file prevents other invocations of ModelSim/Questa tools from +; inadvertently overwriting the WLF file. +; The default is 1, lock the WLF file. +; WLFFileLock = 0 + +; Specify the update interval for the WLF file in live simulation. +; The interval is given in seconds. +; The value is the smallest interval between WLF file updates. The WLF file +; will be flushed (updated) after (at least) the interval has elapsed, ensuring +; that the data is correct when viewed from a separate viewer. +; A value of 0 means that no updating will occur. +; The default value is 10 seconds. +; WLFUpdateInterval = 10 + +; Specify the WLF cache size limit for WLF files. +; The value is given in megabytes. A value of 0 turns off the cache. +; On non-Windows platforms the default WLFCacheSize setting is 2000 (megabytes). +; On Windows, the default value is 1000 (megabytes) to help to avoid filling +; process memory. +; WLFSimCacheSize allows a different cache size to be set for a live simulation +; WLF file, independent of post-simulation WLF file viewing. If WLFSimCacheSize +; is not set, it defaults to the WLFCacheSize value. +; WLFCacheSize = 2000 +; WLFSimCacheSize = 500 + +; Specify the WLF file event collapse mode. +; 0 = Preserve all events and event order. (same as -wlfnocollapse) +; 1 = Only record values of logged objects at the end of a simulator iteration. +; (same as -wlfcollapsedelta) +; 2 = Only record values of logged objects at the end of a simulator time step. +; (same as -wlfcollapsetime) +; The default is 1. +; WLFCollapseMode = 0 + +; Specify whether WLF file logging can use threads on multi-processor machines. +; If 0, no threads will be used; if 1, threads will be used if the system has +; more than one processor. +; WLFUseThreads = 1 + +; Specify the size of objects that will trigger "large object" messages +; at log/wave/list time. The size calculation of the object is the same as that +; used by the WildcardSizeThreshold. The default LargeObjectSize size is 500,000. +; Setting LargeObjectSize to 0 will disable these messages. +; LargeObjectSize = 500000 + +; Specify the depth of stack frames returned by $stacktrace([level]). +; This depth will be picked up when the optional 'level' argument +; is not specified or its value is not a positive integer. +; StackTraceDepth = 100 + +; Turn on/off undebuggable SystemC type warnings. Default is on. +; ShowUndebuggableScTypeWarning = 0 + +; Turn on/off unassociated SystemC name warnings. Default is off. +; ShowUnassociatedScNameWarning = 1 + +; Turn on/off SystemC IEEE 1666 deprecation warnings. Default is off. +; ScShowIeeeDeprecationWarnings = 1 + +; Turn on/off the check for multiple drivers on a SystemC sc_signal. Default is off. +; For SystemC-2.3.2 the valid values are 0,1 and 2 +; 0 = SC_SIGNAL_WRITE_CHECK_DISABLE_ +; 1 = SC_SIGNAL_WRITE_CHECK_DEFAULT_ +; 2 = SC_SIGNAL_WRITE_CHECK_CONFLICT_ +; For SystemC-2.2 the valid values are 0 and 1 +; 0 = DISABLE +; 1 = ENABLE +; ScEnableScSignalWriteCheck = 1 + +; Set SystemC default time unit. +; Set to fs, ps, ns, us, ms, or sec with optional +; prefix of 1, 10, or 100. The default is 1 ns. +; The ScTimeUnit value is honored if it is coarser than Resolution. +; If ScTimeUnit is finer than Resolution, it is set to the value +; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns, +; then the default time unit will be 1 ns. However if Resolution +; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns. +ScTimeUnit = ns + +; Set SystemC sc_main stack size. The stack size is set as an integer +; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or +; Gb(Giga-byte). Default is 10 Mb. The stack size for sc_main depends +; on the amount of data on the sc_main() stack and the memory required +; to succesfully execute the longest function call chain of sc_main(). +ScMainStackSize = 10 Mb + +; Set SystemC thread stack size. The stack size is set as an integer +; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or +; Gb(Giga-byte). The stack size for sc_thread depends +; on the amount of data on the sc_thread stack and the memory required +; to succesfully execute the thread. +; ScStackSize = 1 Mb + +; Turn on/off execution of remainder of sc_main upon quitting the current +; simulation session. If the cumulative length of sc_main() in terms of +; simulation time units is less than the length of the current simulation +; run upon quit or restart, sc_main() will be in the middle of execution. +; This switch gives the option to execute the remainder of sc_main upon +; quitting simulation. The drawback of not running sc_main till the end +; is memory leaks for objects created by sc_main. If on, the remainder of +; sc_main will be executed ignoring all delays. This may cause the simulator +; to crash if the code in sc_main is dependent on some simulation state. +; Default is on. +ScMainFinishOnQuit = 1 + +; Enable calling of the DPI export taks/functions from the +; SystemC start_of_simulation() callback. +; The default is off. +; EnableDpiSosCb = 1 + + +; Set the SCV relationship name that will be used to identify phase +; relations. If the name given to a transactor relation matches this +; name, the transactions involved will be treated as phase transactions +ScvPhaseRelationName = mti_phase + +; Customize the vsim kernel shutdown behavior at the end of the simulation. +; Some common causes of the end of simulation are $finish (implicit or explicit), +; sc_stop(), tf_dofinish(), and assertion failures. +; This should be set to "ask", "exit", or "stop". The default is "ask". +; "ask" -- In batch mode, the vsim kernel will abruptly exit. +; In GUI mode, a dialog box will pop up and ask for user confirmation +; whether or not to quit the simulation. +; "stop" -- Cause the simulation to stay loaded in memory. This can make some +; post-simulation tasks easier. +; "exit" -- The simulation will abruptly exit without asking for any confirmation. +; "final" -- Run SystemVerilog final blocks then behave as "stop". +; Note: This variable can be overridden with the vsim "-onfinish" command line switch. +OnFinish = ask + +; Print pending deferred assertion messages. +; Deferred assertion messages may be scheduled after the $finish in the same +; time step. Deferred assertions scheduled to print after the $finish are +; printed before exiting with severity level NOTE since it's not known whether +; the assertion is still valid due to being printed in the active region +; instead of the reactive region where they are normally printed. +; OnFinishPendingAssert = 1; + +; Print "simstats" result. Default is 0. +; 0 == do not print simstats +; 1 == print at end of simulation +; 2 == print at end of each run command and end of simulation +; PrintSimStats = 1 + +; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages +; AssertFile = assert.log + +; Enable assertion counts. Default is off. +; AssertionCounts = 1 + +; Run simulator in assertion debug mode. Default is off. +; AssertionDebug = 1 + +; Turn on/off PSL/SVA/VHDL assertion enable. Default is on. +; AssertionEnable = 0 + +; Set PSL/SVA/VHDL concurrent assertion fail limit. Default is -1. +; Any positive integer, -1 for infinity. +; AssertionLimit = 1 + +; Turn on/off concurrent assertion pass log. Default is off. +; Assertion pass logging is only enabled when assertion is browseable +; and assertion debug is enabled. +; AssertionPassLog = 1 + +; Turn on/off PSL concurrent assertion fail log. Default is on. +; The flag does not affect SVA +; AssertionFailLog = 0 + +; Turn on/off SVA concurrent assertion local var printing in -assertdebug mode. Default is on. +; AssertionFailLocalVarLog = 0 + +; Set action type for PSL/SVA concurrent assertion fail action. Default is continue. +; 0 = Continue 1 = Break 2 = Exit +; AssertionFailAction = 1 + +; Enable the active thread monitor in the waveform display when assertion debug is enabled. +; AssertionActiveThreadMonitor = 1 + +; Control how many waveform rows will be used for displaying the active threads. Default is 5. +; AssertionActiveThreadMonitorLimit = 5 + +; Assertion thread limit after which assertion would be killed/switched off. +; The default is -1 (unlimited). If the number of threads for an assertion go +; beyond this limit, the assertion would be either switched off or killed. This +; limit applies to only assert directives. +;AssertionThreadLimit = -1 + +; Action to be taken once the assertion thread limit is reached. Default +; is kill. It can have a value of off,kill or killon. In case of kill, all the existing +; threads are terminated and no new attempts are started. In case of off, the +; existing attempts keep on evaluating but no new attempts are started. In case of killon, +; all the existing threads are terminated but new attempts are started. This +; variable applies to only assert directives. +;AssertionThreadLimitAction = kill + +; Cover thread limit after which cover would be killed/switched off. +; The default is -1 (unlimited). If the number of threads for a cover go +; beyond this limit, the cover would be either switched off or killed. This +; limit applies to only cover directives. +;CoverThreadLimit = -1 + +; Action to be taken once the cover thread limit is reached. Default +; is kill. It can have a value of off, kill or killon. In case of kill, all the existing +; threads are terminated and no new attempts are started. In case of off, the +; existing attempts keep on evaluating but no new attempts are started. In case of killon, +; all the existing threads are terminated but new attempts are started. This +; variable applies to only cover directives. +;CoverThreadLimitAction = kill + + +; By default immediate assertions do not participate in Assertion Coverage calculations +; unless they are executed. This switch causes all immediate assertions in the design +; to participate in Assertion Coverage calculations, whether attempted or not. +; UnattemptedImmediateAssertions = 0 + +; By default immediate covers participate in Coverage calculations +; whether they are attempted or not. This switch causes all unattempted +; immediate covers in the design to stop participating in Coverage +; calculations. +; UnattemptedImmediateCovers = 0 + +; By default pass action block is not executed for assertions on vacuous +; success. The following variable is provided to enable execution of +; pass action block on vacuous success. The following variable is only effective +; if the user does not disable pass action block execution by using either +; system tasks or CLI. Also there is a performance penalty for enabling +; the following variable. +;AssertionEnableVacuousPassActionBlock = 1 + +; As per strict 1850-2005 PSL LRM, an always property can either pass +; or fail. However, by default, Questa reports multiple passes and +; multiple fails on top always/never property (always/never operator +; is the top operator under Verification Directive). The reason +; being that Questa reports passes and fails on per attempt of the +; top always/never property. Use the following flag to instruct +; Questa to strictly follow LRM. With this flag, all assert/never +; directives will start an attempt once at start of simulation. +; The attempt can either fail, match or match vacuously. +; For e.g. if always is the top operator under assert, the always will +; keep on checking the property at every clock. If the property under +; always fails, the directive will be considered failed and no more +; checking will be done for that directive. A top always property, +; if it does not fail, will show a pass at end of simulation. +; The default value is '0' (i.e. zero is off). For example: +; PslOneAttempt = 1 + +; Specify the number of clock ticks to represent infinite clock ticks. +; This affects eventually!, until! and until_!. If at End of Simulation +; (EOS) an active strong-property has not clocked this number of +; clock ticks then neither pass or fail (vacuous match) is returned +; else respective fail/pass is returned. The default value is '0' (zero) +; which effectively does not check for clock tick condition. For example: +; PslInfinityThreshold = 5000 + +; Control how many thread start times will be preserved for ATV viewing for a given assertion +; instance. Default is -1 (ALL). +; ATVStartTimeKeepCount = -1 + +; Turn on/off code coverage +; CodeCoverage = 0 + +; This option applies to condition and expression coverage UDP tables. It +; has no effect unless UDP is enabled for coverage with vcom/vlog/vopt -coverudp. +; If this option is used and a match occurs in more than one row in the UDP table, +; none of the counts for all matching rows is incremented. By default, counts are +; incremented for all matching rows. +; CoverCountAll = 1 + +; Turn off automatic inclusion of VHDL integers in toggle coverage. Default +; is to include them. +; ToggleNoIntegers = 1 + +; Set the maximum number of values that are collected for toggle coverage of +; VHDL integers. Default is 100; +; ToggleMaxIntValues = 100 + +; Set the maximum number of values that are collected for toggle coverage of +; Verilog real. Default is 100; +; ToggleMaxRealValues = 100 + +; Turn on automatic inclusion of Verilog integers in toggle coverage, except +; for enumeration types. Default is to include them. +; ToggleVlogIntegers = 0 + +; Turn on automatic inclusion of Verilog real type in toggle coverage, except +; for shortreal types. Default is to not include them. +; ToggleVlogReal = 1 + +; Turn on automatic inclusion of Verilog fixed-size unpacked arrays, VHDL multi-d arrays +; and VHDL arrays-of-arrays in toggle coverage. +; Default is to not include them. +; ToggleFixedSizeArray = 1 + +; Increase or decrease the maximum size of Verilog unpacked fixed-size arrays, +; VHDL multi-d arrays and VHDL arrays-of-arrays that are included for toggle coverage. +; This leads to a longer simulation time with bigger arrays covered with toggle coverage. +; Default is 1024. +; ToggleMaxFixedSizeArray = 1024 + +; Treat Verilog multi-dimensional packed vectors and packed structures as equivalently sized +; one-dimensional packed vectors for toggle coverage. Default is 0. +; TogglePackedAsVec = 0 + +; Treat Verilog enumerated types as equivalently sized one-dimensional packed vectors for +; toggle coverage. Default is 0. +; ToggleVlogEnumBits = 0 + +; Turn off automatic inclusion of VHDL records in toggle coverage. +; Default is to include them. +; ToggleVHDLRecords = 0 + +; Limit the widths of registers automatically tracked for toggle coverage. Default is 128. +; For unlimited width, set to 0. +; ToggleWidthLimit = 128 + +; Limit the counts that are tracked for toggle coverage. When all edges for a bit have +; reached this count, further activity on the bit is ignored. Default is 1. +; For unlimited counts, set to 0. +; ToggleCountLimit = 1 + +; Change the mode of extended toggle coverage. Default is 3. Valid modes are 1, 2 and 3. +; Following is the toggle coverage calculation criteria based on extended toggle mode: +; Mode 1: 0L->1H & 1H->0L & any one 'Z' transition (to/from 'Z'). +; Mode 2: 0L->1H & 1H->0L & one transition to 'Z' & one transition from 'Z'. +; Mode 3: 0L->1H & 1H->0L & all 'Z' transitions. +; ExtendedToggleMode = 3 + +; Enable toggle statistics collection only for ports. Default is 0. +; TogglePortsOnly = 1 + +; Limit the counts that are tracked for Focussed Expression Coverage. When a bin has +; reached this count, further tracking of the input patterns linked to it is ignored. +; Default is 1. For unlimited counts, set to 0. +; NOTE: Changing this value from its default value may affect simulation performance. +; FecCountLimit = 1 + +; Limit the counts that are tracked for UDP Coverage. When a bin has +; reached this count, further tracking of the input patterns linked to it is ignored. +; Default is 1. For unlimited counts, set to 0. +; NOTE: Changing this value from its default value may affect simulation performance. +; UdpCountLimit = 1 + +; Control toggle coverage deglitching period. A period of 0, eliminates delta +; cycle glitches. This is the default. The value of ToggleDeglitchPeriod needs to be either +; 0 or a time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". +; ToggleDeglitchPeriod = 10.0ps + +; Turn on/off all PSL/SVA cover directive enables. Default is on. +; CoverEnable = 0 + +; Turn on/off PSL/SVA cover log. Default is off "0". +; CoverLog = 1 + +; Set "at_least" value for all PSL/SVA cover directives. Default is 1. +; CoverAtLeast = 2 + +; Set "limit" value for all PSL/SVA cover directives. Default is -1. +; Any positive integer, -1 for infinity. +; CoverLimit = 1 + +; Specify the coverage database filename. +; Default is "" (i.e. database is NOT automatically saved on close). +; UCDBFilename = vsim.ucdb + +; Specify the maximum limit for the number of Cross (bin) products reported +; in XML and UCDB report against a Cross. A warning is issued if the limit +; is crossed. Default is zero. vsim switch -cvgmaxrptrhscross can override this +; setting. +; MaxReportRhsSVCrossProducts = 1000 + +; Specify the override for the "auto_bin_max" option for the Covergroups. +; If not specified then value from Covergroup "option" is used. +; SVCoverpointAutoBinMax = 64 + +; Specify the override for the value of "cross_num_print_missing" +; option for the Cross in Covergroups. If not specified then value +; specified in the "option.cross_num_print_missing" is used. This +; is a runtime option. NOTE: This overrides any "cross_num_print_missing" +; value specified by user in source file and any SVCrossNumPrintMissingDefault +; specified in modelsim.ini. +; SVCrossNumPrintMissing = 0 + +; Specify whether to use the value of "cross_num_print_missing" +; option in report and GUI for the Cross in Covergroups. If not specified then +; cross_num_print_missing is ignored for creating reports and displaying +; covergroups in GUI. Default is 0, which means ignore "cross_num_print_missing". +; UseSVCrossNumPrintMissing = 0 + +; Specify the threshold of Coverpoint wildcard bin value range size, above which +; a warning will be triggered. The default is 4K -- 12 wildcard bits. +; SVCoverpointWildCardBinValueSizeWarn = 4096 + +; Specify the override for the value of "strobe" option for the +; Covergroup Type. If not specified then value in "type_option.strobe" +; will be used. This is runtime option which forces "strobe" to +; user specified value and supersedes user specified values in the +; SystemVerilog Code. NOTE: This also overrides the compile time +; default value override specified using "SVCovergroupStrobeDefault" +; SVCovergroupStrobe = 0 + +; Override for explicit assignments in source code to "option.goal" of +; SystemVerilog covergroup, coverpoint, and cross. It also overrides the +; default value of "option.goal" (defined to be 100 in the SystemVerilog +; LRM) and the value of modelsim.ini variable "SVCovergroupGoalDefault". +; SVCovergroupGoal = 100 + +; Override for explicit assignments in source code to "type_option.goal" of +; SystemVerilog covergroup, coverpoint, and cross. It also overrides the +; default value of "type_option.goal" (defined to be 100 in the SystemVerilog +; LRM) and the value of modelsim.ini variable "SVCovergroupTypeGoalDefault". +; SVCovergroupTypeGoal = 100 + +; Enforce the 6.3 behavior of covergroup get_coverage() and get_inst_coverage() +; builtin functions, and report. This setting changes the default values of +; option.get_inst_coverage and type_option.merge_instances to ensure the 6.3 +; behavior if explicit assignments are not made on option.get_inst_coverage and +; type_option.merge_instances by the user. There are two vsim command line +; options, -cvg63 and -nocvg63 to override this setting from vsim command line. +; The default value of this variable from release 6.6 onwards is 0. This default +; drives compliance with the clarified behavior in the IEEE 1800-2009 standard. +; SVCovergroup63Compatibility = 0 + +; Enforce the default behavior of covergroup get_coverage() builtin function, GUI +; and report. This variable sets the default value of type_option.merge_instances. +; There are two vsim command line options, -cvgmergeinstances and +; -nocvgmergeinstances to override this setting from vsim command line. +; The default value of this variable, -1 (don't care), allows the tool to determine +; the effective value, based on factors related to capacity and optimization. +; The type_option.merge_instances appears in the GUI and coverage reports as either +; auto(1) or auto(0), depending on whether the effective value was determined to +; be a 1 or a 0. +; SVCovergroupMergeInstancesDefault = -1 + +; Enable or disable generation of more detailed information about the sampling +; of covergroup, cross, and coverpoints. It provides the details of the number +; of times the covergroup instance and type were sampled, as well as details +; about why covergroup, cross and coverpoint were not covered. A non-zero value +; is to enable this feature. 0 is to disable this feature. Default is 0 +; SVCovergroupSampleInfo = 0 + +; Specify the maximum number of Coverpoint bins in whole design for +; all Covergroups. +; MaxSVCoverpointBinsDesign = 2147483648 + +; Specify maximum number of Coverpoint bins in any instance of a Covergroup, default is 2^10 bins +; MaxSVCoverpointBinsInst = 1048576 + +; Specify the maximum number of Cross bins in whole design for +; all Covergroups. +; MaxSVCrossBinsDesign = 2147483648 + +; Specify maximum number of Cross bins in any instance of a Covergroup, default is 2^16 bins +; MaxSVCrossBinsInst = 67108864 + +; Specify whether vsim will collect the coverage data of zero-weight coverage items or not. +; By default, this variable is set 0, in which case option.no_collect setting will take effect. +; If this variable is set to 1, all zero-weight coverage items will not be saved. +; Note that the usage of vsim switch -cvgzwnocollect, if present, will override the setting +; of this variable. +; CvgZWNoCollect = 1 + +; Specify a space delimited list of double quoted TCL style +; regular expressions which will be matched against the text of all messages. +; If any regular expression is found to be contained within any message, the +; status for that message will not be propagated to the UCDB TESTSTATUS. +; If no match is detected, then the status will be propagated to the +; UCDB TESTSTATUS. More than one such regular expression text is allowed, +; and each message text is compared for each regular expression in the list. +; UCDBTestStatusMessageFilter = "Done with Test Bench" "Ignore .* message" + +; Set weight for all PSL/SVA cover directives. Default is 1. +; CoverWeight = 2 + +; Check vsim plusargs. Default is 0 (off). +; The command line equivalent is -check_plusargs <number>. +; 0 = Don't check plusargs (this is the default) +; 1 = Warning on unrecognized plusarg +; 2 = Error and exit on unrecognized plusarg +; CheckPlusargs = 1 + +; Load the specified shared objects with the RTLD_GLOBAL flag. +; This gives global visibility to all symbols in the shared objects, +; meaning that subsequently loaded shared objects can bind to symbols +; in the global shared objects. The list of shared objects should +; be whitespace delimited. This option is not supported on the +; Windows or AIX platforms. +; GlobalSharedObjectList = example1.so example2.so example3.so + +; Generate the stub definitions for the undefined symbols in the shared libraries being +; loaded in the simulation. When this flow is turned on, the undefined symbols will not +; prevent vsim from loading. Calling undefined symbols at runtime will cause fatal error. +; The valid arguments are: on, off, verbose. +; on : turn on the automatic generation of stub definitions. +; off: turn off the flow. The undefined symbols will trigger an immediate load failure. +; verbose: Turn on the flow and report the undefined symbols for each shared library. +; NOTE: This variable can be overriden with vsim switch "-undefsyms". +; The default is on. +; +; UndefSyms = off + +; Enable the support for automatically checkpointing foreign C/C++ libraries. +; The valid arguments are: 0, 1, 2 +; 0: off (default) +; 1: on (manually save/restore user shared library data) +; 2: auto (automatically save/restore user shared library data) +; This option is not supported on the Windows platforms. +; +; AllowCheckpointCpp = 2 + +; Initial seed for the random number generator of the root thread (SystemVerilog). +; NOTE: This variable can be overridden with the vsim "-sv_seed" command line switch. +; The default value is 0. +; Sv_Seed = 0 + +; Specify the solver "engine" that vsim will select for constrained random +; generation. +; Valid values are: +; "auto" - automatically select the best engine for the current +; constraint scenario +; "bdd" - evaluate all constraint scenarios using the BDD solver engine +; "act" - evaluate all constraint scenarios using the ACT solver engine +; While the BDD solver engine is generally efficient with constraint scenarios +; involving bitwise logical relationships, the ACT solver engine can exhibit +; superior performance with constraint scenarios involving large numbers of +; random variables related via arithmetic operators (+, *, etc). +; NOTE: This variable can be overridden with the vsim "-solveengine" command +; line switch. +; The default value is "auto". +; SolveEngine = auto + +; Specify the maximum size that a random dynamic array or queue may be resized +; to by the solver. If the solver attempts to resize a dynamic array or queue +; to a size greater than the specified limit, an error will be issued and +; randomize() will fail. The default value is 65535. A value of 0 disables the +; resize check (i.e. no error will be issued regardless of size). +; SolveArrayResizeMax = 65535 + +; Specify the maximum size that a random dynamic array or queue may be resized +; to by the solver without a warning. If the solver attempts to resize a dynamic +; array or queue to a size greater than the specified limit, a warning will be +; issued. The default value is 65535. A value of 0 disables the resize check +; (i.e. no warning will be issued regardless of size). +; SolveArrayResizeWarn = 65535 + +; Specify error message severity when randomize() and randomize(null) failures +; are detected. +; +; Integer value up to two digits are allowed with each digit having the following legal values: +; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal +; +; 1) When a value with two digits is used, the digit at tenth place (leftmost digit) represents +; the severtity setting for normal randomize() calls. The digit at ones place (rightmost digit) +; represents the setting for randomize(null) calls. +; +; 2) When a single digit value is used, the setting is applied to both normal randomize() call +; and randomize(null) call. +; +; Example: Fatal error for randomize() failures and NO error for randomize(null) failures +; -solvefailseverity=40 +; +; NOTE: SolveFailSeverity can affect the behavior of SolveFailDebug. When SolveFailDebug is +; enabled, a constraint contradiction report will be displayed for randomize() calls that +; have a message severity >= warning (i.e. constraint contradiction reports will not be +; generated for randomize() calls having a "no error" severity level) +; +; NOTE: This variable can be overridden with the vsim "-solvefailseverity" command +; line switch. +; +; The default is 1 (warning). +; SolveFailSeverity = 1 + +; Error message severity for suppressible errors that are detected in a +; solve/before constraint. +; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal +; NOTE: This variable can be overridden with the vsim "-solvebeforeerrorseverity" +; command line switch. +; The default is 2 (error). +; SolveBeforeErrorSeverity = 2 + +; Error message severity for suppressible errors that are related to +; solve engine capacity limits +; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal +; NOTE: This variable can be overridden with the vsim "-solveengineerrorseverity" +; command line switch. +; The default is 2 (error). +; SolveEngineErrorSeverity = 2 + +; Enable/disable constraint conflicts on randomize() failure +; Valid values: +; 0 - disable solvefaildebug +; 1 - basic debug (no performance penalty) +; 2 - enhanced debug (runtime performance penalty) +; +; NOTE: SolveFailSeverity can affect the behavior of SolveFailDebug. When SolveFailDebug is +; enabled, a constraint contradiction report will be displayed for randomize() calls that +; have a message severity >= warning (i.e. constraint contradiction reports will not be +; generated for randomize() calls having a "no error" severity level) +; +; NOTE: This variable can be overridden with the vsim "-solvefaildebug" command +; line switch. +; +; The default is 1 (basic debug). +; SolveFailDebug = 1 + +; Upon encountering a randomize() failure, generate a simplified testcase that +; will reproduce the failure. Optionally output the testcase to a file. +; Testcases for 'no-solution' failures will only be produced if SolveFailDebug +; is enabled (see above). +; NOTE: This variable can be overridden with the vsim "-solvefailtestcase" +; command line switch. +; The default is OFF (do not generate a testcase). To enable testcase +; generation, uncomment this variable. To redirect testcase generation to a +; file, specify the name of the output file. +; SolveFailTestcase = + +; Specify solver timeout threshold (in seconds). randomize() will fail if the +; CPU time required to evaluate the call exceeds the specified timeout. +; The default value is 1000. A value of 0 will disable timeout failures. +; SolveTimeout = 1000 + +; Specify the alternative behavior during solver replay. Must be used when combined with -solvereplay switch. +; Valid <opt> settings: +; validate : toggle the checking of value changes of non-random variables involved in randomize(). (default is off)" +; SolveReplayOpt=[+|-]<option>[,[+|-]<option>]* + +; Switch to specify options that control the behavior of the solver profiler. +; Valid options are: +; cputime - use CPU time instead of elapsed time (wall time) to measure performance data (default is off) +; randsets - enable detailed profiling of randsets (default is off) +; testgen - generate randset testcases (only when 'randsets' option is enabled, default is off) +; SolverFProf = [+|-]<option>[,[+|-]<option>]* + +; Specify the maximum size of the solution graph generated by the BDD solver. +; This value can be used to force the BDD solver to abort the evaluation of a +; complex constraint scenario that cannot be evaluated with finite memory. +; This value is specified in 1000s of nodes. +; The default value is 10000. A value of 0 indicates no limit. +; SolveGraphMaxSize = 10000 + +; Specify the maximum number of evaluations that may be performed on the +; solution graph by the BDD solver. This value can be used to force the BDD +; solver to abort the evaluation of a complex constraint scenario that cannot +; be evaluated in finite time. This value is specified in 10000s of evaluations. +; The default value is 10000. A value of 0 indicates no limit. +; SolveGraphMaxEval = 10000 + +; Specify random sequence compatiblity with a prior release. This +; option is used to get the same random sequences during simulation as +; as a prior release. Only prior releases with the same major version +; as the current release are allowed. +; NOTE: This variable can be overridden with the vsim "-solverev" command +; line switch. +; Default value set to "" (no compatibility). +; SolveRev = + +; Environment variable expansion of command line arguments has been deprecated +; in favor shell level expansion. Universal environment variable expansion +; inside -f files is support and continued support for MGC Location Maps provide +; alternative methods for handling flexible pathnames. +; The following line may be uncommented and the value set to 1 to re-enable this +; deprecated behavior. The default value is 0. +; DeprecatedEnvironmentVariableExpansion = 0 + +; Specify the memory threshold for the System Verilog garbage collector. +; The value is the number of megabytes of class objects that must accumulate +; before the garbage collector is run. +; The GCThreshold setting is used when class debug mode is disabled to allow +; less frequent garbage collection and better simulation performance. +; The GCThresholdClassDebug setting is used when class debug mode is enabled +; to allow for more frequent garbage collection. +; GCThreshold = 100 +; GCThresholdClassDebug = 5 + +; Turn on/off collapsing of bus ports in VCD dumpports output +DumpportsCollapse = 1 + +; Location of Multi-Level Verification Component (MVC) installation. +; The default location is the product installation directory. +MvcHome = $QUESTA_MVC_HOME + +; Location of InFact installation. The default is $MODEL_TECH/../../infact +; +; InFactHome = $MODEL_TECH/../../infact + +; Initialize SystemVerilog enums using the base type's default value +; instead of the leftmost value. +; EnumBaseInit = 1 + +; Suppress file type registration. +; SuppressFileTypeReg = 1 + +; Controls SystemVerilog Language Extensions. These options enable +; some non-LRM compliant behavior. +; SvExtensions = [+|-]<extension>[,[+|-]<extension>]* + +; Enable/disable non-LRM compliant SystemVerilog constrained-random language extensions. +; Valid extensions are: +; arraymode - consider rand_mode of unpacked array field independently from its elements +; deepcheck - allow randomize(null) to recursively consider constraints from member rand class handles (Default) +; dynext - enhanced evaluation for constraints involving random dynamic arrays that are resized during randomize() +; funcback - enable function backtracking (ACT only) +; nodist - interpret 'dist' constraint as 'inside' (ACT only) +; noorder - ignore solve/before ordering constraints (ACT only) +; oobidx - allow out-of-bounds value for an indexed-expression with random indices if indexed-expression yields a 2-state packed type +; prerandfirst - execute all pre_randomize() functions before evaluating any constraints (Default) +; promotedist - promote priority of 'dist' constraint if LHS has no solve/before +; purecheck - suppress pre_randomize() and post_randomize() calls for randomize(null) +; randcext - allow 'randc' and other 'rand' variables to be solved in the same randset (Default) +; randindex - allow random index in constraint (Default) +; randstruct - consider all fields of unpacked structs as 'rand' +; skew - skew randomize results (ACT only) +; srandom - interpret $srandom(seed) system task calls as equivalent process::self().srandom(seed) calls (Default) +; strictstab - strict random stability +; SvRandExtensions = [+|-]<extension>[,[+|-]<extension>]* + +; Controls the formatting of '%p' and '%P' conversion specification, used in $display +; and similar system tasks. +; 1. SVPrettyPrintFlags=I<n><S|T> use <n> spaces(S) or tabs(T) per indentation level. +; The 'I' flag when present causes relevant data types to be expanded and indented into +; a more readable format. +; (e.g. SVPrettyPrintFlags=I4S will cause 4 spaces to be used per indentation level). +; 2. SVPrettyPrintFlags=L<numLines> limits the output to <numLines> lines. +; (e.g. SVPrettyPrintFlags=L20 will limit the output to 20 lines). +; 3. SVPrettyPrintFlags=C<numChars> limits the output to <numChars> characters. +; (e.g. SVPrettyPrintFlags=C256 will limit the output to 256 characters). +; 4. SVPrettyPrintFlags=F<numFields> limits the output to <numFields> of relevant datatypes +; (e.g. SVPrettyPrintFlags=F4 will limit the output to 4 fields of a structure). +; 5. SVPrettyPrintFlags=E<numElements> limits the output to <numElements> of relevant datatypes +; (e.g. SVPrettyPrintFlags=E50 will limit the output to 50 elements of an array). +; 6. SVPrettyPrintFlags=D<depth> suppresses the output of sub-elements below <depth>. +; (e.g. SVPrettyPrintFlags=D5 will suppresses the output of sub elements below a depth of 5). +; 7. SVPrettyPrintFlags=R<specifier> shows the output of specifier %p as per the specifed radix. +; It changes the output in $display and similar systasks. It does not affect formatted output functions ($displayh etc)). +; (e.g. SVPrettyPrintFlags=Rb will show the output of %p specifier in binary format. +; 8. Items 1-7 above can be combined as a comma separated list. +; (e.g. SVPrettyPrintFlags=I4S,L20,C256,F4,E50,D5,Rb) +; SVPrettyPrintFlags=I4S + +[lmc] +; The simulator's interface to Logic Modeling's SmartModel SWIFT software +libsm = $MODEL_TECH/libsm.sl +; The simulator's interface to Logic Modeling's SmartModel SWIFT software (Windows NT) +; libsm = $MODEL_TECH/libsm.dll +; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700) +; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl +; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000) +; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o +; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris) +; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so +; Logic Modeling's SmartModel SWIFT software (Windows NT) +; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll +; Logic Modeling's SmartModel SWIFT software (non-Enterprise versions of Linux) +; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so +; Logic Modeling's SmartModel SWIFT software (Enterprise versions of Linux) +; libswift = $LMC_HOME/lib/linux.lib/libswift.so + +; The simulator's interface to Logic Modeling's hardware modeler SFI software +libhm = $MODEL_TECH/libhm.sl +; The simulator's interface to Logic Modeling's hardware modeler SFI software (Windows NT) +; libhm = $MODEL_TECH/libhm.dll +; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700) +; libsfi = <sfi_dir>/lib/hp700/libsfi.sl +; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000) +; libsfi = <sfi_dir>/lib/rs6000/libsfi.a +; Logic Modeling's hardware modeler SFI software (Sun4 Solaris) +; libsfi = <sfi_dir>/lib/sun4.solaris/libsfi.so +; Logic Modeling's hardware modeler SFI software (Windows NT) +; libsfi = <sfi_dir>/lib/pcnt/lm_sfi.dll +; Logic Modeling's hardware modeler SFI software (Linux) +; libsfi = <sfi_dir>/lib/linux/libsfi.so + +[msg_system] +; Change a message severity or suppress a message. +; The format is: <msg directive> = <msg number>[,<msg number>...] +; suppress can be used to achieve +nowarn<CODE> functionality +; The format is: suppress = <CODE>,<msg number>,[<CODE>,<msg number>,...] +; Examples: +suppress = 8780 ;an explanation can be had by running: verror 8780 +; note = 3009 +; warning = 3033 +; error = 3010,3016 +; fatal = 3016,3033 +; suppress = 3009,3016,3601 +; suppress = 3009,CNNODP,3601,TFMPC +; suppress = 8683,8684 +; The command verror <msg number> can be used to get the complete +; description of a message. + +; Control transcripting of Verilog display system task messages and +; PLI/FLI print function call messages. The system tasks include +; $display[bho], $strobe[bho], $monitor[bho], and $write[bho]. They +; also include the analogous file I/O tasks that write to STDOUT +; (i.e. $fwrite or $fdisplay). The PLI/FLI calls include io_printf, +; vpi_printf, mti_PrintMessage, and mti_PrintFormatted. The default +; is to have messages appear only in the transcript. The other +; settings are to send messages to the wlf file only (messages that +; are recorded in the wlf file can be viewed in the MsgViewer) or +; to both the transcript and the wlf file. The valid values are +; tran {transcript only (default)} +; wlf {wlf file only} +; both {transcript and wlf file} +; displaymsgmode = tran + +; Control transcripting of elaboration/runtime messages not +; addressed by the displaymsgmode setting. The default is to +; have messages appear only in the transcript. The other settings +; are to send messages to the wlf file only (messages that are +; recorded in the wlf file can be viewed in the MsgViewer) or to both +; the transcript and the wlf file. The valid values are +; tran {transcript only (default)} +; wlf {wlf file only} +; both {transcript and wlf file} +; msgmode = tran + +; Controls number of displays of a particluar message +; default value is 5 +; MsgLimitCount = 5 + +[utils] +; Default Library Type (while creating a library with "vlib") +; 0 - legacy library using subdirectories for design units +; 2 - flat library +; DefaultLibType = 2 + +; Flat Library Page Size (while creating a library with "vlib") +; Set the size in bytes for flat library file pages. Libraries containing +; very large files may benefit from a larger value. +; FlatLibPageSize = 8192 + +; Flat Library Page Cleanup Percentage (while creating a library with "vlib") +; Set the percentage of total pages deleted before library cleanup can occur. +; This setting is applied together with FlatLibPageDeleteThreshold. +; FlatLibPageDeletePercentage = 50 + +; Flat Library Page Cleanup Threshold (while creating a library with "vlib") +; Set the number of pages deleted before library cleanup can occur. +; This setting is applied together with FlatLibPageDeletePercentage. +; FlatLibPageDeleteThreshold = 1000 + +[Project] +** Warning: ; Warning -- Do not edit the project properties directly. +; Property names are dynamic in nature and property +; values have special syntax. Changing property data directly +; can result in a corrupt MPF file. All project properties +; can be modified through project window dialogs. +Project_Version = 6 +Project_DefaultLib = work +Project_SortMethod = unused +Project_Files_Count = 27 +Project_File_0 = C:/Projects/PrivateIsland/pi-betsy/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio.v +Project_File_P_0 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1752165667 cover_fsm 0 cover_branch 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 24 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_1 = C:/Projects/PrivateIsland/pi-betsy/src/sync_fifo.v +Project_File_P_1 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1752165667 cover_fsm 0 cover_branch 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 15 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_2 = C:/Projects/PrivateIsland/pi-betsy/src/dpram_inf.v +Project_File_P_2 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 last_compile 1754328280 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +define+SIMULATION=1 compile_order 2 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_3 = C:/Projects/PrivateIsland/pi-betsy/src/mdio.v +Project_File_P_3 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1752165667 cover_fsm 0 cover_branch 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 9 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_4 = C:/Projects/PrivateIsland/pi-betsy/src/switch.v +Project_File_P_4 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1754328280 cover_fsm 0 cover_branch 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 14 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_5 = C:/Projects/PrivateIsland/pi-betsy/src/udp_rx.v +Project_File_P_5 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1752165667 cover_fsm 0 cover_branch 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 16 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_6 = C:/Projects/PrivateIsland/pi-betsy/src/ethernet_params.v +Project_File_P_6 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1752165667 cover_fsm 0 cover_branch 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 4 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_7 = C:/Projects/PrivateIsland/pi-betsy/manufacturer/altera/cyclone10_lp/src/betsy.v +Project_File_P_7 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1754591995 cover_fsm 0 cover_branch 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +define+SIMULATION=1 compile_order 18 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_8 = C:/Projects/PrivateIsland/pi-betsy/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.v +Project_File_P_8 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1752165667 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 25 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_9 = C:/Projects/PrivateIsland/pi-betsy/src/pkt_filter.v +Project_File_P_9 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1752165667 cover_fsm 0 cover_branch 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 13 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_10 = C:/Projects/PrivateIsland/pi-betsy/src/fcs.v +Project_File_P_10 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1752165667 cover_fsm 0 cover_branch 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 5 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_11 = C:/Projects/PrivateIsland/pi-betsy/manufacturer/altera/cyclone10_lp/sim/src/tb.sv +Project_File_P_11 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1754328280 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 19 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_12 = C:/Projects/PrivateIsland/pi-betsy/src/ipv4_rx_c.v +Project_File_P_12 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1754328280 cover_fsm 0 cover_branch 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 8 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_13 = C:/Projects/PrivateIsland/pi-betsy/src/half_fifo.v +Project_File_P_13 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1752165667 cover_fsm 0 cover_branch 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 6 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_14 = C:/Projects/PrivateIsland/pi-betsy/src/cont_params.v +Project_File_P_14 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1754591995 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 20 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_15 = C:/Projects/PrivateIsland/pi-betsy/src/metrics.v +Project_File_P_15 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1754328280 cover_fsm 0 cover_branch 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 12 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_16 = C:/Projects/PrivateIsland/pi-betsy/src/mac_rgmii.v +Project_File_P_16 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1754328280 cover_fsm 0 cover_branch 0 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 21 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_17 = C:/Projects/PrivateIsland/pi-betsy/src/drop_fifo.v +Project_File_P_17 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1752274407 cover_fsm 0 cover_branch 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 3 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_18 = C:/Projects/PrivateIsland/pi-betsy/src/cam.v +Project_File_P_18 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1754328280 cover_fsm 0 cover_branch 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_19 = C:/Projects/PrivateIsland/pi-betsy/src/rgmii_params.v +Project_File_P_19 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 last_compile 1752165667 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 22 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_20 = C:/Projects/PrivateIsland/pi-betsy/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.v +Project_File_P_20 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1752165667 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 26 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_21 = C:/Projects/PrivateIsland/pi-betsy/manufacturer/altera/cyclone10_lp/ip/pll/pll.v +Project_File_P_21 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1752165667 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 23 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_22 = C:/Projects/PrivateIsland/pi-betsy/src/ipv4_rx.v +Project_File_P_22 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1754328280 cover_fsm 0 cover_branch 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 7 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_23 = C:/Projects/PrivateIsland/pi-betsy/src/mdio_cont.v +Project_File_P_23 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1754328280 cover_fsm 0 cover_branch 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 10 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_24 = C:/Projects/PrivateIsland/pi-betsy/src/udp_rx_c.v +Project_File_P_24 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1752165667 cover_fsm 0 cover_branch 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 17 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_25 = C:/Projects/PrivateIsland/pi-betsy/src/controller.v +Project_File_P_25 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 last_compile 1754945708 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_26 = C:/Projects/PrivateIsland/pi-betsy/src/mdio_data_ti.v +Project_File_P_26 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1752165667 cover_fsm 0 cover_branch 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 11 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_Sim_Count = 0 +Project_Folder_Count = 0 +Echo_Compile_Output = 0 +Save_Compile_Report = 1 +Project_Opt_Count = 0 +ForceSoftPaths = 0 +ProjectStatusDelay = 5000 +VERILOG_DoubleClick = Edit +VERILOG_CustomDoubleClick = +SYSTEMVERILOG_DoubleClick = Edit +SYSTEMVERILOG_CustomDoubleClick = +VHDL_DoubleClick = Edit +VHDL_CustomDoubleClick = +PSL_DoubleClick = Edit +PSL_CustomDoubleClick = +TEXT_DoubleClick = Edit +TEXT_CustomDoubleClick = +SYSTEMC_DoubleClick = Edit +SYSTEMC_CustomDoubleClick = +TCL_DoubleClick = Edit +TCL_CustomDoubleClick = +MACRO_DoubleClick = Edit +MACRO_CustomDoubleClick = +VCD_DoubleClick = Edit +VCD_CustomDoubleClick = +SDF_DoubleClick = Edit +SDF_CustomDoubleClick = +XML_DoubleClick = Edit +XML_CustomDoubleClick = +LOGFILE_DoubleClick = Edit +LOGFILE_CustomDoubleClick = +UCDB_DoubleClick = Edit +UCDB_CustomDoubleClick = +TDB_DoubleClick = Edit +TDB_CustomDoubleClick = +UPF_DoubleClick = Edit +UPF_CustomDoubleClick = +PCF_DoubleClick = Edit +PCF_CustomDoubleClick = +PROJECT_DoubleClick = Edit +PROJECT_CustomDoubleClick = +VRM_DoubleClick = Edit +VRM_CustomDoubleClick = +DEBUGDATABASE_DoubleClick = Edit +DEBUGDATABASE_CustomDoubleClick = +DEBUGARCHIVE_DoubleClick = Edit +DEBUGARCHIVE_CustomDoubleClick = +Project_Major_Version = 2024 +Project_Minor_Version = 3 diff --git a/manufacturer/altera/cyclone10_lp/sim/win/modelsim.ini b/manufacturer/altera/cyclone10_lp/sim/win/modelsim.ini new file mode 100644 index 0000000..61316b0 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/sim/win/modelsim.ini @@ -0,0 +1,2220 @@ +; vsim modelsim.ini file +[Version] +INIVersion = "QA Baseline: 2021.1 Beta - 4536908" + +; Copyright 1991-2020 Mentor Graphics Corporation +; +; All Rights Reserved. +; +; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF +; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. +; + +[Library] +others = $MODEL_TECH/../modelsim.ini +; +; VITAL concerns: +; +; The library ieee contains (among other packages) the packages of the +; VITAL 2000 standard. When a design uses VITAL 2000 exclusively, it should use +; the physical library ieee (recommended), or use the physical library +; vital2000, but not both. The design can use logical library ieee and/or +; vital2000 as long as each of these maps to the same physical library, either +; ieee or vital2000. +; +; A design using the 1995 version of the VITAL packages, whether or not +; it also uses the 2000 version of the VITAL packages, must have logical library +; name ieee mapped to physical library vital1995. (A design cannot use library +; vital1995 directly because some packages in this library use logical name ieee +; when referring to the other packages in the library.) The design source +; should use logical name ieee when referring to any packages there except the +; VITAL 2000 packages. Any VITAL 2000 present in the design must use logical +; name vital2000 (mapped to physical library vital2000) to refer to those +; packages. +; ieee = $MODEL_TECH/../vital1995 +; +; For compatiblity with previous releases, logical library name vital2000 maps +; to library vital2000 (a different library than library ieee, containing the +; same packages). +; A design should not reference VITAL from both the ieee library and the +; vital2000 library because the vital packages are effectively different. +; A design that references both the ieee and vital2000 libraries must have +; both logical names ieee and vital2000 mapped to the same library, either of +; these: +; $MODEL_TECH/../ieee +; $MODEL_TECH/../vital2000 +; + +; added mapping for ADMS + +;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers // Source files only for this release +;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release +;mvc_lib = $MODEL_TECH/../mvc_lib + +; Altera Primitive libraries +; +; VHDL Section +; +; +; Verilog Section +; + + +; Automatically perform logical->physical mapping for physical libraries that +; appear in -L/-Lf options with filesystem path delimiters (e.g. '.' or '/'). +; The tail of the filesystem path name is chosen as the logical library name. +; For example, in the command "vopt -L ./path/to/lib1 -o opttop top", +; vopt automatically performs the mapping "lib1 -> ./path/to/lib1". +; See the User Manual for more details. +; +; AutoLibMapping = 0 + +work = ./libraries/work/ +work_lib = ./libraries/work/ +ram_2port_2050 = ./libraries/ram_2port_2050 +dpram_2kx9 = ./libraries/dpram_2kx9 +altera_common_sv_packages = ./libraries/altera_common_sv_packages +altera_xcvr_atx_pll_a10_191 = ./libraries/altera_xcvr_atx_pll_a10_191 +gige_pll_atx = ./libraries/gige_pll_atx +altera_xcvr_fpll_a10_191 = ./libraries/altera_xcvr_fpll_a10_191 +gige_pll_fract = ./libraries/gige_pll_fract +altera_xcvr_reset_control_1911 = ./libraries/altera_xcvr_reset_control_1911 +gige_reset_cont = ./libraries/gige_reset_cont +altera_xcvr_native_a10_1911 = ./libraries/altera_xcvr_native_a10_1911 +gige_xcvr = ./libraries/gige_xcvr +altera_int_osc_1910 = ./libraries/altera_int_osc_1910 +internal_osc = ./libraries/internal_osc +param_ram = ./libraries/param_ram +sgmii_xcvr = ./libraries/sgmii_xcvr +altera_temp_sense_1910 = ./libraries/altera_temp_sense_1910 +temp_sensor = ./libraries/temp_sensor +[DefineOptionset] +; Define optionset entries for the various compilers, vmake, and vsim. +; These option sets can be used with the "-optionset <optionsetname>" syntax. +; i.e. +; vlog -optionset COMPILEDEBUG top.sv +; vsim -optionset UVMDEBUG my_top +; +; Following are some useful examples. + +; define a vsim optionset for uvm debugging +UVMDEBUG = -uvmcontrol=all -msgmode both -displaymsgmode both -classdebug -onfinish stop + +; define a vopt optionset for debugging +VOPTDEBUG = +acc -debugdb + +[encryption] +; For vencrypt and vhencrypt. + +; Controls whether to encrypt whole files by ignoring all protect directives +; (except "viewport" and "interface_viewport") that are present in the input. +; The default is 0, use embedded protect directives to control the encryption. +; Set this to 1 to encrypt whole files by ignoring embedded protect directives. +; wholefile = 0 + +; Sets the data_method to use for the symmetric session key. +; The session key is a symmetric key that is randomly generated for each +; protected region (envelope) and is the heart of all encryption. This is used +; to set the length of the session key to generate and use when encrypting the +; HDL text. Supported values are aes128, aes192, and aes256. +; data_method = aes128 + +; The following 2 are for specifying an IEEE Std. 1735 Version 2 (V2) encryption +; "recipe" comprising an optional common block, at least one tool block (which +; contains the key public key), and the text to be encrypted. The common block +; and any of the tool blocks may contain rights in the form of the "control" +; directive. The text to be encrypted is specified either by setting +; "wholefile" to 1 or by embedding protect "begin" and "end" directives in +; the input HDL files. + +; Common recipe specification file. This file is optional. Its presence will +; require at least one "toolblock" to be specified. +; Directives such as "author" "author_info" and "data_method", +; as well as the common block license specification, go in this file. +; common = <file name> + +; Tool block specification recipe(s). Public key file with optional tool block +; file name. May be multiply-defined; at least one tool block is required if +; a recipe is being specified. +; Key file is a file name with no extension (.deprecated or .active will be +; supplied by the encryption tool). +; Rights file name is optional. +; toolblock = <key file name>[,<rights file name>]{:<key file name>[,<rights file name>]} + +; Location of directory containing recipe files. +; The default location is in the product installation directory. +; keyring = $MODEL_TECH/../keyring + +; Enable encryption statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list] +; Add '-' to disable specific statistics. Default is [cmd,msg]. +Stats = cmd,msg + +[vcom] +; VHDL93 variable selects language version as the default. +; Default is VHDL-2002. +; Value of 0 or 1987 for VHDL-1987. +; Value of 1 or 1993 for VHDL-1993. +; Default or value of 2 or 2002 for VHDL-2002. +; Value of 3 or 2008 for VHDL-2008 +; Value of 4 or ams99 for VHDL-AMS-1999 +; Value of 5 or ams07 for VHDL-AMS-2007 +VHDL93 = 2002 + +; Ignore VHDL-2008 declaration of REAL_VECTOR in package STANDARD. Default is off. +; ignoreStandardRealVector = 1 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn off unbound-component warnings. Default is on. +; Show_Warning1 = 0 + +; Turn off process-without-a-wait-statement warnings. Default is on. +; Show_Warning2 = 0 + +; Turn off null-range warnings. Default is on. +; Show_Warning3 = 0 + +; Turn off no-space-in-time-literal warnings. Default is on. +; Show_Warning4 = 0 + +; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. +; Show_Warning5 = 0 + +; Turn off optimization for IEEE std_logic_1164 package. Default is on. +; Optimize_1164 = 0 + +; Enable compiler statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list] +; Add '-' to disable specific statistics. Default is [time,cmd,msg]. +; Stats = time,cmd,msg + +; Turn on resolving of ambiguous function overloading in favor of the +; "explicit" function declaration (not the one automatically created by +; the compiler for each type declaration). Default is off. +; The .ini file has Explicit enabled so that std_logic_signed/unsigned +; will match the behavior of synthesis tools. +Explicit = 1 + +; Turn off acceleration of the VITAL packages. Default is to accelerate. +; NoVital = 1 + +; Turn off VITAL compliance checking. Default is checking on. +; NoVitalCheck = 1 + +; Ignore VITAL compliance checking errors. Default is to not ignore. +; IgnoreVitalErrors = 1 + +; Turn off VITAL compliance checking warnings. Default is to show warnings. +; Show_VitalChecksWarnings = 0 + +; Turn off PSL assertion warning messages. Default is to show warnings. +; Show_PslChecksWarnings = 0 + +; Enable parsing of embedded PSL assertions. Default is enabled. +; EmbeddedPsl = 0 + +; Keep silent about case statement static warnings. +; Default is to give a warning. +; NoCaseStaticError = 1 + +; Keep silent about warnings caused by aggregates that are not locally static. +; Default is to give a warning. +; NoOthersStaticError = 1 + +; Treat as errors: +; case statement static warnings +; warnings caused by aggregates that are not locally static +; Overrides NoCaseStaticError, NoOthersStaticError settings. +; PedanticErrors = 1 + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on some limited synthesis rule compliance checking. Checks only: +; -- signals used (read) by a process must be in the sensitivity list +; CheckSynthesis = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +; Require the user to specify a configuration for all bindings, +; and do not generate a compile time default binding for the +; component. This will result in an elaboration error of +; 'component not bound' if the user fails to do so. Avoids the rare +; issue of a false dependency upon the unused default binding. +; RequireConfigForAllDefaultBinding = 1 + +; Perform default binding at compile time. +; Default is to do default binding at load time. +; BindAtCompile = 1; + +; Inhibit range checking on subscripts of arrays. Range checking on +; scalars defined with subtypes is inhibited by default. +; NoIndexCheck = 1 + +; Inhibit range checks on all (implicit and explicit) assignments to +; scalar objects defined with subtypes. +; NoRangeCheck = 1 + +; Set the prefix to be honored for synthesis/coverage pragma recognition. +; Default is "". +; AddPragmaPrefix = "" + +; Ignore synthesis and coverage pragmas with this prefix. +; Default is "". +; IgnorePragmaPrefix = "" + +; Turn on code coverage in VHDL design units. Default is off. +; Coverage = sbceft + +; Turn off code coverage in VHDL subprograms. Default is on. +; CoverSub = 0 + +; Automatically exclude VHDL case statement OTHERS choice branches. +; This includes OTHERS choices in selected signal assigment statements. +; Default is to not exclude. +; CoverExcludeDefault = 1 + +; Control compiler and VOPT optimizations that are allowed when +; code coverage is on. Refer to the comment for this in the [vlog] area. +; CoverOpt = 3 + +; Turn on or off clkOpt optimization for code coverage. Default is on. +; CoverClkOpt = 1 + +; Turn on or off clkOpt optimization builtins for code coverage. Default is on. +; CoverClkOptBuiltins = 0 + +; Inform code coverage optimizations to respect VHDL 'H' and 'L' +; values on signals in conditions and expressions, and to not automatically +; convert them to '1' and '0'. Default is to not convert. +; CoverRespectHandL = 0 + +; Increase or decrease the maximum number of rows allowed in a UDP table +; implementing a VHDL condition coverage or expression coverage expression. +; More rows leads to a longer compile time, but more expressions covered. +; CoverMaxUDPRows = 192 + +; Increase or decrease the maximum number of input patterns that are present +; in FEC table. This leads to a longer compile time with more expressions +; covered with FEC metric. +; CoverMaxFECRows = 192 + +; Increase or decrease the limit on the size of expressions and conditions +; considered for expression and condition coverages. Higher FecUdpEffort leads +; to higher compile, optimize and simulation time, but more expressions and +; conditions are considered for coverage in the design. FecUdpEffort can +; be set to a number ranging from 1 (low) to 3 (high), defined as: +; 1 - (low) Only small expressions and conditions considered for coverage. +; 2 - (medium) Bigger expressions and conditions considered for coverage. +; 3 - (high) Very large expressions and conditions considered for coverage. +; The default setting is 1 (low). +; FecUdpEffort = 1 + +; Enable or disable Focused Expression Coverage analysis for conditions and +; expressions. Focused Expression Coverage data is provided by default when +; expression and/or condition coverage is active. +; CoverFEC = 0 + +; Enable or disable UDP Coverage analysis for conditions and expressions. +; UDP Coverage data is disabled by default when expression and/or condition +; coverage is active. +; CoverUDP = 1 + +; Enable or disable Rapid Expression Coverage mode for conditions and expressions. +; Disabling this would convert non-masking conditions in FEC tables to matching +; input patterns. +; CoverREC = 1 + +; Enable or disable bit-blasting multi-bit operands of reduction prefix expressions +; for expression/condition coverage. +; NOTE: Enabling this may have a negative impact on simulation performance. +; CoverExpandReductionPrefix = 0 + +; Enable or disable short circuit evaluation of conditions and expressions when +; condition or expression coverage is active. Short circuit evaluation is enabled +; by default. +; CoverShortCircuit = 0 + +; Enable code coverage reporting of code that has been optimized away. +; The default is not to report. +; CoverReportCancelled = 1 + +; Enable deglitching of code coverage in combinatorial, non-clocked, processes. +; Default is no deglitching. +; CoverDeglitchOn = 1 + +; Control the code coverage deglitching period. A period of 0, eliminates delta +; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a +; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". +; CoverDeglitchPeriod = 0 + +; Use this directory for compiler temporary files instead of "work/_temp" +; CompilerTempDir = /tmp + +; Set this to cause the compilers to force data to be committed to disk +; when the files are closed. +; SyncCompilerFiles = 1 + +; Add VHDL-AMS declarations to package STANDARD +; Default is not to add +; AmsStandard = 1 + +; Range and length checking will be performed on array indices and discrete +; ranges, and when violations are found within subprograms, errors will be +; reported. Default is to issue warnings for violations, because subprograms +; may not be invoked. +; NoDeferSubpgmCheck = 0 + +; Turn ON detection of FSMs having single bit current state variable. +; FsmSingle = 1 + +; Turn off reset state transitions in FSM. +; FsmResetTrans = 0 + +; Turn ON detection of FSM Implicit Transitions. +; FsmImplicitTrans = 1 + +; Controls whether or not to show immediate assertions with constant expressions +; in GUI/report/UCDB etc. By default, immediate assertions with constant +; expressions are shown in GUI/report/UCDB etc. This does not affect +; evaluation of immediate assertions. +; ShowConstantImmediateAsserts = 0 + +; Controls how VHDL basic identifiers are stored with the design unit. +; Does not make the language case-sensitive, affects only how declarations +; declared with basic identifiers have their names stored and printed +; (in the GUI, examine, etc.). +; Default is to preserve the case as originally depicted in the VHDL source. +; Value of 0 indicates to change all basic identifiers to lower case. +; PreserveCase = 0 + +; For Configuration Declarations, controls the effect that USE clauses have +; on visibility inside the configuration items being configured. If 1 +; (the default), then use pre-10.0 behavior. If 0, then for stricter LRM-compliance, +; extend the visibility of objects made visible through USE clauses into nested +; component configurations. +; OldVHDLConfigurationVisibility = 0 + +; Allows VHDL configuration declarations to be in a different library from +; the corresponding configured entity. Default is to not allow this for +; stricter LRM-compliance. +; SeparateConfigLibrary = 1; + +; Determine how mode OUT subprogram parameters of type array and record are treated. +; If 0 (the default), then only VHDL 2008 will do this initialization. +; If 1, always initialize the mode OUT parameter to its default value. +; If 2, do not initialize the mode OUT out parameter. +; Note that prior to release 10.1, all language versions did not initialize mode +; OUT array and record type parameters, unless overridden here via this mechanism. +; In release 10.1 and later, only files compiled with VHDL 2008 will cause this +; initialization, unless overridden here. +; InitOutCompositeParam = 0 + +; Generate symbols debugging database in only some special cases to save on +; the number of files in the library. For other design-units, this database is +; generated on-demand in vsim. +; Default is to to generate debugging database for all design-units. +; SmartDbgSym = 1 + +; Enable or disable automatic creation of missing libraries. +; Default is 1 (enabled) +; CreateLib = 1 + +; Describe compilation options according to matching file patterns. +; File pattern * matches all printing characters other than '/'. +; File pattern **/x matches all paths containing file/directory x. +; File pattern x/** matches all paths beginning at directory x. +; FileOptMap = (**/*.vhd => -2008); + +; Describe library targets of compilation according to matching file patterns. +; LibMap = (**/*.vhd => work); + +[vlog] +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on Verilog hazard checking (order-dependent accessing of global vars). +; Default is off. +; Hazard = 1 + +; Turn on converting regular Verilog identifiers to uppercase. Allows case +; insensitivity for module names. Default is no conversion. +; UpCase = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn on bad option warning. Default is off. +; Show_BadOptionWarning = 1 + +; Revert back to IEEE 1364-1995 syntax, default is 0 (off). +; vlog95compat = 1 + +; Turn off PSL warning messages. Default is to show warnings. +; Show_PslChecksWarnings = 0 + +; Enable parsing of embedded PSL assertions. Default is enabled. +; EmbeddedPsl = 0 + +; Enable compiler statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list,kb] +; Add '-' to disable specific statistics. Default is [time,cmd,msg]. +; Stats = time,cmd,msg + +; Set the threshold for automatically identifying sparse Verilog memories. +; A memory with total size in bytes equal to or more than the sparse memory +; threshold gets marked as sparse automatically, unless specified otherwise +; in source code or by the +nosparse commandline option of vlog or vopt. +; The default is 1M. (i.e. memories with total size equal +; to or greater than 1Mb are marked as sparse) +; SparseMemThreshold = 1048576 + +; Set the prefix to be honored for synthesis and coverage pragma recognition. +; Default is "". +; AddPragmaPrefix = "" + +; Ignore synthesis and coverage pragmas with this prefix. +; Default is "". +; IgnorePragmaPrefix = "" + +; Set the option to treat all files specified in a vlog invocation as a +; single compilation unit. The default value is set to 0 which will treat +; each file as a separate compilation unit as specified in the P1800 draft standard. +; MultiFileCompilationUnit = 1 + +; Turn on code coverage in Verilog design units. Default is off. +; Coverage = sbceft + +; Automatically exclude Verilog case statement default branches. +; Default is to not automatically exclude defaults. +; CoverExcludeDefault = 1 + +; Increase or decrease the maximum number of rows allowed in a UDP table +; implementing a VHDL condition coverage or expression coverage expression. +; More rows leads to a longer compile time, but more expressions covered. +; CoverMaxUDPRows = 192 + +; Increase or decrease the maximum number of input patterns that are present +; in FEC table. This leads to a longer compile time with more expressions +; covered with FEC metric. +; CoverMaxFECRows = 192 + +; Enable Multi Bit Expression Coverage in a Design, If design has expression with +; multi bit operands, this option enables its Expression Coverage. +; The default value is 0. +; CoverFecMultiBit = 1 + +; Increase or decrease the limit on the size of expressions and conditions +; considered for expression and condition coverages. Higher FecUdpEffort leads +; to higher compile, optimize and simulation time, but more expressions and +; conditions are considered for coverage in the design. FecUdpEffort can +; be set to a number ranging from 1 (low) to 3 (high), defined as: +; 1 - (low) Only small expressions and conditions considered for coverage. +; 2 - (medium) Bigger expressions and conditions considered for coverage. +; 3 - (high) Very large expressions and conditions considered for coverage. +; The default setting is 1 (low). +; FecUdpEffort = 1 + +; Enable or disable Focused Expression Coverage analysis for conditions and +; expressions. Focused Expression Coverage data is provided by default when +; expression and/or condition coverage is active. +; CoverFEC = 0 + +; Enable or disable UDP Coverage analysis for conditions and expressions. +; UDP Coverage data is disabled by default when expression and/or condition +; coverage is active. +; CoverUDP = 1 + +; Enable or disable Rapid Expression Coverage mode for conditions and expressions. +; Disabling this would convert non-masking conditions in FEC tables to matching +; input patterns. +; CoverREC = 1 + +; Enable or disable bit-blasting multi-bit operands of reduction prefix expressions +; for expression/condition coverage. +; NOTE: Enabling this may have a negative impact on simulation performance. +; CoverExpandReductionPrefix = 0 + +; Enable or disable short circuit evaluation of conditions and expressions when +; condition or expression coverage is active. Short circuit evaluation is enabled +; by default. +; CoverShortCircuit = 0 + +; Enable deglitching of code coverage in combinatorial, non-clocked, processes. +; Default is no deglitching. +; CoverDeglitchOn = 1 + +; Control the code coverage deglitching period. A period of 0, eliminates delta +; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a +; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". +; CoverDeglitchPeriod = 0 + +; Turn on code coverage in VLOG `celldefine modules, modules containing +; specify blocks, and modules included using vlog -v and -y. Default is off. +; CoverCells = 1 + +; Enable code coverage reporting of code that has been optimized away. +; The default is not to report. +; CoverReportCancelled = 1 + +; Control compiler and VOPT optimizations that are allowed when +; code coverage is on. This is a number from 0 to 5, with the following +; meanings (the default is 3): +; 5 -- All allowable optimizations are on. +; 4 -- Turn off removing unreferenced code. +; 3 -- Turn off process, always block and if statement merging. +; 2 -- Turn off expression optimization, converting primitives +; to continuous assignments, VHDL subprogram inlining. +; and VHDL clkOpt (converting FF's to builtins). +; 1 -- Turn off continuous assignment optimizations and clock suppression. +; 0 -- Turn off Verilog module inlining and VHDL arch inlining. +; HOWEVER, if fsm coverage is turned on, optimizations will be forced to +; level 3, with also turning off converting primitives to continuous assigns. +; CoverOpt = 3 + +; Specify the override for the default value of "cross_num_print_missing" +; option for the Cross in Covergroups. If not specified then LRM default +; value of 0 (zero) is used. This is a compile time option. +; SVCrossNumPrintMissingDefault = 0 + +; Setting following to 1 would cause creation of variables which +; would represent the value of Coverpoint expressions. This is used +; in conjunction with "SVCoverpointExprVariablePrefix" option +; in the modelsim.ini +; EnableSVCoverpointExprVariable = 0 + +; Specify the override for the prefix used in forming the variable names +; which represent the Coverpoint expressions. This is used in conjunction with +; "EnableSVCoverpointExprVariable" option of the modelsim.ini +; The default prefix is "expr". +; The variable name is +; variable name => <prefix>_<coverpoint name> +; SVCoverpointExprVariablePrefix = expr + +; Override for the default value of the SystemVerilog covergroup, +; coverpoint, and cross option.goal (defined to be 100 in the LRM). +; NOTE: It does not override specific assignments in SystemVerilog +; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal" +; in the [vsim] section can override this value. +; SVCovergroupGoalDefault = 100 + +; Override for the default value of the SystemVerilog covergroup, +; coverpoint, and cross type_option.goal (defined to be 100 in the LRM) +; NOTE: It does not override specific assignments in SystemVerilog +; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal" +; in the [vsim] section can override this value. +; SVCovergroupTypeGoalDefault = 100 + +; Specify the override for the default value of "strobe" option for the +; Covergroup Type. This is a compile time option which forces "strobe" to +; a user specified default value and supersedes SystemVerilog specified +; default value of '0'(zero). NOTE: This can be overriden by a runtime +; modelsim.ini variable "SVCovergroupStrobe" in the [vsim] section. +; SVCovergroupStrobeDefault = 0 + +; Specify the override for the default value of "per_instance" option for the +; Covergroup variables. This is a compile time option which forces "per_instance" +; to a user specified default value and supersedes SystemVerilog specified +; default value of '0'(zero). +; SVCovergroupPerInstanceDefault = 0 + +; Specify the override for the default value of "get_inst_coverage" option for the +; Covergroup variables. This is a compile time option which forces +; "get_inst_coverage" to a user specified default value and supersedes +; SystemVerilog specified default value of '0'(zero). +; SVCovergroupGetInstCoverageDefault = 0 + +; +; A space separated list of resource libraries that contain precompiled +; packages. The behavior is identical to using the "-L" switch. +; +; LibrarySearchPath = <path/lib> [<path/lib> ...] +LibrarySearchPath = mtiAvm mtiRnm mtiOvm mtiUvm mtiUPF infact + +; The behavior is identical to the "-mixedansiports" switch. Default is off. +; MixedAnsiPorts = 1 + +; Enable SystemVerilog 3.1a $typeof() function. Default is off. +; EnableTypeOf = 1 + +; Only allow lower case pragmas. Default is disabled. +; AcceptLowerCasePragmaOnly = 1 + +; Set the maximum depth permitted for a recursive include file nesting. +; IncludeRecursionDepthMax = 5 + +; Turn ON detection of FSMs having single bit current state variable. +; FsmSingle = 1 + +; Turn off reset state transitions in FSM. +; FsmResetTrans = 0 + +; Turn off detections of FSMs having x-assignment. +; FsmXAssign = 0 + +; Turn ON detection of FSM Implicit Transitions. +; FsmImplicitTrans = 1 + +; List of file suffixes which will be read as SystemVerilog. White space +; in extensions can be specified with a back-slash: "\ ". Back-slashes +; can be specified with two consecutive back-slashes: "\\"; +; SvFileSuffixes = sv svp svh + +; This setting is the same as the vlog -sv command line switch. +; Enables SystemVerilog features and keywords when true (1). +; When false (0), the rules of IEEE Std 1364-2005 are followed and +; SystemVerilog keywords are ignored. +; Svlog = 0 + +; Prints attribute placed upon SV packages during package import +; when true (1). The attribute will be ignored when this +; entry is false (0). The attribute name is "mti_design_element_load_message". +; The value of this attribute is a string literal. +; Default is true (1). +; PrintSVPackageLoadingAttribute = 1 + +; Do not show immediate assertions with constant expressions in +; GUI/reports/UCDB etc. By default immediate assertions with constant +; expressions are shown in GUI/reports/UCDB etc. This does not affect +; evaluation of immediate assertions. +; ShowConstantImmediateAsserts = 0 + +; Controls if untyped parameters that are initialized with values greater +; than 2147483647 are mapped to generics of type INTEGER or ignored. +; If mapped to VHDL Integers, values greater than 2147483647 +; are mapped to negative values. +; Default is to map these parameter to generic of type INTEGER +; ForceUnsignedToVHDLInteger = 1 + +; Enable AMS wreal (wired real) extensions. Default is 0. +; WrealType = 1 + +; Controls SystemVerilog Language Extensions. These options enable +; some non-LRM compliant behavior. +; SvExtensions = [+|-]<extension>[,[+|-]<extension>*] + +; Generate symbols debugging database in only some special cases to save on +; the number of files in the library. For other design-units, this database is +; generated on-demand in vsim. +; Default is to to generate debugging database for all design-units. +; SmartDbgSym = 1 + +; Controls how $unit library entries are named. Valid options are: +; "file" (generate name based on the first file on the command line) +; "du" (generate name based on first design unit following an item +; found in $unit scope) +; CUAutoName = file + +; Enable or disable automatic creation of missing libraries. +; Default is 1 (enabled) +; CreateLib = 1 + +[sccom] +; Enable use of SCV include files and library. Default is off. +; UseScv = 1 + +; Add C++ compiler options to the sccom command line by using this variable. +; CppOptions = -g + +; Use custom C++ compiler located at this path rather than the default path. +; The path should point directly at a compiler executable. +; CppPath = /usr/bin/g++ + +; Specify the compiler version from the list of support GNU compilers. +; examples 4.7.4, 5.3.0, 7.4.0 +; CppInstall = 7.4.0 + +; Enable verbose messages from sccom. Default is off. +; SccomVerbose = 1 + +; sccom logfile. Default is no logfile. +; SccomLogfile = sccom.log + +; Enable use of SC_MS include files and library. Default is off. +; UseScMs = 1 + +; Use SystemC-2.2 instead of the default SystemC-2.3. Default is off. +; Sc22Mode = 1 + +; Enable compiler statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list,kb] +; Add '-' to disable specific statistics. Default is [time,cmd,msg]. +; Stats = time,cmd,msg + +; Enable or disable automatic creation of missing libraries. +; Default is 1 (enabled) +; CreateLib = 1 + +; Enable use of UVMC library. Default is off. +; UseUvmc = 1 + +[vopt] +; Turn on code coverage in vopt. Default is off. +; Coverage = sbceft + +; enable or disable param saving in UCDB. +; CoverageSaveParam = 0 + +; Control compiler optimizations that are allowed when +; code coverage is on. Refer to the comment for this in the [vlog] area. +; CoverOpt = 3 + +; Controls set of CoverConstructs that are being considered for Coverage +; Collection. +; Some of Valid options are: default,set1,set2 +; Covermode = default + +; Override all PA VOPT and VSIM commands to run simulation in Non-PA mode. +; NonPAmode = 1 + +; Controls set of HDL cover constructs that would be considered(or not considered) +; for Coverage Collection. (Default corresponds to covermode default). +; Some of Valid options are: "ca", "citf", "cifl", "tcint", "fsmqs". +; Coverconstruct = noca,nocitf,nofsmtf,nofsmds,noctes,nocicl,nocprc,nocfl,nofsmup,nocifl,nocpm,notcint,nocpkg,nocsva + +; Increase or decrease the maximum number of rows allowed in a UDP table +; implementing a VHDL condition coverage or expression coverage expression. +; More rows leads to a longer compile time, but more expressions covered. +; CoverMaxUDPRows = 192 + +; Increase or decrease the maximum number of input patterns that are present +; in FEC table. This leads to a longer compile time with more expressions +; covered with FEC metric. +; CoverMaxFECRows = 192 + +; Enable Multi Bit Expression Coverage in a Design, If design has expression with +; multi bit operands, this option enables its Expression Coverage. +; The default value is 0. +; CoverFecMultiBit = 1 + +; Increase or decrease the limit on the size of expressions and conditions +; considered for expression and condition coverages. Higher FecUdpEffort leads +; to higher compile, optimize and simulation time, but more expressions and +; conditions are considered for coverage in the design. FecUdpEffort can +; be set to a number ranging from 1 (low) to 3 (high), defined as: +; 1 - (low) Only small expressions and conditions considered for coverage. +; 2 - (medium) Bigger expressions and conditions considered for coverage. +; 3 - (high) Very large expressions and conditions considered for coverage. +; The default setting is 1 (low). +; FecUdpEffort = 1 + +; Enable code coverage reporting of code that has been optimized away. +; The default is not to report. +; CoverReportCancelled = 1 + +; Enable deglitching of code coverage in combinatorial, non-clocked, processes. +; Default is no deglitching. +; CoverDeglitchOn = 1 + +; Enable compiler statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list,kb] +; Add '-' to disable specific statistics. Default is [time,cmd,msg]. +; Stats = time,cmd,msg + +; Control the code coverage deglitching period. A period of 0, eliminates delta +; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a +; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". +; CoverDeglitchPeriod = 0 + +; Do not show immediate assertions with constant expressions in +; GUI/reports/UCDB etc. By default immediate assertions with constant +; expressions are shown in GUI/reports/UCDB etc. This does not affect +; evaluation of immediate assertions. +; ShowConstantImmediateAsserts = 0 + +; Set the maximum number of iterations permitted for a generate loop. +; Restricting this permits the implementation to recognize infinite +; generate loops. +; GenerateLoopIterationMax = 100000 + +; Set the maximum depth permitted for a recursive generate instantiation. +; Restricting this permits the implementation to recognize infinite +; recursions. +; GenerateRecursionDepthMax = 200 + +; Set the number of processes created during the code generation phase. +; By default a heuristic is used to set this value. This may be set to 0 +; to disable this feature completely. +; ParallelJobs = 0 + +; Controls SystemVerilog Language Extensions. These options enable +; some non-LRM compliant behavior. +; SvExtensions = [+|-]<extension>[,[+|-]<extension>*] + +; Load the specified shared objects with the RTLD_GLOBAL flag. +; This gives global visibility to all symbols in the shared objects, +; meaning that subsequently loaded shared objects can bind to symbols +; in the global shared objects. The list of shared objects should +; be whitespace delimited. This option is not supported on the +; Windows or AIX platforms. +; GlobalSharedObjectList = example1.so example2.so example3.so + +; Disable SystemVerilog elaboration system task messages +; IgnoreSVAInfo = 1 +; IgnoreSVAWarning = 1 +; IgnoreSVAError = 1 +; IgnoreSVAFatal = 1 + +; Enable or disable automatic creation of missing libraries. +; Default is 1 (enabled) +; CreateLib = 1 + +[vsim] +; vopt flow +; Set to turn on automatic optimization of a design. +; Default is on +VoptFlow = 1 + +; Simulator resolution +; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. +Resolution = ns + +; Disable certain code coverage exclusions automatically. +; Assertions and FSM are exluded from the code coverage by default +; Set AutoExclusionsDisable = fsm to enable code coverage for fsm +; Set AutoExclusionsDisable = assertions to enable code coverage for assertions +; Set AutoExclusionsDisable = all to enable code coverage for all the automatic exclusions +; Or specify comma or space separated list +;AutoExclusionsDisable = fsm,assertions + +; User time unit for run commands +; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the +; unit specified for Resolution. For example, if Resolution is 100ps, +; then UserTimeUnit defaults to ps. +; Should generally be set to default. +UserTimeUnit = default + +; Default run length +RunLength = 100 + +; Maximum iterations that can be run without advancing simulation time +IterationLimit = 10000000 + +; Specify libraries to be searched for precompiled modules +; LibrarySearchPath = <path/lib> [<path/lib> ...] + +; Set XPROP assertion fail limit. Default is 5. +; Any positive integer, -1 for infinity. +; XpropAssertionLimit = 5 + +; Control PSL and Verilog Assume directives during simulation +; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts +; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts +; SimulateAssumeDirectives = 1 + +; Control the simulation of PSL and SVA +; These switches can be overridden by the vsim command line switches: +; -psl, -nopsl, -sva, -nosva. +; Set SimulatePSL = 0 to disable PSL simulation +; Set SimulatePSL = 1 to enable PSL simulation (default) +; SimulatePSL = 1 +; Set SimulateSVA = 0 to disable SVA simulation +; Set SimulateSVA = 1 to enable concurrent SVA simulation (default) +; SimulateSVA = 1 + +; Control SVA and VHDL immediate assertion directives during simulation +; Set SimulateImmedAsserts = 0 to disable simulation of immediate asserts +; Set SimulateImmedAsserts = 1 to enable simulation of immediate asserts +; SimulateImmedAsserts = 1 + +; License feature mappings for Verilog and VHDL +; qhsimvh Single language VHDL license +; qhsimvl Single language Verilog license +; msimhdlsim Language neutral license for either Verilog or VHDL +; msimhdlmix Second language only, language neutral license for either +; Verilog or VHDL +; +; Directives to license manager can be set either as single value or as +; space separated multi-values: +; vhdl Immediately checkout and hold a VHDL license (i.e., one of +; qhsimvh, msimhdlsim, or msimhdlmix) +; vlog Immediately checkout and hold a Verilog license (i.e., one of +; qhsimvl, msimhdlsim, or msimhdlmix) +; plus Immediately checkout and hold a VHDL license and a Verilog license +; noqueue Do not wait in the license queue when a license is not available +; viewsim Try for viewer license but accept simulator license(s) instead +; of queuing for viewer license (PE ONLY) +; noviewer Disable checkout of msimviewer license feature (PE ONLY) +; noslvhdl Disable checkout of qhsimvh license feature +; noslvlog Disable checkout of qhsimvl license feature +; nomix Disable checkout of msimhdlmix license feature +; nolnl Disable checkout of msimhdlsim license feature +; mixedonly Disable checkout of qhsimvh and qhsimvl license features +; lnlonly Disable checkout of qhsimvh,qhsimvl, and msimhdlmix license features +; +; Examples (remove ";" comment character to activate licensing directives): +; Single directive: +; License = plus +; Multi-directive (Note: space delimited directives): +; License = noqueue plus + +; Severity level of a VHDL assertion message or of a SystemVerilog severity system task +; which will cause a running simulation to stop. +; VHDL assertions and SystemVerilog severity system task that occur with the +; given severity or higher will cause a running simulation to stop. +; This value is ignored during elaboration. +; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal +BreakOnAssertion = 3 + +; Severity level of a tool message which will cause a running simulation to +; stop. This value is ignored during elaboration. Default is to not break. +; 0 = Note 1 = Warning 2 = Error 3 = Fatal +;BreakOnMessage = 2 + +; The class debug feature enables more visibility and tracking of class instances +; during simulation. By default this feature is disabled (0). To enable this +; feature set ClassDebug to 1. +; ClassDebug = 1 + +; Message Format conversion specifications: +; %S - Severity Level of message/assertion +; %R - Text of message +; %T - Time of message +; %D - Delta value (iteration number) of Time +; %K - Kind of path: Instance/Region/Signal/Process/Foreign Process/Unknown/Protected +; %i - Instance/Region/Signal pathname with Process name (if available) +; %I - shorthand for one of these: +; " %K: %i" +; " %K: %i File: %F" (when path is not Process or Signal) +; except that the %i in this case does not report the Process name +; %O - Process name +; %P - Instance/Region path without leaf process +; %F - File name +; %L - Line number; if assertion message, then line number of assertion or, if +; assertion is in a subprogram, line from which the call is made +; %u - Design unit name in form library.primary +; %U - Design unit name in form library.primary(secondary) +; %% - The '%' character itself +; +; If specific format for Severity Level is defined, use that format. +; Else, for a message that occurs during elaboration: +; -- Failure/Fatal message in VHDL region that is not a Process, and in +; certain non-VHDL regions, uses MessageFormatBreakLine; +; -- Failure/Fatal message otherwise uses MessageFormatBreak; +; -- Note/Warning/Error message uses MessageFormat. +; Else, for a message that occurs during runtime and triggers a breakpoint because +; of the BreakOnAssertion setting: +; -- if in a VHDL region that is not a Process, uses MessageFormatBreakLine; +; -- otherwise uses MessageFormatBreak. +; Else (a runtime message that does not trigger a breakpoint) uses MessageFormat. +; +; MessageFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n" +; MessageFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n" +; MessageFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormatBreakLine = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F Line: %L\n" +; MessageFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" + +; Error File - alternate file for storing error messages +; ErrorFile = error.log + +; Simulation Breakpoint messages +; This flag controls the display of function names when reporting the location +; where the simulator stops because of a breakpoint or fatal error. +; Example with function name: # Break in Process ctr at counter.vhd line 44 +; Example without function name: # Break at counter.vhd line 44 +; Default value is 1. +ShowFunctions = 1 + +; Default radix for all windows and commands. +; Radix may be one of: symbolic, ascii, binary, octal, decimal, hex, unsigned +; Flags may be one of: enumnumeric, showbase, wreal +DefaultRadix = hexadecimal +DefaultRadixFlags = showbase +; Set to 1 for make the signal_force VHDL and Verilog functions use the +; default radix when processing the force value. Prior to 10.2 signal_force +; used the default radix, now it always uses symbolic unless value explicitly indicates base +;SignalForceFunctionUseDefaultRadix = 0 + +; VSIM Startup command +; Startup = do startup.do + +; VSIM Shutdown file +; Filename to save u/i formats and configurations. +; ShutdownFile = restart.do +; To explicitly disable auto save: +; ShutdownFile = --disable-auto-save + +; Run simulator in batch mode as if -batch were specified on the command line if none of -c, -gui, or -i specified. +; Simulator runs in interactive mode as if -i were specified if this option is 0. Default is 0. +; BatchMode = 1 + +; File for saving command transcript when -batch option used +; This option is ignored when -c, -gui, or -i options are used or if BatchMode above is zero +; default is unset so command transcript only goes to stdout for better performance +; BatchTranscriptFile = transcript + +; File for saving command transcript, this option is ignored when -batch option is used +TranscriptFile = transcript + +; Transcript file long line wrapping mode(s) +; mode == 0 :: no wrapping, line recorded as is +; mode == 1 :: wrap at first whitespace after WSColumn +; or at Column. +; mode == 2 :: wrap as above, but add continuation +; character ('\') at end of each wrapped line +; +; WrapMode = 0 +; WrapColumn = 30000 +; WrapWSColumn = 27000 + +; File for saving command history +; CommandHistory = cmdhist.log + +; Specify whether paths in simulator commands should be described +; in VHDL or Verilog format. +; For VHDL, PathSeparator = / +; For Verilog, PathSeparator = . +; Must not be the same character as DatasetSeparator. +PathSeparator = / + +; Specify the dataset separator for fully rooted contexts. +; The default is ':'. For example: sim:/top +; Must not be the same character as PathSeparator. +DatasetSeparator = : + +; Specify a unique path separator for the Signal Spy set of functions. +; The default will be to use the PathSeparator variable. +; Must not be the same character as DatasetSeparator. +; SignalSpyPathSeparator = / + +; Used to control parsing of HDL identifiers input to the tool. +; This includes CLI commands, vsim/vopt/vlog/vcom options, +; string arguments to FLI/VPI/DPI calls, etc. +; If set to 1, accept either Verilog escaped Id syntax or +; VHDL extended id syntax, regardless of source language. +; If set to 0, the syntax of the source language must be used. +; Each identifier in a hierarchical name may need different syntax, +; e.g. "/top/\vhdl*ext*id\/middle/\vlog*ext*id /bottom" or +; "top.\vhdl*ext*id\.middle.\vlog*ext*id .bottom" +; GenerousIdentifierParsing = 1 + +; Disable VHDL assertion messages +; IgnoreNote = 1 +; IgnoreWarning = 1 +; IgnoreError = 1 +; IgnoreFailure = 1 + +; Disable SystemVerilog assertion messages +; IgnoreSVAInfo = 1 +; IgnoreSVAWarning = 1 +; IgnoreSVAError = 1 +; IgnoreSVAFatal = 1 + +; Do not print any additional information from Severity System tasks. +; Only the message provided by the user is printed along with severity +; information. +; SVAPrintOnlyUserMessage = 1; + +; Default force kind. May be freeze, drive, deposit, or default +; or in other terms, fixed, wired, or charged. +; A value of "default" will use the signal kind to determine the +; force kind, drive for resolved signals, freeze for unresolved signals +; DefaultForceKind = freeze + +; Control the iteration of events when a VHDL signal is forced to a value +; This flag can be set to honour the signal update event in next iteration, +; the default is to update and propagate in the same iteration. +; ForceSigNextIter = 1 + +; Enable simulation statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list,kb,eor] +; Add '-' to disable specific statistics. Default is [time,cmd,msg]. +; Stats = time,cmd,msg + +; If zero, open files when elaborated; otherwise, open files on +; first read or write. Default is 0. +; DelayFileOpen = 1 + +; Control VHDL files opened for write. +; 0 = Buffered, 1 = Unbuffered +UnbufferedOutput = 0 + +; Control the number of VHDL files open concurrently. +; This number should always be less than the current ulimit +; setting for max file descriptors. +; 0 = unlimited +ConcurrentFileLimit = 40 + +; If nonzero, close files as soon as there is either an explicit call to +; file_close, or when the file variable's scope is closed. When zero, a +; file opened in append mode is not closed in case it is immediately +; reopened in append mode; otherwise, the file will be closed at the +; point it is reopened. +; AppendClose = 1 + +; Control the number of hierarchical regions displayed as +; part of a signal name shown in the Wave window. +; A value of zero tells VSIM to display the full name. +; The default is 0. +; WaveSignalNameWidth = 0 + +; Turn off warnings when changing VHDL constants and generics +; Default is 1 to generate warning messages +; WarnConstantChange = 0 + +; Turn off warnings from accelerated versions of the std_logic_arith, +; std_logic_unsigned, and std_logic_signed packages. +; StdArithNoWarnings = 1 + +; Turn off warnings from accelerated versions of the IEEE numeric_std +; and numeric_bit packages. +; NumericStdNoWarnings = 1 + +; Use old-style (pre-6.6) VHDL FOR GENERATE statement iteration names +; in the design hierarchy. +; This style is controlled by the value of the GenerateFormat +; value described next. Default is to use new-style names, which +; comprise the generate statement label, '(', the value of the generate +; parameter, and a closing ')'. +; Set this to 1 to use old-style names. +; OldVhdlForGenNames = 1 + +; Control the format of the old-style VHDL FOR generate statement region +; name for each iteration. Do not quote the value. +; The format string here must contain the conversion codes %s and %d, +; in that order, and no other conversion codes. The %s represents +; the generate statement label; the %d represents the generate parameter value +; at a particular iteration (this is the position number if the generate parameter +; is of an enumeration type). Embedded whitespace is allowed (but discouraged); +; leading and trailing whitespace is ignored. +; Application of the format must result in a unique region name over all +; loop iterations for a particular immediately enclosing scope so that name +; lookup can function properly. The default is %s__%d. +; GenerateFormat = %s__%d + +; Enable more efficient logging of VHDL Variables. +; Logging VHDL variables without this enabled, while possible, is very +; inefficient. Enabling this will provide a more efficient logging methodology +; at the expense of more memory usage. By default this feature is disabled (0). +; To enabled this feature, set this variable to 1. +; VhdlVariableLogging = 1 + +; Enable logging of VHDL access type variables and their designated objects. +; This setting will allow both variables of an access type ("access variables") +; and their designated objects ("access objects") to be logged. Logging a +; variable of an access type will automatically also cause the designated +; object(s) of that variable to be logged as the simulation progresses. +; Further, enabling this allows access objects to be logged by name. By default +; this feature is disabled (0). To enable this feature, set this variable to 1. +; Enabling this will automatically enable the VhdlVariableLogging feature also. +; AccessObjDebug = 1 + +; Make each VHDL package in a PDU has its own separate copy of the package instead +; of sharing the package between PDUs. The default is to share packages. +; To ensure that each PDU has its own set of packages, set this variable to 1. +; VhdlSeparatePduPackage = 1 + +; Specify whether checkpoint files should be compressed. +; The default is 1 (compressed). +; CheckpointCompressMode = 0 + +; Specify gcc compiler used in the compilation of automatically generated DPI exportwrapper. +; Use custom gcc compiler located at this path rather than the default path. +; The path should point directly at a compiler executable. +; DpiCppPath = <your-gcc-installation>/bin/gcc +; +; Specify the compiler version from the list of support GNU compilers. +; examples 4.7.4, 5.3.0, 7.4.0 +; DpiCppInstall = 7.4.0 + +; Specify whether to enable SystemVerilog DPI "out-of-the-blue" calls. +; The term "out-of-the-blue" refers to SystemVerilog export function calls +; made from C functions that don't have the proper context setup +; (as is the case when running under "DPI-C" import functions). +; When this is enabled, one can call a DPI export function +; (but not task) from any C code. +; the setting of this variable can be one of the following values: +; 0 : dpioutoftheblue call is disabled (default) +; 1 : dpioutoftheblue call is enabled, but export call debug support is not available. +; 2 : dpioutoftheblue call is enabled, and limited export call debug support is available. +; DpiOutOfTheBlue = 1 + +; Specify whether continuous assignments are run before other normal priority +; processes scheduled in the same iteration. This event ordering minimizes race +; differences between optimized and non-optimized designs, and is the default +; behavior beginning with the 6.5 release. For pre-6.5 event ordering, set +; ImmediateContinuousAssign to 0. +; The default is 1 (enabled). +; ImmediateContinuousAssign = 0 + +; List of dynamically loaded objects for Verilog PLI applications +; Veriuser = veriuser.sl + +; Which default VPI object model should the tool conform to? +; The 1364 modes are Verilog-only, for backwards compatibility with older +; libraries, and SystemVerilog objects are not available in these modes. +; +; In the absence of a user-specified default, the tool default is the +; latest available LRM behavior. +; Options for PliCompatDefault are: +; VPI_COMPATIBILITY_VERSION_1364v1995 +; VPI_COMPATIBILITY_VERSION_1364v2001 +; VPI_COMPATIBILITY_VERSION_1364v2005 +; VPI_COMPATIBILITY_VERSION_1800v2005 +; VPI_COMPATIBILITY_VERSION_1800v2008 +; +; Synonyms for each string are also recognized: +; VPI_COMPATIBILITY_VERSION_1364v1995 (1995, 95, 1364v1995, 1364V1995, VL1995) +; VPI_COMPATIBILITY_VERSION_1364v2001 (2001, 01, 1364v2001, 1364V2001, VL2001) +; VPI_COMPATIBILITY_VERSION_1364v2005 (1364v2005, 1364V2005, VL2005) +; VPI_COMPATIBILITY_VERSION_1800v2005 (2005, 05, 1800v2005, 1800V2005, SV2005) +; VPI_COMPATIBILITY_VERSION_1800v2008 (2008, 08, 1800v2008, 1800V2008, SV2008) + + +; PliCompatDefault = VPI_COMPATIBILITY_VERSION_1800v2005 + +; Specify whether the Verilog system task $fopen or vpi_mcd_open() +; will create directories that do not exist when opening the file +; in "a" or "w" mode. +; The default is 0 (do not create non-existent directories) +; CreateDirForFileAccess = 1 + +; Specify default options for the restart command. Options can be one +; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions +; DefaultRestartOptions = -force + + +; Specify default UVM-aware debug options if the vsim -uvmcontrol switch is not used. +; Valid options include: all, none, verbose, disable, struct, reseed, msglog, trlog, certe. +; Options can be enabled by just adding the name, or disabled by prefixing the option with a "-". +; The list of options must be delimited by commas, without spaces or tabs. +; +; Some examples +; To turn on all available UVM-aware debug features: +; UVMControl = all +; To turn on the struct window, mesage logging, and transaction logging: +; UVMControl = struct,msglog,trlog +; To turn on all options except certe: +; UVMControl = all,-certe +; To completely disable all UVM-aware debug functionality: +; UVMControl = disable + +; Specify the WildcardFilter setting. +; A space separated list of object types to be excluded when performing +; wildcard matches with log, wave, etc commands. The default value for this variable is: +; "Variable Constant Generic Parameter SpecParam Memory Assertion Cover Endpoint ScVariable CellInternal ImmediateAssert VHDLFile" +; See "Using the WildcardFilter Preference Variable" in the documentation for +; details on how to use this variable and for descriptions of the filter types. +WildcardFilter = Variable Constant Generic Parameter SpecParam Memory Assertion Cover Endpoint ScVariable CellInternal ImmediateAssert VHDLFile + +; Specify the WildcardSizeThreshold setting. +; This integer setting specifies the size at which objects will be excluded when +; performing wildcard matches with log, wave, etc commands. Objects of size equal +; to or greater than the WildcardSizeThreshold will be filtered out from the wildcard +; matches. The size is a simple calculation of number of bits or items in the object. +; The default value is 8k (8192). Setting this value to 0 will disable the checking +; of object size against this threshold and allow all objects of any size to be logged. +WildcardSizeThreshold = 8192 + +; Specify whether warning messages are output when objects are filtered out due to the +; WildcardSizeThreshold. The default is 0 (no messages generated). +WildcardSizeThresholdVerbose = 0 + +; Turn on (1) or off (0) WLF file compression. +; The default is 1 (compress WLF file). +; WLFCompress = 0 + +; Specify whether to save all design hierarchy (1) in the WLF file +; or only regions containing logged signals (0). +; The default is 0 (save only regions with logged signals). +; WLFSaveAllRegions = 1 + +; WLF file time limit. Limit WLF file by time, as closely as possible, +; to the specified amount of simulation time. When the limit is exceeded +; the earliest times get truncated from the file. +; If both time and size limits are specified the most restrictive is used. +; UserTimeUnits are used if time units are not specified. +; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} +; WLFTimeLimit = 0 + +; WLF file size limit. Limit WLF file size, as closely as possible, +; to the specified number of megabytes. If both time and size limits +; are specified then the most restrictive is used. +; The default is 0 (no limit). +; WLFSizeLimit = 1000 + +; Specify whether or not a WLF file should be deleted when the +; simulation ends. A value of 1 will cause the WLF file to be deleted. +; The default is 0 (do not delete WLF file when simulation ends). +; WLFDeleteOnQuit = 1 + +; Specify whether or not a WLF file should be optimized during +; simulation. If set to 0, the WLF file will not be optimized. +; The default is 1, optimize the WLF file. +; WLFOptimize = 0 + +; Specify the name of the WLF file. +; The default is vsim.wlf +; WLFFilename = vsim.wlf + +; Specify whether to lock the WLF file. +; Locking the file prevents other invocations of ModelSim/Questa tools from +; inadvertently overwriting the WLF file. +; The default is 1, lock the WLF file. +; WLFFileLock = 0 + +; Specify the update interval for the WLF file in live simulation. +; The interval is given in seconds. +; The value is the smallest interval between WLF file updates. The WLF file +; will be flushed (updated) after (at least) the interval has elapsed, ensuring +; that the data is correct when viewed from a separate viewer. +; A value of 0 means that no updating will occur. +; The default value is 10 seconds. +; WLFUpdateInterval = 10 + +; Specify the WLF cache size limit for WLF files. +; The value is given in megabytes. A value of 0 turns off the cache. +; On non-Windows platforms the default WLFCacheSize setting is 2000 (megabytes). +; On Windows, the default value is 1000 (megabytes) to help to avoid filling +; process memory. +; WLFSimCacheSize allows a different cache size to be set for a live simulation +; WLF file, independent of post-simulation WLF file viewing. If WLFSimCacheSize +; is not set, it defaults to the WLFCacheSize value. +; WLFCacheSize = 2000 +; WLFSimCacheSize = 500 + +; Specify the WLF file event collapse mode. +; 0 = Preserve all events and event order. (same as -wlfnocollapse) +; 1 = Only record values of logged objects at the end of a simulator iteration. +; (same as -wlfcollapsedelta) +; 2 = Only record values of logged objects at the end of a simulator time step. +; (same as -wlfcollapsetime) +; The default is 1. +; WLFCollapseMode = 0 + +; Specify whether WLF file logging can use threads on multi-processor machines. +; If 0, no threads will be used; if 1, threads will be used if the system has +; more than one processor. +; WLFUseThreads = 1 + +; Specify the size of objects that will trigger "large object" messages +; at log/wave/list time. The size calculation of the object is the same as that +; used by the WildcardSizeThreshold. The default LargeObjectSize size is 500,000. +; Setting LargeObjectSize to 0 will disable these messages. +; LargeObjectSize = 500000 + +; Specify the depth of stack frames returned by $stacktrace([level]). +; This depth will be picked up when the optional 'level' argument +; is not specified or its value is not a positive integer. +; StackTraceDepth = 100 + +; Turn on/off undebuggable SystemC type warnings. Default is on. +; ShowUndebuggableScTypeWarning = 0 + +; Turn on/off unassociated SystemC name warnings. Default is off. +; ShowUnassociatedScNameWarning = 1 + +; Turn on/off SystemC IEEE 1666 deprecation warnings. Default is off. +; ScShowIeeeDeprecationWarnings = 1 + +; Turn on/off the check for multiple drivers on a SystemC sc_signal. Default is off. +; For SystemC-2.3.2 the valid values are 0,1 and 2 +; 0 = SC_SIGNAL_WRITE_CHECK_DISABLE_ +; 1 = SC_SIGNAL_WRITE_CHECK_DEFAULT_ +; 2 = SC_SIGNAL_WRITE_CHECK_CONFLICT_ +; For SystemC-2.2 the valid values are 0 and 1 +; 0 = DISABLE +; 1 = ENABLE +; ScEnableScSignalWriteCheck = 1 + +; Set SystemC default time unit. +; Set to fs, ps, ns, us, ms, or sec with optional +; prefix of 1, 10, or 100. The default is 1 ns. +; The ScTimeUnit value is honored if it is coarser than Resolution. +; If ScTimeUnit is finer than Resolution, it is set to the value +; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns, +; then the default time unit will be 1 ns. However if Resolution +; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns. +ScTimeUnit = ns + +; Set SystemC sc_main stack size. The stack size is set as an integer +; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or +; Gb(Giga-byte). Default is 10 Mb. The stack size for sc_main depends +; on the amount of data on the sc_main() stack and the memory required +; to succesfully execute the longest function call chain of sc_main(). +ScMainStackSize = 10 Mb + +; Set SystemC thread stack size. The stack size is set as an integer +; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or +; Gb(Giga-byte). The stack size for sc_thread depends +; on the amount of data on the sc_thread stack and the memory required +; to succesfully execute the thread. +; ScStackSize = 1 Mb + +; Turn on/off execution of remainder of sc_main upon quitting the current +; simulation session. If the cumulative length of sc_main() in terms of +; simulation time units is less than the length of the current simulation +; run upon quit or restart, sc_main() will be in the middle of execution. +; This switch gives the option to execute the remainder of sc_main upon +; quitting simulation. The drawback of not running sc_main till the end +; is memory leaks for objects created by sc_main. If on, the remainder of +; sc_main will be executed ignoring all delays. This may cause the simulator +; to crash if the code in sc_main is dependent on some simulation state. +; Default is on. +ScMainFinishOnQuit = 1 + +; Enable calling of the DPI export taks/functions from the +; SystemC start_of_simulation() callback. +; The default is off. +; EnableDpiSosCb = 1 + + +; Set the SCV relationship name that will be used to identify phase +; relations. If the name given to a transactor relation matches this +; name, the transactions involved will be treated as phase transactions +ScvPhaseRelationName = mti_phase + +; Customize the vsim kernel shutdown behavior at the end of the simulation. +; Some common causes of the end of simulation are $finish (implicit or explicit), +; sc_stop(), tf_dofinish(), and assertion failures. +; This should be set to "ask", "exit", or "stop". The default is "ask". +; "ask" -- In batch mode, the vsim kernel will abruptly exit. +; In GUI mode, a dialog box will pop up and ask for user confirmation +; whether or not to quit the simulation. +; "stop" -- Cause the simulation to stay loaded in memory. This can make some +; post-simulation tasks easier. +; "exit" -- The simulation will abruptly exit without asking for any confirmation. +; "final" -- Run SystemVerilog final blocks then behave as "stop". +; Note: This variable can be overridden with the vsim "-onfinish" command line switch. +OnFinish = ask + +; Print pending deferred assertion messages. +; Deferred assertion messages may be scheduled after the $finish in the same +; time step. Deferred assertions scheduled to print after the $finish are +; printed before exiting with severity level NOTE since it's not known whether +; the assertion is still valid due to being printed in the active region +; instead of the reactive region where they are normally printed. +; OnFinishPendingAssert = 1; + +; Print "simstats" result. Default is 0. +; 0 == do not print simstats +; 1 == print at end of simulation +; 2 == print at end of each run command and end of simulation +; PrintSimStats = 1 + +; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages +; AssertFile = assert.log + +; Enable assertion counts. Default is off. +; AssertionCounts = 1 + +; Run simulator in assertion debug mode. Default is off. +; AssertionDebug = 1 + +; Turn on/off PSL/SVA/VHDL assertion enable. Default is on. +; AssertionEnable = 0 + +; Set PSL/SVA/VHDL concurrent assertion fail limit. Default is -1. +; Any positive integer, -1 for infinity. +; AssertionLimit = 1 + +; Turn on/off concurrent assertion pass log. Default is off. +; Assertion pass logging is only enabled when assertion is browseable +; and assertion debug is enabled. +; AssertionPassLog = 1 + +; Turn on/off PSL concurrent assertion fail log. Default is on. +; The flag does not affect SVA +; AssertionFailLog = 0 + +; Turn on/off SVA concurrent assertion local var printing in -assertdebug mode. Default is on. +; AssertionFailLocalVarLog = 0 + +; Set action type for PSL/SVA concurrent assertion fail action. Default is continue. +; 0 = Continue 1 = Break 2 = Exit +; AssertionFailAction = 1 + +; Enable the active thread monitor in the waveform display when assertion debug is enabled. +; AssertionActiveThreadMonitor = 1 + +; Control how many waveform rows will be used for displaying the active threads. Default is 5. +; AssertionActiveThreadMonitorLimit = 5 + +; Assertion thread limit after which assertion would be killed/switched off. +; The default is -1 (unlimited). If the number of threads for an assertion go +; beyond this limit, the assertion would be either switched off or killed. This +; limit applies to only assert directives. +;AssertionThreadLimit = -1 + +; Action to be taken once the assertion thread limit is reached. Default +; is kill. It can have a value of off or kill. In case of kill, all the existing +; threads are terminated and no new attempts are started. In case of off, the +; existing attempts keep on evaluating but no new attempts are started. This +; variable applies to only assert directives. +;AssertionThreadLimitAction = kill + +; Cover thread limit after which cover would be killed/switched off. +; The default is -1 (unlimited). If the number of threads for a cover go +; beyond this limit, the cover would be either switched off or killed. This +; limit applies to only cover directives. +;CoverThreadLimit = -1 + +; Action to be taken once the cover thread limit is reached. Default +; is kill. It can have a value of off or kill. In case of kill, all the existing +; threads are terminated and no new attempts are started. In case of off, the +; existing attempts keep on evaluating but no new attempts are started. This +; variable applies to only cover directives. +;CoverThreadLimitAction = kill + + +; By default immediate assertions do not participate in Assertion Coverage calculations +; unless they are executed. This switch causes all immediate assertions in the design +; to participate in Assertion Coverage calculations, whether attempted or not. +; UnattemptedImmediateAssertions = 0 + +; By default immediate covers participate in Coverage calculations +; whether they are attempted or not. This switch causes all unattempted +; immediate covers in the design to stop participating in Coverage +; calculations. +; UnattemptedImmediateCovers = 0 + +; By default pass action block is not executed for assertions on vacuous +; success. The following variable is provided to enable execution of +; pass action block on vacuous success. The following variable is only effective +; if the user does not disable pass action block execution by using either +; system tasks or CLI. Also there is a performance penalty for enabling +; the following variable. +;AssertionEnableVacuousPassActionBlock = 1 + +; As per strict 1850-2005 PSL LRM, an always property can either pass +; or fail. However, by default, Questa reports multiple passes and +; multiple fails on top always/never property (always/never operator +; is the top operator under Verification Directive). The reason +; being that Questa reports passes and fails on per attempt of the +; top always/never property. Use the following flag to instruct +; Questa to strictly follow LRM. With this flag, all assert/never +; directives will start an attempt once at start of simulation. +; The attempt can either fail, match or match vacuously. +; For e.g. if always is the top operator under assert, the always will +; keep on checking the property at every clock. If the property under +; always fails, the directive will be considered failed and no more +; checking will be done for that directive. A top always property, +; if it does not fail, will show a pass at end of simulation. +; The default value is '0' (i.e. zero is off). For example: +; PslOneAttempt = 1 + +; Specify the number of clock ticks to represent infinite clock ticks. +; This affects eventually!, until! and until_!. If at End of Simulation +; (EOS) an active strong-property has not clocked this number of +; clock ticks then neither pass or fail (vacuous match) is returned +; else respective fail/pass is returned. The default value is '0' (zero) +; which effectively does not check for clock tick condition. For example: +; PslInfinityThreshold = 5000 + +; Control how many thread start times will be preserved for ATV viewing for a given assertion +; instance. Default is -1 (ALL). +; ATVStartTimeKeepCount = -1 + +; Turn on/off code coverage +; CodeCoverage = 0 + +; This option applies to condition and expression coverage UDP tables. It +; has no effect unless UDP is enabled for coverage with vcom/vlog/vopt -coverudp. +; If this option is used and a match occurs in more than one row in the UDP table, +; none of the counts for all matching rows is incremented. By default, counts are +; incremented for all matching rows. +; CoverCountAll = 1 + +; Turn off automatic inclusion of VHDL integers in toggle coverage. Default +; is to include them. +; ToggleNoIntegers = 1 + +; Set the maximum number of values that are collected for toggle coverage of +; VHDL integers. Default is 100; +; ToggleMaxIntValues = 100 + +; Set the maximum number of values that are collected for toggle coverage of +; Verilog real. Default is 100; +; ToggleMaxRealValues = 100 + +; Turn on automatic inclusion of Verilog integers in toggle coverage, except +; for enumeration types. Default is to include them. +; ToggleVlogIntegers = 0 + +; Turn on automatic inclusion of Verilog real type in toggle coverage, except +; for shortreal types. Default is to not include them. +; ToggleVlogReal = 1 + +; Turn on automatic inclusion of Verilog fixed-size unpacked arrays, VHDL multi-d arrays +; and VHDL arrays-of-arrays in toggle coverage. +; Default is to not include them. +; ToggleFixedSizeArray = 1 + +; Increase or decrease the maximum size of Verilog unpacked fixed-size arrays, +; VHDL multi-d arrays and VHDL arrays-of-arrays that are included for toggle coverage. +; This leads to a longer simulation time with bigger arrays covered with toggle coverage. +; Default is 1024. +; ToggleMaxFixedSizeArray = 1024 + +; Treat Verilog multi-dimensional packed vectors and packed structures as equivalently sized +; one-dimensional packed vectors for toggle coverage. Default is 0. +; TogglePackedAsVec = 0 + +; Treat Verilog enumerated types as equivalently sized one-dimensional packed vectors for +; toggle coverage. Default is 0. +; ToggleVlogEnumBits = 0 + +; Turn off automatic inclusion of VHDL records in toggle coverage. +; Default is to include them. +; ToggleVHDLRecords = 0 + +; Limit the widths of registers automatically tracked for toggle coverage. Default is 128. +; For unlimited width, set to 0. +; ToggleWidthLimit = 128 + +; Limit the counts that are tracked for toggle coverage. When all edges for a bit have +; reached this count, further activity on the bit is ignored. Default is 1. +; For unlimited counts, set to 0. +; ToggleCountLimit = 1 + +; Change the mode of extended toggle coverage. Default is 3. Valid modes are 1, 2 and 3. +; Following is the toggle coverage calculation criteria based on extended toggle mode: +; Mode 1: 0L->1H & 1H->0L & any one 'Z' transition (to/from 'Z'). +; Mode 2: 0L->1H & 1H->0L & one transition to 'Z' & one transition from 'Z'. +; Mode 3: 0L->1H & 1H->0L & all 'Z' transitions. +; ExtendedToggleMode = 3 + +; Enable toggle statistics collection only for ports. Default is 0. +; TogglePortsOnly = 1 + +; Limit the counts that are tracked for Focussed Expression Coverage. When a bin has +; reached this count, further tracking of the input patterns linked to it is ignored. +; Default is 1. For unlimited counts, set to 0. +; NOTE: Changing this value from its default value may affect simulation performance. +; FecCountLimit = 1 + +; Limit the counts that are tracked for UDP Coverage. When a bin has +; reached this count, further tracking of the input patterns linked to it is ignored. +; Default is 1. For unlimited counts, set to 0. +; NOTE: Changing this value from its default value may affect simulation performance. +; UdpCountLimit = 1 + +; Control toggle coverage deglitching period. A period of 0, eliminates delta +; cycle glitches. This is the default. The value of ToggleDeglitchPeriod needs to be either +; 0 or a time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". +; ToggleDeglitchPeriod = 10.0ps + +; Turn on/off all PSL/SVA cover directive enables. Default is on. +; CoverEnable = 0 + +; Turn on/off PSL/SVA cover log. Default is off "0". +; CoverLog = 1 + +; Set "at_least" value for all PSL/SVA cover directives. Default is 1. +; CoverAtLeast = 2 + +; Set "limit" value for all PSL/SVA cover directives. Default is -1. +; Any positive integer, -1 for infinity. +; CoverLimit = 1 + +; Specify the coverage database filename. +; Default is "" (i.e. database is NOT automatically saved on close). +; UCDBFilename = vsim.ucdb + +; Specify the maximum limit for the number of Cross (bin) products reported +; in XML and UCDB report against a Cross. A warning is issued if the limit +; is crossed. Default is zero. vsim switch -cvgmaxrptrhscross can override this +; setting. +; MaxReportRhsSVCrossProducts = 1000 + +; Specify the override for the "auto_bin_max" option for the Covergroups. +; If not specified then value from Covergroup "option" is used. +; SVCoverpointAutoBinMax = 64 + +; Specify the override for the value of "cross_num_print_missing" +; option for the Cross in Covergroups. If not specified then value +; specified in the "option.cross_num_print_missing" is used. This +; is a runtime option. NOTE: This overrides any "cross_num_print_missing" +; value specified by user in source file and any SVCrossNumPrintMissingDefault +; specified in modelsim.ini. +; SVCrossNumPrintMissing = 0 + +; Specify whether to use the value of "cross_num_print_missing" +; option in report and GUI for the Cross in Covergroups. If not specified then +; cross_num_print_missing is ignored for creating reports and displaying +; covergroups in GUI. Default is 0, which means ignore "cross_num_print_missing". +; UseSVCrossNumPrintMissing = 0 + +; Specify the threshold of Coverpoint wildcard bin value range size, above which +; a warning will be triggered. The default is 4K -- 12 wildcard bits. +; SVCoverpointWildCardBinValueSizeWarn = 4096 + +; Specify the override for the value of "strobe" option for the +; Covergroup Type. If not specified then value in "type_option.strobe" +; will be used. This is runtime option which forces "strobe" to +; user specified value and supersedes user specified values in the +; SystemVerilog Code. NOTE: This also overrides the compile time +; default value override specified using "SVCovergroupStrobeDefault" +; SVCovergroupStrobe = 0 + +; Override for explicit assignments in source code to "option.goal" of +; SystemVerilog covergroup, coverpoint, and cross. It also overrides the +; default value of "option.goal" (defined to be 100 in the SystemVerilog +; LRM) and the value of modelsim.ini variable "SVCovergroupGoalDefault". +; SVCovergroupGoal = 100 + +; Override for explicit assignments in source code to "type_option.goal" of +; SystemVerilog covergroup, coverpoint, and cross. It also overrides the +; default value of "type_option.goal" (defined to be 100 in the SystemVerilog +; LRM) and the value of modelsim.ini variable "SVCovergroupTypeGoalDefault". +; SVCovergroupTypeGoal = 100 + +; Enforce the 6.3 behavior of covergroup get_coverage() and get_inst_coverage() +; builtin functions, and report. This setting changes the default values of +; option.get_inst_coverage and type_option.merge_instances to ensure the 6.3 +; behavior if explicit assignments are not made on option.get_inst_coverage and +; type_option.merge_instances by the user. There are two vsim command line +; options, -cvg63 and -nocvg63 to override this setting from vsim command line. +; The default value of this variable from release 6.6 onwards is 0. This default +; drives compliance with the clarified behavior in the IEEE 1800-2009 standard. +; SVCovergroup63Compatibility = 0 + +; Enforce the default behavior of covergroup get_coverage() builtin function, GUI +; and report. This variable sets the default value of type_option.merge_instances. +; There are two vsim command line options, -cvgmergeinstances and +; -nocvgmergeinstances to override this setting from vsim command line. +; The default value of this variable, -1 (don't care), allows the tool to determine +; the effective value, based on factors related to capacity and optimization. +; The type_option.merge_instances appears in the GUI and coverage reports as either +; auto(1) or auto(0), depending on whether the effective value was determined to +; be a 1 or a 0. +; SVCovergroupMergeInstancesDefault = -1 + +; Enable or disable generation of more detailed information about the sampling +; of covergroup, cross, and coverpoints. It provides the details of the number +; of times the covergroup instance and type were sampled, as well as details +; about why covergroup, cross and coverpoint were not covered. A non-zero value +; is to enable this feature. 0 is to disable this feature. Default is 0 +; SVCovergroupSampleInfo = 0 + +; Specify the maximum number of Coverpoint bins in whole design for +; all Covergroups. +; MaxSVCoverpointBinsDesign = 2147483648 + +; Specify maximum number of Coverpoint bins in any instance of a Covergroup, default is 2^10 bins +; MaxSVCoverpointBinsInst = 1048576 + +; Specify the maximum number of Cross bins in whole design for +; all Covergroups. +; MaxSVCrossBinsDesign = 2147483648 + +; Specify maximum number of Cross bins in any instance of a Covergroup, default is 2^16 bins +; MaxSVCrossBinsInst = 67108864 + +; Specify whether vsim will collect the coverage data of zero-weight coverage items or not. +; By default, this variable is set 0, in which case option.no_collect setting will take effect. +; If this variable is set to 1, all zero-weight coverage items will not be saved. +; Note that the usage of vsim switch -cvgzwnocollect, if present, will override the setting +; of this variable. +; CvgZWNoCollect = 1 + +; Specify a space delimited list of double quoted TCL style +; regular expressions which will be matched against the text of all messages. +; If any regular expression is found to be contained within any message, the +; status for that message will not be propagated to the UCDB TESTSTATUS. +; If no match is detected, then the status will be propagated to the +; UCDB TESTSTATUS. More than one such regular expression text is allowed, +; and each message text is compared for each regular expression in the list. +; UCDBTestStatusMessageFilter = "Done with Test Bench" "Ignore .* message" + +; Set weight for all PSL/SVA cover directives. Default is 1. +; CoverWeight = 2 + +; Check vsim plusargs. Default is 0 (off). +; 0 = Don't check plusargs +; 1 = Warning on unrecognized plusarg +; 2 = Error and exit on unrecognized plusarg +; CheckPlusargs = 1 + +; Load the specified shared objects with the RTLD_GLOBAL flag. +; This gives global visibility to all symbols in the shared objects, +; meaning that subsequently loaded shared objects can bind to symbols +; in the global shared objects. The list of shared objects should +; be whitespace delimited. This option is not supported on the +; Windows or AIX platforms. +; GlobalSharedObjectList = example1.so example2.so example3.so + +; Generate the stub definitions for the undefined symbols in the shared libraries being +; loaded in the simulation. When this flow is turned on, the undefined symbols will not +; prevent vsim from loading. Calling undefined symbols at runtime will cause fatal error. +; The valid arguments are: on, off, verbose. +; on : turn on the automatic generation of stub definitions. +; off: turn off the flow. The undefined symbols will trigger an immediate load failure. +; verbose: Turn on the flow and report the undefined symbols for each shared library. +; NOTE: This variable can be overriden with vsim switch "-undefsyms". +; The default is on. +; +; UndefSyms = off + +; Enable the support for checkpointing foreign C/C++ libraries. +; The valid arguments are: 0, 1, 2 +; 0: off (default) +; 1: on (manually save/restore user shared library data) +; 2: auto (automatically save/restore user shared library data) +; This option is not supported on the Windows platforms. +; +; AllowCheckpointCpp = 2 + +; Initial seed for the random number generator of the root thread (SystemVerilog). +; NOTE: This variable can be overridden with the vsim "-sv_seed" command line switch. +; The default value is 0. +; Sv_Seed = 0 + +; Specify the solver "engine" that vsim will select for constrained random +; generation. +; Valid values are: +; "auto" - automatically select the best engine for the current +; constraint scenario +; "bdd" - evaluate all constraint scenarios using the BDD solver engine +; "act" - evaluate all constraint scenarios using the ACT solver engine +; While the BDD solver engine is generally efficient with constraint scenarios +; involving bitwise logical relationships, the ACT solver engine can exhibit +; superior performance with constraint scenarios involving large numbers of +; random variables related via arithmetic operators (+, *, etc). +; NOTE: This variable can be overridden with the vsim "-solveengine" command +; line switch. +; The default value is "auto". +; SolveEngine = auto + +; Specify the maximum size that a random dynamic array or queue may be resized +; to by the solver. If the solver attempts to resize a dynamic array or queue +; to a size greater than the specified limit, the solver will abort with an error. +; The default value is 10000. The maximum value is 10000000. A value of 0 is +; equivalent to specifying the maximum value. +; SolveArrayResizeMax = 10000 + +; Specify error message severity when randomize() and randomize(null) failures +; are detected. +; +; Integer value up to two digits are allowed with each digit having the following legal values: +; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal +; +; 1) When a value with two digits is used, the digit at tenth place (leftmost digit) represents +; the severtity setting for normal randomize() calls. The digit at ones place (rightmost digit) +; represents the setting for randomize(null) calls. +; +; 2) When a single digit value is used, the setting is applied to both normal randomize() call +; and randomize(null) call. +; +; Example: Fatal error for randomize() failures and NO error for randomize(null) failures +; -solvefailseverity=40 +; +; NOTE: SolveFailSeverity can affect the behavior of SolveFailDebug. When SolveFailDebug is +; enabled, a constraint contradiction report will be displayed for randomize() calls that +; have a message severity >= warning (i.e. constraint contradiction reports will not be +; generated for randomize() calls having a "no error" severity level) +; +; NOTE: This variable can be overridden with the vsim "-solvefailseverity" command +; line switch. +; +; The default is 1 (warning). +; SolveFailSeverity = 1 + +; Error message severity for suppressible errors that are detected in a +; solve/before constraint. +; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal +; NOTE: This variable can be overridden with the vsim "-solvebeforeerrorseverity" +; command line switch. +; The default is 3 (failure). +; SolveBeforeErrorSeverity = 3 + +; Error message severity for suppressible errors that are related to +; solve engine capacity limits +; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal +; NOTE: This variable can be overridden with the vsim "-solveengineerrorseverity" +; command line switch. +; The default is 3 (failure). +; SolveEngineErrorSeverity = 3 + +; Enable/disable constraint conflicts on randomize() failure +; Valid values: +; 0 - disable solvefaildebug +; 1 - basic debug (no performance penalty) +; 2 - enhanced debug (runtime performance penalty) +; +; NOTE: SolveFailSeverity can affect the behavior of SolveFailDebug. When SolveFailDebug is +; enabled, a constraint contradiction report will be displayed for randomize() calls that +; have a message severity >= warning (i.e. constraint contradiction reports will not be +; generated for randomize() calls having a "no error" severity level) +; +; NOTE: This variable can be overridden with the vsim "-solvefaildebug" command +; line switch. +; +; The default is 1 (basic debug). +; SolveFailDebug = 1 + +; Upon encountering a randomize() failure, generate a simplified testcase that +; will reproduce the failure. Optionally output the testcase to a file. +; Testcases for 'no-solution' failures will only be produced if SolveFailDebug +; is enabled (see above). +; NOTE: This variable can be overridden with the vsim "-solvefailtestcase" +; command line switch. +; The default is OFF (do not generate a testcase). To enable testcase +; generation, uncomment this variable. To redirect testcase generation to a +; file, specify the name of the output file. +; SolveFailTestcase = + +; Specify solver timeout threshold (in seconds). randomize() will fail if the +; CPU time required to evaluate any randset exceeds the specified timeout. +; The default value is 500. A value of 0 will disable timeout failures. +; SolveTimeout = 500 + +; Specify the alternative behavior during solver replay. Must be used when combined with -solvereplay switch. +; SolveReplayOpt=[+|-]<opt>[,[+|-]<opt>]*" +' Valid <opt> settings: +; validate : toggle the checking of value changes of non-random variables involved in randomize(). (default is off)" +; SolveReplayOpt=validate + +; Switch to specify options that control the behavior of the solver profiler.. +; Valid options are: +; cputime - use CPU time instead of elapsed time (wall time) to measure performance data (default is off) +; randsets - enable detailed profiling of randsets (default is off) +; testgen - generate testcases for profiled randsets (only when randsets option is enabled) (default is off) +; SolverFProf = [+|-]<option>[,[+|-]<option>*] + +; Specify the maximum size of the solution graph generated by the BDD solver. +; This value can be used to force the BDD solver to abort the evaluation of a +; complex constraint scenario that cannot be evaluated with finite memory. +; This value is specified in 1000s of nodes. +; The default value is 10000. A value of 0 indicates no limit. +; SolveGraphMaxSize = 10000 + +; Specify the maximum number of evaluations that may be performed on the +; solution graph by the BDD solver. This value can be used to force the BDD +; solver to abort the evaluation of a complex constraint scenario that cannot +; be evaluated in finite time. This value is specified in 10000s of evaluations. +; The default value is 10000. A value of 0 indicates no limit. +; SolveGraphMaxEval = 10000 + +; Specify random sequence compatiblity with a prior release. This +; option is used to get the same random sequences during simulation as +; as a prior release. Only prior releases with the same major version +; as the current release are allowed. +; NOTE: Only those random sequence changes due to solver optimizations are +; reverted by this variable. Random sequence changes due to solver bugfixes +; cannot be un-done. +; NOTE: This variable can be overridden with the vsim "-solverev" command +; line switch. +; Default value set to "" (no compatibility). +; SolveRev = + +; Environment variable expansion of command line arguments has been depricated +; in favor shell level expansion. Universal environment variable expansion +; inside -f files is support and continued support for MGC Location Maps provide +; alternative methods for handling flexible pathnames. +; The following line may be uncommented and the value set to 1 to re-enable this +; deprecated behavior. The default value is 0. +; DeprecatedEnvironmentVariableExpansion = 0 + +; Specify the memory threshold for the System Verilog garbage collector. +; The value is the number of megabytes of class objects that must accumulate +; before the garbage collector is run. +; The GCThreshold setting is used when class debug mode is disabled to allow +; less frequent garbage collection and better simulation performance. +; The GCThresholdClassDebug setting is used when class debug mode is enabled +; to allow for more frequent garbage collection. +; GCThreshold = 100 +; GCThresholdClassDebug = 5 + +; Turn on/off collapsing of bus ports in VCD dumpports output +DumpportsCollapse = 1 + +; Location of Multi-Level Verification Component (MVC) installation. +; The default location is the product installation directory. +MvcHome = $QUESTA_MVC_HOME + +; Location of InFact installation. The default is $MODEL_TECH/../../infact +; +; InFactHome = $MODEL_TECH/../../infact + +; Initialize SystemVerilog enums using the base type's default value +; instead of the leftmost value. +; EnumBaseInit = 1 + +; Suppress file type registration. +; SuppressFileTypeReg = 1 + +; Enable/disable non-LRM compliant SystemVerilog language extensions. +; Valid extensions are: +; altdpiheader - Alternative style function signature generated in DPI header", +; cfce - generate an error if $cast fails as a function +; cfmt - C like formatting for specifiers with '#' prefix ('%#x', '%#h') +; dfsp - sets default format specifier as %p, if no format specifier is given for unpacked array in $display and related systasks +; expdfmt - enable format string extensions for $display/$sformatf +; extscan - support values greater than 32 bit for string builtin methods (atohex, atobin, atooct, atoi) +; fmtcap - prints capital hex digits with %X/%H in display calls +; iddp - ignore DPI disable protocol check +; lfmt - zero-pad data if '0' prefixes width in format specifier (e.g. "%04h") +; noexptc - ignore DPI export type name overloading check +; realrand - support randomize() with real variables and constraints (Default) +; SvExtensions = [+|-]<extension>[,[+|-]<extension>*] + +; Enable/disable non-LRM compliant SystemVerilog constrained-random language extensions. +; Valid extensions are: +; arraymode - consider rand_mode of unpacked array field independently from its elements +; deepcheck - allow randomize(null) to recursively consider constraints from member rand class handles (Default) +; funcback - enable function backtracking (ACT only) +; genmodseedfix - enable LRM-compliant seeding of module/interface instances under for-generate blocks (Default) +; impvecindex - inject constraints on random indices of 2-state vectors +; nodist - interpret 'dist' constraint as 'inside' (ACT only) +; noorder - ignore solve/before ordering constraints (ACT only) +; pathseed - enable unique seeding of module instances based on hierarchical path name +; prerandfirst - execute all pre_randomize() functions before evaluating any constraints +; promotedist - promote priority of 'dist' constraint if LHS has no solve/before +; purecheck - suppress pre_randomize() and post_randomize() calls for randomize(null) +; randindex - allow random index in constraint (Default) +; randstruct - consider all fields of unpacked structs as 'rand' +; skew - skew randomize results (ACT only) +; strictstab - strict random stability +; SvRandExtensions = [+|-]<extension>[,[+|-]<extension>*] + +; Controls the formatting of '%p' and '%P' conversion specification, used in $display +; and similar system tasks. +; 1. SVPrettyPrintFlags=I<n><S|T> use <n> spaces(S) or tabs(T) per indentation level. +; The 'I' flag when present causes relevant data types to be expanded and indented into +; a more readable format. +; (e.g. SVPrettyPrintFlags=I4S will cause 4 spaces to be used per indentation level). +; 2. SVPrettyPrintFlags=L<numLines> limits the output to <numLines> lines. +; (e.g. SVPrettyPrintFlags=L20 will limit the output to 20 lines). +; 3. SVPrettyPrintFlags=C<numChars> limits the output to <numChars> characters. +; (e.g. SVPrettyPrintFlags=C256 will limit the output to 256 characters). +; 4. SVPrettyPrintFlags=F<numFields> limits the output to <numFields> of relevant datatypes +; (e.g. SVPrettyPrintFlags=F4 will limit the output to 4 fields of a structure). +; 5. SVPrettyPrintFlags=E<numElements> limits the output to <numElements> of relevant datatypes +; (e.g. SVPrettyPrintFlags=E50 will limit the output to 50 elements of an array). +; 6. SVPrettyPrintFlags=D<depth> suppresses the output of sub-elements below <depth>. +; (e.g. SVPrettyPrintFlags=D5 will suppresses the output of sub elements below a depth of 5). +; 7. SVPrettyPrintFlags=R<specifier> shows the output of specifier %p as per the specifed radix. +; It changes the output in $display and similar systasks. It does not affect formatted output functions ($displayh etc)). +; (e.g. SVPrettyPrintFlags=Rb will show the output of %p specifier in binary format. +; 8. Items 1-7 above can be combined as a comma separated list. +; (e.g. SVPrettyPrintFlags=I4S,L20,C256,F4,E50,D5,Rb) +; SVPrettyPrintFlags=I4S + +[lmc] +; The simulator's interface to Logic Modeling's SmartModel SWIFT software +libsm = $MODEL_TECH/libsm.sl +; The simulator's interface to Logic Modeling's SmartModel SWIFT software (Windows NT) +; libsm = $MODEL_TECH/libsm.dll +; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700) +; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl +; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000) +; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o +; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris) +; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so +; Logic Modeling's SmartModel SWIFT software (Windows NT) +; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll +; Logic Modeling's SmartModel SWIFT software (non-Enterprise versions of Linux) +; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so +; Logic Modeling's SmartModel SWIFT software (Enterprise versions of Linux) +; libswift = $LMC_HOME/lib/linux.lib/libswift.so + +; The simulator's interface to Logic Modeling's hardware modeler SFI software +libhm = $MODEL_TECH/libhm.sl +; The simulator's interface to Logic Modeling's hardware modeler SFI software (Windows NT) +; libhm = $MODEL_TECH/libhm.dll +; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700) +; libsfi = <sfi_dir>/lib/hp700/libsfi.sl +; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000) +; libsfi = <sfi_dir>/lib/rs6000/libsfi.a +; Logic Modeling's hardware modeler SFI software (Sun4 Solaris) +; libsfi = <sfi_dir>/lib/sun4.solaris/libsfi.so +; Logic Modeling's hardware modeler SFI software (Windows NT) +; libsfi = <sfi_dir>/lib/pcnt/lm_sfi.dll +; Logic Modeling's hardware modeler SFI software (Linux) +; libsfi = <sfi_dir>/lib/linux/libsfi.so + +[msg_system] +; Change a message severity or suppress a message. +; The format is: <msg directive> = <msg number>[,<msg number>...] +; suppress can be used to achieve +nowarn<CODE> functionality +; The format is: suppress = <CODE>,<msg number>,[<CODE>,<msg number>,...] +; Examples: +suppress = 8780 ;an explanation can be had by running: verror 8780 +;suppress = 12110 ; +; note = 3009 +; warning = 3033 +; error = 3010,3016 +; fatal = 3016,3033 +; suppress = 3009,3016,3601 +; suppress = 3009,CNNODP,3601,TFMPC +; suppress = 8683,8684 +; The command verror <msg number> can be used to get the complete +; description of a message. + +; Control transcripting of Verilog display system task messages and +; PLI/FLI print function call messages. The system tasks include +; $display[bho], $strobe[bho], $monitor[bho], and $write[bho]. They +; also include the analogous file I/O tasks that write to STDOUT +; (i.e. $fwrite or $fdisplay). The PLI/FLI calls include io_printf, +; vpi_printf, mti_PrintMessage, and mti_PrintFormatted. The default +; is to have messages appear only in the transcript. The other +; settings are to send messages to the wlf file only (messages that +; are recorded in the wlf file can be viewed in the MsgViewer) or +; to both the transcript and the wlf file. The valid values are +; tran {transcript only (default)} +; wlf {wlf file only} +; both {transcript and wlf file} +; displaymsgmode = tran + +; Control transcripting of elaboration/runtime messages not +; addressed by the displaymsgmode setting. The default is to +; have messages appear only in the transcript. The other settings +; are to send messages to the wlf file only (messages that are +; recorded in the wlf file can be viewed in the MsgViewer) or to both +; the transcript and the wlf file. The valid values are +; tran {transcript only (default)} +; wlf {wlf file only} +; both {transcript and wlf file} +; msgmode = tran + +; Controls number of displays of a particluar message +; default value is 5 +; MsgLimitCount = 5 + +[utils] +; Default Library Type (while creating a library with "vlib") +; 0 - legacy library using subdirectories for design units +; 2 - flat library +; DefaultLibType = 2 + +; Flat Library Page Size (while creating a library with "vlib") +; Set the size in bytes for flat library file pages. Libraries containing +; very large files may benefit from a larger value. +; FlatLibPageSize = 8192 + +; Flat Library Page Cleanup Percentage (while creating a library with "vlib") +; Set the percentage of total pages deleted before library cleanup can occur. +; This setting is applied together with FlatLibPageDeleteThreshold. +; FlatLibPageDeletePercentage = 50 + +; Flat Library Page Cleanup Threshold (while creating a library with "vlib") +; Set the number of pages deleted before library cleanup can occur. +; This setting is applied together with FlatLibPageDeletePercentage. +; FlatLibPageDeleteThreshold = 1000 + diff --git a/manufacturer/altera/cyclone10_lp/src/betsy.v b/manufacturer/altera/cyclone10_lp/src/betsy.v new file mode 100644 index 0000000..2116b34 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/src/betsy.v @@ -0,0 +1,1916 @@ +/* + * betsy.v + * + * Copyright (C) 2025 Private Island Networks Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * function: top module for three instantiated Ethernet PHYs + controllers + * + * + */ + +// `define PASSTHROUGH +`define PHY2_PRESENT + +module betsy ( + input rstn, + input clk_i, // 25Mhz + + input phy0_clk, + output phy1_clk, + +`ifdef SIMULATION + output pll_locked_o, + output pclk_o, + output [2:0] phy_up_o, +`endif + + // PHY0 RGMII + output phy0_rstn, + + input phy0_rx_clk, + input phy0_rx_ctl, + input [3:0] phy0_rx_d, + + output phy0_tx_clk, + output phy0_tx_ctl, + output [3:0] phy0_tx_d, + + output phy0_mdc, + inout phy0_mdio, + + input phy0_intn, // TODO: resolve PWRDN input option + inout [1:0] phy0_gpio, + + // PHY1 RGMII + output phy1_rstn, + + input phy1_rx_clk, + input phy1_rx_ctl, + input [3:0] phy1_rx_d, + + output phy1_tx_clk, + output phy1_tx_ctl, + output [3:0] phy1_tx_d, + + output phy1_mdc, + inout phy1_mdio, + + input phy1_intn, + inout [1:0] phy1_gpio, + + // PHY2 RGMII + output phy2_rstn, + + input phy2_rx_clk, + input phy2_rx_ctl, + input [3:0] phy2_rx_d, + + output phy2_tx_clk, + output phy2_tx_ctl, + output[3:0] phy2_tx_d, + + output phy2_mdc, + inout phy2_mdio, + + input phy2_intn, + inout [1:0] phy2_gpio, + + // FLASH + output flash_clk, + input flash_dqs, + output flash_seln, + inout [7:0] flash_d, + + // Debug + output [2:0] fpga_led +); + +`define INCLUDED +`include "../../../../src/ethernet_params.v" +`undef INCLUDED + + /* PARAMS */ + parameter NUM_PHYS = 3; + parameter NUM_PLLS = 1; + parameter MDIO_ROM_ADDR_SZ = 7; + parameter NUM_ML_IF = 3; + + wire reset, pll_locked; + reg sys_rstn; + wire cont_clk, clk_25, clk_125; + wire pclk; // main fabric clock for Ethernet pipeline + reg [3:0] cnt_init; + reg [25:0] heart_beat_cnt; + wire [NUM_PHYS-1:0] phy_up; + + `ifdef SIMULATION + assign pll_locked_o = pll_locked; + assign pclk_o = pclk; + assign phy_up_o = phy_up; + `endif + + // misc resets + wire [NUM_PHYS-1:0] phy_resetn; + wire [NUM_PHYS-1:0] mac_reset; + wire [NUM_PHYS-1:0] phy_int; + + wire [NUM_PHYS-1:0] rx_sample; + + // receive data + ctl input + wire [1:0] rx0_ctl_i, rx1_ctl_i, rx2_ctl_i; + wire [7:0] rx0_d_i, rx1_d_i, rx2_d_i; + + // transmit data + ctl output + wire [1:0] tx0_ctl, tx1_ctl, tx2_ctl; + wire [7:0] tx0_d, tx1_d, tx2_d; + + + // Delayed RX input data + reg [1:0] rx0_ctl_i_m1, rx0_ctl_i_m2, rx0_ctl_i_m3, rx0_ctl_i_m4; + reg [7:0] rx0_d_i_m1, rx0_d_i_m2, rx0_d_i_m3, rx0_d_i_m4; + + reg [1:0] rx1_ctl_i_m1, rx1_ctl_i_m2, rx1_ctl_i_m3, rx1_ctl_i_m4; + reg [7:0] rx1_d_i_m1, rx1_d_i_m2, rx1_d_i_m3, rx1_d_i_m4; + + reg [1:0] rx2_ctl_i_m1, rx2_ctl_i_m2, rx2_ctl_i_m3, rx2_ctl_i_m4; + reg [7:0] rx2_d_i_m1, rx2_d_i_m2, rx2_d_i_m3, rx2_d_i_m4; + + // Delayed data shared between modules + wire [1:0] rx0_ctl_m1, rx0_ctl_m2, rx0_ctl_m3, rx0_ctl_m4; + wire [7:0] rx0_d_m1, rx0_d_m2, rx0_d_m3, rx0_d_m4; + + wire [1:0] rx1_ctl_m1, rx1_ctl_m2, rx1_ctl_m3, rx1_ctl_m4; + wire [7:0] rx1_d_m1, rx1_d_m2, rx1_d_m3, rx1_d_m4; + + wire [1:0] rx2_ctl_m1, rx2_ctl_m2, rx2_ctl_m3, rx2_ctl_m4; + wire [7:0] rx2_d_m1, rx2_d_m2, rx2_d_m3, rx2_d_m4; + + + // MAC asserts when it determines RX data should be kept + wire [NUM_PHYS-1:0] rx_mac_keep; + wire [NUM_PHYS-1:0] rx_mac_wr_done; + + // drop filter outputs + wire rx_df_fifo_we_01, rx_df_fifo_we_02, rx_df_fifo_we_0u; + wire rx_df_fifo_we_10, rx_df_fifo_we_12; + wire rx_df_fifo_we_20, rx_df_fifo_we_21; + + wire [8:0] rx_df_fifo_d_01, rx_df_fifo_d_02, rx_df_fifo_d_0u; + wire [8:0] rx_df_fifo_d_10, rx_df_fifo_d_12; + wire [8:0] rx_df_fifo_d_20, rx_df_fifo_d_21; + wire [8:0] rx_df_fifo_d_u0; + + // pkt filter + wire [NUM_PHYS-1:0] trigger; + wire [NUM_PHYS-1:0] rx_enet_bcast; + wire [NUM_PHYS-1:0] rx_ipv4_arp; + wire rx_pf_keep_01, rx_pf_keep_02; + wire rx_pf_keep_10, rx_pf_keep_12; + wire rx_pf_keep_20, rx_pf_keep_21; + wire rx_pf_keep_0u; + wire rx_pf_keep_u0; + + // rx_fifos + wire [NUM_PHYS-1:0] rx_mac_fifo_we; + + // Read Enable from Switch to FIFO for transmit data + wire rx_sw_fifo_re_01, rx_sw_fifo_re_02, rx_sw_fifo_re_0u; + wire rx_sw_fifo_re_10, rx_sw_fifo_re_12; + wire rx_sw_fifo_re_20, rx_sw_fifo_re_21; + wire rx_sw_fifo_re_u0; + + // FIFO empty flags from FIFO to switch + wire rx_sf_fifo_empty_01, rx_sf_fifo_empty_02, rx_sf_fifo_empty_0u; + wire rx_sf_fifo_empty_10, rx_sf_fifo_empty_12; + wire rx_sf_fifo_empty_20, rx_sf_fifo_empty_21; + wire rx_uc_fifo_empty_u0; + + wire rx_sf_almost_full_01; + wire rx_sf_almost_full_10; + wire rx_sf_almost_full_20; + wire rx_sf_almost_full_0u; + + // data from FIFO to switch + wire [8:0] rx_sf_fifo_d_01, rx_sf_fifo_d_02, rx_sf_fifo_d_0u; + wire [8:0] rx_sf_fifo_d_10, rx_sf_fifo_d_12; + wire [8:0] rx_sf_fifo_d_20, rx_sf_fifo_d_21; + wire [8:0] rx_uc_fifo_d_u0; + + // data from MAC + wire [8:0] rx_mac_fifo_d0, rx_mac_fifo_d1, rx_mac_fifo_d2; + + // RX byte cnt and mode from MAC + wire [1:0] rx0_mode, rx1_mode, rx2_mode; + wire [NUM_PHYS-1:0] rx_byte_cnt; + wire [10:0] rx0_mac_byte_cnt; + wire [10:0] rx1_mac_byte_cnt; + wire [10:0] rx2_mac_byte_cnt; + wire [10:0] rxu_byte_cnt, rx_mle_byte_cnt; + + // ml_engine + wire mle_evt_start, mle_evt_active; + wire [NUM_ML_IF-1:0] mle_enable, mle_empty, mle_we; + wire mle_oe; + wire [8:0] mle_d_0, mle_d_1, mle_d_2, mle_d_3; + reg [8:0] mle_d_i; + wire mle_fifo_empty, mle_fifo_re; + wire [8:0] mle_fifo_d_o; + + // TX between switch and MAC + wire [8:0] tx_sw_fifo_d0, tx_sw_fifo_d1, tx_sw_fifo_d2, tx_sw_fifo_du; + wire [NUM_PHYS-1:0] tx_mac_fifo_re; + wire tx_uc_fifo_re; + wire [NUM_PHYS-1:0] tx_sw_fifo_empty; + wire tx_sw_fifo_we; // for controller path + wire [2:0] tx_sw_mode0, tx_sw_mode1, tx_sw_mode2; + wire [2:0] tx_modeu; + wire [NUM_PHYS-1:0] tx_mac_done; + wire [10:0] tx0_byte_cnt, tx1_byte_cnt, tx2_byte_cnt; + wire [2:0] tx_src_sel0, tx_src_sel1, tx_src_sel2; + + // TX between L3/L4 controller and MAC + wire tx_uc_fifo_empty, tx_mle_fifo_empty; + wire [8:0] tx_uc_fifo_d0, tx_mle_fifo_d0; + + // 100 Mbit + wire [NUM_PHYS-1:0] mode_100Mbit; + + // Controller Peripheral Address Decode and Select + wire mac_sel, pkt_filter_sel, mle_sel; + wire [1:0] mac_addr; + wire [15:0] pkt_filter_addr; + + // FCS RX + wire [1:0] fcs_rx_addr0, fcs_rx_addr1, fcs_rx_addr2; + wire [7:0] fcs_rx_din0, fcs_rx_din1, fcs_rx_din2; + wire [7:0] fcs_rx_dout0, fcs_rx_dout1, fcs_rx_dout2; + wire [NUM_PHYS-1:0] fcs_rx_init, fcs_rx_enable; + + // FCS TX + wire [1:0] fcs_tx_addr0, fcs_tx_addr1, fcs_tx_addr2; + wire [7:0] fcs_tx_din0, fcs_tx_din1, fcs_tx_din2; + wire [7:0] fcs_tx_dout0, fcs_tx_dout1, fcs_tx_dout2; + wire [NUM_PHYS-1:0] fcs_tx_init, fcs_tx_enable; + + // IPv4 + wire [NUM_PHYS-1:0] ipv4_pkt_start; + wire [NUM_PHYS-1:0] ipv4_pkt_complete; + wire [NUM_PHYS-1:0] ipv4_rx_keep; + wire [NUM_PHYS-1:0] ipv4_trigger_dst_addr; + wire ipv4_pkt_complete_c, ipv4_addr_match_c; + + // UDP + wire udp_port_match_c; + + // Network Debug & Metrics + wire [NUM_PHYS-1:0] mac_int; + wire [NUM_PHYS-1:0] mac_rx_active, mac_tx_active; + wire [NUM_PHYS-1:0] drop_rx0_active, drop_rx1_active, drop_rx2_active; + wire [NUM_PHYS-1:0] sync_rx0_active, sync_rx1_active, sync_rx2_active; + wire drop_rx0_active_u, sync_rx0_active_u; + wire [NUM_PHYS-1:0] rx_idle; + wire [NUM_PHYS-1:0] rx_mac_error; + wire [NUM_PHYS-1:0] rx_eop, rx_sop; + wire [NUM_PHYS-1:0] tx_eop, tx_sop, tx_error; + + // Common Internal Memory Bus + wire[15:0] mem_addr; + reg [31:0] mem_d_i; // direction is from the point of view of the controller + wire [31:0] mem_d_o; + wire mem_we, mem_oe; + wire mem_tgt_ready, mem_tgt_ready_mac_0, mem_tgt_ready_mac_1; + wire [15:0] mac_0_d_o, mac_1_d_o, mac_2_d_o; + wire [15:0] mle_d_o; + wire [10:0] hfifo_d_o; + + // half FIFO / Interface for Controller + wire hf_rx_fifo_int, hf_rx_fifo_int_acked; + wire hf_ptrs_sel, hf_rx_sel, hf_tx_sel; + + // DPRAM PARAM data from controller + wire [10:0] param_phy0_addr, param_phy1_addr, param_phy2_addr; + wire [8:0] param_phy0_din, param_phy1_din, param_phy2_din; + wire [8:0] param_phy0_dout, param_phy1_dout, param_phy2_dout; + wire [8:0] param_ram_0_do, param_ram_1_do, param_ram_2_do; + wire param_phy0_ce, param_phy1_ce, param_phy2_ce; + wire param_phy0_we, param_phy1_we, param_phy2_we; + wire [NUM_PHYS-1:0] param_sel; + + // MDIO controller and driver + wire mdio_cont_work_start, mdio_cont_work_done, mdio_cont_work_run; + wire [MDIO_ROM_ADDR_SZ-1:0] mdio_routine_addr; + wire mdio_done, mdo_oe; + wire mdo; + reg mdi; + wire [15:0] mdio_wd, mdio_rd; // write data, read data + wire mdio_rd_we; + wire mdio_ld, mdio_run; + wire mdio_rwn; + wire [4:0] mdio_reg_addr; // passed from mdio_cont -> mdio + wire [4:0] mdio_phy_addr; + wire [1:0] mdio_mux_sel; + + // MDIO Data block + wire [MDIO_ROM_ADDR_SZ-1:0] mdio_rom_a; + wire [7:0] mdio_rom_d; + wire [4:0] mdio_reg_addr_set; + wire [7:0] mdio_w_data_h_set, mdio_w_data_l_set; + + // Debug + wire [7:0] gpio_controller, gpio_ipv4; + reg evt_toggle; + + // Fabric PLL + pll pll_0( + .areset(reset), + .inclk0(clk_i), + .c0(clk_25), // 25 MHz + .c1(clk_125), // 125 MHz + .locked(pll_locked)); + + assign reset = ~rstn; + assign cont_clk = clk_25; + assign phy1_clk = clk_25; + assign pclk = clk_125; + + always @(posedge cont_clk, negedge rstn) + if (!rstn) + cnt_init <= 4'd0; + else if (cnt_init <= 4'd10) + cnt_init <= cnt_init + 1'b1; + + // Place holder logic to remove reset properly per system requirements + // TODO: Review this since it probably should negate after PLL_LOCK + always @(posedge cont_clk, negedge rstn) + if (!rstn) + sys_rstn <= 1'b0; + else if (cnt_init >= 10'd9) + sys_rstn <= 1'b1; + + // TODO: Review sequence and move to Controller control + assign phy0_rstn = sys_rstn; + assign phy1_rstn = pll_locked; + assign phy2_rstn = pll_locked; + + // TODO: Fix this + assign phy_resetn = {pll_locked, pll_locked, pll_locked}; + + assign phy_int = {~phy2_intn, ~phy1_intn, ~phy0_intn}; + + // TODO: This will be replaced when the SPI master peripheral is ready + assign flash_d = 8'hab; + assign flash_seln = 1'b1; + assign flash_clk = cont_clk; + + assign param_sel = 3'b000; + + // TODO: Gate these when not in use + assign phy0_mdc = cont_clk; + assign phy1_mdc = cont_clk; + assign phy2_mdc = cont_clk; + + assign phy2_gpio[0] = gpio_ipv4[0]; + assign phy2_gpio[1] = gpio_ipv4[1]; + + + // Bits 3:0 on the positive edge of RX_CLK and bits 7:4 on the negative edge of RX_CLK. + ddri rgmi_rx_0 ( + .datain ({phy0_rx_ctl, phy0_rx_d}), + .inclock (phy0_rx_clk), + .dataout_h ({rx0_ctl_i[0],rx0_d_i[3:0]}), + .dataout_l ({rx0_ctl_i[1],rx0_d_i[7:4]}) + ); + + ddri rgmi_rx_1 ( + .datain ({phy1_rx_ctl, phy1_rx_d}), + .inclock (phy1_rx_clk), + .dataout_h ({rx1_ctl_i[0],rx1_d_i[3:0]}), + .dataout_l ({rx1_ctl_i[1],rx1_d_i[7:4]}) + ); + + ddri rgmi_rx_2 ( + .datain ({phy2_rx_ctl, phy2_rx_d}), + .inclock (phy2_rx_clk), + .dataout_h ({rx2_ctl_i[0],rx2_d_i[3:0]}), + .dataout_l ({rx2_ctl_i[1],rx2_d_i[7:4]}) + ); + + + // Simple Pipeline to Make Timing + always @(posedge phy0_rx_clk, negedge rstn) + if (!rstn) begin + rx0_d_i_m1 <= 8'h0; + rx0_d_i_m2 <= 8'h0; + rx0_d_i_m3 <= 8'h0; + rx0_d_i_m4 <= 8'h0; + end + else begin + rx0_d_i_m1 <= rx0_d_i; + rx0_d_i_m2 <= {rx0_d_i[7:4], rx0_d_i_m1[3:0]} ; + rx0_d_i_m3 <= rx0_d_i_m2; + rx0_d_i_m4 <= rx0_d_i_m3; + end + + always @(posedge phy0_rx_clk, negedge rstn) + if (!rstn) begin + rx0_ctl_i_m1 <= 2'h0; + rx0_ctl_i_m2 <= 2'h0; + rx0_ctl_i_m3 <= 2'h0; + rx0_ctl_i_m4 <= 2'h0; + end + else begin + rx0_ctl_i_m1 <= rx0_ctl_i; + rx0_ctl_i_m2 <= {rx0_ctl_i[1],rx0_ctl_i_m1[0]}; + rx0_ctl_i_m3 <= rx0_ctl_i_m2; + rx0_ctl_i_m4 <= rx0_ctl_i_m3; + end + + // pipeline regs for PHY1 + always @(posedge phy1_rx_clk, negedge rstn) + if (!rstn) begin + rx1_d_i_m1 <= 8'h0; + rx1_d_i_m2 <= 8'h0; + rx1_d_i_m3 <= 8'h0; + rx1_d_i_m4 <= 8'h0; + end + else begin + rx1_d_i_m1 <= rx1_d_i; + rx1_d_i_m2 <= {rx1_d_i[7:4], rx1_d_i_m1[3:0]} ; + rx1_d_i_m3 <= rx1_d_i_m2; + rx1_d_i_m4 <= rx1_d_i_m3; + end + + always @(posedge phy1_rx_clk, negedge rstn) + if (!rstn) begin + rx1_ctl_i_m1 <= 2'h0; + rx1_ctl_i_m2 <= 2'h0; + rx1_ctl_i_m3 <= 2'h0; + rx1_ctl_i_m4 <= 2'h0; + end + else begin + rx1_ctl_i_m1 <= rx1_ctl_i; + rx1_ctl_i_m2 <= {rx1_ctl_i[1], rx1_ctl_i_m1[0]}; + rx1_ctl_i_m3 <= rx1_ctl_i_m2; + rx1_ctl_i_m4 <= rx1_ctl_i_m3; + end + +`ifdef PHY2_PRESENT + // pipeline regs for PHY2 + always @(posedge phy2_rx_clk, negedge rstn) + if (!rstn) begin + rx2_d_i_m1 <= 8'h0; + rx2_d_i_m2 <= 8'h0; + rx2_d_i_m3 <= 8'h0; + rx2_d_i_m4 <= 8'h0; + end + else begin + rx2_d_i_m1 <= rx2_d_i; + rx2_d_i_m2 <= {rx2_d_i[7:4], rx2_d_i_m1[3:0]} ; + rx2_d_i_m3 <= rx2_d_i_m2; + rx2_d_i_m4 <= rx2_d_i_m3; + end + + always @(posedge phy2_rx_clk, negedge rstn) + if (!rstn) begin + rx2_ctl_i_m1 <= 2'h0; + rx2_ctl_i_m2 <= 2'h0; + rx2_ctl_i_m3 <= 2'h0; + rx2_ctl_i_m4 <= 2'h0; + end + else begin + rx2_ctl_i_m1 <= rx2_ctl_i; + rx2_ctl_i_m2 <= {rx2_ctl_i[1], rx2_ctl_i_m1[0]}; + rx2_ctl_i_m3 <= rx2_ctl_i_m2; + rx2_ctl_i_m4 <= rx2_ctl_i_m3; + end +`endif + + + /* + * main controller + * + */ + controller #(.MDIO_ADDR_SZ(MDIO_ROM_ADDR_SZ), .NUM_PHYS(NUM_PHYS)) controller_0( + .rstn(sys_rstn), + .clk(cont_clk), + // status & errors + .phy_int(phy_int), + .mac_int(rx_mac_error), + // link status + .phy_up(phy_up), + // Memory Controller I/F + .mem_we(mem_we), + .mem_oe(mem_oe), + .mem_addr(mem_addr), + .mem_d_o(mem_d_o), + .mem_d_i(mem_d_i), + .mem_tgt_ready(mem_tgt_ready), + // Internal Device Selects + .mac_addr(mac_addr), + .pkt_filter_addr(pkt_filter_addr), + .pkt_filter_sel(pkt_filter_sel), + .mac_sel(mac_sel), + .mle_sel(mle_sel), + .hf_ptrs_sel(hf_ptrs_sel), + .hf_rx_sel(hf_rx_sel), + .hf_tx_sel(hf_tx_sel), + // half FIFO interface + .rx_fifo_int(hf_rx_fifo_int), + .rx_fifo_int_acked(hf_rx_fifo_int_acked), + .tx_fifo_empty(rx_uc_fifo_empty_u0), + // mdio_controller interface + .mdio_cont_start(mdio_cont_work_start), + .mdio_cont_done(mdio_cont_work_done), + .mdio_routine_addr(mdio_routine_addr), + .mdio_run(mdio_run), + .mdio_we(mdio_rd_we), + .mdio_d_i(mdio_rd), + .mdio_mux_sel(mdio_mux_sel), + // mdio_data params + .mdio_phy_addr(mdio_phy_addr), + .mdio_reg_addr(mdio_reg_addr_set), + .mdio_w_data_h(mdio_w_data_h_set), + .mdio_w_data_l(mdio_w_data_l_set), + // Device Resets + .phy_resetn(), + .mac_reset(mac_reset), + // Debug + .gpio(gpio_controller) + + ); + + assign mem_tgt_ready = mem_tgt_ready_mac_0 && mem_tgt_ready_mac_1; + + // controller data mux + always @(*) + casex({ hf_tx_sel, hf_rx_sel, hf_ptrs_sel, mle_sel, mac_sel, mac_addr}) + 7'b0000100: mem_d_i = {16'h0000, mac_0_d_o}; + 7'b0000101: mem_d_i = {16'h0000, mac_1_d_o}; + 7'b0000110: mem_d_i = {16'h0000, mac_2_d_o}; + 7'b00010??: mem_d_i = {16'h0000, mle_d_o}; + 7'b00100??: mem_d_i = {21'h0000, hfifo_d_o}; + 7'b01000??: mem_d_i = {21'h0000, hfifo_d_o}; + 7'b10000??: mem_d_i = {21'h0000, hfifo_d_o}; + default: mem_d_i = 32'd0; + endcase + + /* + * controller I/F FIFO + * FIFO side connects to network switch + * Switch/system perspective: + * RX: controller writes (data received into switch) + * TX: controller reads (data transmitted from switch) + */ + half_fifo micro_fifo_0 ( + .rstn( sys_rstn ), + .fifo_clk(pclk), + .uc_clk(cont_clk), + // controller interrupt support + .rx_fifo_int (hf_rx_fifo_int), + .rx_fifo_int_acked (hf_rx_fifo_int_acked), + // controller interface + .dpram_addr(mem_addr[10:0]), + .dpram_din(mem_d_o[10:0]), + .dpram_dout(hfifo_d_o), + .dpram_we(mem_we), + .dpram_oe(mem_oe), + .dpram_ptrs_sel(hf_ptrs_sel), + .dpram_tx_sel(hf_tx_sel), + .dpram_rx_sel(hf_rx_sel), + // TX: switch -> hfifo -> controller + .fifo_we(tx_sw_fifo_we), + .fifo_d_in(tx_sw_fifo_du), + // RX: controller -> hfifo -> switch + .fifo_re(rx_sw_fifo_re_u0), + .tx_byte_cnt(rxu_byte_cnt), + .fifo_d_out(rx_uc_fifo_d_u0), + .tx_empty(rx_uc_fifo_empty_u0) + ); + + mdio_cont #(.ADDR_SZ(MDIO_ROM_ADDR_SZ)) mdio_cont_0( + .rstn(sys_rstn), + .clk(cont_clk), + .work_start(mdio_cont_work_start), + .work_run(mdio_cont_work_run), + .work_done(mdio_cont_work_done), + .routine_addr(mdio_routine_addr), + .buffer_full(1'b0), + .addr(mdio_rom_a), + .di(mdio_rom_d), + .reg_addr(mdio_reg_addr), + .dout(mdio_wd), + .ld(mdio_ld), + .rwn(mdio_rwn), + .done(mdio_done) + ); + + mdio_data_ti mdio_data_ti_0( + .ad(mdio_rom_a), + .reg_addr(mdio_reg_addr_set), + .data_in_h(mdio_w_data_h_set), + .data_in_l(mdio_w_data_l_set), + .d(mdio_rom_d), + .oe(1'b1) + ); + + mdio mdio_0( + .rstn(sys_rstn), + .mdc(cont_clk), + // MDIO + .mdi(mdi), + .mdo(mdo), + .mdo_oe(mdo_oe), + // mdio controller interface + .rwn(mdio_rwn), + .phy_addr(mdio_phy_addr), + .reg_addr(mdio_reg_addr), + .di(mdio_wd), + .ld(mdio_ld), + .run(mdio_run), + .done(mdio_done), // signal controller that mdio xfer is done + // output port to converter + .dout(mdio_rd), + .we(mdio_rd_we) + ); + + + /* MDIO mux and output enables, infer open drain for each mdio I/O */ + always @(*) begin + case (mdio_mux_sel) + 2'b00: mdi = phy0_mdio; + 2'b01: mdi = phy1_mdio; + 2'b10: mdi = phy2_mdio; + endcase + end + + // Support all PHYs + assign phy0_mdio = (mdo_oe && mdio_mux_sel == 2'b00) ? mdo : 1'bz; + assign phy1_mdio = (mdo_oe && mdio_mux_sel == 2'b01) ? mdo : 1'bz; + assign phy2_mdio = (mdo_oe && mdio_mux_sel == 2'b10) ? mdo : 1'bz; + + + always@(*) + case(mle_enable) + 3'b001: mle_d_i = mle_d_0; + 3'b010: mle_d_i = mle_d_1; + 3'b100: mle_d_i = mle_d_2; + default: mle_d_i = 'd0; + endcase + + + ml_engine #(.NUM_IF(NUM_ML_IF)) ml_engine_0( + .rstn(sys_rstn), + .clk(pclk), + // controller interface + .cont_clk(cont_clk), + .cont_sel(mle_sel), + .cont_we(mem_we), + .cont_addr(mem_addr), + .cont_d_i(mem_d_o[15:0]), + .cont_d_o(mle_d_o), + .cont_tgt_ready(), + // module interface + .evt_start(mle_evt_start), + .evt_active(mle_evt_active), + .enable(mle_enable), + .clk_e(1'b1), + .we(|mle_we), + .empty(mle_empty), + .d_i(mle_d_i), + // switch interface + .fifo_empty_o(mle_fifo_empty), + .fifo_re(mle_fifo_re), + .fifo_d_o(mle_fifo_d_o), + .byte_cnt(rx_mle_byte_cnt) + ); + + /* + * Controls the routing of data and transmit modes + */ + switch switch_0( + .rstn(sys_rstn), + .clk(pclk), + // PHY status + .phy_up(phy_up), + .mode_100Mbit (mode_100Mbit), + // FIFO input data from RX FIFOs + .rx_d_01(rx_sf_fifo_d_01), + .rx_d_02(rx_sf_fifo_d_02), + .rx_d_0u(rx_sf_fifo_d_0u), + .rx_d_10(rx_sf_fifo_d_10), + .rx_d_12(rx_sf_fifo_d_12), + .rx_d_20(rx_sf_fifo_d_20), + .rx_d_21(rx_sf_fifo_d_21), + .rx_d_u0(rx_uc_fifo_d_u0), + .rx_mle_fifo_d(mle_fifo_d_o), + // RX FIFO read enables + .rx_fifo_re_01(rx_sw_fifo_re_01), + .rx_fifo_re_02(rx_sw_fifo_re_02), + .rx_fifo_re_0u(rx_sw_fifo_re_0u), + .rx_fifo_re_10(rx_sw_fifo_re_10), + .rx_fifo_re_12(rx_sw_fifo_re_12), + .rx_fifo_re_20(rx_sw_fifo_re_20), + .rx_fifo_re_21(rx_sw_fifo_re_21), + .rx_fifo_re_u0(rx_sw_fifo_re_u0), + .rx_fifo_re_mle(mle_fifo_re), + // RX FIFO Empty flags + .rx_fifo_empty_01(rx_sf_fifo_empty_01), + .rx_fifo_empty_02(rx_sf_fifo_empty_02), + .rx_fifo_empty_0u(rx_sf_fifo_empty_0u), + .rx_fifo_empty_10(rx_sf_fifo_empty_10), + .rx_fifo_empty_12(rx_sf_fifo_empty_12), + .rx_fifo_empty_20(rx_sf_fifo_empty_20), + .rx_fifo_empty_21(rx_sf_fifo_empty_21), + .rx_fifo_empty_u0(rx_uc_fifo_empty_u0), + .rx_fifo_empty_mle(mle_fifo_empty), + // Write done event + .rx_wr_done(rx_mac_wr_done), + // RX Byte Count + .rx0_byte_cnt(rx0_mac_byte_cnt), + .rx1_byte_cnt(rx1_mac_byte_cnt), + .rx2_byte_cnt(rx2_mac_byte_cnt), + .rxu_byte_cnt(rxu_byte_cnt), + .rx_mle_byte_cnt(rx_mle_byte_cnt), + // TX FIFO data output + .tx_d0(tx_sw_fifo_d0), + .tx_d1(tx_sw_fifo_d1), + .tx_d2(tx_sw_fifo_d2), + .tx_du(tx_sw_fifo_du), + // TX FIFO read enable + .tx_fifo_re(tx_mac_fifo_re), + .tx_fifo_we_u (tx_sw_fifo_we), + // TX FIFO Empty Flags + .tx_fifo_empty(tx_sw_fifo_empty), + // TX modes for the PHYs and uc + .tx_mode0(tx_sw_mode0), + .tx_mode1(tx_sw_mode1), + .tx_mode2(tx_sw_mode2), + .tx_modeu(tx_modeu), + // TX byte cnt + .tx0_byte_cnt(tx0_byte_cnt), + .tx1_byte_cnt(tx1_byte_cnt), + .tx2_byte_cnt(tx2_byte_cnt), + // TX Source Select + .tx0_src_sel(tx_src_sel0), + .tx1_src_sel(tx_src_sel1), + .tx2_src_sel(tx_src_sel2), + // TX state machine done flag + .tx_f(tx_mac_done), + .tx_custom(1'b0) + ); + + /* + * + * PHY0 IEEE 802.3 ETHERNET for Interface to 1000BASE-T LAN + * + */ + mac_rgmii mac_0( + .rstn(sys_rstn), + .phy_resetn (phy_resetn[0]), + .rx_clk(phy0_rx_clk), + .tx_clk(pclk), + .tap_port (1'b0), + // controller interface + .cont_clk(cont_clk), + .cont_sel(mac_sel & mac_addr == 2'b00), + .cont_we(mem_we), + .cont_addr(mem_addr[7:0]), + .cont_d_i(mem_d_o[15:0]), + .cont_d_o(mac_0_d_o), + .cont_tgt_ready(mem_tgt_ready_mac_0), + // ML engine interface + .mle_active(mle_evt_active), + .mle_if_enable(mle_enable[0]), + .mle_if_oe(mle_oe), + .mle_if_we(mle_we[0]), + .mle_if_empty(mle_empty[0]), + .mle_if_d_o(mle_d_0), + // Line State + .fixed_speed(1'b1), + .mode_100Mbit(mode_100Mbit[0]), + .phy_up(phy_up[0]), + // Switch I/F + .tx_mode(tx_sw_mode0), + .tx_f(tx_mac_done[0]), + // RGMII data I/F + .rx_ctl({rx0_ctl_i[1],rx0_ctl_i_m1[0]}), + .rx_d({rx0_d_i[7:4], rx0_d_i_m1[3:0]}), + .tx_ctl(tx0_ctl), + .tx_d(tx0_d), + // RX FCS + .fcs_rx_init(fcs_rx_init[0]), + .fcs_rx_enable(fcs_rx_enable[0]), + .fcs_rx_addr(fcs_rx_addr0), + .fcs_rx_dout(fcs_rx_din0), + .fcs_rx_din(fcs_rx_dout0), + // TX FCS + .fcs_tx_init(fcs_tx_init[0]), + .fcs_tx_enable(fcs_tx_enable[0]), + .fcs_tx_addr(fcs_tx_addr0), + .fcs_tx_dout(fcs_tx_din0), + .fcs_tx_din(fcs_tx_dout0), + // MAC RX / FIFO Write + .rx_fifo_we(rx_mac_fifo_we[0]), + .rx_fifo_d(rx_mac_fifo_d0), + .rx_keep(rx_mac_keep[0]), + .rx_wr_done(rx_mac_wr_done[0]), + .rx_byte_cnt(rx0_mac_byte_cnt), + .rx_idle(rx_idle[0]), + .rx_error(rx_mac_error[0]), + // MAC TX / FIFO Read + .tx_byte_cnt_i(tx0_byte_cnt), + .tx_src_sel(tx_src_sel0), + .tx_fifo_re(tx_mac_fifo_re[0]), + .tx_fifo_d(tx_sw_fifo_d0), + .tx_fifo_empty(tx_sw_fifo_empty[0]), + // Alternate TX Port (uC) + .tx_uc_fifo_empty(tx_uc_fifo_empty), + .tx_uc_fifo_d(tx_uc_fifo_d0), + // Alternate TX Port (MLE) + .tx_mle_fifo_empty(tx_mle_fifo_empty), + .tx_mle_fifo_d(tx_mle_fifo_d0), + // Packet Filter + .rx_sample(rx_sample[0]), + .ipv4_pkt_start(ipv4_pkt_start[0]), + .trigger(), + .rx_ctl_m1(rx0_ctl_m1), + .rx_ctl_m2(rx0_ctl_m2), + .rx_ctl_m3(rx0_ctl_m3), + .rx_ctl_m4(rx0_ctl_m4), + .rx_d_m1(rx0_d_m1), + .rx_d_m2(rx0_d_m2), + .rx_d_m3(rx0_d_m3), + .rx_d_m4(rx0_d_m4), + // Param RAM + .dpr_ad(param_phy0_addr), + .dpr_we(param_phy0_we), + .dpr_ce(param_phy0_ce), + .dpr_di(param_phy0_din), + .dpr_do(param_phy0_dout), + // Metrics and Interrupts + .rx_enet_bcast(rx_enet_bcast[0]), + .rx_ipv4_arp(rx_ipv4_arp[0]), + .rx_l3_proto(), + .rx_pkt_length(), + .mac_int(mac_int[0]), + .rx_sop(rx_sop[0]), + .rx_eop(rx_eop[0]), + .tx_sop(tx_sop[0]), + .tx_eop(tx_eop[0]), + .rx_active(mac_rx_active[0]), + .tx_active(mac_tx_active[0]) + ); + + + ipv4_rx ipv4_rx_0( + .rstn(sys_rstn), + .clk(phy0_rx_clk), + // control + .phy_resetn (phy_resetn[0]), + .phy_up(phy_up[0]), + // packet data + .pkt_start(ipv4_pkt_start[0]), + .rx_sample(rx_sample[0]), + .rx_eop(rx_eop[0]), + .rx_data_m1(rx0_d_m1), + .rx_data_m2(rx0_d_m2), + .rx_data_m3(rx0_d_m3), + .rx_data_m4(rx0_d_m4), + // flags + .pkt_complete(ipv4_pkt_complete[0]), + .trigger_src_addr(), + .trigger_dst_addr(ipv4_trigger_dst_addr[0]), + .keep(ipv4_rx_keep[0]) + ); + + udp_rx udp_rx_0( + .rstn(sys_rstn), + .clk(phy0_rx_clk), + // control + .phy_resetn (phy_resetn[0]), + .phy_up(phy_up[0]), + // packet data + .pkt_start(ipv4_trigger_dst_addr[0]), + .rx_sample(rx_sample[0]), + .rx_eop(rx_eop[0]), + .rx_data_m1(rx0_d_m1), + .rx_data_m2(rx0_d_m2), + .rx_data_m3(rx0_d_m3), + .rx_data_m4(rx0_d_m4), + // flags + .pkt_complete(), + .trigger_src_port(), + .trigger_dst_port(trigger[0]), + .keep() + ); + + + // PHY0 MAC -> PHY1 + pkt_filter pkt_filter_01( + .rstn(sys_rstn), + .clk(phy0_rx_clk), + // input for programming + .prgclk(cont_clk), + .sel(pkt_filter_sel && pkt_filter_addr == 16'h0001), + .we(mem_we), + .addr(mem_addr[2:0]), + .d_i(mem_d_o), + .d_o(), + // registered data + .rx_d_m1(rx0_d_m1), + .rx_d_m2(rx0_d_m2), + .rx_d_m3(rx0_d_m3), + .rx_d_m4(rx0_d_m4), + // filter + .new_frame (rx_sop[0]), + .block(1'b0), + .invert(1'b1), + .trigger(rx_mac_keep[0]), + .keep(rx_pf_keep_01) + ); + + drop_fifo drop_fifo_01( + .rstn(sys_rstn), + .phy_up(phy_up[0]), + .rx_clk(phy0_rx_clk), + .tx_clk(pclk), + .enable(1'b1), // ipv4_rx_keep[0] + // control + .keep (rx_pf_keep_01), + .passthrough(1'b0), + // input + .we_in(rx_mac_fifo_we[0]), + .wr_done(rx_mac_wr_done[0]), + .rx_idle(rx_idle[0]), + .rx_error(rx_mac_error[0]), + .d_in(rx_mac_fifo_d0), + // output + .we_out(rx_df_fifo_we_01), + .d_out(rx_df_fifo_d_01), + // debug + .active(drop_rx0_active[1]) + ); + + sync_fifo sync_fifo_rx_01( + .rstn(sys_rstn), + .clk (pclk), + // input + .we (rx_df_fifo_we_01 & phy_up[1]), + .d_in (rx_df_fifo_d_01), + // output + .re (rx_sw_fifo_re_01), + .d_out(rx_sf_fifo_d_01), + .empty(rx_sf_fifo_empty_01), + .almost_full(), + .reset_ptrs(1'b0), + // debug + .active(sync_rx0_active[1]) + ); + + +`ifdef PHY2_PRESENT + // PHY0 MAC -> PHY1 + pkt_filter pkt_filter_02( + .rstn(sys_rstn), + .clk(phy0_rx_clk), + // input for programming + .prgclk(cont_clk), + .sel(pkt_filter_sel && pkt_filter_addr == 16'h0002), + .we(mem_we), + .addr(mem_addr[2:0]), + .d_i(mem_d_o), + .d_o(), + // registered data + .rx_d_m1(rx0_d_m1), + .rx_d_m2(rx0_d_m2), + .rx_d_m3(rx0_d_m3), + .rx_d_m4(rx0_d_m4), + // filter + .new_frame (rx_sop[0]), + .block(1'b0), + .invert(1'b1), + .trigger(rx_mac_keep[0]), + .keep(rx_pf_keep_02) + ); + + drop_fifo drop_fifo_02( + .rstn(sys_rstn), + .phy_up(phy_up[0]), + .rx_clk(phy0_rx_clk), + .tx_clk(pclk), + .enable(1'b1), // ipv4_rx_keep[0] + // control + .keep (rx_pf_keep_02), + .passthrough(1'b0), + // input + .we_in(rx_mac_fifo_we[0]), + .wr_done(rx_mac_wr_done[0]), + .rx_idle(rx_idle[0]), + .rx_error(rx_mac_error[0]), + .d_in(rx_mac_fifo_d0), + // output + .we_out(rx_df_fifo_we_02), + .d_out(rx_df_fifo_d_02), + // debug + .active(drop_rx0_active[2]) + ); + + sync_fifo sync_fifo_rx_02( + .rstn(sys_rstn), + .clk (pclk), + // input + .we (rx_df_fifo_we_02 & phy_up[2]), + .d_in (rx_df_fifo_d_02), + // output + .re (rx_sw_fifo_re_02), + .d_out(rx_sf_fifo_d_02), + .empty(rx_sf_fifo_empty_02), + .almost_full(), + .reset_ptrs(1'b0), + // debug + .active(sync_rx0_active[2]) + ); +`endif + + ipv4_rx_c #(.IP_DST_MATCH_4(100)) ipv4_rx_c_0( + .rstn(sys_rstn), + .clk(phy0_rx_clk), + // control + .phy_up(phy_up[0]), + // packet data + .pkt_start(ipv4_pkt_start[0]), + .rx_sample(rx_sample[0]), + .rx_eop(rx_eop[0]), + .rx_data_m1(rx0_d_m1), + .rx_data_m2(rx0_d_m2), + .rx_data_m3(rx0_d_m3), + .rx_data_m4(rx0_d_m4), + // flags + .pkt_complete(ipv4_pkt_complete_c), + .ip_addr_match(ipv4_addr_match_c) + ); + + udp_rx_c udp_rx_c_0( + .rstn(sys_rstn), + .clk(phy0_rx_clk), + // control + .phy_up(phy_up[0]), + // packet data + .rx_sample(1'b1), + .pkt_start(ipv4_trigger_dst_addr[0]), + .rx_eop(rx_eop[0]), + .rx_data_m1(rx0_d_m1), + .rx_data_m2(rx0_d_m2), + .rx_data_m3(rx0_d_m3), + .rx_data_m4(rx0_d_m4), + // flags + .pkt_complete(), + .udp_port_match(udp_port_match_c) + ); + + + drop_fifo drop_fifo_0u( + .rstn(sys_rstn), + .phy_up(phy_up[0]), + .rx_clk(phy0_rx_clk), + .tx_clk(pclk), + .enable(ipv4_addr_match_c), + // control + .keep (udp_port_match_c), + .passthrough(1'b0), + // input + .we_in(rx_mac_fifo_we[0]), + .wr_done(rx_mac_wr_done[0]), + .rx_idle(rx_idle[0]), + .rx_error(rx_mac_error[0]), + .d_in(rx_mac_fifo_d0), + // output + .we_out(rx_df_fifo_we_0u), + .d_out(rx_df_fifo_d_0u), + .active(drop_rx0_active_u) + ); + + sync_fifo sync_fifo_rx_0u( + .rstn(sys_rstn), + .clk (pclk), + // input + .we (rx_df_fifo_we_0u), + .d_in (rx_df_fifo_d_0u), + // output + .re (rx_sw_fifo_re_0u), + .d_out(rx_sf_fifo_d_0u), + .empty(rx_sf_fifo_empty_0u), + .almost_full(rx_sf_almost_full_0u), + .reset_ptrs(1'b0), + // debug + .active(sync_rx0_active_u ) + ); + + dpram_inf #(.ADDR_WIDTH(10), .DPRAM_INIT("param_ram_0.txt")) param_ram_0( + .rstn(sys_rstn), + // Port A + .a_clk(cont_clk), + .a_clk_e(param_sel[0]), + .a_we(1'b0), + .a_oe(mem_oe), + .a_addr(mem_addr[9:0]), + .a_din(mem_d_o[8:0]), + .a_dout(param_ram_0_do), + // Port B + .b_clk(pclk), + .b_clk_e(param_phy0_ce), + .b_we(param_phy0_we), + .b_oe(1'b1), + .b_addr(param_phy0_addr[9:0]), + .b_din(param_phy0_dout), + .b_dout(param_phy0_din) + ); + + fcs fcs_rx_0( + .rstn(sys_rstn), + .clk(phy0_rx_clk), + .init(fcs_rx_init[0]), + .enable(fcs_rx_enable[0]), + .addr(fcs_rx_addr0), + .din(fcs_rx_din0), + .dout(fcs_rx_dout0) + ); + + fcs fcs_tx_0( + .rstn(sys_rstn), + .clk(pclk), + .init(fcs_tx_init[0]), + .enable(fcs_tx_enable[0]), + .addr(fcs_tx_addr0), + .din(fcs_tx_din0), + .dout(fcs_tx_dout0) + ); + + ipv4_tx_c ipv4_tx_c_0( + .rstn(sys_rstn), + .phy_resetn(phy_resetn[0]), + .clk(pclk), + // Control Interface + .cont_clk(cont_clk), + .cont_sel(ipv4_tx_c_sel), + .cont_we(mem_we), + .cont_addr(mem_addr[7:0]), + .cont_d_i(mem_d_o[15:0]), + .cont_d_o(), + // Line State + .mode_100Mbit(mode_100Mbit[0]), + .phy_up(phy_up[0]), + // Switch I/F + .tx_mode(tx_sw_mode0), + .tx_src_sel(tx_src_sel0), + .byte_cnt_i(tx0_byte_cnt), + // MAC Interface + .fifo_re_i(tx_mac_fifo_re[0]), + .fifo_empty_o(tx_uc_fifo_empty), + .fifo_d_o(tx_uc_fifo_d0), + // Debug + .gpio(gpio_ipv4) + ); + + ipv4_tx_mle ipv4_tx_mle_0( + .rstn(sys_rstn), + .phy_resetn(phy_resetn[0]), + .clk(pclk), + // Control Interface + .cont_clk(cont_clk), + .cont_sel(ipv4_tx_mle_sel), + .cont_we(mem_we), + .cont_addr(mem_addr[7:0]), + .cont_d_i(mem_d_o[15:0]), + .cont_d_o(), + // Line State + .mode_100Mbit(mode_100Mbit[0]), + .phy_up(phy_up[0]), + // Switch I/F + .tx_mode(tx_sw_mode0), + .tx_src_sel(tx_src_sel0), + .byte_cnt_i(tx0_byte_cnt), + // MAC Interface + .fifo_re_i(tx_mac_fifo_re[0]), + .fifo_empty_o(tx_mle_fifo_empty), + .fifo_d_o(tx_mle_fifo_d0), + // Debug + .gpio() + ); + + + /* + * + * PHY1 IEEE 802.3 ETHERNET for Interface to 1000BASE-T LAN + * + */ + mac_rgmii mac_1( + .rstn(sys_rstn), + .phy_resetn (phy_resetn[1]), + .rx_clk(phy1_rx_clk), + .tx_clk(pclk), + .tap_port (1'b0), + // Control Interface + .cont_clk(cont_clk), + .cont_sel(mac_sel & mac_addr == 2'b01), + .cont_we(mem_we), + .cont_addr(mem_addr[7:0]), + .cont_d_i(mem_d_o[15:0]), + .cont_d_o(mac_1_d_o), + .cont_tgt_ready(mem_tgt_ready_mac_1), + // ML engine interface + .mle_active(mle_evt_active), + .mle_if_enable(mle_enable[1]), + .mle_if_oe(mle_oe), + .mle_if_we(mle_we[1]), + .mle_if_empty(mle_empty[1]), + .mle_if_d_o(mle_d_1), + // Line State + .fixed_speed(1'b1), + .mode_100Mbit(mode_100Mbit[1]), + .phy_up(phy_up[1]), + // Switch I/F + .tx_mode(tx_sw_mode1), + .tx_f(tx_mac_done[1]), + // RGMII data I/F + .rx_ctl({rx1_ctl_i[1],rx1_ctl_i_m1[0]}), + .rx_d({rx1_d_i[7:4], rx1_d_i_m1[3:0]}), + .tx_ctl(tx1_ctl), + .tx_d(tx1_d), + // RX FCS + .fcs_rx_init(fcs_rx_init[1]), + .fcs_rx_enable(fcs_rx_enable[1]), + .fcs_rx_addr(fcs_rx_addr1), + .fcs_rx_dout(fcs_rx_din1), + .fcs_rx_din(fcs_rx_dout1), + // TX FCS + .fcs_tx_init(fcs_tx_init[1]), + .fcs_tx_enable(fcs_tx_enable[1]), + .fcs_tx_addr(fcs_tx_addr1), + .fcs_tx_dout(fcs_tx_din1), + .fcs_tx_din(fcs_tx_dout1), + // MAC RX / FIFO Write + .rx_fifo_we(rx_mac_fifo_we[1]), + .rx_fifo_d(rx_mac_fifo_d1), + .rx_keep(rx_mac_keep[1]), + .rx_wr_done(rx_mac_wr_done[1]), + .rx_byte_cnt(rx1_mac_byte_cnt), + .rx_idle(rx_idle[1]), + .rx_error(rx_mac_error[1]), + // MAC TX / FIFO Read + .tx_byte_cnt_i(tx1_byte_cnt), + .tx_src_sel(tx_src_sel1), + .tx_fifo_re(tx_mac_fifo_re[1]), + .tx_fifo_d(tx_sw_fifo_d1), + .tx_fifo_empty(tx_sw_fifo_empty[1]), + // Alternate TX Port + .tx_uc_fifo_empty(1'b1), // tie off to disable port + .tx_uc_fifo_d(9'd0), + .tx_mle_fifo_empty(1'b1), + .tx_mle_fifo_d(9'd0), + // Packet Filter + .rx_sample(rx_sample[1]), + .ipv4_pkt_start(ipv4_pkt_start[1]), + .trigger(), + .rx_ctl_m1(rx1_ctl_m1), + .rx_ctl_m2(rx1_ctl_m2), + .rx_ctl_m3(rx1_ctl_m3), + .rx_ctl_m4(rx1_ctl_m4), + .rx_d_m1(rx1_d_m1), + .rx_d_m2(rx1_d_m2), + .rx_d_m3(rx1_d_m3), + .rx_d_m4(rx1_d_m4), + // Param RAM + .dpr_ad(param_phy1_addr), + .dpr_we(param_phy1_we), + .dpr_ce(param_phy1_ce), + .dpr_di(param_phy1_din), + .dpr_do(param_phy1_dout), + // Metrics and Interrupts + .rx_enet_bcast(rx_enet_bcast[1]), + .rx_ipv4_arp(rx_ipv4_arp[1]), + .rx_l3_proto(), + .rx_pkt_length(), + .mac_int(mac_int[1]), + .rx_sop(rx_sop[1]), + .rx_eop(rx_eop[1]), + .tx_sop(tx_sop[1]), + .tx_eop(tx_eop[1]), + .rx_active(mac_rx_active[1]), + .tx_active(mac_tx_active[1]) + ); + + ipv4_rx ipv4_rx_1( + .rstn(sys_rstn), + .clk(phy1_rx_clk), + // control + .phy_resetn (phy_resetn[1]), + .phy_up(phy_up[1]), + // packet data + .pkt_start(ipv4_pkt_start[1]), + .rx_sample(rx_sample[1]), + .rx_eop(rx_eop[1]), + .rx_data_m1(rx1_d_m1), + .rx_data_m2(rx1_d_m2), + .rx_data_m3(rx1_d_m3), + .rx_data_m4(rx1_d_m4), + // flags + .pkt_complete(ipv4_pkt_complete[1]), + .trigger_src_addr(), + .trigger_dst_addr(ipv4_trigger_dst_addr[1]), + .keep(ipv4_rx_keep[1]) + ); + + udp_rx udp_rx_1( + .rstn(sys_rstn), + .clk(phy1_rx_clk), + // control + .phy_resetn (phy_resetn[1]), + .phy_up(phy_up[1]), + // packet data + .pkt_start(ipv4_trigger_dst_addr[1]), + .rx_sample(rx_sample[1]), + .rx_eop(rx_eop[1]), + .rx_data_m1(rx1_d_m1), + .rx_data_m2(rx1_d_m2), + .rx_data_m3(rx1_d_m3), + .rx_data_m4(rx1_d_m4), + // flags + .pkt_complete(), + .trigger_src_port(), + .trigger_dst_port(trigger[1]), + .keep() + ); + + + // PHY1 MAC -> PHY 0 + pkt_filter pkt_filter_10( + .rstn(sys_rstn), + .clk(phy1_rx_clk), + // input for programming + .prgclk(cont_clk), + .sel(pkt_filter_sel && pkt_filter_addr == 16'h1000), + .we(mem_we), + .addr(mem_addr[2:0]), + .d_i(mem_d_o), + .d_o(), + // registered data + .rx_d_m1(rx1_d_m1), + .rx_d_m2(rx1_d_m2), + .rx_d_m3(rx1_d_m3), + .rx_d_m4(rx1_d_m4), + // filter + .new_frame (rx_sop[1]), + .block(1'b0), + .invert(1'b1), + .trigger(rx_mac_keep[1]), + .keep(rx_pf_keep_10) + ); + + drop_fifo drop_fifo_10( + .rstn(sys_rstn), + .phy_up(phy_up[1]), + .rx_clk(phy1_rx_clk), + .tx_clk(pclk), + .enable(1'b1), // ipv4_rx_keep[1] + // control + .keep (rx_pf_keep_10), + .passthrough(1'b0), + // input + .we_in(rx_mac_fifo_we[1]), + .wr_done(rx_mac_wr_done[1]), + .rx_idle(rx_idle[1]), + .rx_error(rx_mac_error[1]), + .d_in(rx_mac_fifo_d1), + // output + .we_out(rx_df_fifo_we_10), + .d_out(rx_df_fifo_d_10), + // debug + .active(drop_rx1_active[0]) + ); + + sync_fifo sync_fifo_rx_10( + .rstn(sys_rstn), + .clk (pclk), + // input + .we (rx_df_fifo_we_10 & phy_up[0]), + .d_in (rx_df_fifo_d_10), + // output + .re (rx_sw_fifo_re_10), + .d_out(rx_sf_fifo_d_10), + .empty(rx_sf_fifo_empty_10), + .almost_full(), + .reset_ptrs(1'b0), + // debug + .active(sync_rx1_active[0]) + ); + +`ifdef PHY2_PRESENT + + // PHY1 MAC -> PHY2 + pkt_filter pkt_filter_12( + .rstn(sys_rstn), + .clk(phy1_rx_clk), + // input for programming + .prgclk(cont_clk), + .sel(pkt_filter_sel && pkt_filter_addr == 16'h1002), + .we(mem_we), + .addr(mem_addr[2:0]), + .d_i(mem_d_o), + .d_o(), + // registered data + .rx_d_m1(rx1_d_m1), + .rx_d_m2(rx1_d_m2), + .rx_d_m3(rx1_d_m3), + .rx_d_m4(rx1_d_m4), + // filter + .new_frame (rx_sop[1]), + .block(1'b0), + .invert(1'b1), + .trigger(rx_mac_keep[1]), + .keep(rx_pf_keep_12) + ); + + drop_fifo drop_fifo_12( + .rstn(sys_rstn), + .phy_up(phy_up[1]), + .rx_clk(phy1_rx_clk), + .tx_clk(pclk), + .enable(1'b1), // ipv4_rx_keep[1] + // control + .keep (rx_pf_keep_12), + .passthrough(1'b0), + // input + .we_in(rx_mac_fifo_we[1]), + .wr_done(rx_mac_wr_done[1]), + .rx_idle(rx_idle[1]), + .rx_error(rx_mac_error[1]), + .d_in(rx_mac_fifo_d1), + // output + .we_out(rx_df_fifo_we_12), + .d_out(rx_df_fifo_d_12), + // debug + .active(drop_rx1_active[2]) + ); + + sync_fifo sync_fifo_rx_12( + .rstn(sys_rstn), + .clk (pclk), + // input + .we (rx_df_fifo_we_12 & phy_up[2]), + .d_in (rx_df_fifo_d_12), + // output + .re (rx_sw_fifo_re_12), + .d_out(rx_sf_fifo_d_12), + .empty(rx_sf_fifo_empty_12), + .almost_full(), + .reset_ptrs(1'b0), + // debug + .active(sync_rx1_active[2]) + ); + +`endif + + dpram_inf #(.ADDR_WIDTH(10), .DPRAM_INIT("param_ram_1.txt")) param_ram_1( + .rstn(sys_rstn), + // Port A + .a_clk(cont_clk), + .a_clk_e(param_sel[1]), + .a_we(1'b0), + .a_oe(mem_oe), + .a_addr(mem_addr[9:0]), + .a_din(mem_d_o[8:0]), + .a_dout(param_ram_1_do), + // Port B + .b_clk(pclk), + .b_clk_e(param_phy1_ce), + .b_we(param_phy1_we), + .b_oe(1'b1), + .b_addr(param_phy1_addr[9:0]), + .b_din(param_phy1_dout), + .b_dout(param_phy1_din) + ); + + fcs fcs_rx_1( + .rstn(sys_rstn), + .clk(phy1_rx_clk), + .init(fcs_rx_init[1]), + .enable(fcs_rx_enable[1]), + .addr(fcs_rx_addr1), + .din(fcs_rx_din1), + .dout(fcs_rx_dout1) + ); + + fcs fcs_tx_1( + .rstn(sys_rstn), + .clk(pclk), + .init(fcs_tx_init[1]), + .enable(fcs_tx_enable[1]), + .addr(fcs_tx_addr1), + .din(fcs_tx_din1), + .dout(fcs_tx_dout1) + ); + +`ifdef PHY2_PRESENT + /* + * + * PHY2 IEEE 802.3 ETHERNET for Interface to 1000BASE-T LAN + * + */ + mac_rgmii mac_2( + .rstn(sys_rstn), + .phy_resetn (phy_resetn[2]), + .rx_clk(phy2_rx_clk), + .tx_clk(pclk), + .tap_port (1'b0), + // Control Interface + .cont_clk(cont_clk), + .cont_sel(mac_sel & mac_addr == 2'b10), + .cont_we(mem_we), + .cont_addr(mem_addr[7:0]), + .cont_d_i(mem_d_o[15:0]), + .cont_d_o(mac_2_d_o), + .cont_tgt_ready(mem_tgt_ready_mac_2), + // ML engine interface + .mle_active(mle_evt_active), + .mle_if_enable(mle_enable[2]), + .mle_if_oe(mle_oe), + .mle_if_we(mle_we[2]), + .mle_if_empty(mle_empty[2]), + .mle_if_d_o(mle_d_2), + // Line State + .fixed_speed(1'b1), + .mode_100Mbit(mode_100Mbit[2]), + .phy_up(phy_up[2]), + // Switch I/F + .tx_mode(tx_sw_mode2), + .tx_f(tx_mac_done[2]), + // RGMII data I/F + .rx_ctl({rx2_ctl_i[1],rx2_ctl_i_m1[0]}), + .rx_d({rx2_d_i[7:4], rx2_d_i_m1[3:0]}), + .tx_ctl(tx2_ctl), + .tx_d(tx2_d), + // RX FCS + .fcs_rx_init(fcs_rx_init[2]), + .fcs_rx_enable(fcs_rx_enable[2]), + .fcs_rx_addr(fcs_rx_addr2), + .fcs_rx_dout(fcs_rx_din2), + .fcs_rx_din(fcs_rx_dout2), + // TX FCS + .fcs_tx_init(fcs_tx_init[2]), + .fcs_tx_enable(fcs_tx_enable[2]), + .fcs_tx_addr(fcs_tx_addr2), + .fcs_tx_dout(fcs_tx_din2), + .fcs_tx_din(fcs_tx_dout2), + // MAC RX / FIFO Write + .rx_fifo_we(rx_mac_fifo_we[2]), + .rx_fifo_d(rx_mac_fifo_d2), + .rx_keep(rx_mac_keep[2]), + .rx_wr_done(rx_mac_wr_done[2]), + .rx_byte_cnt(rx2_mac_byte_cnt), + .rx_idle(rx_idle[2]), + .rx_error(rx_mac_error[2]), + // MAC TX / FIFO Read + .tx_byte_cnt_i(tx2_byte_cnt), + .tx_src_sel(tx_src_sel2), + .tx_fifo_re(tx_mac_fifo_re[2]), + .tx_fifo_d(tx_sw_fifo_d2), + .tx_fifo_empty(tx_sw_fifo_empty[2]), + // Alternate TX Port + .tx_uc_fifo_empty(1'b1), // tie off to disable port + .tx_uc_fifo_d(9'd0), + .tx_mle_fifo_empty(1'b1), + .tx_mle_fifo_d(9'd0), + // Packet Filter + .rx_sample(rx_sample[2]), + .ipv4_pkt_start(ipv4_pkt_start[2]), + .trigger(), + .rx_ctl_m1(rx2_ctl_m1), + .rx_ctl_m2(rx2_ctl_m2), + .rx_ctl_m3(rx2_ctl_m3), + .rx_ctl_m4(rx2_ctl_m4), + .rx_d_m1(rx2_d_m1), + .rx_d_m2(rx2_d_m2), + .rx_d_m3(rx2_d_m3), + .rx_d_m4(rx2_d_m4), + // Param RAM + .dpr_ad(param_phy2_addr), + .dpr_we(param_phy2_we), + .dpr_ce(param_phy2_ce), + .dpr_di(param_phy2_din), + .dpr_do(param_phy2_dout), + // Metrics and Interrupts + .rx_enet_bcast(rx_enet_bcast[2]), + .rx_ipv4_arp(rx_ipv4_arp[2]), + .rx_l3_proto(), + .rx_pkt_length(), + .mac_int(mac_int[2]), + .rx_sop(rx_sop[2]), + .rx_eop(rx_eop[2]), + .tx_sop(tx_sop[2]), + .tx_eop(tx_eop[2]), + .rx_active(mac_rx_active[2]), + .tx_active(mac_tx_active[2]) + ); + + ipv4_rx ipv4_rx_2( + .rstn(sys_rstn), + .clk(phy2_rx_clk), + // control + .phy_resetn (phy_resetn[2]), + .phy_up(phy_up[2]), + // packet data + .pkt_start(ipv4_pkt_start[2]), + .rx_sample(rx_sample[2]), + .rx_eop(rx_eop[2]), + .rx_data_m1(rx2_d_m1), + .rx_data_m2(rx2_d_m2), + .rx_data_m3(rx2_d_m3), + .rx_data_m4(rx2_d_m4), + // flags + .pkt_complete(ipv4_pkt_complete[2]), + .trigger_src_addr(), + .trigger_dst_addr(ipv4_trigger_dst_addr[2]), + .keep(ipv4_rx_keep[2]) + ); + + udp_rx udp_rx_2( + .rstn(sys_rstn), + .clk(phy2_rx_clk), + // control + .phy_resetn (phy_resetn[2]), + .phy_up(phy_up[2]), + // packet data + .pkt_start(ipv4_trigger_dst_addr[2]), + .rx_sample(rx_sample[2]), + .rx_eop(rx_eop[2]), + .rx_data_m1(rx2_d_m1), + .rx_data_m2(rx2_d_m2), + .rx_data_m3(rx2_d_m3), + .rx_data_m4(rx2_d_m4), + // flags + .pkt_complete(), + .trigger_src_port(), + .trigger_dst_port(trigger[2]), + .keep() + ); + + + // PHY2 MAC -> PHY 0 + pkt_filter pkt_filter_20( + .rstn(sys_rstn), + .clk(phy2_rx_clk), + // input for programming + .prgclk(cont_clk), + .sel(pkt_filter_sel && pkt_filter_addr == 16'h2000), + .we(mem_we), + .addr(mem_addr[2:0]), + .d_i(mem_d_o), + .d_o(), + // registered data + .rx_d_m1(rx2_d_m1), + .rx_d_m2(rx2_d_m2), + .rx_d_m3(rx2_d_m3), + .rx_d_m4(rx2_d_m4), + // filter + .new_frame (rx_sop[2]), + .block(1'b0), + .invert(1'b1), + .trigger(rx_mac_keep[2]), + .keep(rx_pf_keep_20) + ); + + drop_fifo drop_fifo_20( + .rstn(sys_rstn), + .phy_up(phy_up[2]), + .rx_clk(phy2_rx_clk), + .tx_clk(pclk), + .enable(1'b1), // ipv4_rx_keep[2] + // control + .keep (rx_pf_keep_20), + .passthrough(1'b0), + // input + .we_in(rx_mac_fifo_we[2]), + .wr_done(rx_mac_wr_done[2]), + .rx_idle(rx_idle[2]), + .rx_error(rx_mac_error[2]), + .d_in(rx_mac_fifo_d2), + // output + .we_out(rx_df_fifo_we_20), + .d_out(rx_df_fifo_d_20), + // debug + .active(drop_rx2_active[0]) + ); + + sync_fifo sync_fifo_rx_20( + .rstn(sys_rstn), + .clk (pclk), + // input + .we (rx_df_fifo_we_20 & phy_up[0]), + .d_in (rx_df_fifo_d_20), + // output + .re (rx_sw_fifo_re_20), + .d_out(rx_sf_fifo_d_20), + .empty(rx_sf_fifo_empty_20), + .almost_full(), + .reset_ptrs(1'b0), + // debug + .active(sync_rx2_active[0]) + ); + + + // PHY1 MAC -> PHY2 + pkt_filter pkt_filter_21( + .rstn(sys_rstn), + .clk(phy2_rx_clk), + // input for programming + .prgclk(cont_clk), + .sel(pkt_filter_sel && pkt_filter_addr == 16'h2001), + .we(mem_we), + .addr(mem_addr[2:0]), + .d_i(mem_d_o), + .d_o(), + // registered data + .rx_d_m1(rx2_d_m1), + .rx_d_m2(rx2_d_m2), + .rx_d_m3(rx2_d_m3), + .rx_d_m4(rx2_d_m4), + // filter + .new_frame (rx_sop[2]), + .block(1'b0), + .invert(1'b1), + .trigger(rx_mac_keep[2]), + .keep(rx_pf_keep_21) + ); + + drop_fifo drop_fifo_21( + .rstn(sys_rstn), + .phy_up(phy_up[2]), + .rx_clk(phy2_rx_clk), + .tx_clk(pclk), + .enable(1'b1), // ipv4_rx_keep[1] + // control + .keep (rx_pf_keep_21), + .passthrough(1'b0), + // input + .we_in(rx_mac_fifo_we[2]), + .wr_done(rx_mac_wr_done[2]), + .rx_idle(rx_idle[2]), + .rx_error(rx_mac_error[2]), + .d_in(rx_mac_fifo_d2), + // output + .we_out(rx_df_fifo_we_21), + .d_out(rx_df_fifo_d_21), + // debug + .active(drop_rx2_active[1]) + ); + + sync_fifo sync_fifo_rx_21( + .rstn(sys_rstn), + .clk (pclk), + // input + .we (rx_df_fifo_we_21 & phy_up[1]), + .d_in (rx_df_fifo_d_21), + // output + .re (rx_sw_fifo_re_21), + .d_out(rx_sf_fifo_d_21), + .empty(rx_sf_fifo_empty_21), + .almost_full(), + .reset_ptrs(1'b0), + // debug + .active(sync_rx2_active[2]) + ); + +`endif + + dpram_inf #(.ADDR_WIDTH(10), .DPRAM_INIT("param_ram_2.txt")) param_ram_2( + .rstn(sys_rstn), + // Port A + .a_clk(cont_clk), + .a_clk_e(param_sel[2]), + .a_we(1'b0), + .a_oe(mem_oe), + .a_addr(mem_addr[9:0]), + .a_din(mem_d_o[8:0]), + .a_dout(param_ram_2_do), + // Port B + .b_clk(pclk), + .b_clk_e(param_phy2_ce), + .b_we(param_phy2_we), + .b_oe(1'b1), + .b_addr(param_phy2_addr[9:0]), + .b_din(param_phy2_dout), + .b_dout(param_phy2_din) + ); + + fcs fcs_rx_2( + .rstn(sys_rstn), + .clk(phy2_rx_clk), + .init(fcs_rx_init[2]), + .enable(fcs_rx_enable[2]), + .addr(fcs_rx_addr2), + .din(fcs_rx_din2), + .dout(fcs_rx_dout2) + ); + + fcs fcs_tx_2( + .rstn(sys_rstn), + .clk(pclk), + .init(fcs_tx_init[2]), + .enable(fcs_tx_enable[2]), + .addr(fcs_tx_addr2), + .din(fcs_tx_din2), + .dout(fcs_tx_dout2) + ); + + +`ifdef PASSTHROUGH + // phy0_tx_clk = phy1_rx_clk; + // Bits 3:0 on the positive edge of TX_CLK and bits 7:4 on the negative edge of TX_CLK. + // Note that PHY TX (output) clocks are routed through a DDR. + ddro rgmii_tx_0( + .aclr(1'b0), + .datain_h({1'b1, rx1_ctl_i_m4[0],rx1_d_i_m4[3:0]}), + .datain_l({1'b0, rx1_ctl_i_m4[1],rx1_d_i_m4[7:4]}), + .oe(1'b1), + .outclock(phy1_rx_clk), + .dataout({phy0_tx_clk, phy0_tx_ctl, phy0_tx_d})); + + // phy1_tx_clk = phy0_rx_clk; + ddro rgmii_tx_1( + .aclr(1'b0), + .datain_h({1'b1, rx0_ctl_i_m4[0],rx0_d_i_m4[3:0]}), + .datain_l({1'b0, rx0_ctl_i_m4[1],rx0_d_i_m4[7:4]}), + .oe(1'b1), + .outclock(phy0_rx_clk), + .dataout({phy1_tx_clk, phy1_tx_ctl, phy1_tx_d})); + + // phy2_tx_clk = phy0_rx_clk; + ddro rgmii_tx_2( + .aclr(1'b0), + .datain_h({1'b1, rx0_ctl_i_m4[0],rx0_d_i_m4[3:0]}), + .datain_l({1'b0, rx0_ctl_i_m4[1],rx0_d_i_m4[7:4]}), + .oe(1'b1), + .outclock(phy0_rx_clk), + .dataout({phy2_tx_clk, phy2_tx_ctl, phy2_tx_d})); + +`else + + ddro rgmii_tx_0( + .aclr(1'b0), + .datain_h({1'b1, tx0_ctl[0], tx0_d[3:0]}), + .datain_l({1'b0, tx0_ctl[1], tx0_d[7:4]}), + .oe(1'b1), + .outclock(pclk), + .dataout({phy0_tx_clk, phy0_tx_ctl, phy0_tx_d})); + + ddro rgmii_tx_1( + .aclr(1'b0), + .datain_h({1'b1, tx1_ctl[0],tx1_d[3:0]}), + .datain_l({1'b0, tx1_ctl[1],tx1_d[7:4]}), + .oe(1'b1), + .outclock(pclk), + .dataout({phy1_tx_clk, phy1_tx_ctl, phy1_tx_d})); + + ddro rgmii_tx_2( + .aclr(1'b0), + .datain_h({1'b1, tx2_ctl[0],tx2_d[3:0]}), + .datain_l({1'b0, tx2_ctl[1],tx2_d[7:4]}), + .oe(1'b1), + .outclock(pclk), + .dataout({phy2_tx_clk, phy2_tx_ctl, phy2_tx_d})); + +`endif + +// Debug + + //Heart beat cnt for LEDs and general debug + always @(posedge cont_clk, negedge sys_rstn) + if (!sys_rstn) + heart_beat_cnt <= 26'h0; + else + heart_beat_cnt <= heart_beat_cnt + 1'b1; + + always @(posedge pclk, negedge sys_rstn) + if (!sys_rstn) + evt_toggle <= 1'b0; + else if (mle_evt_start) + evt_toggle <= ~evt_toggle; + + assign fpga_led[0] = heart_beat_cnt[22]; + assign fpga_led[1] = heart_beat_cnt[23]; + assign fpga_led[2] = evt_toggle; + +endmodule diff --git a/manufacturer/altera/cyclone10_lp/src/betsy_passthrough_regs.v b/manufacturer/altera/cyclone10_lp/src/betsy_passthrough_regs.v new file mode 100644 index 0000000..2ebf8a1 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/src/betsy_passthrough_regs.v @@ -0,0 +1,375 @@ +/* + * betsy.v + * + * Copyright (C) 2024 Private Island Networks Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * function: top module for three instantiated Ethernet PHYs + controllers + * + * + */ + +module betsy ( + input rstn, + input clk, // 25Mhz + + input phy0_clk, + output phy1_clk, + + // PHY0 RGMII + output phy0_rstn, + + input phy0_rx_clk, + input phy0_rx_ctl, + input [3:0] phy0_rx_d, + + output phy0_tx_clk, + output phy0_tx_ctl, + output [3:0] phy0_tx_d, + + output phy0_mdc, + inout phy0_mdio, + + input phy0_intn, + inout [1:0] phy0_gpio, + + // PHY1 RGMII + output phy1_rstn, + + input phy1_rx_clk, + input phy1_rx_ctl, + input [3:0] phy1_rx_d, + + output phy1_tx_clk, + output phy1_tx_ctl, + output [3:0] phy1_tx_d, + + output phy1_mdc, + inout phy1_mdio, + + input phy1_intn, + inout [1:0] phy1_gpio, + + // PHY2 RGMII + output phy2_rstn, + + input phy2_rx_clk, + input phy2_rx_ctl, + input [3:0] phy2_rx_d, + + output phy2_tx_clk, + output phy2_tx_ctl, + output[3:0] phy2_tx_d, + + output phy2_mdc, + inout phy2_mdio, + + input phy2_intn, + inout [1:0] phy2_gpio, + + // FLASH + output flash_clk, + input flash_dqs, + output flash_seln, + inout [7:0] flash_d, + + // Debug + output [2:0] fpga_led + ); + +localparam LINK_NORMAL_INTERFRAME = 2'b00, + LINK_PHY_STATUS = 2'b01, + LINK_ERROR_DATA_RX = 2'b10, + LINK_NORMAL_DATA_RX = 2'b11; + +localparam MDIO_ROM_ADDR_SZ = 7; + + +reg [25:0] heart_beat_cnt; +reg [7:0] datain_h_sig, datain_l_sig; +wire [7:0] dataout_h_sig, dataout_l_sig; + +wire [7:0] rx0_d, rx1_d; +wire [1:0] rx0_ctl, rx1_ctl; +reg [7:0] rx0_d_m1, rx0_d_m2, rx0_d_m3, rx0_d_m4; +reg [1:0] rx0_ctl_m1, rx0_ctl_m2, rx0_ctl_m3, rx0_ctl_m4; +reg rx0_sop, rx0_eop; +reg [7:0] rx1_d_m1, rx1_d_m2, rx1_d_m3, rx1_d_m4; +reg [1:0] rx1_ctl_m1, rx1_ctl_m2, rx1_ctl_m3, rx1_ctl_m4; +reg [15:0] rx_cnt; +reg [1:0] link_state; +reg link_up; + +reg [1:0] link_speed; // TODO: what's the right IEEE name? +reg link_duplex; + +// MDIO controller and driver +wire mdio_cont_work_start, mdio_cont_work_run; +wire mdio_cont_work_done; +wire [MDIO_ROM_ADDR_SZ-1:0] mdio_routine_addr; +wire [1:0] mdio_mux_sel; +wire mdio_done, mdo_oe; +wire mdo; +reg mdi; +wire [15:0] mdio_wd; +wire [15:0] mdio_rd; +wire [4:0] mdio_reg_addr; +wire mdio_ld, mdio_run; +wire mdio_rwn; +wire bin_to_ascii_run; + +// MDIO Data block +wire [MDIO_ROM_ADDR_SZ-1:0] rom_a; +wire [7:0] rom_d; +wire [4:0] mdio_reg_addr_set; +wire [7:0] mdio_w_data_h_set, mdio_w_data_l_set; +wire [4:0] mdio_page_set; +wire bin_to_ascii_we, mdio_rd_we, cont_rd_we; + +// Debug +wire pcs_pclk; // main fabric clock for Ethernet pipeline +wire pll_locked; + +pll pll_0( + .areset(~rstn), + .inclk0(clk), + .c0(phy1_clk), + .c1(pcs_pclk), + .locked(pll_locked)); + +// TODO: I have the h/l assignments backwards, SDC is wrong +ddri rgmi_rx_0 ( + .datain ( {phy0_rx_ctl, phy0_rx_d} ), + .inclock ( phy0_rx_clk ), + .dataout_h ( {rx0_ctl[1],rx0_d[7:4]} ), + .dataout_l ( {rx0_ctl[0],rx0_d[3:0]} ) + ); + + +ddri rgmi_rx_1 ( + .datain ( {phy1_rx_ctl, phy1_rx_d} ), + .inclock ( phy1_rx_clk ), + .dataout_h ( {rx1_ctl[1],rx1_d[7:4]} ), + .dataout_l ( {rx1_ctl[0],rx1_d[3:0]} ) + ); + +assign phy0_tx_clk = phy1_rx_clk; +ddro rgmii_tx_0( + .aclr(1'b0), + .datain_l({rx1_ctl_m4[1],rx1_d_m4[7:4]}), + .datain_h({rx1_ctl_m4[0],rx1_d_m4[3:0]}), + .oe(1'b1), + .outclock(phy1_rx_clk), + .dataout({phy0_tx_ctl, phy0_tx_d})); + +assign phy1_tx_clk = phy0_rx_clk; +ddro rgmii_tx_1( + .aclr(1'b0), + .datain_l({rx0_ctl_m4[1],rx0_d_m4[7:4]}), + .datain_h({rx0_ctl_m4[0],rx0_d_m4[3:0]}), + .oe(1'b1), + .outclock(phy0_rx_clk), + .dataout({phy1_tx_ctl, phy1_tx_d})); + +assign phy2_tx_clk = phy0_rx_clk; +ddro rgmii_tx_2( + .aclr(1'b0), + .datain_h({rx0_ctl_m4[1],rx0_d_m4[7:4]}), + .datain_l({rx0_ctl_m4[0],rx0_d_m4[3:0]}), + .oe(1'b1), + .outclock(phy0_rx_clk), + .dataout({phy2_tx_ctl, phy2_tx_d})); + +// pipeline regs +always @(posedge phy0_rx_clk, negedge rstn) + if (!rstn) begin + rx0_d_m1 <= 8'h0; + rx0_d_m2 <= 8'h0; + rx0_d_m3 <= 8'h0; + rx0_d_m4 <= 8'h0; + end + else begin + rx0_d_m1 <= rx0_d; + rx0_d_m2 <= rx0_d_m1; + rx0_d_m3 <= rx0_d_m2; + rx0_d_m4 <= rx0_d_m3; + end + +always @(posedge phy0_rx_clk, negedge rstn) + if (!rstn) begin + rx0_ctl_m1 <= 2'h0; + rx0_ctl_m2 <= 2'h0; + rx0_ctl_m3 <= 2'h0; + rx0_ctl_m4 <= 2'h0; + end + else begin + rx0_ctl_m1 <= rx0_ctl; + rx0_ctl_m2 <= rx0_ctl_m1; + rx0_ctl_m3 <= rx0_ctl_m2; + rx0_ctl_m4 <= rx0_ctl_m3; + end + +// TODO: take into account errors RXERR +always @(posedge phy0_rx_clk, negedge rstn) + if (!rstn) + rx0_sop <= 1'b0; + else if (!rx0_ctl_m1[0] && rx0_ctl[0]) + rx0_sop <= 1'b1; + else + rx0_sop <= 1'b0; + +// TODO: take into account errors take into account errors +always @(posedge phy0_rx_clk, negedge rstn) + if (!rstn) + rx0_eop <= 1'b0; + else if (rx0_ctl_m1[0] && !rx0_ctl[0]) + rx0_eop <= 1'b1; + else + rx0_eop <= 1'b0; + +// pipeline regs +always @(posedge phy0_rx_clk, negedge rstn) + if (!rstn) begin + rx1_d_m1 <= 8'h0; + rx1_d_m2 <= 8'h0; + rx1_d_m3 <= 8'h0; + rx1_d_m4 <= 8'h0; + end + else begin + rx1_d_m1 <= rx1_d; + rx1_d_m2 <= rx1_d_m1; + rx1_d_m3 <= rx1_d_m2; + rx1_d_m4 <= rx1_d_m3; + end + +always @(posedge phy0_rx_clk, negedge rstn) + if (!rstn) begin + rx1_ctl_m1 <= 2'h0; + rx1_ctl_m2 <= 2'h0; + rx1_ctl_m3 <= 2'h0; + rx1_ctl_m4 <= 2'h0; + end + else begin + rx1_ctl_m1 <= rx1_ctl; + rx1_ctl_m2 <= rx1_ctl_m1; + rx1_ctl_m3 <= rx1_ctl_m2; + rx1_ctl_m4 <= rx1_ctl_m3; + end + + +// capture link metrics during normal inter-frame +always @(posedge phy0_rx_clk, negedge rstn) + if (!rstn) begin + link_up <= 1'b0; + link_speed <= 2'b11; // reserved + link_duplex <= 1'b0; + end + else if (rx0_ctl_m1 == 2'b00) begin + link_up <= rx0_d_m1[0]; + link_speed <= rx0_d_m1[2:1]; + link_duplex <= rx0_d_m1[3]; + end + +// capture link_state +always @(posedge phy0_rx_clk, negedge rstn) + if (!rstn) + link_state <= LINK_NORMAL_INTERFRAME; + else + link_state <= rx0_ctl_m1; + +assign phy0_rstn = 1'b1; +assign phy1_rstn = pll_locked; +assign phy2_rstn = pll_locked; + +assign flash_d = 8'hab; +assign flash_seln = 1'b1; +assign flash_clk = clk; + +//Heart beat by 50MHz clock +always @(posedge clk or negedge rstn) + if (!rstn) begin + heart_beat_cnt <= 26'h0; //0x3FFFFFF + end + else begin + heart_beat_cnt <= heart_beat_cnt + 1'b1; + end + + +assign phy0_mdc = clk; +assign phy1_mdc = clk; +assign phy2_mdc = clk; + +assign phy0_mdio = mdo_oe ? mdo : 1'bz; +assign phy1_mdio = 1'b0; +assign phy2_mdio = 1'b0; + +assign fpga_led[0] = heart_beat_cnt[22]; +assign fpga_led[1] = heart_beat_cnt[23]; +assign fpga_led[2] = heart_beat_cnt[24]; + +assign phy2_gpio[0] = rx0_sop; +assign phy2_gpio[1] = rx0_eop; + + + +mdio_controller #(.ADDR_SZ( MDIO_ROM_ADDR_SZ )) mdio_controller_0 + ( + .rstn(rstn), + .clk(clk), + .work_start(mdio_cont_work_start), + .work_run(mdio_cont_work_run), + .work_done(mdio_cont_work_done), + .routine_addr( mdio_routine_addr ), + .buffer_full(1'b0), + .addr(rom_a), + .di(rom_d), + .reg_addr(mdio_reg_addr), + .dout(mdio_wd), + .ld(mdio_ld), + .rwn(mdio_rwn), + .done(mdio_done) + ); + +mdio_data_ti #(.ADDR_SZ( MDIO_ROM_ADDR_SZ )) mdio_data_ti_0( + .ad( rom_a ), + .page( mdio_page_set ), + .reg_addr( mdio_reg_addr_set ), + .data_in_h( mdio_w_data_h_set ), + .data_in_l( mdio_w_data_l_set ), + .d( rom_d ), + .oe( 1'b1 ) + ); + +mdio mdio_0( + .rstn(rstn), + .mdc(clk_10), + // MDIO + .mdi(mdi), + .mdo(mdo), + .mdo_oe(mdo_oe), + // mdio controller interface + .rwn(mdio_rwn), + .phy_addr(5'h00), + .reg_addr(mdio_reg_addr), + .di(mdio_wd), + .ld(mdio_ld), + .run( mdio_run ), + .done(mdio_done), // signal controller that mdio xfer is done + // output port to converter + .dout(mdio_rd), + .we( mdio_rd_we ) + ); + + +endmodule diff --git a/manufacturer/altera/cyclone10_lp/zero.txt b/manufacturer/altera/cyclone10_lp/zero.txt new file mode 100644 index 0000000..1de4c4e --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/zero.txt @@ -0,0 +1,2048 @@ +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 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