manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio_inst.v


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ddrio	ddrio_inst (
	.aclr ( aclr_sig ),
	.datain_h ( datain_h_sig ),
	.datain_l ( datain_l_sig ),
	.inclock ( inclock_sig ),
	.inclocken ( inclocken_sig ),
	.oe ( oe_sig ),
	.outclock ( outclock_sig ),
	.outclocken ( outclocken_sig ),
	.dataout_h ( dataout_h_sig ),
	.dataout_l ( dataout_l_sig ),
	.padio ( padio_sig )
	);