summaryrefslogtreecommitdiffhomepage
path: root/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.qip
blob: 3eb030b265af5e2eb86d19851f13b0f91bc8bbd6 (plain)
1
2
3
4
5
6
7
8
9
10
set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT"
set_global_assignment -name IP_TOOL_VERSION "25.1"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone 10 LP}"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ddro.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddro.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddro_inst.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddro_bb.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddro.inc"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddro.cmp"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddro.ppf"]

Highly Recommended Verilog Books