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diff --git a/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.qip b/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.qip
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+++ b/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.qip
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+set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT"
+set_global_assignment -name IP_TOOL_VERSION "25.1"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone 10 LP}"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ddro.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddro.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddro_inst.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddro_bb.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddro.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddro.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddro.ppf"]

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