diff options
Diffstat (limited to 'manufacturer/altera/cyclone10_lp/ip/rgmii_txd')
8 files changed, 364 insertions, 0 deletions
diff --git a/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.bsf b/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.bsf new file mode 100644 index 0000000..1cf5c0d --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.bsf @@ -0,0 +1,79 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 2025 Altera Corporation. All rights reserved. +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, the Altera Quartus Prime License Agreement, +the Altera IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Altera and sold by Altera or its authorized distributors. Please +refer to the Altera Software License Subscription Agreements +on the Quartus Prime software download page. +*/ +(header "symbol" (version "1.2")) +(symbol + (rect 0 0 224 144) + (text "ddro" (rect 99 -2 133 16)(font "Dialog" (font_size 10))) + (text "inst" (rect 8 129 24 140)(font "Arial" )) + (port + (pt 0 48) + (input) + (text "datain_h[5..0]" (rect 0 0 82 15)(font "Dialog" (font_size 8))) + (text "datain_h[5..0]" (rect 4 33 73 47)(font "Dialog" (font_size 8))) + (line (pt 0 48)(pt 80 48)(line_width 3)) + ) + (port + (pt 0 64) + (input) + (text "datain_l[5..0]" (rect 0 0 79 15)(font "Dialog" (font_size 8))) + (text "datain_l[5..0]" (rect 4 49 69 63)(font "Dialog" (font_size 8))) + (line (pt 0 64)(pt 80 64)(line_width 3)) + ) + (port + (pt 0 80) + (input) + (text "oe" (rect 0 0 15 15)(font "Dialog" (font_size 8))) + (text "oe" (rect 4 65 16 79)(font "Dialog" (font_size 8))) + (line (pt 0 80)(pt 80 80)) + ) + (port + (pt 0 96) + (input) + (text "outclock" (rect 0 0 51 15)(font "Dialog" (font_size 8))) + (text "outclock" (rect 4 81 47 95)(font "Dialog" (font_size 8))) + (line (pt 0 96)(pt 80 96)) + ) + (port + (pt 0 112) + (input) + (text "aclr" (rect 0 0 22 15)(font "Dialog" (font_size 8))) + (text "aclr" (rect 4 97 23 111)(font "Dialog" (font_size 8))) + (line (pt 0 112)(pt 80 112)) + ) + (port + (pt 224 48) + (output) + (text "dataout[5..0]" (rect 0 0 79 15)(font "Dialog" (font_size 8))) + (text "dataout[5..0]" (rect 168 33 233 47)(font "Dialog" (font_size 8))) + (line (pt 224 48)(pt 144 48)(line_width 3)) + ) + (drawing + (line (pt 80 32)(pt 144 32)) + (line (pt 144 32)(pt 144 128)) + (line (pt 80 128)(pt 144 128)) + (line (pt 80 32)(pt 80 128)) + (line (pt 0 0)(pt 224 0)) + (line (pt 224 0)(pt 224 144)) + (line (pt 0 144)(pt 224 144)) + (line (pt 0 0)(pt 0 144)) + ) +) diff --git a/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.cmp b/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.cmp new file mode 100644 index 0000000..dbbc5a8 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.cmp @@ -0,0 +1,27 @@ +--Copyright (C) 2025 Altera Corporation. All rights reserved. +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and any partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, the Altera Quartus Prime License Agreement, +--the Altera IP License Agreement, or other applicable license +--agreement, including, without limitation, that your use is for +--the sole purpose of programming logic devices manufactured by +--Altera and sold by Altera or its authorized distributors. Please +--refer to the Altera Software License Subscription Agreements +--on the Quartus Prime software download page. + + +component ddro + PORT + ( + aclr : IN STD_LOGIC ; + datain_h : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + datain_l : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + oe : IN STD_LOGIC ; + outclock : IN STD_LOGIC ; + dataout : OUT STD_LOGIC_VECTOR (5 DOWNTO 0) + ); +end component; diff --git a/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.inc b/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.inc new file mode 100644 index 0000000..98c6145 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.inc @@ -0,0 +1,28 @@ +--Copyright (C) 2025 Altera Corporation. All rights reserved. +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and any partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, the Altera Quartus Prime License Agreement, +--the Altera IP License Agreement, or other applicable license +--agreement, including, without limitation, that your use is for +--the sole purpose of programming logic devices manufactured by +--Altera and sold by Altera or its authorized distributors. Please +--refer to the Altera Software License Subscription Agreements +--on the Quartus Prime software download page. + + +FUNCTION ddro +( + aclr, + datain_h[5..0], + datain_l[5..0], + oe, + outclock +) + +RETURNS ( + dataout[5..0] +); diff --git a/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.ppf b/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.ppf new file mode 100644 index 0000000..2d6a4da --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.ppf @@ -0,0 +1,13 @@ +<?xml version="1.0" encoding="UTF-8" ?> +<!DOCTYPE pinplan> +<pinplan intended_family="Cyclone 10 LP" variation_name="ddro" megafunction_name="ALTDDIO_OUT" specifies="all_ports"> +<global> +<pin name="aclr" direction="input" scope="external" /> +<pin name="datain_h[5..0]" direction="input" scope="external" /> +<pin name="datain_l[5..0]" direction="input" scope="external" /> +<pin name="oe" direction="input" scope="external" /> +<pin name="outclock" direction="input" scope="external" source="clock" /> +<pin name="dataout[5..0]" direction="output" scope="external" /> + +</global> +</pinplan> diff --git a/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.qip b/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.qip new file mode 100644 index 0000000..3eb030b --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.qip @@ -0,0 +1,10 @@ +set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT" +set_global_assignment -name IP_TOOL_VERSION "25.1" +set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone 10 LP}" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ddro.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddro.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddro_inst.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddro_bb.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddro.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddro.cmp"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddro.ppf"] diff --git a/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.v b/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.v new file mode 100644 index 0000000..87d2856 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.v @@ -0,0 +1,115 @@ +// megafunction wizard: %ALTDDIO_OUT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: ALTDDIO_OUT + +// ============================================================ +// File Name: ddro.v +// Megafunction Name(s): +// ALTDDIO_OUT +// +// Simulation Library Files(s): +// +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 25.1std.0 Build 1129 10/21/2025 SC Standard Edition +// ************************************************************ + + +//Copyright (C) 2025 Altera Corporation. All rights reserved. +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and any partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, the Altera Quartus Prime License Agreement, +//the Altera IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Altera and sold by Altera or its authorized distributors. Please +//refer to the Altera Software License Subscription Agreements +//on the Quartus Prime software download page. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module ddro ( + aclr, + datain_h, + datain_l, + oe, + outclock, + dataout); + + input aclr; + input [5:0] datain_h; + input [5:0] datain_l; + input oe; + input outclock; + output [5:0] dataout; + + wire [5:0] sub_wire0; + wire [5:0] dataout = sub_wire0[5:0]; + + altddio_out ALTDDIO_OUT_component ( + .aclr (aclr), + .datain_h (datain_h), + .datain_l (datain_l), + .oe (oe), + .outclock (outclock), + .dataout (sub_wire0), + .aset (1'b0), + .oe_out (), + .outclocken (1'b1), + .sclr (1'b0), + .sset (1'b0)); + defparam + ALTDDIO_OUT_component.extend_oe_disable = "OFF", + ALTDDIO_OUT_component.intended_device_family = "Cyclone 10 LP", + ALTDDIO_OUT_component.invert_output = "OFF", + ALTDDIO_OUT_component.lpm_hint = "UNUSED", + ALTDDIO_OUT_component.lpm_type = "altddio_out", + ALTDDIO_OUT_component.oe_reg = "UNREGISTERED", + ALTDDIO_OUT_component.power_up_high = "OFF", + ALTDDIO_OUT_component.width = 6; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP" +// Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "OFF" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP" +// Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF" +// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out" +// Retrieval info: CONSTANT: OE_REG STRING "UNREGISTERED" +// Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF" +// Retrieval info: CONSTANT: WIDTH NUMERIC "6" +// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr" +// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +// Retrieval info: USED_PORT: datain_h 0 0 6 0 INPUT NODEFVAL "datain_h[5..0]" +// Retrieval info: CONNECT: @datain_h 0 0 6 0 datain_h 0 0 6 0 +// Retrieval info: USED_PORT: datain_l 0 0 6 0 INPUT NODEFVAL "datain_l[5..0]" +// Retrieval info: CONNECT: @datain_l 0 0 6 0 datain_l 0 0 6 0 +// Retrieval info: USED_PORT: dataout 0 0 6 0 OUTPUT NODEFVAL "dataout[5..0]" +// Retrieval info: CONNECT: dataout 0 0 6 0 @dataout 0 0 6 0 +// Retrieval info: USED_PORT: oe 0 0 0 0 INPUT NODEFVAL "oe" +// Retrieval info: CONNECT: @oe 0 0 0 0 oe 0 0 0 0 +// Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "outclock" +// Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL ddro.v TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddro.qip TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddro.bsf TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddro_inst.v TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddro_bb.v TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddro.inc TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddro.cmp TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddro.ppf TRUE FALSE diff --git a/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro_bb.v b/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro_bb.v new file mode 100644 index 0000000..1529ff1 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro_bb.v @@ -0,0 +1,84 @@ +// megafunction wizard: %ALTDDIO_OUT%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: ALTDDIO_OUT + +// ============================================================ +// File Name: ddro.v +// Megafunction Name(s): +// ALTDDIO_OUT +// +// Simulation Library Files(s): +// +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 25.1std.0 Build 1129 10/21/2025 SC Standard Edition +// ************************************************************ + +//Copyright (C) 2025 Altera Corporation. All rights reserved. +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and any partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, the Altera Quartus Prime License Agreement, +//the Altera IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Altera and sold by Altera or its authorized distributors. Please +//refer to the Altera Software License Subscription Agreements +//on the Quartus Prime software download page. + +module ddro ( + aclr, + datain_h, + datain_l, + oe, + outclock, + dataout); + + input aclr; + input [5:0] datain_h; + input [5:0] datain_l; + input oe; + input outclock; + output [5:0] dataout; + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP" +// Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "OFF" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP" +// Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF" +// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out" +// Retrieval info: CONSTANT: OE_REG STRING "UNREGISTERED" +// Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF" +// Retrieval info: CONSTANT: WIDTH NUMERIC "6" +// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr" +// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +// Retrieval info: USED_PORT: datain_h 0 0 6 0 INPUT NODEFVAL "datain_h[5..0]" +// Retrieval info: CONNECT: @datain_h 0 0 6 0 datain_h 0 0 6 0 +// Retrieval info: USED_PORT: datain_l 0 0 6 0 INPUT NODEFVAL "datain_l[5..0]" +// Retrieval info: CONNECT: @datain_l 0 0 6 0 datain_l 0 0 6 0 +// Retrieval info: USED_PORT: dataout 0 0 6 0 OUTPUT NODEFVAL "dataout[5..0]" +// Retrieval info: CONNECT: dataout 0 0 6 0 @dataout 0 0 6 0 +// Retrieval info: USED_PORT: oe 0 0 0 0 INPUT NODEFVAL "oe" +// Retrieval info: CONNECT: @oe 0 0 0 0 oe 0 0 0 0 +// Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "outclock" +// Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL ddro.v TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddro.qip TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddro.bsf TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddro_inst.v TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddro_bb.v TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddro.inc TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddro.cmp TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddro.ppf TRUE FALSE diff --git a/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro_inst.v b/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro_inst.v new file mode 100644 index 0000000..32dfbbb --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro_inst.v @@ -0,0 +1,8 @@ +ddro ddro_inst ( + .aclr ( aclr_sig ), + .datain_h ( datain_h_sig ), + .datain_l ( datain_l_sig ), + .oe ( oe_sig ), + .outclock ( outclock_sig ), + .dataout ( dataout_sig ) + ); |
