diff options
Diffstat (limited to 'manufacturer/altera/cyclone10_lp/ip')
28 files changed, 1790 insertions, 0 deletions
diff --git a/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio.bsf b/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio.bsf new file mode 100644 index 0000000..9eba5e3 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio.bsf @@ -0,0 +1,114 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 2025 Altera Corporation. All rights reserved. +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, the Altera Quartus Prime License Agreement, +the Altera IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Altera and sold by Altera or its authorized distributors. Please +refer to the Altera Software License Subscription Agreements +on the Quartus Prime software download page. +*/ +(header "symbol" (version "1.2")) +(symbol + (rect 0 0 224 192) + (text "ddrio" (rect 98 -2 136 16)(font "Dialog" (font_size 10))) + (text "inst" (rect 8 177 24 188)(font "Arial" )) + (port + (pt 0 48) + (input) + (text "datain_h[7..0]" (rect 0 0 82 15)(font "Dialog" (font_size 8))) + (text "datain_h[7..0]" (rect 4 33 73 47)(font "Dialog" (font_size 8))) + (line (pt 0 48)(pt 80 48)(line_width 3)) + ) + (port + (pt 0 64) + (input) + (text "datain_l[7..0]" (rect 0 0 79 15)(font "Dialog" (font_size 8))) + (text "datain_l[7..0]" (rect 4 49 69 63)(font "Dialog" (font_size 8))) + (line (pt 0 64)(pt 80 64)(line_width 3)) + ) + (port + (pt 0 80) + (input) + (text "oe" (rect 0 0 15 15)(font "Dialog" (font_size 8))) + (text "oe" (rect 4 65 16 79)(font "Dialog" (font_size 8))) + (line (pt 0 80)(pt 80 80)) + ) + (port + (pt 0 96) + (input) + (text "inclock" (rect 0 0 42 15)(font "Dialog" (font_size 8))) + (text "inclock" (rect 4 81 39 95)(font "Dialog" (font_size 8))) + (line (pt 0 96)(pt 80 96)) + ) + (port + (pt 0 112) + (input) + (text "inclocken" (rect 0 0 57 15)(font "Dialog" (font_size 8))) + (text "inclocken" (rect 4 97 51 111)(font "Dialog" (font_size 8))) + (line (pt 0 112)(pt 80 112)) + ) + (port + (pt 0 128) + (input) + (text "outclock" (rect 0 0 51 15)(font "Dialog" (font_size 8))) + (text "outclock" (rect 4 113 47 127)(font "Dialog" (font_size 8))) + (line (pt 0 128)(pt 80 128)) + ) + (port + (pt 0 144) + (input) + (text "outclocken" (rect 0 0 67 15)(font "Dialog" (font_size 8))) + (text "outclocken" (rect 4 129 59 143)(font "Dialog" (font_size 8))) + (line (pt 0 144)(pt 80 144)) + ) + (port + (pt 0 160) + (input) + (text "aclr" (rect 0 0 22 15)(font "Dialog" (font_size 8))) + (text "aclr" (rect 4 145 23 159)(font "Dialog" (font_size 8))) + (line (pt 0 160)(pt 80 160)) + ) + (port + (pt 224 48) + (output) + (text "dataout_h[7..0]" (rect 0 0 92 15)(font "Dialog" (font_size 8))) + (text "dataout_h[7..0]" (rect 158 33 235 47)(font "Dialog" (font_size 8))) + (line (pt 224 48)(pt 144 48)(line_width 3)) + ) + (port + (pt 224 64) + (output) + (text "dataout_l[7..0]" (rect 0 0 87 15)(font "Dialog" (font_size 8))) + (text "dataout_l[7..0]" (rect 162 49 235 63)(font "Dialog" (font_size 8))) + (line (pt 224 64)(pt 144 64)(line_width 3)) + ) + (port + (pt 224 80) + (output) + (text "padio[7..0]" (rect 0 0 64 15)(font "Dialog" (font_size 8))) + (text "padio[7..0]" (rect 177 65 231 79)(font "Dialog" (font_size 8))) + (line (pt 224 80)(pt 144 80)(line_width 3)) + ) + (drawing + (line (pt 80 32)(pt 144 32)) + (line (pt 144 32)(pt 144 176)) + (line (pt 80 176)(pt 144 176)) + (line (pt 80 32)(pt 80 176)) + (line (pt 0 0)(pt 224 0)) + (line (pt 224 0)(pt 224 192)) + (line (pt 0 192)(pt 224 192)) + (line (pt 0 0)(pt 0 192)) + ) +) diff --git a/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio.ppf b/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio.ppf new file mode 100644 index 0000000..03c4cef --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio.ppf @@ -0,0 +1,18 @@ +<?xml version="1.0" encoding="UTF-8" ?> +<!DOCTYPE pinplan> +<pinplan intended_family="Cyclone 10 LP" variation_name="ddrio" megafunction_name="ALTDDIO_BIDIR" specifies="all_ports"> +<global> +<pin name="aclr" direction="input" scope="external" /> +<pin name="datain_h[7..0]" direction="input" scope="external" /> +<pin name="datain_l[7..0]" direction="input" scope="external" /> +<pin name="inclock" direction="input" scope="external" source="clock" /> +<pin name="inclocken" direction="input" scope="external" /> +<pin name="oe" direction="input" scope="external" /> +<pin name="outclock" direction="input" scope="external" source="clock" /> +<pin name="outclocken" direction="input" scope="external" /> +<pin name="dataout_h[7..0]" direction="output" scope="external" /> +<pin name="dataout_l[7..0]" direction="output" scope="external" /> +<pin name="padio[7..0]" direction="bidir" scope="external" /> + +</global> +</pinplan> diff --git a/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio.qip b/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio.qip new file mode 100644 index 0000000..b3dfeb4 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio.qip @@ -0,0 +1,8 @@ +set_global_assignment -name IP_TOOL_NAME "ALTDDIO_BIDIR" +set_global_assignment -name IP_TOOL_VERSION "25.1" +set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone 10 LP}" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ddrio.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddrio.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddrio_inst.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddrio_bb.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddrio.ppf"] diff --git a/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio.v b/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio.v new file mode 100644 index 0000000..44b81db --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio.v @@ -0,0 +1,145 @@ +// megafunction wizard: %ALTDDIO_BIDIR% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: ALTDDIO_BIDIR + +// ============================================================ +// File Name: ddrio.v +// Megafunction Name(s): +// ALTDDIO_BIDIR +// +// Simulation Library Files(s): +// +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 25.1std.0 Build 1129 10/21/2025 SC Standard Edition +// ************************************************************ + + +//Copyright (C) 2025 Altera Corporation. All rights reserved. +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and any partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, the Altera Quartus Prime License Agreement, +//the Altera IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Altera and sold by Altera or its authorized distributors. Please +//refer to the Altera Software License Subscription Agreements +//on the Quartus Prime software download page. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module ddrio ( + aclr, + datain_h, + datain_l, + inclock, + inclocken, + oe, + outclock, + outclocken, + dataout_h, + dataout_l, + padio); + + input aclr; + input [7:0] datain_h; + input [7:0] datain_l; + input inclock; + input inclocken; + input oe; + input outclock; + input outclocken; + output [7:0] dataout_h; + output [7:0] dataout_l; + inout [7:0] padio; + + wire [7:0] sub_wire0; + wire [7:0] sub_wire1; + wire [7:0] dataout_h = sub_wire0[7:0]; + wire [7:0] dataout_l = sub_wire1[7:0]; + + altddio_bidir ALTDDIO_BIDIR_component ( + .padio (padio), + .aclr (aclr), + .datain_h (datain_h), + .datain_l (datain_l), + .inclock (inclock), + .inclocken (inclocken), + .oe (oe), + .outclock (outclock), + .outclocken (outclocken), + .dataout_h (sub_wire0), + .dataout_l (sub_wire1), + .aset (1'b0), + .combout (), + .dqsundelayedout (), + .oe_out (), + .sclr (1'b0), + .sset (1'b0)); + defparam + ALTDDIO_BIDIR_component.extend_oe_disable = "ON", + ALTDDIO_BIDIR_component.implement_input_in_lcell = "ON", + ALTDDIO_BIDIR_component.intended_device_family = "Cyclone 10 LP", + ALTDDIO_BIDIR_component.invert_output = "OFF", + ALTDDIO_BIDIR_component.lpm_hint = "UNUSED", + ALTDDIO_BIDIR_component.lpm_type = "altddio_bidir", + ALTDDIO_BIDIR_component.oe_reg = "REGISTERED", + ALTDDIO_BIDIR_component.power_up_high = "OFF", + ALTDDIO_BIDIR_component.width = 8; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP" +// Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "ON" +// Retrieval info: CONSTANT: IMPLEMENT_INPUT_IN_LCELL STRING "ON" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP" +// Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF" +// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_bidir" +// Retrieval info: CONSTANT: OE_REG STRING "REGISTERED" +// Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF" +// Retrieval info: CONSTANT: WIDTH NUMERIC "8" +// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr" +// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +// Retrieval info: USED_PORT: datain_h 0 0 8 0 INPUT NODEFVAL "datain_h[7..0]" +// Retrieval info: CONNECT: @datain_h 0 0 8 0 datain_h 0 0 8 0 +// Retrieval info: USED_PORT: datain_l 0 0 8 0 INPUT NODEFVAL "datain_l[7..0]" +// Retrieval info: CONNECT: @datain_l 0 0 8 0 datain_l 0 0 8 0 +// Retrieval info: USED_PORT: dataout_h 0 0 8 0 OUTPUT NODEFVAL "dataout_h[7..0]" +// Retrieval info: CONNECT: dataout_h 0 0 8 0 @dataout_h 0 0 8 0 +// Retrieval info: USED_PORT: dataout_l 0 0 8 0 OUTPUT NODEFVAL "dataout_l[7..0]" +// Retrieval info: CONNECT: dataout_l 0 0 8 0 @dataout_l 0 0 8 0 +// Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "inclock" +// Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0 +// Retrieval info: USED_PORT: inclocken 0 0 0 0 INPUT NODEFVAL "inclocken" +// Retrieval info: CONNECT: @inclocken 0 0 0 0 inclocken 0 0 0 0 +// Retrieval info: USED_PORT: oe 0 0 0 0 INPUT NODEFVAL "oe" +// Retrieval info: CONNECT: @oe 0 0 0 0 oe 0 0 0 0 +// Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "outclock" +// Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0 +// Retrieval info: USED_PORT: outclocken 0 0 0 0 INPUT NODEFVAL "outclocken" +// Retrieval info: CONNECT: @outclocken 0 0 0 0 outclocken 0 0 0 0 +// Retrieval info: USED_PORT: padio 0 0 8 0 BIDIR NODEFVAL "padio[7..0]" +// Retrieval info: CONNECT: padio 0 0 8 0 @padio 0 0 8 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio.v TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio.qip TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio.bsf TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio_inst.v TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio_bb.v TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio.inc FALSE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio.cmp FALSE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio.ppf TRUE FALSE diff --git a/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio_bb.v b/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio_bb.v new file mode 100644 index 0000000..f489c24 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio_bb.v @@ -0,0 +1,105 @@ +// megafunction wizard: %ALTDDIO_BIDIR%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: ALTDDIO_BIDIR + +// ============================================================ +// File Name: ddrio.v +// Megafunction Name(s): +// ALTDDIO_BIDIR +// +// Simulation Library Files(s): +// +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 25.1std.0 Build 1129 10/21/2025 SC Standard Edition +// ************************************************************ + +//Copyright (C) 2025 Altera Corporation. All rights reserved. +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and any partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, the Altera Quartus Prime License Agreement, +//the Altera IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Altera and sold by Altera or its authorized distributors. Please +//refer to the Altera Software License Subscription Agreements +//on the Quartus Prime software download page. + +module ddrio ( + aclr, + datain_h, + datain_l, + inclock, + inclocken, + oe, + outclock, + outclocken, + dataout_h, + dataout_l, + padio); + + input aclr; + input [7:0] datain_h; + input [7:0] datain_l; + input inclock; + input inclocken; + input oe; + input outclock; + input outclocken; + output [7:0] dataout_h; + output [7:0] dataout_l; + inout [7:0] padio; + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP" +// Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "ON" +// Retrieval info: CONSTANT: IMPLEMENT_INPUT_IN_LCELL STRING "ON" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP" +// Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF" +// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_bidir" +// Retrieval info: CONSTANT: OE_REG STRING "REGISTERED" +// Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF" +// Retrieval info: CONSTANT: WIDTH NUMERIC "8" +// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr" +// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +// Retrieval info: USED_PORT: datain_h 0 0 8 0 INPUT NODEFVAL "datain_h[7..0]" +// Retrieval info: CONNECT: @datain_h 0 0 8 0 datain_h 0 0 8 0 +// Retrieval info: USED_PORT: datain_l 0 0 8 0 INPUT NODEFVAL "datain_l[7..0]" +// Retrieval info: CONNECT: @datain_l 0 0 8 0 datain_l 0 0 8 0 +// Retrieval info: USED_PORT: dataout_h 0 0 8 0 OUTPUT NODEFVAL "dataout_h[7..0]" +// Retrieval info: CONNECT: dataout_h 0 0 8 0 @dataout_h 0 0 8 0 +// Retrieval info: USED_PORT: dataout_l 0 0 8 0 OUTPUT NODEFVAL "dataout_l[7..0]" +// Retrieval info: CONNECT: dataout_l 0 0 8 0 @dataout_l 0 0 8 0 +// Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "inclock" +// Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0 +// Retrieval info: USED_PORT: inclocken 0 0 0 0 INPUT NODEFVAL "inclocken" +// Retrieval info: CONNECT: @inclocken 0 0 0 0 inclocken 0 0 0 0 +// Retrieval info: USED_PORT: oe 0 0 0 0 INPUT NODEFVAL "oe" +// Retrieval info: CONNECT: @oe 0 0 0 0 oe 0 0 0 0 +// Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "outclock" +// Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0 +// Retrieval info: USED_PORT: outclocken 0 0 0 0 INPUT NODEFVAL "outclocken" +// Retrieval info: CONNECT: @outclocken 0 0 0 0 outclocken 0 0 0 0 +// Retrieval info: USED_PORT: padio 0 0 8 0 BIDIR NODEFVAL "padio[7..0]" +// Retrieval info: CONNECT: padio 0 0 8 0 @padio 0 0 8 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio.v TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio.qip TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio.bsf TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio_inst.v TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio_bb.v TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio.inc FALSE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio.cmp FALSE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio.ppf TRUE FALSE diff --git a/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio_inst.v b/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio_inst.v new file mode 100644 index 0000000..a999d47 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio_inst.v @@ -0,0 +1,13 @@ +ddrio ddrio_inst ( + .aclr ( aclr_sig ), + .datain_h ( datain_h_sig ), + .datain_l ( datain_l_sig ), + .inclock ( inclock_sig ), + .inclocken ( inclocken_sig ), + .oe ( oe_sig ), + .outclock ( outclock_sig ), + .outclocken ( outclocken_sig ), + .dataout_h ( dataout_h_sig ), + .dataout_l ( dataout_l_sig ), + .padio ( padio_sig ) + ); diff --git a/manufacturer/altera/cyclone10_lp/ip/pll/pll.bsf b/manufacturer/altera/cyclone10_lp/ip/pll/pll.bsf new file mode 100644 index 0000000..0e82eda --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/pll/pll.bsf @@ -0,0 +1,96 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 2025 Altera Corporation. All rights reserved. +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, the Altera Quartus Prime License Agreement, +the Altera IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Altera and sold by Altera or its authorized distributors. Please +refer to the Altera Software License Subscription Agreements +on the Quartus Prime software download page. +*/ +(header "symbol" (version "1.2")) +(symbol + (rect 0 0 272 160) + (text "pll" (rect 129 0 144 15)(font "Arial" (font_size 10))) + (text "inst" (rect 8 145 24 156)(font "Arial" )) + (port + (pt 0 64) + (input) + (text "inclk0" (rect 0 0 34 13)(font "Arial" (font_size 8))) + (text "inclk0" (rect 4 52 31 63)(font "Arial" (font_size 8))) + (line (pt 0 64)(pt 48 64)) + ) + (port + (pt 0 80) + (input) + (text "areset" (rect 0 0 36 13)(font "Arial" (font_size 8))) + (text "areset" (rect 4 68 34 79)(font "Arial" (font_size 8))) + (line (pt 0 80)(pt 48 80)) + ) + (port + (pt 272 64) + (output) + (text "c0" (rect 0 0 14 13)(font "Arial" (font_size 8))) + (text "c0" (rect 255 52 266 63)(font "Arial" (font_size 8))) + ) + (port + (pt 272 80) + (output) + (text "c1" (rect 0 0 14 13)(font "Arial" (font_size 8))) + (text "c1" (rect 255 68 266 79)(font "Arial" (font_size 8))) + ) + (port + (pt 272 96) + (output) + (text "locked" (rect 0 0 37 13)(font "Arial" (font_size 8))) + (text "locked" (rect 232 84 263 95)(font "Arial" (font_size 8))) + ) + (drawing + (text "Cyclone 10 LP" (rect 186 147 430 303)(font "Arial" )) + (text "inclk0 frequency: 25.000 MHz" (rect 58 60 234 129)(font "Arial" )) + (text "Operation Mode: Normal" (rect 58 71 214 151)(font "Arial" )) + (text "Clk " (rect 59 89 131 187)(font "Arial" )) + (text "Ratio" (rect 80 89 180 187)(font "Arial" )) + (text "Ph (dg)" (rect 107 89 243 187)(font "Arial" )) + (text "DC (%)" (rect 143 89 315 187)(font "Arial" )) + (text "c0" (rect 62 101 133 211)(font "Arial" )) + (text "1/1" (rect 84 101 180 211)(font "Arial" )) + (text "0.00" (rect 113 101 243 211)(font "Arial" )) + (text "50.00" (rect 146 101 314 211)(font "Arial" )) + (text "c1" (rect 62 113 133 235)(font "Arial" )) + (text "5/1" (rect 84 113 180 235)(font "Arial" )) + (text "0.00" (rect 113 113 243 235)(font "Arial" )) + (text "50.00" (rect 146 113 314 235)(font "Arial" )) + (line (pt 0 0)(pt 273 0)) + (line (pt 273 0)(pt 273 161)) + (line (pt 0 161)(pt 273 161)) + (line (pt 0 0)(pt 0 161)) + (line (pt 56 87)(pt 176 87)) + (line (pt 56 98)(pt 176 98)) + (line (pt 56 110)(pt 176 110)) + (line (pt 56 122)(pt 176 122)) + (line (pt 56 87)(pt 56 122)) + (line (pt 77 87)(pt 77 122)(line_width 3)) + (line (pt 104 87)(pt 104 122)(line_width 3)) + (line (pt 140 87)(pt 140 122)(line_width 3)) + (line (pt 175 87)(pt 175 122)) + (line (pt 48 48)(pt 223 48)) + (line (pt 223 48)(pt 223 143)) + (line (pt 48 143)(pt 223 143)) + (line (pt 48 48)(pt 48 143)) + (line (pt 271 64)(pt 223 64)) + (line (pt 271 80)(pt 223 80)) + (line (pt 271 96)(pt 223 96)) + ) +) diff --git a/manufacturer/altera/cyclone10_lp/ip/pll/pll.ppf b/manufacturer/altera/cyclone10_lp/ip/pll/pll.ppf new file mode 100644 index 0000000..f563c40 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/pll/pll.ppf @@ -0,0 +1,12 @@ +<?xml version="1.0" encoding="UTF-8" ?> +<!DOCTYPE pinplan> +<pinplan intended_family="Cyclone 10 LP" variation_name="pll" megafunction_name="ALTPLL" specifies="all_ports"> +<global> +<pin name="areset" direction="input" scope="external" /> +<pin name="inclk0" direction="input" scope="external" source="clock" /> +<pin name="c0" direction="output" scope="external" source="clock" /> +<pin name="c1" direction="output" scope="external" source="clock" /> +<pin name="locked" direction="output" scope="external" /> + +</global> +</pinplan> diff --git a/manufacturer/altera/cyclone10_lp/ip/pll/pll.qip b/manufacturer/altera/cyclone10_lp/ip/pll/pll.qip new file mode 100644 index 0000000..5df3c41 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/pll/pll.qip @@ -0,0 +1,8 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "25.1" +set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone 10 LP}" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_inst.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_bb.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/manufacturer/altera/cyclone10_lp/ip/pll/pll.v b/manufacturer/altera/cyclone10_lp/ip/pll/pll.v new file mode 100644 index 0000000..cbe5878 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/pll/pll.v @@ -0,0 +1,348 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: pll.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 25.1std.0 Build 1129 10/21/2025 SC Standard Edition +// ************************************************************ + + +//Copyright (C) 2025 Altera Corporation. All rights reserved. +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and any partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, the Altera Quartus Prime License Agreement, +//the Altera IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Altera and sold by Altera or its authorized distributors. Please +//refer to the Altera Software License Subscription Agreements +//on the Quartus Prime software download page. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module pll ( + areset, + inclk0, + c0, + c1, + locked); + + input areset; + input inclk0; + output c0; + output c1; + output locked; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri0 areset; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [4:0] sub_wire0; + wire sub_wire3; + wire [0:0] sub_wire6 = 1'h0; + wire [1:1] sub_wire2 = sub_wire0[1:1]; + wire [0:0] sub_wire1 = sub_wire0[0:0]; + wire c0 = sub_wire1; + wire c1 = sub_wire2; + wire locked = sub_wire3; + wire sub_wire4 = inclk0; + wire [1:0] sub_wire5 = {sub_wire6, sub_wire4}; + + altpll altpll_component ( + .areset (areset), + .inclk (sub_wire5), + .clk (sub_wire0), + .locked (sub_wire3), + .activeclock (), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .fref (), + .icdrclk (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.bandwidth_type = "AUTO", + altpll_component.clk0_divide_by = 1, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 1, + altpll_component.clk0_phase_shift = "0", + altpll_component.clk1_divide_by = 1, + altpll_component.clk1_duty_cycle = 50, + altpll_component.clk1_multiply_by = 5, + altpll_component.clk1_phase_shift = "0", + altpll_component.compensate_clock = "CLK0", + altpll_component.inclk0_input_frequency = 40000, + altpll_component.intended_device_family = "Cyclone 10 LP", + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_USED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_USED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_USED", + altpll_component.port_clk2 = "PORT_UNUSED", + altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.self_reset_on_loss_lock = "OFF", + altpll_component.width_clock = 5; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "25.000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "125.000000" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "25.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "125.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLK1 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "5" +// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "40000" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v TRUE +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/manufacturer/altera/cyclone10_lp/ip/pll/pll_bb.v b/manufacturer/altera/cyclone10_lp/ip/pll/pll_bb.v new file mode 100644 index 0000000..0f86c48 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/pll/pll_bb.v @@ -0,0 +1,232 @@ +// megafunction wizard: %ALTPLL%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: pll.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 25.1std.0 Build 1129 10/21/2025 SC Standard Edition +// ************************************************************ + +//Copyright (C) 2025 Altera Corporation. All rights reserved. +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and any partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, the Altera Quartus Prime License Agreement, +//the Altera IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Altera and sold by Altera or its authorized distributors. Please +//refer to the Altera Software License Subscription Agreements +//on the Quartus Prime software download page. + +module pll ( + areset, + inclk0, + c0, + c1, + locked); + + input areset; + input inclk0; + output c0; + output c1; + output locked; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri0 areset; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "25.000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "125.000000" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "25.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "125.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLK1 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "5" +// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "40000" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v TRUE +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/manufacturer/altera/cyclone10_lp/ip/pll/pll_inst.v b/manufacturer/altera/cyclone10_lp/ip/pll/pll_inst.v new file mode 100644 index 0000000..6da79e5 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/pll/pll_inst.v @@ -0,0 +1,7 @@ +pll pll_inst ( + .areset ( areset_sig ), + .inclk0 ( inclk0_sig ), + .c0 ( c0_sig ), + .c1 ( c1_sig ), + .locked ( locked_sig ) + ); diff --git a/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.bsf b/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.bsf new file mode 100644 index 0000000..c5f6b16 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.bsf @@ -0,0 +1,65 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 2025 Altera Corporation. All rights reserved. +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, the Altera Quartus Prime License Agreement, +the Altera IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Altera and sold by Altera or its authorized distributors. Please +refer to the Altera Software License Subscription Agreements +on the Quartus Prime software download page. +*/ +(header "symbol" (version "1.2")) +(symbol + (rect 0 0 208 96) + (text "ddri" (rect 93 -2 122 16)(font "Dialog" (font_size 10))) + (text "inst" (rect 8 81 24 92)(font "Arial" )) + (port + (pt 0 48) + (input) + (text "datain[4..0]" (rect 0 0 69 15)(font "Dialog" (font_size 8))) + (text "datain[4..0]" (rect 4 33 61 47)(font "Dialog" (font_size 8))) + (line (pt 0 48)(pt 64 48)(line_width 3)) + ) + (port + (pt 0 64) + (input) + (text "inclock" (rect 0 0 42 15)(font "Dialog" (font_size 8))) + (text "inclock" (rect 4 49 39 63)(font "Dialog" (font_size 8))) + (line (pt 0 64)(pt 64 64)) + ) + (port + (pt 208 48) + (output) + (text "dataout_l[4..0]" (rect 0 0 87 15)(font "Dialog" (font_size 8))) + (text "dataout_l[4..0]" (rect 146 33 219 47)(font "Dialog" (font_size 8))) + (line (pt 208 48)(pt 128 48)(line_width 3)) + ) + (port + (pt 208 64) + (output) + (text "dataout_h[4..0]" (rect 0 0 92 15)(font "Dialog" (font_size 8))) + (text "dataout_h[4..0]" (rect 142 49 219 63)(font "Dialog" (font_size 8))) + (line (pt 208 64)(pt 128 64)(line_width 3)) + ) + (drawing + (line (pt 64 32)(pt 128 32)) + (line (pt 128 32)(pt 128 80)) + (line (pt 64 80)(pt 128 80)) + (line (pt 64 32)(pt 64 80)) + (line (pt 0 0)(pt 208 0)) + (line (pt 208 0)(pt 208 96)) + (line (pt 0 96)(pt 208 96)) + (line (pt 0 0)(pt 0 96)) + ) +) diff --git a/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.cmp b/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.cmp new file mode 100644 index 0000000..86f1250 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.cmp @@ -0,0 +1,25 @@ +--Copyright (C) 2025 Altera Corporation. All rights reserved. +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and any partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, the Altera Quartus Prime License Agreement, +--the Altera IP License Agreement, or other applicable license +--agreement, including, without limitation, that your use is for +--the sole purpose of programming logic devices manufactured by +--Altera and sold by Altera or its authorized distributors. Please +--refer to the Altera Software License Subscription Agreements +--on the Quartus Prime software download page. + + +component ddri + PORT + ( + datain : IN STD_LOGIC_VECTOR (4 DOWNTO 0); + inclock : IN STD_LOGIC ; + dataout_h : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + dataout_l : OUT STD_LOGIC_VECTOR (4 DOWNTO 0) + ); +end component; diff --git a/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.inc b/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.inc new file mode 100644 index 0000000..3418b17 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.inc @@ -0,0 +1,26 @@ +--Copyright (C) 2025 Altera Corporation. All rights reserved. +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and any partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, the Altera Quartus Prime License Agreement, +--the Altera IP License Agreement, or other applicable license +--agreement, including, without limitation, that your use is for +--the sole purpose of programming logic devices manufactured by +--Altera and sold by Altera or its authorized distributors. Please +--refer to the Altera Software License Subscription Agreements +--on the Quartus Prime software download page. + + +FUNCTION ddri +( + datain[4..0], + inclock +) + +RETURNS ( + dataout_h[4..0], + dataout_l[4..0] +); diff --git a/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.ppf b/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.ppf new file mode 100644 index 0000000..b1742aa --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.ppf @@ -0,0 +1,11 @@ +<?xml version="1.0" encoding="UTF-8" ?> +<!DOCTYPE pinplan> +<pinplan intended_family="Cyclone 10 LP" variation_name="ddri" megafunction_name="ALTDDIO_IN" specifies="all_ports"> +<global> +<pin name="datain[4..0]" direction="input" scope="external" /> +<pin name="inclock" direction="input" scope="external" source="clock" /> +<pin name="dataout_h[4..0]" direction="output" scope="external" /> +<pin name="dataout_l[4..0]" direction="output" scope="external" /> + +</global> +</pinplan> diff --git a/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.qip b/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.qip new file mode 100644 index 0000000..18f0cc0 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.qip @@ -0,0 +1,10 @@ +set_global_assignment -name IP_TOOL_NAME "ALTDDIO_IN" +set_global_assignment -name IP_TOOL_VERSION "25.1" +set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone 10 LP}" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ddri.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddri.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddri_inst.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddri_bb.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddri.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddri.cmp"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddri.ppf"] diff --git a/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.v b/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.v new file mode 100644 index 0000000..f2d0c47 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.v @@ -0,0 +1,103 @@ +// megafunction wizard: %ALTDDIO_IN% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: ALTDDIO_IN + +// ============================================================ +// File Name: ddri.v +// Megafunction Name(s): +// ALTDDIO_IN +// +// Simulation Library Files(s): +// +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 25.1std.0 Build 1129 10/21/2025 SC Standard Edition +// ************************************************************ + + +//Copyright (C) 2025 Altera Corporation. All rights reserved. +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and any partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, the Altera Quartus Prime License Agreement, +//the Altera IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Altera and sold by Altera or its authorized distributors. Please +//refer to the Altera Software License Subscription Agreements +//on the Quartus Prime software download page. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module ddri ( + datain, + inclock, + dataout_h, + dataout_l); + + input [4:0] datain; + input inclock; + output [4:0] dataout_h; + output [4:0] dataout_l; + + wire [4:0] sub_wire0; + wire [4:0] sub_wire1; + wire [4:0] dataout_h = sub_wire0[4:0]; + wire [4:0] dataout_l = sub_wire1[4:0]; + + altddio_in ALTDDIO_IN_component ( + .datain (datain), + .inclock (inclock), + .dataout_h (sub_wire0), + .dataout_l (sub_wire1), + .aclr (1'b0), + .aset (1'b0), + .inclocken (1'b1), + .sclr (1'b0), + .sset (1'b0)); + defparam + ALTDDIO_IN_component.intended_device_family = "Cyclone 10 LP", + ALTDDIO_IN_component.invert_input_clocks = "OFF", + ALTDDIO_IN_component.lpm_hint = "UNUSED", + ALTDDIO_IN_component.lpm_type = "altddio_in", + ALTDDIO_IN_component.power_up_high = "ON", + ALTDDIO_IN_component.width = 5; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP" +// Retrieval info: CONSTANT: INVERT_INPUT_CLOCKS STRING "OFF" +// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_in" +// Retrieval info: CONSTANT: POWER_UP_HIGH STRING "ON" +// Retrieval info: CONSTANT: WIDTH NUMERIC "5" +// Retrieval info: USED_PORT: datain 0 0 5 0 INPUT NODEFVAL "datain[4..0]" +// Retrieval info: CONNECT: @datain 0 0 5 0 datain 0 0 5 0 +// Retrieval info: USED_PORT: dataout_h 0 0 5 0 OUTPUT NODEFVAL "dataout_h[4..0]" +// Retrieval info: CONNECT: dataout_h 0 0 5 0 @dataout_h 0 0 5 0 +// Retrieval info: USED_PORT: dataout_l 0 0 5 0 OUTPUT NODEFVAL "dataout_l[4..0]" +// Retrieval info: CONNECT: dataout_l 0 0 5 0 @dataout_l 0 0 5 0 +// Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "inclock" +// Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL ddri.v TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddri.qip TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddri.bsf TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddri_inst.v TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddri_bb.v TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddri.inc TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddri.cmp TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddri.ppf TRUE FALSE diff --git a/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri_bb.v b/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri_bb.v new file mode 100644 index 0000000..ec7ac20 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri_bb.v @@ -0,0 +1,74 @@ +// megafunction wizard: %ALTDDIO_IN%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: ALTDDIO_IN + +// ============================================================ +// File Name: ddri.v +// Megafunction Name(s): +// ALTDDIO_IN +// +// Simulation Library Files(s): +// +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 25.1std.0 Build 1129 10/21/2025 SC Standard Edition +// ************************************************************ + +//Copyright (C) 2025 Altera Corporation. All rights reserved. +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and any partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, the Altera Quartus Prime License Agreement, +//the Altera IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Altera and sold by Altera or its authorized distributors. Please +//refer to the Altera Software License Subscription Agreements +//on the Quartus Prime software download page. + +module ddri ( + datain, + inclock, + dataout_h, + dataout_l); + + input [4:0] datain; + input inclock; + output [4:0] dataout_h; + output [4:0] dataout_l; + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP" +// Retrieval info: CONSTANT: INVERT_INPUT_CLOCKS STRING "OFF" +// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_in" +// Retrieval info: CONSTANT: POWER_UP_HIGH STRING "ON" +// Retrieval info: CONSTANT: WIDTH NUMERIC "5" +// Retrieval info: USED_PORT: datain 0 0 5 0 INPUT NODEFVAL "datain[4..0]" +// Retrieval info: CONNECT: @datain 0 0 5 0 datain 0 0 5 0 +// Retrieval info: USED_PORT: dataout_h 0 0 5 0 OUTPUT NODEFVAL "dataout_h[4..0]" +// Retrieval info: CONNECT: dataout_h 0 0 5 0 @dataout_h 0 0 5 0 +// Retrieval info: USED_PORT: dataout_l 0 0 5 0 OUTPUT NODEFVAL "dataout_l[4..0]" +// Retrieval info: CONNECT: dataout_l 0 0 5 0 @dataout_l 0 0 5 0 +// Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "inclock" +// Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL ddri.v TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddri.qip TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddri.bsf TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddri_inst.v TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddri_bb.v TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddri.inc TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddri.cmp TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddri.ppf TRUE FALSE diff --git a/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri_inst.v b/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri_inst.v new file mode 100644 index 0000000..0574ba9 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri_inst.v @@ -0,0 +1,6 @@ +ddri ddri_inst ( + .datain ( datain_sig ), + .inclock ( inclock_sig ), + .dataout_h ( dataout_h_sig ), + .dataout_l ( dataout_l_sig ) + ); diff --git a/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.bsf b/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.bsf new file mode 100644 index 0000000..1cf5c0d --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.bsf @@ -0,0 +1,79 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 2025 Altera Corporation. All rights reserved. +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, the Altera Quartus Prime License Agreement, +the Altera IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Altera and sold by Altera or its authorized distributors. Please +refer to the Altera Software License Subscription Agreements +on the Quartus Prime software download page. +*/ +(header "symbol" (version "1.2")) +(symbol + (rect 0 0 224 144) + (text "ddro" (rect 99 -2 133 16)(font "Dialog" (font_size 10))) + (text "inst" (rect 8 129 24 140)(font "Arial" )) + (port + (pt 0 48) + (input) + (text "datain_h[5..0]" (rect 0 0 82 15)(font "Dialog" (font_size 8))) + (text "datain_h[5..0]" (rect 4 33 73 47)(font "Dialog" (font_size 8))) + (line (pt 0 48)(pt 80 48)(line_width 3)) + ) + (port + (pt 0 64) + (input) + (text "datain_l[5..0]" (rect 0 0 79 15)(font "Dialog" (font_size 8))) + (text "datain_l[5..0]" (rect 4 49 69 63)(font "Dialog" (font_size 8))) + (line (pt 0 64)(pt 80 64)(line_width 3)) + ) + (port + (pt 0 80) + (input) + (text "oe" (rect 0 0 15 15)(font "Dialog" (font_size 8))) + (text "oe" (rect 4 65 16 79)(font "Dialog" (font_size 8))) + (line (pt 0 80)(pt 80 80)) + ) + (port + (pt 0 96) + (input) + (text "outclock" (rect 0 0 51 15)(font "Dialog" (font_size 8))) + (text "outclock" (rect 4 81 47 95)(font "Dialog" (font_size 8))) + (line (pt 0 96)(pt 80 96)) + ) + (port + (pt 0 112) + (input) + (text "aclr" (rect 0 0 22 15)(font "Dialog" (font_size 8))) + (text "aclr" (rect 4 97 23 111)(font "Dialog" (font_size 8))) + (line (pt 0 112)(pt 80 112)) + ) + (port + (pt 224 48) + (output) + (text "dataout[5..0]" (rect 0 0 79 15)(font "Dialog" (font_size 8))) + (text "dataout[5..0]" (rect 168 33 233 47)(font "Dialog" (font_size 8))) + (line (pt 224 48)(pt 144 48)(line_width 3)) + ) + (drawing + (line (pt 80 32)(pt 144 32)) + (line (pt 144 32)(pt 144 128)) + (line (pt 80 128)(pt 144 128)) + (line (pt 80 32)(pt 80 128)) + (line (pt 0 0)(pt 224 0)) + (line (pt 224 0)(pt 224 144)) + (line (pt 0 144)(pt 224 144)) + (line (pt 0 0)(pt 0 144)) + ) +) diff --git a/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.cmp b/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.cmp new file mode 100644 index 0000000..dbbc5a8 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.cmp @@ -0,0 +1,27 @@ +--Copyright (C) 2025 Altera Corporation. All rights reserved. +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and any partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, the Altera Quartus Prime License Agreement, +--the Altera IP License Agreement, or other applicable license +--agreement, including, without limitation, that your use is for +--the sole purpose of programming logic devices manufactured by +--Altera and sold by Altera or its authorized distributors. Please +--refer to the Altera Software License Subscription Agreements +--on the Quartus Prime software download page. + + +component ddro + PORT + ( + aclr : IN STD_LOGIC ; + datain_h : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + datain_l : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + oe : IN STD_LOGIC ; + outclock : IN STD_LOGIC ; + dataout : OUT STD_LOGIC_VECTOR (5 DOWNTO 0) + ); +end component; diff --git a/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.inc b/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.inc new file mode 100644 index 0000000..98c6145 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.inc @@ -0,0 +1,28 @@ +--Copyright (C) 2025 Altera Corporation. All rights reserved. +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and any partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, the Altera Quartus Prime License Agreement, +--the Altera IP License Agreement, or other applicable license +--agreement, including, without limitation, that your use is for +--the sole purpose of programming logic devices manufactured by +--Altera and sold by Altera or its authorized distributors. Please +--refer to the Altera Software License Subscription Agreements +--on the Quartus Prime software download page. + + +FUNCTION ddro +( + aclr, + datain_h[5..0], + datain_l[5..0], + oe, + outclock +) + +RETURNS ( + dataout[5..0] +); diff --git a/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.ppf b/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.ppf new file mode 100644 index 0000000..2d6a4da --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.ppf @@ -0,0 +1,13 @@ +<?xml version="1.0" encoding="UTF-8" ?> +<!DOCTYPE pinplan> +<pinplan intended_family="Cyclone 10 LP" variation_name="ddro" megafunction_name="ALTDDIO_OUT" specifies="all_ports"> +<global> +<pin name="aclr" direction="input" scope="external" /> +<pin name="datain_h[5..0]" direction="input" scope="external" /> +<pin name="datain_l[5..0]" direction="input" scope="external" /> +<pin name="oe" direction="input" scope="external" /> +<pin name="outclock" direction="input" scope="external" source="clock" /> +<pin name="dataout[5..0]" direction="output" scope="external" /> + +</global> +</pinplan> diff --git a/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.qip b/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.qip new file mode 100644 index 0000000..3eb030b --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.qip @@ -0,0 +1,10 @@ +set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT" +set_global_assignment -name IP_TOOL_VERSION "25.1" +set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone 10 LP}" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ddro.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddro.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddro_inst.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddro_bb.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddro.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddro.cmp"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddro.ppf"] diff --git a/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.v b/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.v new file mode 100644 index 0000000..87d2856 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.v @@ -0,0 +1,115 @@ +// megafunction wizard: %ALTDDIO_OUT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: ALTDDIO_OUT + +// ============================================================ +// File Name: ddro.v +// Megafunction Name(s): +// ALTDDIO_OUT +// +// Simulation Library Files(s): +// +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 25.1std.0 Build 1129 10/21/2025 SC Standard Edition +// ************************************************************ + + +//Copyright (C) 2025 Altera Corporation. All rights reserved. +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and any partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, the Altera Quartus Prime License Agreement, +//the Altera IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Altera and sold by Altera or its authorized distributors. Please +//refer to the Altera Software License Subscription Agreements +//on the Quartus Prime software download page. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module ddro ( + aclr, + datain_h, + datain_l, + oe, + outclock, + dataout); + + input aclr; + input [5:0] datain_h; + input [5:0] datain_l; + input oe; + input outclock; + output [5:0] dataout; + + wire [5:0] sub_wire0; + wire [5:0] dataout = sub_wire0[5:0]; + + altddio_out ALTDDIO_OUT_component ( + .aclr (aclr), + .datain_h (datain_h), + .datain_l (datain_l), + .oe (oe), + .outclock (outclock), + .dataout (sub_wire0), + .aset (1'b0), + .oe_out (), + .outclocken (1'b1), + .sclr (1'b0), + .sset (1'b0)); + defparam + ALTDDIO_OUT_component.extend_oe_disable = "OFF", + ALTDDIO_OUT_component.intended_device_family = "Cyclone 10 LP", + ALTDDIO_OUT_component.invert_output = "OFF", + ALTDDIO_OUT_component.lpm_hint = "UNUSED", + ALTDDIO_OUT_component.lpm_type = "altddio_out", + ALTDDIO_OUT_component.oe_reg = "UNREGISTERED", + ALTDDIO_OUT_component.power_up_high = "OFF", + ALTDDIO_OUT_component.width = 6; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP" +// Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "OFF" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP" +// Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF" +// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out" +// Retrieval info: CONSTANT: OE_REG STRING "UNREGISTERED" +// Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF" +// Retrieval info: CONSTANT: WIDTH NUMERIC "6" +// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr" +// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +// Retrieval info: USED_PORT: datain_h 0 0 6 0 INPUT NODEFVAL "datain_h[5..0]" +// Retrieval info: CONNECT: @datain_h 0 0 6 0 datain_h 0 0 6 0 +// Retrieval info: USED_PORT: datain_l 0 0 6 0 INPUT NODEFVAL "datain_l[5..0]" +// Retrieval info: CONNECT: @datain_l 0 0 6 0 datain_l 0 0 6 0 +// Retrieval info: USED_PORT: dataout 0 0 6 0 OUTPUT NODEFVAL "dataout[5..0]" +// Retrieval info: CONNECT: dataout 0 0 6 0 @dataout 0 0 6 0 +// Retrieval info: USED_PORT: oe 0 0 0 0 INPUT NODEFVAL "oe" +// Retrieval info: CONNECT: @oe 0 0 0 0 oe 0 0 0 0 +// Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "outclock" +// Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL ddro.v TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddro.qip TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddro.bsf TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddro_inst.v TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddro_bb.v TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddro.inc TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddro.cmp TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddro.ppf TRUE FALSE diff --git a/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro_bb.v b/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro_bb.v new file mode 100644 index 0000000..1529ff1 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro_bb.v @@ -0,0 +1,84 @@ +// megafunction wizard: %ALTDDIO_OUT%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: ALTDDIO_OUT + +// ============================================================ +// File Name: ddro.v +// Megafunction Name(s): +// ALTDDIO_OUT +// +// Simulation Library Files(s): +// +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 25.1std.0 Build 1129 10/21/2025 SC Standard Edition +// ************************************************************ + +//Copyright (C) 2025 Altera Corporation. All rights reserved. +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and any partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, the Altera Quartus Prime License Agreement, +//the Altera IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Altera and sold by Altera or its authorized distributors. Please +//refer to the Altera Software License Subscription Agreements +//on the Quartus Prime software download page. + +module ddro ( + aclr, + datain_h, + datain_l, + oe, + outclock, + dataout); + + input aclr; + input [5:0] datain_h; + input [5:0] datain_l; + input oe; + input outclock; + output [5:0] dataout; + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP" +// Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "OFF" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP" +// Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF" +// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out" +// Retrieval info: CONSTANT: OE_REG STRING "UNREGISTERED" +// Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF" +// Retrieval info: CONSTANT: WIDTH NUMERIC "6" +// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr" +// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +// Retrieval info: USED_PORT: datain_h 0 0 6 0 INPUT NODEFVAL "datain_h[5..0]" +// Retrieval info: CONNECT: @datain_h 0 0 6 0 datain_h 0 0 6 0 +// Retrieval info: USED_PORT: datain_l 0 0 6 0 INPUT NODEFVAL "datain_l[5..0]" +// Retrieval info: CONNECT: @datain_l 0 0 6 0 datain_l 0 0 6 0 +// Retrieval info: USED_PORT: dataout 0 0 6 0 OUTPUT NODEFVAL "dataout[5..0]" +// Retrieval info: CONNECT: dataout 0 0 6 0 @dataout 0 0 6 0 +// Retrieval info: USED_PORT: oe 0 0 0 0 INPUT NODEFVAL "oe" +// Retrieval info: CONNECT: @oe 0 0 0 0 oe 0 0 0 0 +// Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "outclock" +// Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL ddro.v TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddro.qip TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddro.bsf TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddro_inst.v TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddro_bb.v TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddro.inc TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddro.cmp TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddro.ppf TRUE FALSE diff --git a/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro_inst.v b/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro_inst.v new file mode 100644 index 0000000..32dfbbb --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro_inst.v @@ -0,0 +1,8 @@ +ddro ddro_inst ( + .aclr ( aclr_sig ), + .datain_h ( datain_h_sig ), + .datain_l ( datain_l_sig ), + .oe ( oe_sig ), + .outclock ( outclock_sig ), + .dataout ( dataout_sig ) + ); |
