blob: 86f1250415ceec1d8b9ff63bb8a816e55ba659eb (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
|
--Copyright (C) 2025 Altera Corporation. All rights reserved.
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and any partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, the Altera Quartus Prime License Agreement,
--the Altera IP License Agreement, or other applicable license
--agreement, including, without limitation, that your use is for
--the sole purpose of programming logic devices manufactured by
--Altera and sold by Altera or its authorized distributors. Please
--refer to the Altera Software License Subscription Agreements
--on the Quartus Prime software download page.
component ddri
PORT
(
datain : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
inclock : IN STD_LOGIC ;
dataout_h : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
dataout_l : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
end component;
|
