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Diffstat (limited to 'manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio.ppf')
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diff --git a/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio.ppf b/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio.ppf
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+++ b/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio.ppf
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+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone 10 LP" variation_name="ddrio" megafunction_name="ALTDDIO_BIDIR" specifies="all_ports">
+<global>
+<pin name="aclr" direction="input" scope="external" />
+<pin name="datain_h[7..0]" direction="input" scope="external" />
+<pin name="datain_l[7..0]" direction="input" scope="external" />
+<pin name="inclock" direction="input" scope="external" source="clock" />
+<pin name="inclocken" direction="input" scope="external" />
+<pin name="oe" direction="input" scope="external" />
+<pin name="outclock" direction="input" scope="external" source="clock" />
+<pin name="outclocken" direction="input" scope="external" />
+<pin name="dataout_h[7..0]" direction="output" scope="external" />
+<pin name="dataout_l[7..0]" direction="output" scope="external" />
+<pin name="padio[7..0]" direction="bidir" scope="external" />
+
+</global>
+</pinplan>

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