diff options
Diffstat (limited to 'manufacturer/altera/cyclone10_lp/ip/ddrio')
| -rw-r--r-- | manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio.bsf | 114 | ||||
| -rw-r--r-- | manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio.ppf | 18 | ||||
| -rw-r--r-- | manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio.qip | 8 | ||||
| -rw-r--r-- | manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio.v | 145 | ||||
| -rw-r--r-- | manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio_bb.v | 105 | ||||
| -rw-r--r-- | manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio_inst.v | 13 |
6 files changed, 403 insertions, 0 deletions
diff --git a/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio.bsf b/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio.bsf new file mode 100644 index 0000000..9eba5e3 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio.bsf @@ -0,0 +1,114 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 2025 Altera Corporation. All rights reserved. +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, the Altera Quartus Prime License Agreement, +the Altera IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Altera and sold by Altera or its authorized distributors. Please +refer to the Altera Software License Subscription Agreements +on the Quartus Prime software download page. +*/ +(header "symbol" (version "1.2")) +(symbol + (rect 0 0 224 192) + (text "ddrio" (rect 98 -2 136 16)(font "Dialog" (font_size 10))) + (text "inst" (rect 8 177 24 188)(font "Arial" )) + (port + (pt 0 48) + (input) + (text "datain_h[7..0]" (rect 0 0 82 15)(font "Dialog" (font_size 8))) + (text "datain_h[7..0]" (rect 4 33 73 47)(font "Dialog" (font_size 8))) + (line (pt 0 48)(pt 80 48)(line_width 3)) + ) + (port + (pt 0 64) + (input) + (text "datain_l[7..0]" (rect 0 0 79 15)(font "Dialog" (font_size 8))) + (text "datain_l[7..0]" (rect 4 49 69 63)(font "Dialog" (font_size 8))) + (line (pt 0 64)(pt 80 64)(line_width 3)) + ) + (port + (pt 0 80) + (input) + (text "oe" (rect 0 0 15 15)(font "Dialog" (font_size 8))) + (text "oe" (rect 4 65 16 79)(font "Dialog" (font_size 8))) + (line (pt 0 80)(pt 80 80)) + ) + (port + (pt 0 96) + (input) + (text "inclock" (rect 0 0 42 15)(font "Dialog" (font_size 8))) + (text "inclock" (rect 4 81 39 95)(font "Dialog" (font_size 8))) + (line (pt 0 96)(pt 80 96)) + ) + (port + (pt 0 112) + (input) + (text "inclocken" (rect 0 0 57 15)(font "Dialog" (font_size 8))) + (text "inclocken" (rect 4 97 51 111)(font "Dialog" (font_size 8))) + (line (pt 0 112)(pt 80 112)) + ) + (port + (pt 0 128) + (input) + (text "outclock" (rect 0 0 51 15)(font "Dialog" (font_size 8))) + (text "outclock" (rect 4 113 47 127)(font "Dialog" (font_size 8))) + (line (pt 0 128)(pt 80 128)) + ) + (port + (pt 0 144) + (input) + (text "outclocken" (rect 0 0 67 15)(font "Dialog" (font_size 8))) + (text "outclocken" (rect 4 129 59 143)(font "Dialog" (font_size 8))) + (line (pt 0 144)(pt 80 144)) + ) + (port + (pt 0 160) + (input) + (text "aclr" (rect 0 0 22 15)(font "Dialog" (font_size 8))) + (text "aclr" (rect 4 145 23 159)(font "Dialog" (font_size 8))) + (line (pt 0 160)(pt 80 160)) + ) + (port + (pt 224 48) + (output) + (text "dataout_h[7..0]" (rect 0 0 92 15)(font "Dialog" (font_size 8))) + (text "dataout_h[7..0]" (rect 158 33 235 47)(font "Dialog" (font_size 8))) + (line (pt 224 48)(pt 144 48)(line_width 3)) + ) + (port + (pt 224 64) + (output) + (text "dataout_l[7..0]" (rect 0 0 87 15)(font "Dialog" (font_size 8))) + (text "dataout_l[7..0]" (rect 162 49 235 63)(font "Dialog" (font_size 8))) + (line (pt 224 64)(pt 144 64)(line_width 3)) + ) + (port + (pt 224 80) + (output) + (text "padio[7..0]" (rect 0 0 64 15)(font "Dialog" (font_size 8))) + (text "padio[7..0]" (rect 177 65 231 79)(font "Dialog" (font_size 8))) + (line (pt 224 80)(pt 144 80)(line_width 3)) + ) + (drawing + (line (pt 80 32)(pt 144 32)) + (line (pt 144 32)(pt 144 176)) + (line (pt 80 176)(pt 144 176)) + (line (pt 80 32)(pt 80 176)) + (line (pt 0 0)(pt 224 0)) + (line (pt 224 0)(pt 224 192)) + (line (pt 0 192)(pt 224 192)) + (line (pt 0 0)(pt 0 192)) + ) +) diff --git a/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio.ppf b/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio.ppf new file mode 100644 index 0000000..03c4cef --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio.ppf @@ -0,0 +1,18 @@ +<?xml version="1.0" encoding="UTF-8" ?> +<!DOCTYPE pinplan> +<pinplan intended_family="Cyclone 10 LP" variation_name="ddrio" megafunction_name="ALTDDIO_BIDIR" specifies="all_ports"> +<global> +<pin name="aclr" direction="input" scope="external" /> +<pin name="datain_h[7..0]" direction="input" scope="external" /> +<pin name="datain_l[7..0]" direction="input" scope="external" /> +<pin name="inclock" direction="input" scope="external" source="clock" /> +<pin name="inclocken" direction="input" scope="external" /> +<pin name="oe" direction="input" scope="external" /> +<pin name="outclock" direction="input" scope="external" source="clock" /> +<pin name="outclocken" direction="input" scope="external" /> +<pin name="dataout_h[7..0]" direction="output" scope="external" /> +<pin name="dataout_l[7..0]" direction="output" scope="external" /> +<pin name="padio[7..0]" direction="bidir" scope="external" /> + +</global> +</pinplan> diff --git a/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio.qip b/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio.qip new file mode 100644 index 0000000..b3dfeb4 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio.qip @@ -0,0 +1,8 @@ +set_global_assignment -name IP_TOOL_NAME "ALTDDIO_BIDIR" +set_global_assignment -name IP_TOOL_VERSION "25.1" +set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone 10 LP}" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ddrio.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddrio.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddrio_inst.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddrio_bb.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddrio.ppf"] diff --git a/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio.v b/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio.v new file mode 100644 index 0000000..44b81db --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio.v @@ -0,0 +1,145 @@ +// megafunction wizard: %ALTDDIO_BIDIR% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: ALTDDIO_BIDIR + +// ============================================================ +// File Name: ddrio.v +// Megafunction Name(s): +// ALTDDIO_BIDIR +// +// Simulation Library Files(s): +// +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 25.1std.0 Build 1129 10/21/2025 SC Standard Edition +// ************************************************************ + + +//Copyright (C) 2025 Altera Corporation. All rights reserved. +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and any partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, the Altera Quartus Prime License Agreement, +//the Altera IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Altera and sold by Altera or its authorized distributors. Please +//refer to the Altera Software License Subscription Agreements +//on the Quartus Prime software download page. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module ddrio ( + aclr, + datain_h, + datain_l, + inclock, + inclocken, + oe, + outclock, + outclocken, + dataout_h, + dataout_l, + padio); + + input aclr; + input [7:0] datain_h; + input [7:0] datain_l; + input inclock; + input inclocken; + input oe; + input outclock; + input outclocken; + output [7:0] dataout_h; + output [7:0] dataout_l; + inout [7:0] padio; + + wire [7:0] sub_wire0; + wire [7:0] sub_wire1; + wire [7:0] dataout_h = sub_wire0[7:0]; + wire [7:0] dataout_l = sub_wire1[7:0]; + + altddio_bidir ALTDDIO_BIDIR_component ( + .padio (padio), + .aclr (aclr), + .datain_h (datain_h), + .datain_l (datain_l), + .inclock (inclock), + .inclocken (inclocken), + .oe (oe), + .outclock (outclock), + .outclocken (outclocken), + .dataout_h (sub_wire0), + .dataout_l (sub_wire1), + .aset (1'b0), + .combout (), + .dqsundelayedout (), + .oe_out (), + .sclr (1'b0), + .sset (1'b0)); + defparam + ALTDDIO_BIDIR_component.extend_oe_disable = "ON", + ALTDDIO_BIDIR_component.implement_input_in_lcell = "ON", + ALTDDIO_BIDIR_component.intended_device_family = "Cyclone 10 LP", + ALTDDIO_BIDIR_component.invert_output = "OFF", + ALTDDIO_BIDIR_component.lpm_hint = "UNUSED", + ALTDDIO_BIDIR_component.lpm_type = "altddio_bidir", + ALTDDIO_BIDIR_component.oe_reg = "REGISTERED", + ALTDDIO_BIDIR_component.power_up_high = "OFF", + ALTDDIO_BIDIR_component.width = 8; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP" +// Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "ON" +// Retrieval info: CONSTANT: IMPLEMENT_INPUT_IN_LCELL STRING "ON" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP" +// Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF" +// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_bidir" +// Retrieval info: CONSTANT: OE_REG STRING "REGISTERED" +// Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF" +// Retrieval info: CONSTANT: WIDTH NUMERIC "8" +// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr" +// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +// Retrieval info: USED_PORT: datain_h 0 0 8 0 INPUT NODEFVAL "datain_h[7..0]" +// Retrieval info: CONNECT: @datain_h 0 0 8 0 datain_h 0 0 8 0 +// Retrieval info: USED_PORT: datain_l 0 0 8 0 INPUT NODEFVAL "datain_l[7..0]" +// Retrieval info: CONNECT: @datain_l 0 0 8 0 datain_l 0 0 8 0 +// Retrieval info: USED_PORT: dataout_h 0 0 8 0 OUTPUT NODEFVAL "dataout_h[7..0]" +// Retrieval info: CONNECT: dataout_h 0 0 8 0 @dataout_h 0 0 8 0 +// Retrieval info: USED_PORT: dataout_l 0 0 8 0 OUTPUT NODEFVAL "dataout_l[7..0]" +// Retrieval info: CONNECT: dataout_l 0 0 8 0 @dataout_l 0 0 8 0 +// Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "inclock" +// Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0 +// Retrieval info: USED_PORT: inclocken 0 0 0 0 INPUT NODEFVAL "inclocken" +// Retrieval info: CONNECT: @inclocken 0 0 0 0 inclocken 0 0 0 0 +// Retrieval info: USED_PORT: oe 0 0 0 0 INPUT NODEFVAL "oe" +// Retrieval info: CONNECT: @oe 0 0 0 0 oe 0 0 0 0 +// Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "outclock" +// Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0 +// Retrieval info: USED_PORT: outclocken 0 0 0 0 INPUT NODEFVAL "outclocken" +// Retrieval info: CONNECT: @outclocken 0 0 0 0 outclocken 0 0 0 0 +// Retrieval info: USED_PORT: padio 0 0 8 0 BIDIR NODEFVAL "padio[7..0]" +// Retrieval info: CONNECT: padio 0 0 8 0 @padio 0 0 8 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio.v TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio.qip TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio.bsf TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio_inst.v TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio_bb.v TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio.inc FALSE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio.cmp FALSE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio.ppf TRUE FALSE diff --git a/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio_bb.v b/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio_bb.v new file mode 100644 index 0000000..f489c24 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio_bb.v @@ -0,0 +1,105 @@ +// megafunction wizard: %ALTDDIO_BIDIR%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: ALTDDIO_BIDIR + +// ============================================================ +// File Name: ddrio.v +// Megafunction Name(s): +// ALTDDIO_BIDIR +// +// Simulation Library Files(s): +// +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 25.1std.0 Build 1129 10/21/2025 SC Standard Edition +// ************************************************************ + +//Copyright (C) 2025 Altera Corporation. All rights reserved. +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and any partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, the Altera Quartus Prime License Agreement, +//the Altera IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Altera and sold by Altera or its authorized distributors. Please +//refer to the Altera Software License Subscription Agreements +//on the Quartus Prime software download page. + +module ddrio ( + aclr, + datain_h, + datain_l, + inclock, + inclocken, + oe, + outclock, + outclocken, + dataout_h, + dataout_l, + padio); + + input aclr; + input [7:0] datain_h; + input [7:0] datain_l; + input inclock; + input inclocken; + input oe; + input outclock; + input outclocken; + output [7:0] dataout_h; + output [7:0] dataout_l; + inout [7:0] padio; + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP" +// Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "ON" +// Retrieval info: CONSTANT: IMPLEMENT_INPUT_IN_LCELL STRING "ON" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP" +// Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF" +// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_bidir" +// Retrieval info: CONSTANT: OE_REG STRING "REGISTERED" +// Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF" +// Retrieval info: CONSTANT: WIDTH NUMERIC "8" +// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr" +// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +// Retrieval info: USED_PORT: datain_h 0 0 8 0 INPUT NODEFVAL "datain_h[7..0]" +// Retrieval info: CONNECT: @datain_h 0 0 8 0 datain_h 0 0 8 0 +// Retrieval info: USED_PORT: datain_l 0 0 8 0 INPUT NODEFVAL "datain_l[7..0]" +// Retrieval info: CONNECT: @datain_l 0 0 8 0 datain_l 0 0 8 0 +// Retrieval info: USED_PORT: dataout_h 0 0 8 0 OUTPUT NODEFVAL "dataout_h[7..0]" +// Retrieval info: CONNECT: dataout_h 0 0 8 0 @dataout_h 0 0 8 0 +// Retrieval info: USED_PORT: dataout_l 0 0 8 0 OUTPUT NODEFVAL "dataout_l[7..0]" +// Retrieval info: CONNECT: dataout_l 0 0 8 0 @dataout_l 0 0 8 0 +// Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "inclock" +// Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0 +// Retrieval info: USED_PORT: inclocken 0 0 0 0 INPUT NODEFVAL "inclocken" +// Retrieval info: CONNECT: @inclocken 0 0 0 0 inclocken 0 0 0 0 +// Retrieval info: USED_PORT: oe 0 0 0 0 INPUT NODEFVAL "oe" +// Retrieval info: CONNECT: @oe 0 0 0 0 oe 0 0 0 0 +// Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "outclock" +// Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0 +// Retrieval info: USED_PORT: outclocken 0 0 0 0 INPUT NODEFVAL "outclocken" +// Retrieval info: CONNECT: @outclocken 0 0 0 0 outclocken 0 0 0 0 +// Retrieval info: USED_PORT: padio 0 0 8 0 BIDIR NODEFVAL "padio[7..0]" +// Retrieval info: CONNECT: padio 0 0 8 0 @padio 0 0 8 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio.v TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio.qip TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio.bsf TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio_inst.v TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio_bb.v TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio.inc FALSE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio.cmp FALSE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddrio.ppf TRUE FALSE diff --git a/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio_inst.v b/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio_inst.v new file mode 100644 index 0000000..a999d47 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio_inst.v @@ -0,0 +1,13 @@ +ddrio ddrio_inst ( + .aclr ( aclr_sig ), + .datain_h ( datain_h_sig ), + .datain_l ( datain_l_sig ), + .inclock ( inclock_sig ), + .inclocken ( inclocken_sig ), + .oe ( oe_sig ), + .outclock ( outclock_sig ), + .outclocken ( outclocken_sig ), + .dataout_h ( dataout_h_sig ), + .dataout_l ( dataout_l_sig ), + .padio ( padio_sig ) + ); |
