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create_clock -name clk -period 40.0 [get_ports clk_i];
create_clock -name phy0_rx_clk_v -period 8.0; # virtual clock for input constraint timing
create_clock -name phy0_rx_clk -period 8.0 -waveform { 2 6 } [get_ports phy0_rx_clk];
create_clock -name phy1_rx_clk_v -period 8.0; # virtual clock for input constraint timing
create_clock -name phy1_rx_clk -period 8.0 -waveform { 2 6 } [get_ports phy1_rx_clk];
create_clock -name phy2_rx_clk_v -period 8.0; # virtual clock for input constraint timi
create_clock -name phy2_rx_clk -period 8.0 -waveform { 2 6 } [get_ports phy2_rx_clk];
create_clock -name phy0_tx_clk -period 8.0 [get_ports phy0_tx_clk];
create_clock -name phy0_tx_clk_v -period 8.0; # virtual clock for input constraint timing
create_clock -name phy1_tx_clk -period 8.0 [get_ports phy1_tx_clk];
create_clock -name phy1_tx_clk_v -period 8.0; # virtual clock for input constraint timing
create_clock -name phy2_tx_clk -period 8.0 [get_ports phy2_tx_clk];
create_clock -name phy2_tx_clk_v -period 8.0; # virtual clock for input constraint timing
create_clock -name phy0_clk -period 8.0 [get_ports phy0_clk];
derive_pll_clocks -create_base_clocks -use_net_name
create_clock -name flash_dqs -period 10.0 [get_ports flash_dqs];
# PHY0 Input Clock
set_input_delay -min -0.8 -clock { phy0_rx_clk_v } [get_ports {phy0_rx_d[0] phy0_rx_d[1] phy0_rx_d[2] phy0_rx_d[3] phy0_rx_ctl}] -add_delay
set_input_delay -min -0.8 -clock { phy0_rx_clk_v } -clock_fall [get_ports {phy0_rx_d[0] phy0_rx_d[1] phy0_rx_d[2] phy0_rx_d[3] phy0_rx_ctl}] -add_delay
set_input_delay -max 0.8 -clock { phy0_rx_clk_v } [get_ports {phy0_rx_d[0] phy0_rx_d[1] phy0_rx_d[2] phy0_rx_d[3] phy0_rx_ctl}] -add_delay
set_input_delay -max 0.8 -clock { phy0_rx_clk_v } -clock_fall [get_ports {phy0_rx_d[0] phy0_rx_d[1] phy0_rx_d[2] phy0_rx_d[3] phy0_rx_ctl}] -add_delay
# PHY1 Input Clock
set_input_delay -min -0.8 -clock { phy1_rx_clk_v } [get_ports {phy1_rx_d[0] phy1_rx_d[1] phy1_rx_d[2] phy1_rx_d[3] phy1_rx_ctl}] -add_delay
set_input_delay -min -0.8 -clock { phy1_rx_clk_v } -clock_fall [get_ports {phy1_rx_d[0] phy1_rx_d[1] phy1_rx_d[2] phy1_rx_d[3] phy1_rx_ctl}] -add_delay;
set_input_delay -max 0.8 -clock { phy1_rx_clk_v } [get_ports {phy1_rx_d[0] phy1_rx_d[1] phy1_rx_d[2] phy1_rx_d[3] phy1_rx_ctl}] -add_delay
set_input_delay -max 0.8 -clock { phy1_rx_clk_v } -clock_fall [get_ports {phy1_rx_d[0] phy1_rx_d[1] phy1_rx_d[2] phy1_rx_d[3] phy1_rx_ctl}] -add_delay;
# phy2 Input Clock
set_input_delay -min -0.8 -clock { phy2_rx_clk_v } [get_ports {phy2_rx_d[0] phy2_rx_d[1] phy2_rx_d[2] phy2_rx_d[3] phy2_rx_ctl}] -add_delay
set_input_delay -min -0.8 -clock { phy2_rx_clk_v } -clock_fall [get_ports {phy2_rx_d[0] phy2_rx_d[1] phy2_rx_d[2] phy2_rx_d[3] phy2_rx_ctl}] -add_delay;
set_input_delay -max 0.8 -clock { phy2_rx_clk_v } [get_ports {phy2_rx_d[0] phy2_rx_d[1] phy2_rx_d[2] phy2_rx_d[3] phy2_rx_ctl}] -add_delay
set_input_delay -max 0.8 -clock { phy2_rx_clk_v } -clock_fall [get_ports {phy2_rx_d[0] phy2_rx_d[1] phy2_rx_d[2] phy2_rx_d[3] phy2_rx_ctl}] -add_delay;
# Set false paths to remove irrelevant setup and hold analysis
set_false_path -fall_from [get_clocks phy0_rx_clk_v] -rise_to [get_clocks {phy0_rx_clk}] -setup
set_false_path -rise_from [get_clocks phy0_rx_clk_v] -fall_to [get_clocks {phy0_rx_clk}] -setup
set_false_path -fall_from [get_clocks phy0_rx_clk_v] -fall_to [get_clocks {phy0_rx_clk}] -hold
set_false_path -rise_from [get_clocks phy0_rx_clk_v] -rise_to [get_clocks {phy0_rx_clk}] -hold
set_false_path -fall_from [get_clocks phy1_rx_clk_v] -rise_to [get_clocks {phy1_rx_clk}] -setup
set_false_path -rise_from [get_clocks phy1_rx_clk_v] -fall_to [get_clocks {phy1_rx_clk}] -setup
set_false_path -fall_from [get_clocks phy1_rx_clk_v] -fall_to [get_clocks {phy1_rx_clk}] -hold
set_false_path -rise_from [get_clocks phy1_rx_clk_v] -rise_to [get_clocks {phy1_rx_clk}] -hold
set_false_path -fall_from [get_clocks phy2_rx_clk_v] -rise_to [get_clocks {phy2_rx_clk}] -setup
set_false_path -rise_from [get_clocks phy2_rx_clk_v] -fall_to [get_clocks {phy2_rx_clk}] -setup
set_false_path -fall_from [get_clocks phy2_rx_clk_v] -fall_to [get_clocks {phy2_rx_clk}] -hold
set_false_path -rise_from [get_clocks phy2_rx_clk_v] -rise_to [get_clocks {phy2_rx_clk}] -hold
set_output_delay -max 0.5 -clock { phy0_tx_clk } [get_ports {phy0_tx_d[0] phy0_tx_d[1] phy0_tx_d[2] phy0_tx_d[3] phy0_tx_ctl}] -add_delay
set_output_delay -max 0.5 -clock { phy0_tx_clk } -clock_fall [get_ports {phy0_tx_d[0] phy0_tx_d[1] phy0_tx_d[2] phy0_tx_d[3] phy0_tx_ctl}] -add_delay
set_output_delay -min -0.5 -clock { phy0_tx_clk } [get_ports {phy0_tx_d[0] phy0_tx_d[1] phy0_tx_d[2] phy0_tx_d[3] phy0_tx_ctl}] -add_delay
set_output_delay -min -0.5 -clock { phy0_tx_clk } -clock_fall [get_ports {phy0_tx_d[0] phy0_tx_d[1] phy0_tx_d[2] phy0_tx_d[3] phy0_tx_ctl}] -add_delay
set_output_delay -max 0.5 -clock { phy1_tx_clk } [get_ports {phy1_tx_d[0] phy1_tx_d[1] phy1_tx_d[2] phy1_tx_d[3] phy1_tx_ctl}]
set_output_delay -max 0.5 -clock { phy1_tx_clk } -clock_fall [get_ports {phy1_tx_d[0] phy1_tx_d[1] phy1_tx_d[2] phy1_tx_d[3] phy1_tx_ctl}] -add_delay
set_output_delay -min -0.5 -clock { phy1_tx_clk } [get_ports {phy1_tx_d[0] phy1_tx_d[1] phy1_tx_d[2] phy1_tx_d[3] phy1_tx_ctl}] -add_delay
set_output_delay -min -0.5 -clock { phy1_tx_clk } -clock_fall [get_ports {phy1_tx_d[0] phy1_tx_d[1] phy1_tx_d[2] phy1_tx_d[3] phy1_tx_ctl}] -add_delay
set_output_delay -max 0.5 -clock { phy2_tx_clk } [get_ports {phy2_tx_d[0] phy2_tx_d[2] phy2_tx_d[2] phy2_tx_d[3] phy2_tx_ctl}]
set_output_delay -max 0.5 -clock { phy2_tx_clk } -clock_fall [get_ports {phy2_tx_d[0] phy2_tx_d[2] phy2_tx_d[2] phy2_tx_d[3] phy2_tx_ctl}] -add_delay
set_output_delay -min -0.5 -clock { phy2_tx_clk } [get_ports {phy2_tx_d[0] phy2_tx_d[2] phy2_tx_d[2] phy2_tx_d[3] phy2_tx_ctl}] -add_delay
set_output_delay -min -0.5 -clock { phy2_tx_clk } -clock_fall [get_ports {phy2_tx_d[0] phy2_tx_d[2] phy2_tx_d[2] phy2_tx_d[3] phy2_tx_ctl}] -add_delay
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