diff options
Diffstat (limited to 'manufacturer/altera/cyclone10_lp/ip/rgmii_rxd')
8 files changed, 320 insertions, 0 deletions
diff --git a/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.bsf b/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.bsf new file mode 100644 index 0000000..c5f6b16 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.bsf @@ -0,0 +1,65 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 2025 Altera Corporation. All rights reserved. +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, the Altera Quartus Prime License Agreement, +the Altera IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Altera and sold by Altera or its authorized distributors. Please +refer to the Altera Software License Subscription Agreements +on the Quartus Prime software download page. +*/ +(header "symbol" (version "1.2")) +(symbol + (rect 0 0 208 96) + (text "ddri" (rect 93 -2 122 16)(font "Dialog" (font_size 10))) + (text "inst" (rect 8 81 24 92)(font "Arial" )) + (port + (pt 0 48) + (input) + (text "datain[4..0]" (rect 0 0 69 15)(font "Dialog" (font_size 8))) + (text "datain[4..0]" (rect 4 33 61 47)(font "Dialog" (font_size 8))) + (line (pt 0 48)(pt 64 48)(line_width 3)) + ) + (port + (pt 0 64) + (input) + (text "inclock" (rect 0 0 42 15)(font "Dialog" (font_size 8))) + (text "inclock" (rect 4 49 39 63)(font "Dialog" (font_size 8))) + (line (pt 0 64)(pt 64 64)) + ) + (port + (pt 208 48) + (output) + (text "dataout_l[4..0]" (rect 0 0 87 15)(font "Dialog" (font_size 8))) + (text "dataout_l[4..0]" (rect 146 33 219 47)(font "Dialog" (font_size 8))) + (line (pt 208 48)(pt 128 48)(line_width 3)) + ) + (port + (pt 208 64) + (output) + (text "dataout_h[4..0]" (rect 0 0 92 15)(font "Dialog" (font_size 8))) + (text "dataout_h[4..0]" (rect 142 49 219 63)(font "Dialog" (font_size 8))) + (line (pt 208 64)(pt 128 64)(line_width 3)) + ) + (drawing + (line (pt 64 32)(pt 128 32)) + (line (pt 128 32)(pt 128 80)) + (line (pt 64 80)(pt 128 80)) + (line (pt 64 32)(pt 64 80)) + (line (pt 0 0)(pt 208 0)) + (line (pt 208 0)(pt 208 96)) + (line (pt 0 96)(pt 208 96)) + (line (pt 0 0)(pt 0 96)) + ) +) diff --git a/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.cmp b/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.cmp new file mode 100644 index 0000000..86f1250 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.cmp @@ -0,0 +1,25 @@ +--Copyright (C) 2025 Altera Corporation. All rights reserved. +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and any partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, the Altera Quartus Prime License Agreement, +--the Altera IP License Agreement, or other applicable license +--agreement, including, without limitation, that your use is for +--the sole purpose of programming logic devices manufactured by +--Altera and sold by Altera or its authorized distributors. Please +--refer to the Altera Software License Subscription Agreements +--on the Quartus Prime software download page. + + +component ddri + PORT + ( + datain : IN STD_LOGIC_VECTOR (4 DOWNTO 0); + inclock : IN STD_LOGIC ; + dataout_h : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + dataout_l : OUT STD_LOGIC_VECTOR (4 DOWNTO 0) + ); +end component; diff --git a/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.inc b/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.inc new file mode 100644 index 0000000..3418b17 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.inc @@ -0,0 +1,26 @@ +--Copyright (C) 2025 Altera Corporation. All rights reserved. +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and any partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, the Altera Quartus Prime License Agreement, +--the Altera IP License Agreement, or other applicable license +--agreement, including, without limitation, that your use is for +--the sole purpose of programming logic devices manufactured by +--Altera and sold by Altera or its authorized distributors. Please +--refer to the Altera Software License Subscription Agreements +--on the Quartus Prime software download page. + + +FUNCTION ddri +( + datain[4..0], + inclock +) + +RETURNS ( + dataout_h[4..0], + dataout_l[4..0] +); diff --git a/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.ppf b/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.ppf new file mode 100644 index 0000000..b1742aa --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.ppf @@ -0,0 +1,11 @@ +<?xml version="1.0" encoding="UTF-8" ?> +<!DOCTYPE pinplan> +<pinplan intended_family="Cyclone 10 LP" variation_name="ddri" megafunction_name="ALTDDIO_IN" specifies="all_ports"> +<global> +<pin name="datain[4..0]" direction="input" scope="external" /> +<pin name="inclock" direction="input" scope="external" source="clock" /> +<pin name="dataout_h[4..0]" direction="output" scope="external" /> +<pin name="dataout_l[4..0]" direction="output" scope="external" /> + +</global> +</pinplan> diff --git a/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.qip b/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.qip new file mode 100644 index 0000000..18f0cc0 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.qip @@ -0,0 +1,10 @@ +set_global_assignment -name IP_TOOL_NAME "ALTDDIO_IN" +set_global_assignment -name IP_TOOL_VERSION "25.1" +set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone 10 LP}" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ddri.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddri.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddri_inst.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddri_bb.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddri.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddri.cmp"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddri.ppf"] diff --git a/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.v b/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.v new file mode 100644 index 0000000..f2d0c47 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.v @@ -0,0 +1,103 @@ +// megafunction wizard: %ALTDDIO_IN% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: ALTDDIO_IN + +// ============================================================ +// File Name: ddri.v +// Megafunction Name(s): +// ALTDDIO_IN +// +// Simulation Library Files(s): +// +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 25.1std.0 Build 1129 10/21/2025 SC Standard Edition +// ************************************************************ + + +//Copyright (C) 2025 Altera Corporation. All rights reserved. +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and any partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, the Altera Quartus Prime License Agreement, +//the Altera IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Altera and sold by Altera or its authorized distributors. Please +//refer to the Altera Software License Subscription Agreements +//on the Quartus Prime software download page. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module ddri ( + datain, + inclock, + dataout_h, + dataout_l); + + input [4:0] datain; + input inclock; + output [4:0] dataout_h; + output [4:0] dataout_l; + + wire [4:0] sub_wire0; + wire [4:0] sub_wire1; + wire [4:0] dataout_h = sub_wire0[4:0]; + wire [4:0] dataout_l = sub_wire1[4:0]; + + altddio_in ALTDDIO_IN_component ( + .datain (datain), + .inclock (inclock), + .dataout_h (sub_wire0), + .dataout_l (sub_wire1), + .aclr (1'b0), + .aset (1'b0), + .inclocken (1'b1), + .sclr (1'b0), + .sset (1'b0)); + defparam + ALTDDIO_IN_component.intended_device_family = "Cyclone 10 LP", + ALTDDIO_IN_component.invert_input_clocks = "OFF", + ALTDDIO_IN_component.lpm_hint = "UNUSED", + ALTDDIO_IN_component.lpm_type = "altddio_in", + ALTDDIO_IN_component.power_up_high = "ON", + ALTDDIO_IN_component.width = 5; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP" +// Retrieval info: CONSTANT: INVERT_INPUT_CLOCKS STRING "OFF" +// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_in" +// Retrieval info: CONSTANT: POWER_UP_HIGH STRING "ON" +// Retrieval info: CONSTANT: WIDTH NUMERIC "5" +// Retrieval info: USED_PORT: datain 0 0 5 0 INPUT NODEFVAL "datain[4..0]" +// Retrieval info: CONNECT: @datain 0 0 5 0 datain 0 0 5 0 +// Retrieval info: USED_PORT: dataout_h 0 0 5 0 OUTPUT NODEFVAL "dataout_h[4..0]" +// Retrieval info: CONNECT: dataout_h 0 0 5 0 @dataout_h 0 0 5 0 +// Retrieval info: USED_PORT: dataout_l 0 0 5 0 OUTPUT NODEFVAL "dataout_l[4..0]" +// Retrieval info: CONNECT: dataout_l 0 0 5 0 @dataout_l 0 0 5 0 +// Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "inclock" +// Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL ddri.v TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddri.qip TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddri.bsf TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddri_inst.v TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddri_bb.v TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddri.inc TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddri.cmp TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddri.ppf TRUE FALSE diff --git a/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri_bb.v b/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri_bb.v new file mode 100644 index 0000000..ec7ac20 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri_bb.v @@ -0,0 +1,74 @@ +// megafunction wizard: %ALTDDIO_IN%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: ALTDDIO_IN + +// ============================================================ +// File Name: ddri.v +// Megafunction Name(s): +// ALTDDIO_IN +// +// Simulation Library Files(s): +// +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 25.1std.0 Build 1129 10/21/2025 SC Standard Edition +// ************************************************************ + +//Copyright (C) 2025 Altera Corporation. All rights reserved. +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and any partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, the Altera Quartus Prime License Agreement, +//the Altera IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Altera and sold by Altera or its authorized distributors. Please +//refer to the Altera Software License Subscription Agreements +//on the Quartus Prime software download page. + +module ddri ( + datain, + inclock, + dataout_h, + dataout_l); + + input [4:0] datain; + input inclock; + output [4:0] dataout_h; + output [4:0] dataout_l; + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP" +// Retrieval info: CONSTANT: INVERT_INPUT_CLOCKS STRING "OFF" +// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_in" +// Retrieval info: CONSTANT: POWER_UP_HIGH STRING "ON" +// Retrieval info: CONSTANT: WIDTH NUMERIC "5" +// Retrieval info: USED_PORT: datain 0 0 5 0 INPUT NODEFVAL "datain[4..0]" +// Retrieval info: CONNECT: @datain 0 0 5 0 datain 0 0 5 0 +// Retrieval info: USED_PORT: dataout_h 0 0 5 0 OUTPUT NODEFVAL "dataout_h[4..0]" +// Retrieval info: CONNECT: dataout_h 0 0 5 0 @dataout_h 0 0 5 0 +// Retrieval info: USED_PORT: dataout_l 0 0 5 0 OUTPUT NODEFVAL "dataout_l[4..0]" +// Retrieval info: CONNECT: dataout_l 0 0 5 0 @dataout_l 0 0 5 0 +// Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "inclock" +// Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL ddri.v TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddri.qip TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddri.bsf TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddri_inst.v TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddri_bb.v TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddri.inc TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddri.cmp TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddri.ppf TRUE FALSE diff --git a/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri_inst.v b/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri_inst.v new file mode 100644 index 0000000..0574ba9 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri_inst.v @@ -0,0 +1,6 @@ +ddri ddri_inst ( + .datain ( datain_sig ), + .inclock ( inclock_sig ), + .dataout_h ( dataout_h_sig ), + .dataout_l ( dataout_l_sig ) + ); |
