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-rw-r--r--manufacturer/altera/cyclone10_lp/sim/data/etoe0.dat52
-rw-r--r--manufacturer/altera/cyclone10_lp/sim/data/etoe1.dat42
-rw-r--r--manufacturer/altera/cyclone10_lp/sim/data/etoe2.dat66
-rw-r--r--manufacturer/altera/cyclone10_lp/sim/src/tb.sv4
-rw-r--r--manufacturer/altera/cyclone10_lp/sim/wav/wave.do34
-rw-r--r--manufacturer/altera/cyclone10_lp/sim/wav/wave_etoe.do170
-rw-r--r--manufacturer/altera/cyclone10_lp/sim/win/betsy.mpf124
7 files changed, 236 insertions, 256 deletions
diff --git a/manufacturer/altera/cyclone10_lp/sim/data/etoe0.dat b/manufacturer/altera/cyclone10_lp/sim/data/etoe0.dat
index 59e747a..76b1583 100644
--- a/manufacturer/altera/cyclone10_lp/sim/data/etoe0.dat
+++ b/manufacturer/altera/cyclone10_lp/sim/data/etoe0.dat
@@ -7,9 +7,9 @@
D5
02 // Dest MAC Address
00
-02
03
04
+04
05
C8 // Source MAC Address
F7
@@ -41,19 +41,19 @@ A8
65
30 // UDP Source Port
00
-90 // UDP Dest Port
-20
+20 // UDP Dest Port
+30
00 // UDP Length
-0f
-AC // UDP Checksum
-E6
-00
-00
-00
-00
-05
-06
-07
+12
+00 // UDP Checksum
+00
+01
+01
+01
+01
+01
+01
+01
08
09
0A
@@ -69,7 +69,7 @@ E6
E3 //
95
184
-ff // Idle Clocks * 16
+40 // Idle Clocks * 16
55 // Preamble
55
55
@@ -80,8 +80,8 @@ D5
02 // Dest MAC Address
00
02
-03
-04
+05
+06
05
C8 // Source MAC Address
F7
@@ -113,19 +113,19 @@ A8
65
30 // UDP Source Port
00
-90 // UDP Dest Port
-20
+00 // UDP Dest Port
+50
00 // UDP Length
-0f
+12
AC // UDP Checksum
E6
-00
-00
-00
-00
-05
-06
-07
+01
+01
+01
+01
+01
+01
+01
08
09
0A
diff --git a/manufacturer/altera/cyclone10_lp/sim/data/etoe1.dat b/manufacturer/altera/cyclone10_lp/sim/data/etoe1.dat
index ca1df41..e65674a 100644
--- a/manufacturer/altera/cyclone10_lp/sim/data/etoe1.dat
+++ b/manufacturer/altera/cyclone10_lp/sim/data/etoe1.dat
@@ -5,12 +5,12 @@
55
55
D5
-02 // Dest MAC Address
-00
+01 // Dest MAC Address
02
03
04
05
+06
C8 // Source MAC Address
F7
50
@@ -41,19 +41,19 @@ A8
65
30 // UDP Source Port
00
-90 // UDP Dest Port
+70 // UDP Dest Port
00
00 // UDP Length
-0f
+12
AC // UDP Checksum
E6
-01
-01
-01
-01
-05
-06
-07
+02
+02
+02
+02
+02
+02
+02
08
09
0A
@@ -69,7 +69,7 @@ E6
E3 //
95
184
-ff // Idle Clocks * 16
+30 // Idle Clocks * 16
55 // Preamble
55
55
@@ -113,19 +113,19 @@ A8
65
30 // UDP Source Port
00
-90 // UDP Dest Port
-20
+70 // UDP Dest Port
+00
00 // UDP Length
-0f
+12
AC // UDP Checksum
E6
-01
02
-03
-04
-05
-06
-07
+02
+02
+02
+02
+02
+02
08
09
0A
diff --git a/manufacturer/altera/cyclone10_lp/sim/data/etoe2.dat b/manufacturer/altera/cyclone10_lp/sim/data/etoe2.dat
index ad08f1b..5607da4 100644
--- a/manufacturer/altera/cyclone10_lp/sim/data/etoe2.dat
+++ b/manufacturer/altera/cyclone10_lp/sim/data/etoe2.dat
@@ -5,12 +5,12 @@
55
55
D5
-02 // Dest MAC Address
-00
-02
-03
-04
-05
+0a // Dest MAC Address
+0b
+0c
+0d
+0e
+0f
C8 // Source MAC Address
F7
50
@@ -41,19 +41,19 @@ A8
65
30 // UDP Source Port
00
-90 // UDP Dest Port
-00
+20 // UDP Dest Port
+aa
00 // UDP Length
0f
AC // UDP Checksum
E6
-02
-02
-02
-02
-05
-06
-07
+03
+03
+03
+03
+03
+03
+03
08
09
0A
@@ -62,14 +62,11 @@ E6
0D
0E
0F
-10
-11
-12
71 // FCS
E3 //
95
184
-ff // Idle Clocks * 16
+20 // Idle Clocks * 16
55 // Preamble
55
55
@@ -77,12 +74,12 @@ ff // Idle Clocks * 16
55
55
D5
-02 // Dest MAC Address
-00
-02
-03
-04
-05
+0a // Dest MAC Address
+0b
+0c
+0d
+0e
+0f
C8 // Source MAC Address
F7
50
@@ -113,19 +110,19 @@ A8
65
30 // UDP Source Port
00
-90 // UDP Dest Port
-20
+20 // UDP Dest Port
+ab
00 // UDP Length
0f
AC // UDP Checksum
E6
-01
-02
03
-04
-05
-06
-07
+03
+03
+03
+03
+03
+03
08
09
0A
@@ -134,9 +131,6 @@ E6
0D
0E
0F
-10
-11
-12
71 // FCS
E3 //
95
diff --git a/manufacturer/altera/cyclone10_lp/sim/src/tb.sv b/manufacturer/altera/cyclone10_lp/sim/src/tb.sv
index 9b6b3a2..25fbe75 100644
--- a/manufacturer/altera/cyclone10_lp/sim/src/tb.sv
+++ b/manufacturer/altera/cyclone10_lp/sim/src/tb.sv
@@ -26,8 +26,8 @@
`timescale 1ns / 1ps
-//`define TEST_ETOE
-`define ML_ENGINE
+`define TEST_ETOE
+//`define ML_ENGINE
//`define TEST_CONTROLLER
`define INCLUDED
diff --git a/manufacturer/altera/cyclone10_lp/sim/wav/wave.do b/manufacturer/altera/cyclone10_lp/sim/wav/wave.do
index b64b7d5..9fbd0d8 100644
--- a/manufacturer/altera/cyclone10_lp/sim/wav/wave.do
+++ b/manufacturer/altera/cyclone10_lp/sim/wav/wave.do
@@ -6,7 +6,6 @@ add wave -noupdate /tb/pclk
add wave -noupdate /tb/clk_25
add wave -noupdate /tb/clk_phy
add wave -noupdate /tb/clk_phyx2
-add wave -noupdate /tb/rx_cnt
add wave -noupdate /tb/phy0_rx_clk
add wave -noupdate /tb/phy0_rx_ctl
add wave -noupdate /tb/phy0_rx_d
@@ -25,19 +24,11 @@ add wave -noupdate /tb/phy1_mdio
add wave -noupdate /tb/phy1_resetn
add wave -noupdate /tb/phy1_intn
add wave -noupdate /tb/phy_up
-add wave -noupdate /tb/word_sync_active
-add wave -noupdate /tb/rx_cnt
-add wave -noupdate /tb/rx0_f
-add wave -noupdate /tb/rx0_f_reg
add wave -noupdate /tb/rx0_data_cnt
-add wave -noupdate /tb/rx0_data_interval
add wave -noupdate /tb/rx0_d
add wave -noupdate /tb/rx1_d
add wave -noupdate /tb/rx2_d
-add wave -noupdate /tb/rx0_packets
-add wave -noupdate /tb/rx0_packet_active
add wave -noupdate /tb/rx1_data_cnt
-add wave -noupdate /tb/rx1
add wave -noupdate /tb/rx2_data_cnt
add wave -noupdate /tb/phy0_tx_clk
add wave -noupdate /tb/phy0_tx_ctl
@@ -62,7 +53,6 @@ add wave -noupdate /tb/dut/sys_rstn
add wave -noupdate /tb/dut/phy_resetn
add wave -noupdate /tb/dut/phy0_rstn
add wave -noupdate /tb/dut/phy1_rstn
-add wave -noupdate /tb/rx_cnt
add wave -noupdate /tb/clk_phy
add wave -noupdate /tb/clk_phyx2
add wave -noupdate {/tb/dut/phy_up[0]}
@@ -71,8 +61,6 @@ add wave -noupdate /tb/dut/rgmi_rx_0/datain
add wave -noupdate /tb/dut/rgmi_rx_0/inclock
add wave -noupdate /tb/dut/rgmi_rx_0/dataout_h
add wave -noupdate /tb/dut/rgmi_rx_0/dataout_l
-add wave -noupdate /tb/dut/rx0_ctl
-add wave -noupdate /tb/dut/rx0_d
add wave -noupdate /tb/dut/rx0_ctl_m1
add wave -noupdate /tb/dut/rx0_d_m1
add wave -noupdate /tb/dut/rx0_ctl_m2
@@ -124,7 +112,6 @@ add wave -noupdate /tb/dut/mac_0/dpr_we
add wave -noupdate /tb/dut/mac_0/tx_sample
add wave -noupdate /tb/dut/mac_0/tx_sample_re
add wave -noupdate /tb/dut/mac_0/tx_active
-add wave -noupdate /tb/dut/mac_0/tx_byte_cnt
add wave -noupdate /tb/dut/mac_0/tx_byte_cnt_i
add wave -noupdate /tb/dut/mac_0/tx_src_sel
add wave -noupdate /tb/dut/mac_0/tx_mode
@@ -209,25 +196,17 @@ add wave -noupdate /tb/dut/micro_fifo_0/dpram_dout
add wave -noupdate /tb/dut/micro_fifo_0/dpram_oe
add wave -noupdate /tb/dut/micro_fifo_0/dpram_ptrs_sel
add wave -noupdate /tb/dut/micro_fifo_0/dpram_rx_dout
-add wave -noupdate /tb/dut/micro_fifo_0/dpram_rx_enable
add wave -noupdate /tb/dut/micro_fifo_0/dpram_rx_sel
add wave -noupdate /tb/dut/micro_fifo_0/dpram_tx_dout
-add wave -noupdate /tb/dut/micro_fifo_0/dpram_tx_enable
add wave -noupdate /tb/dut/micro_fifo_0/dpram_tx_sel
add wave -noupdate /tb/dut/micro_fifo_0/dpram_we
add wave -noupdate /tb/dut/micro_fifo_0/fifo_clk
add wave -noupdate /tb/dut/micro_fifo_0/fifo_d_out
-add wave -noupdate /tb/dut/micro_fifo_0/fifo_int
-add wave -noupdate /tb/dut/micro_fifo_0/fifo_int_acked
add wave -noupdate /tb/dut/micro_fifo_0/fifo_re
add wave -noupdate /tb/dut/micro_fifo_0/fifo_we
add wave -noupdate /tb/dut/micro_fifo_0/fifo_we_m1
add wave -noupdate /tb/dut/micro_fifo_0/reset_ptrs
-add wave -noupdate /tb/dut/micro_fifo_0/rx_byte_cnt
-add wave -noupdate /tb/dut/micro_fifo_0/rx_empty
-add wave -noupdate /tb/dut/micro_fifo_0/rx_rd_ptr
add wave -noupdate /tb/dut/micro_fifo_0/rx_wr_ptr
-add wave -noupdate /tb/dut/micro_fifo_0/tx_mode
add wave -noupdate /tb/dut/micro_fifo_0/tx_rd_ptr
add wave -noupdate /tb/dut/micro_fifo_0/tx_wr_ptr
add wave -noupdate /tb/dut/micro_fifo_0/tx_wr_ptr_latched
@@ -236,16 +215,6 @@ add wave -noupdate /tb/dut/micro_fifo_0/uc_clk
add wave -noupdate -divider Controller
add wave -noupdate /tb/dut/controller_0/clk
add wave -noupdate /tb/dut/controller_0/cont_state
-add wave -noupdate /tb/dut/controller_0/cmd_ack
-add wave -noupdate /tb/dut/controller_0/cmd_addr
-add wave -noupdate /tb/dut/controller_0/cmd_addr_ro
-add wave -noupdate /tb/dut/controller_0/cmd_addr_valid
-add wave -noupdate /tb/dut/controller_0/cmd_data
-add wave -noupdate /tb/dut/controller_0/cmd_error
-add wave -noupdate /tb/dut/controller_0/cmd_id
-add wave -noupdate /tb/dut/controller_0/cmd_response
-add wave -noupdate /tb/dut/controller_0/cmd_size
-add wave -noupdate /tb/dut/controller_0/cmd_type
add wave -noupdate /tb/dut/controller_0/hf_ptrs_sel
add wave -noupdate /tb/dut/controller_0/hf_rx_sel
add wave -noupdate /tb/dut/controller_0/hf_tx_sel
@@ -259,7 +228,6 @@ add wave -noupdate /tb/dut/controller_0/mem_d_o
add wave -noupdate /tb/dut/controller_0/mem_state
add wave -noupdate /tb/dut/controller_0/mem_we
add wave -noupdate /tb/dut/controller_0/mem_oe
-add wave -noupdate /tb/dut/controller_0/rx_cmd
add wave -noupdate /tb/dut/controller_0/rx_cnt
add wave -noupdate /tb/dut/controller_0/rx_fifo_int
add wave -noupdate /tb/dut/controller_0/rx_fifo_int_acked
@@ -270,10 +238,8 @@ add wave -noupdate /tb/dut/controller_0/rx_wr_ptr
add wave -noupdate /tb/dut/controller_0/rx_rd_ptr
add wave -noupdate /tb/dut/controller_0/tx_cnt
add wave -noupdate /tb/dut/controller_0/tx_fifo_empty
-add wave -noupdate /tb/dut/controller_0/tx_pkt_cnt
add wave -noupdate /tb/dut/controller_0/tx_wr_active
add wave -noupdate /tb/dut/controller_0/tx_wr_ptr
-add wave -noupdate /tb/dut/controller_0/mem_event_handling
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {3188000 ps} 0}
quietly wave cursor active 1
diff --git a/manufacturer/altera/cyclone10_lp/sim/wav/wave_etoe.do b/manufacturer/altera/cyclone10_lp/sim/wav/wave_etoe.do
index 7459b26..7a88ecf 100644
--- a/manufacturer/altera/cyclone10_lp/sim/wav/wave_etoe.do
+++ b/manufacturer/altera/cyclone10_lp/sim/wav/wave_etoe.do
@@ -8,6 +8,7 @@ add wave -noupdate /tb/clk_phyx2
add wave -noupdate /tb/pll_lock
add wave -noupdate /tb/phy_up
add wave -noupdate /tb/pclk
+add wave -noupdate /tb/rx0_d
add wave -noupdate -radix unsigned /tb/rx0_data_cnt
add wave -noupdate /tb/rx0_last_byte
add wave -noupdate /tb/rx0_idle_cnt
@@ -18,12 +19,20 @@ add wave -noupdate /tb/phy0_tx_d
add wave -noupdate /tb/phy0_rx_clk
add wave -noupdate /tb/phy0_rx_ctl
add wave -noupdate /tb/phy0_rx_d
+add wave -noupdate /tb/rx1_idle_cnt
add wave -noupdate /tb/phy1_rx_clk
add wave -noupdate /tb/phy1_rx_ctl
add wave -noupdate /tb/phy1_rx_d
add wave -noupdate /tb/phy1_tx_clk
add wave -noupdate /tb/phy1_tx_ctl
add wave -noupdate /tb/phy1_tx_d
+add wave -noupdate /tb/rx2_idle_cnt
+add wave -noupdate /tb/phy2_rx_clk
+add wave -noupdate /tb/phy2_rx_ctl
+add wave -noupdate /tb/phy2_rx_d
+add wave -noupdate /tb/phy2_tx_clk
+add wave -noupdate /tb/phy2_tx_ctl
+add wave -noupdate /tb/phy2_tx_d
add wave -noupdate -divider Top
add wave -noupdate /tb/dut/rstn
add wave -noupdate /tb/dut/sys_rstn
@@ -35,105 +44,110 @@ add wave -noupdate /tb/dut/phy0_clk
add wave -noupdate /tb/dut/phy1_clk
add wave -noupdate {/tb/dut/phy_up[0]}
add wave -noupdate -divider {MAC 0}
+add wave -noupdate /tb/dut/phy0_rx_clk
add wave -noupdate /tb/dut/mac_0/rx_ctl
add wave -noupdate /tb/dut/mac_0/rx_d
+add wave -noupdate /tb/dut/mac_0/rx_state
+add wave -noupdate /tb/dut/mac_0/rx_pkt_length
+add wave -noupdate /tb/dut/mac_0/rx_packet_complete
+add wave -noupdate /tb/dut/mac_0/rx_keep
+add wave -noupdate /tb/dut/mac_0/rx_wr_done
+add wave -noupdate /tb/dut/mac_0/rx_fifo_we
+add wave -noupdate /tb/dut/mac_0/rx_sop
+add wave -noupdate /tb/dut/mac_0/rx_eop
+add wave -noupdate /tb/dut/pclk
add wave -noupdate /tb/dut/mac_0/tx_ctl
add wave -noupdate /tb/dut/mac_0/tx_d
+add wave -noupdate /tb/dut/mac_0/tx_sop
+add wave -noupdate /tb/dut/mac_0/tx_eop
add wave -noupdate -divider {MAC 1}
+add wave -noupdate /tb/dut/phy1_rx_clk
add wave -noupdate /tb/dut/mac_1/rx_ctl
add wave -noupdate /tb/dut/mac_1/rx_d
+add wave -noupdate /tb/dut/mac_1/rx_state
+add wave -noupdate /tb/dut/mac_1/rx_pkt_length
+add wave -noupdate /tb/dut/mac_1/rx_packet_complete
+add wave -noupdate /tb/dut/mac_1/rx_keep
+add wave -noupdate /tb/dut/mac_1/rx_wr_done
+add wave -noupdate /tb/dut/mac_1/rx_fifo_we
+add wave -noupdate /tb/dut/mac_1/rx_sop
+add wave -noupdate /tb/dut/mac_1/rx_eop
+add wave -noupdate /tb/dut/pclk
add wave -noupdate /tb/dut/mac_1/tx_ctl
add wave -noupdate /tb/dut/mac_1/tx_d
+add wave -noupdate /tb/dut/mac_1/tx_sop
+add wave -noupdate /tb/dut/mac_1/tx_eop
add wave -noupdate -divider {MAC 2}
+add wave -noupdate /tb/dut/phy2_rx_clk
add wave -noupdate /tb/dut/mac_2/rx_ctl
add wave -noupdate /tb/dut/mac_2/rx_d
+add wave -noupdate /tb/dut/mac_2/rx_state
+add wave -noupdate /tb/dut/mac_2/rx_pkt_length
+add wave -noupdate /tb/dut/mac_2/rx_packet_complete
+add wave -noupdate /tb/dut/mac_2/rx_keep
+add wave -noupdate /tb/dut/mac_2/rx_wr_done
+add wave -noupdate /tb/dut/mac_2/rx_fifo_we
+add wave -noupdate /tb/dut/mac_2/rx_sop
+add wave -noupdate /tb/dut/mac_2/rx_eop
+add wave -noupdate /tb/dut/pclk
add wave -noupdate /tb/dut/mac_2/tx_ctl
add wave -noupdate /tb/dut/mac_2/tx_d
+add wave -noupdate /tb/dut/mac_2/tx_sop
+add wave -noupdate /tb/dut/mac_2/tx_eop
add wave -noupdate -divider {SWITCH 0}
add wave -noupdate /tb/dut/switch_0/clk
add wave -noupdate /tb/dut/switch_0/phy_up
-add wave -noupdate /tb/dut/switch_0/rx_d_01
-add wave -noupdate /tb/dut/switch_0/rx_d_0u
-add wave -noupdate /tb/dut/switch_0/rx0_byte_cnt
-add wave -noupdate /tb/dut/switch_0/rx_fifo_empty_0u
-add wave -noupdate /tb/dut/switch_0/rx_fifo_empty_01
-add wave -noupdate /tb/dut/switch_0/rx_fifo_empty_u0
-add wave -noupdate /tb/dut/switch_0/rx_fifo_re_01
-add wave -noupdate /tb/dut/switch_0/rx_fifo_re_0u
+add wave -noupdate /tb/dut/switch_0/i_rx0_byte_cnt
+add wave -noupdate /tb/dut/switch_0/i_rx1_byte_cnt
+add wave -noupdate /tb/dut/switch_0/i_rx2_byte_cnt
+add wave -noupdate -divider tx0
add wave -noupdate {/tb/dut/switch_0/tx_f[0]}
+add wave -noupdate /tb/dut/switch_0/tx_mode0
+add wave -noupdate /tb/dut/switch_0/tx0_src_sel
+add wave -noupdate /tb/dut/switch_0/tx0_byte_cnt
+add wave -noupdate /tb/dut/switch_0/rx_fifo_empty_u0_m2
+add wave -noupdate /tb/dut/switch_0/rx_fifo_empty_mle
+add wave -noupdate /tb/dut/switch_0/rx_fifo_empty_20
+add wave -noupdate /tb/dut/switch_0/rx_fifo_empty_10
+add wave -noupdate /tb/dut/switch_0/tx_d0
+add wave -noupdate /tb/dut/switch_0/rx_d_10
+add wave -noupdate /tb/dut/switch_0/rx_d_20
+add wave -noupdate /tb/dut/switch_0/rx_fifo_re_10
+add wave -noupdate /tb/dut/switch_0/rx_fifo_re_20
+add wave -noupdate /tb/dut/switch_0/rx_fifo_re_mle
+add wave -noupdate /tb/dut/switch_0/rx_fifo_re_u0
+add wave -noupdate {/tb/dut/switch_0/tx_fifo_re[0]}
add wave -noupdate {/tb/dut/switch_0/tx_fifo_empty[0]}
+add wave -noupdate -divider tx1
add wave -noupdate {/tb/dut/switch_0/tx_f[1]}
+add wave -noupdate /tb/dut/switch_0/tx_mode1
+add wave -noupdate /tb/dut/switch_0/tx1_src_sel
+add wave -noupdate /tb/dut/switch_0/tx1_byte_cnt
+add wave -noupdate /tb/dut/switch_0/rx_fifo_empty_21
+add wave -noupdate /tb/dut/switch_0/rx_fifo_empty_01
+add wave -noupdate /tb/dut/switch_0/tx_d1
+add wave -noupdate /tb/dut/switch_0/rx_d_01
+add wave -noupdate /tb/dut/switch_0/rx_d_21
add wave -noupdate {/tb/dut/switch_0/tx_fifo_empty[1]}
-add wave -noupdate /tb/dut/switch_0/tx_mode0
-add wave -noupdate /tb/dut/switch_0/tx0_byte_cnt
-add wave -noupdate /tb/dut/switch_0/tx0_src_sel
-add wave -noupdate -divider {MAC 0}
-add wave -noupdate /tb/dut/mac_0/rx_clk
-add wave -noupdate /tb/dut/mac_0/rx_sop
-add wave -noupdate /tb/dut/mac_0/rx_ctl_m1
-add wave -noupdate /tb/dut/mac_0/rx_d_m1
-add wave -noupdate /tb/dut/mac_0/fcs_rx_init
-add wave -noupdate /tb/dut/mac_0/fcs_rx_enable
-add wave -noupdate /tb/dut/mac_0/fcs_rx_addr
-add wave -noupdate /tb/dut/mac_0/fcs_rx_addr_e
-add wave -noupdate /tb/dut/mac_0/fcs_rx_din
-add wave -noupdate /tb/dut/mac_0/fcs_rx_dout
-add wave -noupdate /tb/dut/mac_0/fcs_rx_error
-add wave -noupdate /tb/dut/mac_0/rx_state
-add wave -noupdate -radix unsigned /tb/dut/mac_0/rx_byte_cnt
-add wave -noupdate -radix unsigned /tb/dut/mac_0/rx_pkt_length
-add wave -noupdate /tb/dut/mac_0/rx_l3_proto
-add wave -noupdate /tb/dut/mac_0/rx_packet_complete
-add wave -noupdate /tb/dut/mac_0/rx_wr_done
-add wave -noupdate /tb/dut/mac_0/rx_keep
-add wave -noupdate /tb/dut/mac_0/rx_ctl
-add wave -noupdate /tb/dut/mac_0/rx_d
-add wave -noupdate /tb/dut/mac_0/rx_ctl_m1
-add wave -noupdate /tb/dut/mac_0/rx_d_m1
-add wave -noupdate /tb/dut/mac_0/rx_line_up_cnt
-add wave -noupdate /tb/dut/mac_0/phy_up
-add wave -noupdate /tb/dut/mac_0/dpr_ad
-add wave -noupdate /tb/dut/mac_0/dpr_ce
-add wave -noupdate /tb/dut/mac_0/dpr_di
-add wave -noupdate /tb/dut/mac_0/dpr_di_reg
-add wave -noupdate /tb/dut/mac_0/dpr_do
-add wave -noupdate /tb/dut/mac_0/dpr_we
-add wave -noupdate /tb/dut/mac_0/tx_sample
-add wave -noupdate /tb/dut/mac_0/tx_sample_re
-add wave -noupdate /tb/dut/mac_0/tx_active
-add wave -noupdate /tb/dut/mac_0/tx_byte_cnt_i
-add wave -noupdate /tb/dut/mac_0/tx_clk
-add wave -noupdate /tb/dut/mac_0/tx_src_sel
-add wave -noupdate /tb/dut/mac_0/tx_mode
-add wave -noupdate /tb/dut/mac_0/tx_state
-add wave -noupdate /tb/dut/mac_0/tx_fifo_re
-add wave -noupdate /tb/dut/mac_0/tx_last_byte
-add wave -noupdate /tb/dut/mac_0/tx_finished
-add wave -noupdate /tb/dut/mac_0/tx_fifo_d
-add wave -noupdate /tb/dut/mac_0/tx_fifo_d_m1
-add wave -noupdate /tb/dut/mac_0/tx_fifo_empty
-add wave -noupdate /tb/dut/mac_0/tx_f_pkt
-add wave -noupdate /tb/dut/mac_0/tx_sop
-add wave -noupdate /tb/dut/mac_0/tx_eop
-add wave -noupdate /tb/dut/mac_0/tx_clk
-add wave -noupdate /tb/dut/mac_0/tx_ctl
-add wave -noupdate /tb/dut/mac_0/tx_d
-add wave -noupdate /tb/dut/mac_0/tx_f
-add wave -noupdate /tb/dut/phy0_tx_clk
-add wave -noupdate /tb/dut/phy0_tx_ctl
-add wave -noupdate /tb/dut/phy0_tx_d
-add wave -noupdate /tb/dut/mac_0/tx_ctl_idle
-add wave -noupdate /tb/dut/mac_0/tx_d_idle
-add wave -noupdate /tb/dut/mac_0/tx_ctl_pkt
-add wave -noupdate /tb/dut/mac_0/tx_data_pkt
-add wave -noupdate /tb/dut/mac_0/fcs_tx_init
-add wave -noupdate /tb/dut/mac_0/fcs_tx_enable
-add wave -noupdate /tb/dut/mac_0/fcs_tx_dout
-add wave -noupdate /tb/dut/mac_0/fcs_tx_addr
-add wave -noupdate /tb/dut/mac_0/fcs_tx_addr_e
-add wave -noupdate /tb/dut/mac_0/fcs_tx_din
+add wave -noupdate /tb/dut/switch_0/rx_fifo_re_01
+add wave -noupdate /tb/dut/switch_0/rx_fifo_re_21
+add wave -noupdate -divider tx2
+add wave -noupdate /tb/dut/switch_0/tx_mode2
+add wave -noupdate /tb/dut/switch_0/tx2_src_sel
+add wave -noupdate /tb/dut/switch_0/tx2_byte_cnt
+add wave -noupdate /tb/dut/switch_0/rx_fifo_empty_12
+add wave -noupdate /tb/dut/switch_0/rx_fifo_empty_02
+add wave -noupdate /tb/dut/switch_0/tx_d2
+add wave -noupdate /tb/dut/switch_0/rx_d_02
+add wave -noupdate /tb/dut/switch_0/rx_d_12
+add wave -noupdate /tb/dut/switch_0/rx_fifo_re_02
+add wave -noupdate /tb/dut/switch_0/rx_fifo_re_12
+add wave -noupdate {/tb/dut/switch_0/tx_fifo_re[2]}
+add wave -noupdate {/tb/dut/switch_0/tx_fifo_empty[2]}
+add wave -noupdate /tb/dut/switch_0/rx_fifo_empty_02
+add wave -noupdate /tb/dut/switch_0/rx_fifo_empty_12
TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {652000 ps} 0}
+WaveRestoreCursors {{Cursor 1} {2154000 ps} 0}
quietly wave cursor active 1
configure wave -namecolwidth 257
configure wave -valuecolwidth 100
@@ -149,4 +163,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ps
update
-WaveRestoreZoom {0 ps} {10500 ns}
+WaveRestoreZoom {0 ps} {21 us}
diff --git a/manufacturer/altera/cyclone10_lp/sim/win/betsy.mpf b/manufacturer/altera/cyclone10_lp/sim/win/betsy.mpf
index af316f2..241cb09 100644
--- a/manufacturer/altera/cyclone10_lp/sim/win/betsy.mpf
+++ b/manufacturer/altera/cyclone10_lp/sim/win/betsy.mpf
@@ -921,7 +921,7 @@ Resolution = ns
UserTimeUnit = default
; Default run length
-RunLength = 10 us
+RunLength = 20 us
; Maximum iterations that can be run without advancing simulation time
IterationLimit = 10000000
@@ -2236,67 +2236,73 @@ suppress = 8780 ;an explanation can be had by running: verror 8780
Project_Version = 6
Project_DefaultLib = work
Project_SortMethod = unused
-Project_Files_Count = 27
-Project_File_0 = C:/Projects/PrivateIsland/pi-betsy/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio.v
-Project_File_P_0 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1752165667 cover_fsm 0 cover_branch 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 24 cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_1 = C:/Projects/PrivateIsland/pi-betsy/src/sync_fifo.v
-Project_File_P_1 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1752165667 cover_fsm 0 cover_branch 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 15 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_2 = C:/Projects/PrivateIsland/pi-betsy/src/dpram_inf.v
-Project_File_P_2 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 last_compile 1754328280 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +define+SIMULATION=1 compile_order 2 cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_3 = C:/Projects/PrivateIsland/pi-betsy/src/mdio.v
-Project_File_P_3 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1752165667 cover_fsm 0 cover_branch 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 9 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_4 = C:/Projects/PrivateIsland/pi-betsy/src/switch.v
-Project_File_P_4 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1754328280 cover_fsm 0 cover_branch 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 14 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_5 = C:/Projects/PrivateIsland/pi-betsy/src/udp_rx.v
-Project_File_P_5 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1752165667 cover_fsm 0 cover_branch 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 16 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_6 = C:/Projects/PrivateIsland/pi-betsy/src/ethernet_params.v
-Project_File_P_6 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1752165667 cover_fsm 0 cover_branch 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 4 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_7 = C:/Projects/PrivateIsland/pi-betsy/manufacturer/altera/cyclone10_lp/src/betsy.v
-Project_File_P_7 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1754591995 cover_fsm 0 cover_branch 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +define+SIMULATION=1 compile_order 18 cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_8 = C:/Projects/PrivateIsland/pi-betsy/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.v
-Project_File_P_8 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1752165667 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 25 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_9 = C:/Projects/PrivateIsland/pi-betsy/src/pkt_filter.v
-Project_File_P_9 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1752165667 cover_fsm 0 cover_branch 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 13 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_10 = C:/Projects/PrivateIsland/pi-betsy/src/fcs.v
-Project_File_P_10 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1752165667 cover_fsm 0 cover_branch 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 5 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_11 = C:/Projects/PrivateIsland/pi-betsy/manufacturer/altera/cyclone10_lp/sim/src/tb.sv
-Project_File_P_11 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1754328280 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 19 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_12 = C:/Projects/PrivateIsland/pi-betsy/src/ipv4_rx_c.v
-Project_File_P_12 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1754328280 cover_fsm 0 cover_branch 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 8 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_13 = C:/Projects/PrivateIsland/pi-betsy/src/half_fifo.v
-Project_File_P_13 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1752165667 cover_fsm 0 cover_branch 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 6 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_14 = C:/Projects/PrivateIsland/pi-betsy/src/cont_params.v
-Project_File_P_14 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1754591995 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 20 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_15 = C:/Projects/PrivateIsland/pi-betsy/src/metrics.v
-Project_File_P_15 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1754328280 cover_fsm 0 cover_branch 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 12 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_16 = C:/Projects/PrivateIsland/pi-betsy/src/mac_rgmii.v
-Project_File_P_16 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1754328280 cover_fsm 0 cover_branch 0 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 21 cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_17 = C:/Projects/PrivateIsland/pi-betsy/src/drop_fifo.v
-Project_File_P_17 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1752274407 cover_fsm 0 cover_branch 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 3 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_18 = C:/Projects/PrivateIsland/pi-betsy/src/cam.v
-Project_File_P_18 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1754328280 cover_fsm 0 cover_branch 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_19 = C:/Projects/PrivateIsland/pi-betsy/src/rgmii_params.v
-Project_File_P_19 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 last_compile 1752165667 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 22 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_20 = C:/Projects/PrivateIsland/pi-betsy/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.v
-Project_File_P_20 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1752165667 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 26 cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_21 = C:/Projects/PrivateIsland/pi-betsy/manufacturer/altera/cyclone10_lp/ip/pll/pll.v
-Project_File_P_21 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1752165667 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 23 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_22 = C:/Projects/PrivateIsland/pi-betsy/src/ipv4_rx.v
-Project_File_P_22 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1754328280 cover_fsm 0 cover_branch 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 7 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_23 = C:/Projects/PrivateIsland/pi-betsy/src/mdio_cont.v
-Project_File_P_23 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1754328280 cover_fsm 0 cover_branch 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 10 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_24 = C:/Projects/PrivateIsland/pi-betsy/src/udp_rx_c.v
-Project_File_P_24 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1752165667 cover_fsm 0 cover_branch 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 17 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_25 = C:/Projects/PrivateIsland/pi-betsy/src/controller.v
-Project_File_P_25 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 last_compile 1754945708 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_26 = C:/Projects/PrivateIsland/pi-betsy/src/mdio_data_ti.v
-Project_File_P_26 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1752165667 cover_fsm 0 cover_branch 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 11 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_Files_Count = 30
+Project_File_0 = C:/Projects/PrivateIsland/privateisland/src/mdio_data_ti.v
+Project_File_P_0 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1782576101 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 11 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_1 = C:/Projects/PrivateIsland/privateisland/src/half_fifo.v
+Project_File_P_1 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1782576101 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 6 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_2 = C:/Projects/PrivateIsland/privateisland/src/ipv4_rx_c.v
+Project_File_P_2 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1782576101 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 8 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_3 = C:/Projects/PrivateIsland/privateisland/src/cont_params.v
+Project_File_P_3 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 last_compile 1782576101 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 19 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_4 = C:/Projects/PrivateIsland/privateisland/src/ipv4_tx_c.v
+Project_File_P_4 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1782576101 cover_fsm 0 cover_branch 0 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 28 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_5 = C:/Projects/PrivateIsland/privateisland/src/drop_fifo.v
+Project_File_P_5 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1782576101 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 3 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_6 = C:/Projects/PrivateIsland/privateisland/src/mac_rgmii.v
+Project_File_P_6 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 last_compile 1782576101 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 20 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_7 = C:/Projects/PrivateIsland/privateisland/src/cam.v
+Project_File_P_7 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1782736853 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_8 = C:/Projects/PrivateIsland/privateisland/src/mle_params.v
+Project_File_P_8 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1782576101 cover_fsm 0 cover_branch 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 27 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_9 = C:/Projects/PrivateIsland/privateisland/src/mdio.v
+Project_File_P_9 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1782576101 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 9 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_10 = C:/Projects/PrivateIsland/privateisland/src/switch.v
+Project_File_P_10 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1782576101 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +define+PHY2_PRESENT=1 compile_order 13 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_11 = C:/Projects/PrivateIsland/privateisland/src/udp_rx.v
+Project_File_P_11 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1782576101 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 15 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_12 = C:/Projects/PrivateIsland/privateisland/manufacturer/altera/cyclone10_lp/src/betsy.v
+Project_File_P_12 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1782576101 cover_fsm 0 cover_branch 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +define+SIMULATION=1 compile_to work vlog_upper 0 cover_noshort 0 compile_order 17 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_13 = C:/Projects/PrivateIsland/privateisland/src/mdio_cont.v
+Project_File_P_13 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1782576101 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 10 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_14 = C:/Projects/PrivateIsland/privateisland/src/ipv4_rx.v
+Project_File_P_14 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1782576101 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 7 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_15 = C:/Projects/PrivateIsland/privateisland/manufacturer/altera/cyclone10_lp/ip/pll/pll.v
+Project_File_P_15 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1782576101 cover_fsm 0 cover_branch 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 22 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_16 = C:/Projects/PrivateIsland/privateisland/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.v
+Project_File_P_16 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1782576101 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 24 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_17 = C:/Projects/PrivateIsland/privateisland/src/pkt_filter.v
+Project_File_P_17 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1782576101 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 12 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_18 = C:/Projects/PrivateIsland/privateisland/manufacturer/altera/cyclone10_lp/sim/src/tb.sv
+Project_File_P_18 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1782578131 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 18 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_19 = C:/Projects/PrivateIsland/privateisland/src/ml_engine.v
+Project_File_P_19 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1782576101 cover_fsm 0 cover_branch 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 26 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_20 = C:/Projects/PrivateIsland/privateisland/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio.v
+Project_File_P_20 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1782576101 cover_fsm 0 cover_branch 0 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 23 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_21 = C:/Projects/PrivateIsland/privateisland/src/sync_fifo.v
+Project_File_P_21 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1782576101 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 14 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_22 = C:/Projects/PrivateIsland/privateisland/src/dpram_inf.v
+Project_File_P_22 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1782576101 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +define+SIMULATION=1 compile_order 2 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_23 = C:/Projects/PrivateIsland/privateisland/src/ethernet_params.v
+Project_File_P_23 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1782576101 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 4 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_24 = C:/Projects/PrivateIsland/privateisland/src/ipv4_tx_mle.v
+Project_File_P_24 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1782576101 cover_fsm 0 cover_branch 0 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 29 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_25 = C:/Projects/PrivateIsland/privateisland/src/rgmii_params.v
+Project_File_P_25 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1782576101 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 21 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_26 = C:/Projects/PrivateIsland/privateisland/src/controller.v
+Project_File_P_26 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1782576101 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_27 = C:/Projects/PrivateIsland/privateisland/src/udp_rx_c.v
+Project_File_P_27 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1782576101 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 16 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_28 = C:/Projects/PrivateIsland/privateisland/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.v
+Project_File_P_28 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1782576101 cover_fsm 0 cover_branch 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 25 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_29 = C:/Projects/PrivateIsland/privateisland/src/fcs.v
+Project_File_P_29 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1782576101 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 5 dont_compile 0 cover_expr 0 cover_stmt 0
Project_Sim_Count = 0
Project_Folder_Count = 0
Echo_Compile_Output = 0
Save_Compile_Report = 1
Project_Opt_Count = 0
-ForceSoftPaths = 0
+ForceSoftPaths = 1
ProjectStatusDelay = 5000
VERILOG_DoubleClick = Edit
VERILOG_CustomDoubleClick =
@@ -2338,5 +2344,5 @@ DEBUGDATABASE_DoubleClick = Edit
DEBUGDATABASE_CustomDoubleClick =
DEBUGARCHIVE_DoubleClick = Edit
DEBUGARCHIVE_CustomDoubleClick =
-Project_Major_Version = 2024
-Project_Minor_Version = 3
+Project_Major_Version = 2025
+Project_Minor_Version = 2
generated by cgit v1.2.3-8-gadcc (git 2.29.0) at 2026-06-29 21:16:47 +0000

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