summaryrefslogtreecommitdiffhomepage
AgeCommit message (Collapse)Author
7 hourssim: update sim related files for website article ↵HEADmasterPrivate Island Networks Inc
https://privateisland.tech/dev/pi-sim-betsy
2026-02-03mle: patch files to support FSM3, MLE header, and bug fixesPrivate Island Networks Inc
2025-12-21README: update for BetsyPrivate Island Networks Inc
2025-12-21betsy: preliminary beta snapshotPrivate Island Networks Inc
2025-12-21simulation: remove top level directoryPrivate Island Networks Inc
2025-12-21python: add python unit test scriptsPrivate Island Networks Inc
2025-09-01cont: update controller complex for Betsy: see ↵Private Island Networks
privateisland.tech/dev/pi-controller
2025-09-01rename source to srcPrivate Island Networks
2025-07-03manu: prune and rename to make currentdarsenaPrivate Island Networks
2023-12-27drop_fifo: fix up logic when packets are droppedPrivate Island Networks Inc
2021-06-30controller: rm i2c_fifo_priority because it is no longer usedmindchasers
2021-06-30top/controller: re i2c_fifo_priority because it is no longer usedmindchasers
2021-03-02top: remap shield I/O to use GPIO rather than specific names, default is now ↵mindchasers
network tap, misc cleanup
2021-03-02ecp5um: include this Lattice file for easy referencemindchasers
2021-03-02update project filemindchasers
2021-03-02switch: add tx_src_selmindchasers
2021-03-02spi: fix write bugmindchasers
2021-03-02pkt_filter: add wire for matchmindchasers
2021-03-02directives: clean up, default is now to define a GIGE shield presentmindchasers
2021-03-02controller: clean up, tx_metrics becomes tx_custommindchasers
2021-03-02drop_fifo: first pass at a simplified approachmindchasers
2021-03-02mac: use an module rather than embedding logic, minor cleanupsmindchasers
2021-03-02an: encapsulate a simpliied version of SGMII auto negotiationmindchasers
2021-03-02lpf: use GPIO for directly instead of specific shield I/O names and general ↵mindchasers
clean up
2021-03-02pin_mux: document GPIO mapping for supported shieldsmindchasers
2021-03-02add Cyclone 10 LP folder to projectmindchasers
2020-11-26project: remove DARSENA_V01 support and minor cleanupmindchasers
2020-11-20manufacturer: estblish trion and cyclone 10 gx foldersmindchasers
2020-11-20top: move darsena top under ecp5um foldermindchasers
2020-11-19lattice: clean up project files to match latest topmindchasers
2020-11-19fifos: remove specific sized fifosmindchasers
2020-11-19top: add support for custom packet and misc. cleanupsmindchasers
2020-11-19switch: add support for custom packetsmindchasers
2020-11-19mac: update for custom packets and clean up logicmindchasers
2020-11-16sgmii_params: add additional K codesmindchasers
2020-11-16eth_params: add TX_MODE_CUSTOM to support custom MAC layersmindchasers
2020-11-16project: rename device to lattice to include specific manufacturersmindchasers
2020-11-16directives: rename file and update for new optionsmindchasers
2020-11-16project: rename sim folder, update READMEmindchasers
2020-11-15ecp5um project: restructure so we can add more devicesmindchasers
2020-10-01link_timer: Generate link timer pulse (1.6 and 10 ms) per SGMII and IEEE 802.3mindchasers
2020-09-27clarity: update SERDES/PCS block to be compatible with Diamond 3.11mindchasers
2019-07-08ldf: update project file to include reveal files for lab exercisesmindchasers
also update .gitignore and prune boards directory to remove *.trc from repo since it's not a source file.
2019-07-08reveal: add labs reveal files to support lab exercisesmindchasers
2019-07-08top: fix typo for debug defines: DEBUG_I2Cmindchasers
2019-07-08lpf: increase PAR Adjust on pcs_pclk to ease meeting timingmindchasers
2019-05-01initial commit, all basic functions work on Darsena V02mindchasers
generated by cgit v1.2.3-8-gadcc (git 2.29.0) at 2026-06-29 23:28:37 +0000

Highly Recommended Verilog Books

Digital VLSI Design with Verilog: A Textbook from Silicon Valley Polytechnic Institute
The Verilog Hardware Description Language
Verilog HDL A Guide to Digital Design and Synthesis