diff options
author | mindchasers <privateisland@mindchasers.com> | 2021-03-02 13:13:46 -0500 |
---|---|---|
committer | mindchasers <privateisland@mindchasers.com> | 2021-03-02 13:13:46 -0500 |
commit | 1fc49e4234f7dfc7954224c21036b4a453121abc (patch) | |
tree | bcb01c06a884ed894e1dec8dc21c14e876bae118 | |
parent | 70cc96d7a94f6ceabde7de511c28db7bc4536278 (diff) |
switch: add tx_src_sel
-rw-r--r-- | source/switch.v | 89 |
1 files changed, 45 insertions, 44 deletions
diff --git a/source/switch.v b/source/switch.v index 6d70c5b..98aec4a 100644 --- a/source/switch.v +++ b/source/switch.v @@ -1,7 +1,7 @@ /* * switch.v * - * Copyright 2018, 2019, 2020 Mind Chasers Inc. + * Copyright 2018, 2019, 2020, 2021 Mind Chasers Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -93,17 +93,18 @@ module switch( output reg [10:0] tx2_byte_cnt, output reg [10:0] tx3_byte_cnt, + // TX Source Select + output reg [2:0] tx_src_sel0, + output reg [2:0] tx_src_sel1, + output reg [2:0] tx_src_sel2, + output reg [2:0] tx_src_sel3, + // TX state machine done flag input [3:0] tx_f, // TX custom packet input tx_custom ); - -reg [2:0] tx0_src_sel; -reg [2:0] tx1_src_sel; -reg [2:0] tx2_src_sel; -reg [2:0] tx3_src_sel; // IPG for Port 0 wire ipg_met; @@ -178,7 +179,7 @@ always @(posedge clk, negedge rstn) if ( !rstn ) begin tx_mode0 <= TX_MODE_AN; - tx0_src_sel <= SEL_PHY1; + tx_src_sel0 <= SEL_PHY1; tx0_byte_cnt <= 'h0; end else if ( tx_f[0] ) @@ -191,22 +192,22 @@ always @(posedge clk, negedge rstn) tx_mode0 <= TX_MODE_AN; else if ( !ipg_met ) tx_mode0 <= TX_MODE_IDLE; - else if (tx0_src_sel==SEL_PHY1 && !rx_fifo_empty_20 ) + else if (tx_src_sel0==SEL_PHY1 && !rx_fifo_empty_20 ) begin tx_mode0 <= TX_MODE_XMT_CUSTOM; - tx0_src_sel <= SEL_PHY2; + tx_src_sel0 <= SEL_PHY2; tx0_byte_cnt <= i_rx2_byte_cnt; end else if (!rx_fifo_empty_10 ) begin tx_mode0 <= TX_MODE_XMT_PKT; - tx0_src_sel <= SEL_PHY1; + tx_src_sel0 <= SEL_PHY1; tx0_byte_cnt <= i_rx1_byte_cnt; end else if (!rx_fifo_empty_20 ) begin tx_mode0 <= TX_MODE_XMT_CUSTOM; - tx0_src_sel <= SEL_PHY2; + tx_src_sel0 <= SEL_PHY2; tx0_byte_cnt <= i_rx2_byte_cnt; end TX_MODE_XMT_PKT: @@ -219,7 +220,7 @@ always @(posedge clk, negedge rstn) // TX0 data mux always @(*) begin - case(tx0_src_sel) + case(tx_src_sel0) SEL_PHY0: tx_d0 = 9'h000; SEL_PHY1: tx_d0 = rx_d_10; SEL_PHY2: tx_d0 = rx_d_20; @@ -233,7 +234,7 @@ always @(*) begin rx_fifo_re_10 = 1'b0; rx_fifo_re_20 = 1'b0; rx_fifo_re_30 = 1'b0; - case(tx0_src_sel) + case(tx_src_sel0) SEL_PHY1: rx_fifo_re_10 = tx_fifo_re[0]; SEL_PHY2: rx_fifo_re_20 = tx_fifo_re[0]; SEL_PHY3: rx_fifo_re_30 = tx_fifo_re[0]; @@ -242,7 +243,7 @@ end // TX0 FIFO Empty Routing always @(*) begin - case(tx0_src_sel) + case(tx_src_sel0) SEL_PHY1: tx_fifo_empty[0] = rx_fifo_empty_10; SEL_PHY2: tx_fifo_empty[0] = rx_fifo_empty_20; SEL_PHY3: tx_fifo_empty[0] = rx_fifo_empty_30; @@ -256,7 +257,7 @@ always @(posedge clk, negedge rstn) if ( !rstn ) begin tx_mode1 <= TX_MODE_AN; - tx1_src_sel <= SEL_PHY0; + tx_src_sel1 <= SEL_PHY0; end else if ( tx_f[1] ) case( tx_mode1 ) @@ -266,30 +267,30 @@ always @(posedge clk, negedge rstn) TX_MODE_IDLE: if ( !phy_up[1] ) tx_mode1 <= TX_MODE_AN; - else if (tx1_src_sel==SEL_PHY0 && !rx_fifo_empty_21 ) + else if (tx_src_sel1==SEL_PHY0 && !rx_fifo_empty_21 ) begin tx_mode1 <= TX_MODE_XMT_PKT; - tx1_src_sel <= SEL_PHY2; + tx_src_sel1 <= SEL_PHY2; end - else if (tx1_src_sel==SEL_PHY0 && !rx_fifo_empty_31 ) + else if (tx_src_sel1==SEL_PHY0 && !rx_fifo_empty_31 ) begin tx_mode1 <= TX_MODE_XMT_PKT; - tx1_src_sel <= SEL_PHY3; + tx_src_sel1 <= SEL_PHY3; end else if (!rx_fifo_empty_01 ) begin tx_mode1 <= TX_MODE_XMT_PKT; - tx1_src_sel <= SEL_PHY0; + tx_src_sel1 <= SEL_PHY0; end else if (!rx_fifo_empty_21 ) begin tx_mode1 <= TX_MODE_XMT_PKT; - tx1_src_sel <= SEL_PHY2; + tx_src_sel1 <= SEL_PHY2; end else if (!rx_fifo_empty_31 ) begin tx_mode1 <= TX_MODE_XMT_PKT; - tx1_src_sel <= SEL_PHY3; + tx_src_sel1 <= SEL_PHY3; end TX_MODE_XMT_PKT: if ( !phy_up[1] ) @@ -301,7 +302,7 @@ always @(posedge clk, negedge rstn) // TX1 data mux always @(*) begin - case(tx1_src_sel) + case(tx_src_sel1) SEL_PHY0: tx_d1 = rx_d_01; SEL_PHY1: tx_d1 = 9'h000; SEL_PHY2: tx_d1 = rx_d_21; @@ -316,7 +317,7 @@ always @(*) begin rx_fifo_re_01 = 1'b0; rx_fifo_re_21 = 1'b0; rx_fifo_re_31 = 1'b0; - case(tx1_src_sel) + case(tx_src_sel1) SEL_PHY0: rx_fifo_re_01 = tx_fifo_re[1]; SEL_PHY2: rx_fifo_re_21 = tx_fifo_re[1]; SEL_PHY3: rx_fifo_re_31 = tx_fifo_re[1]; @@ -325,7 +326,7 @@ end // TX1 FIFO Empty Routing always @(*) begin - case(tx1_src_sel) + case(tx_src_sel1) SEL_PHY0: tx_fifo_empty[1] = rx_fifo_empty_01; SEL_PHY1: tx_fifo_empty[1] = 1'b1; SEL_PHY2: tx_fifo_empty[1] = rx_fifo_empty_21; @@ -347,7 +348,7 @@ always @(posedge clk, negedge rstn) if ( !rstn ) begin tx_mode2 <= TX_MODE_AN; - tx2_src_sel <= SEL_PHY0; + tx_src_sel2 <= SEL_PHY0; end else if ( tx_f[2] ) case( tx_mode2 ) @@ -357,30 +358,30 @@ always @(posedge clk, negedge rstn) TX_MODE_IDLE: if ( !phy_up[2] ) tx_mode2 <= TX_MODE_AN; - else if (tx2_src_sel==SEL_PHY0 && !rx_fifo_empty_12 ) + else if (tx_src_sel2==SEL_PHY0 && !rx_fifo_empty_12 ) begin tx_mode2 <= TX_MODE_XMT_PKT; - tx2_src_sel <= SEL_PHY1; + tx_src_sel2 <= SEL_PHY1; end else if (!rx_fifo_empty_02 ) begin tx_mode2 <= TX_MODE_XMT_PKT; - tx2_src_sel <= SEL_PHY0; + tx_src_sel2 <= SEL_PHY0; end else if (!rx_fifo_empty_12 ) begin tx_mode2 <= TX_MODE_XMT_PKT; - tx2_src_sel <= SEL_PHY1; + tx_src_sel2 <= SEL_PHY1; end else if (!rx_fifo_empty_u2) begin tx_mode2 <= TX_MODE_XMT_PKT; - tx2_src_sel <= SEL_UC; + tx_src_sel2 <= SEL_UC; end else if (tx_custom) begin tx_mode2 <= TX_MODE_XMT_CUSTOM; - tx2_src_sel <= SEL_PHY2; + tx_src_sel2 <= SEL_PHY2; end TX_MODE_XMT_PKT: if ( !phy_up[2] ) @@ -392,7 +393,7 @@ always @(posedge clk, negedge rstn) // TX2 data mux always @(*) begin - case(tx2_src_sel) + case(tx_src_sel2) SEL_PHY0: tx_d2 = rx_d_02; SEL_PHY1: tx_d2 = rx_d_12; SEL_PHY2: tx_d2 = 9'h000; @@ -406,7 +407,7 @@ always @(*) begin rx_fifo_re_02 = 1'b0; rx_fifo_re_12 = 1'b0; rx_fifo_re_u2 = 1'b0; - case(tx2_src_sel) + case(tx_src_sel2) SEL_PHY0: rx_fifo_re_02 = tx_fifo_re[2]; SEL_PHY1: rx_fifo_re_12 = tx_fifo_re[2]; SEL_UC: rx_fifo_re_u2 = tx_fifo_re[2]; @@ -415,7 +416,7 @@ end // TX2 FIFO Empty Routing always @(*) begin - case(tx2_src_sel) + case(tx_src_sel2) SEL_PHY0: tx_fifo_empty[2] = rx_fifo_empty_02; SEL_PHY1: tx_fifo_empty[2] = rx_fifo_empty_12; SEL_PHY2: tx_fifo_empty[2] = 1'b0; // @@ -431,7 +432,7 @@ always @(posedge clk, negedge rstn) if ( !rstn ) begin tx_mode3 <= TX_MODE_AN; - tx3_src_sel <= SEL_PHY1; + tx_src_sel3 <= SEL_PHY1; end else if ( tx_f[3] ) case( tx_mode3 ) @@ -441,20 +442,20 @@ always @(posedge clk, negedge rstn) TX_MODE_IDLE: if ( !phy_up[3] ) tx_mode3 <= TX_MODE_AN; - else if (tx3_src_sel==SEL_PHY1 && !rx_fifo_empty_03 ) + else if (tx_src_sel3==SEL_PHY1 && !rx_fifo_empty_03 ) begin tx_mode3 <= TX_MODE_XMT_PKT; - tx3_src_sel <= SEL_PHY0; + tx_src_sel3 <= SEL_PHY0; end else if (!rx_fifo_empty_13 ) begin tx_mode3 <= TX_MODE_XMT_PKT; - tx3_src_sel <= SEL_PHY1; + tx_src_sel3 <= SEL_PHY1; end else if (!rx_fifo_empty_03 ) begin tx_mode3 <= TX_MODE_XMT_PKT; - tx3_src_sel <= SEL_PHY0; + tx_src_sel3 <= SEL_PHY0; end TX_MODE_XMT_PKT: if ( !phy_up[3] ) @@ -466,7 +467,7 @@ always @(posedge clk, negedge rstn) // TX3 data mux always @(*) begin - case(tx3_src_sel) + case(tx_src_sel3) SEL_PHY0: tx_d3 = rx_d_03; SEL_PHY1: tx_d3 = rx_d_13; SEL_PHY2: tx_d3 = rx_d_23; @@ -481,7 +482,7 @@ always @(posedge clk, negedge rstn) rx_fifo_re_03 = 1'b0; rx_fifo_re_13 = 1'b0; rx_fifo_re_23 = 1'b0; - case(tx3_src_sel) + case(tx_src_sel3) SEL_PHY0: rx_fifo_re_03 = tx_fifo_re[3]; SEL_PHY1: rx_fifo_re_13 = tx_fifo_re[3]; SEL_PHY2: rx_fifo_re_23 = tx_fifo_re[3]; @@ -490,7 +491,7 @@ always @(posedge clk, negedge rstn) // TX3 FIFO Empty Routing always @(*) begin - case(tx3_src_sel) + case(tx_src_sel3) SEL_PHY0: tx_fifo_empty[3] = rx_fifo_empty_03; SEL_PHY1: tx_fifo_empty[3] = rx_fifo_empty_13; SEL_PHY2: tx_fifo_empty[3] = rx_fifo_empty_23; @@ -527,4 +528,4 @@ always @(posedge clk, negedge rstn) tx_fifo_we_u <= i_tx_fifo_we_u; -endmodule
\ No newline at end of file +endmodule |