diff options
| author | mindchasers <privateisland@mindchasers.com> | 2019-05-01 18:16:45 -0400 |
|---|---|---|
| committer | mindchasers <privateisland@mindchasers.com> | 2019-05-01 18:16:45 -0400 |
| commit | 5723ec1a34181f1cfef9b8e870ab2e9a0362487c (patch) | |
| tree | 0dc958d5b1931934ded5d0302b2b5fedab081d2c | |
initial commit, all basic functions work on Darsena V02
60 files changed, 21043 insertions, 0 deletions
diff --git a/.gitattributes b/.gitattributes new file mode 100644 index 0000000..176a458 --- /dev/null +++ b/.gitattributes @@ -0,0 +1 @@ +* text=auto diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..f7960cc --- /dev/null +++ b/.gitignore @@ -0,0 +1,34 @@ +.project +.svproject +syn_results +archiv +impl1 +.recovery +*_tcr.dir +.*.ini +*.asd +*.asdb +*.awb +*.awc +*.bak +*.bak.* +*.ccl +*.cfg +*.cmd +*.cst +*.htm +*.html +*.log +*.rva +*.rvs +*.trc +*.rvl +*.ngd +*.ngo +*.tcl +*.svf +*.vhm +*.xml +*.zip +*.vhd +*~ @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + + Copyright [yyyy] [name of copyright owner] + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. @@ -0,0 +1,26 @@ +# privateisland + +Open Source FPGA Network Processor for Security, IoT, and Control. + +See LICENSE in this folder and reference to LICENSE in header of each Verilog source file. + +Contributors must agree to Contributor License Agreement (to be added). + +Brief Overview: + +FPGAs are amazing! + +Multi-port Etherent MAC, network switch, classifier, filter and more. + +Define the operation of your own device. Do things truly in parallel. See packets like you never thought possible. + +The initial version of this project targets a Lattice ECP5UM FPGA. + +Project is Veriog only. Test benches are Verilog / System Verilog and will be added to project soon. + +Build bit image using Lattice Diamond. Project files are based on Windws 10 at C:\projects\lattice\privateisland\ + +The FPGA architecture assumes an external micro controller / processor. The Darsena board uses an NXP K02. Test code for the K02 will be available in a separate github repo. + +Please see further documentation at https://mindchasers.com/dev/private-island and additional related documentation referenced from this page. + diff --git a/boards/darsena/darsena.sty b/boards/darsena/darsena.sty new file mode 100644 index 0000000..e45715c --- /dev/null +++ b/boards/darsena/darsena.sty @@ -0,0 +1,203 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!DOCTYPE strategy> +<Strategy version="1.0" predefined="0" description="CmdLineArgs" label="Strategy1"> + <Property name="PROP_BD_CmdLineArgs" value="" time="0"/> + <Property name="PROP_BD_EdfHardtimer" value="Enable" time="0"/> + <Property name="PROP_BD_EdfInBusNameConv" value="None" time="0"/> + <Property name="PROP_BD_EdfInLibPath" value="" time="0"/> + <Property name="PROP_BD_EdfInRemLoc" value="Off" time="0"/> + <Property name="PROP_BD_EdfMemPath" value="" time="0"/> + <Property name="PROP_BD_ParSearchPath" value="" time="0"/> + <Property name="PROP_BIT_AddressBitGen" value="Increment" time="0"/> + <Property name="PROP_BIT_AllowReadBitGen" value="Disable" time="0"/> + <Property name="PROP_BIT_ByteWideBitMirror" value="Disable" time="0"/> + <Property name="PROP_BIT_CapReadBitGen" value="Disable" time="0"/> + <Property name="PROP_BIT_ConModBitGen" value="Disable" time="0"/> + <Property name="PROP_BIT_CreateBitFile" value="True" time="0"/> + <Property name="PROP_BIT_DisRAMResBitGen" value="True" time="0"/> + <Property name="PROP_BIT_DisableUESBitgen" value="False" time="0"/> + <Property name="PROP_BIT_DonePinBitGen" value="Pullup" time="0"/> + <Property name="PROP_BIT_DoneSigBitGen" value="4" time="0"/> + <Property name="PROP_BIT_EnIOBitGen" value="TriStateDuringReConfig" time="0"/> + <Property name="PROP_BIT_EnIntOscBitGen" value="Disable" time="0"/> + <Property name="PROP_BIT_ExtClockBitGen" value="False" time="0"/> + <Property name="PROP_BIT_GSREnableBitGen" value="True" time="0"/> + <Property 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name="PROP_SYN_ResolvedMixedDrivers" value="False" time="0"/> + <Property name="PROP_SYN_UpdateCompilePtTimData" value="False" time="0"/> + <Property name="PROP_SYN_UseLPF" value="True" time="0"/> + <Property name="PROP_SYN_VHDL2008" value="False" time="0"/> + <Property name="PROP_THERMAL_DefaultFreq" value="0" time="0"/> + <Property name="PROP_TIM_MaxDelSimDes" value="" time="0"/> + <Property name="PROP_TIM_MinSpeedGrade" value="False" time="0"/> + <Property name="PROP_TIM_ModPreSimDes" value="" time="0"/> + <Property name="PROP_TIM_NegStupHldTim" value="True" time="0"/> + <Property name="PROP_TIM_TimSimGenPUR" value="True" time="0"/> + <Property name="PROP_TIM_TimSimGenX" value="False" time="0"/> + <Property name="PROP_TIM_TimSimHierSep" value="" time="0"/> + <Property name="PROP_TIM_TransportModeOfPathDelay" value="False" time="0"/> + <Property name="PROP_TIM_TrgtSpeedGrade" value="" time="0"/> + <Property name="PROP_TIM_WriteVerboseNetlist" value="False" time="0"/> +</Strategy> diff --git a/boards/darsena/darsena_v02.lpf b/boards/darsena/darsena_v02.lpf new file mode 100644 index 0000000..236d392 --- /dev/null +++ b/boards/darsena/darsena_v02.lpf @@ -0,0 +1,154 @@ +rvl_alias "pcs_pclk" "pcs_pclk"; +RVL_ALIAS "refclko" "refclko"; +RVL_ALIAS "refclko" "refclko"; +RVL_ALIAS "refclko" "refclko"; +######################################### +# versa.lpf +######################################### +FREQUENCY 140.000000 MHz ; +FREQUENCY NET "pcs_pclk" 125.000000 MHz PAR_ADJ 12.000000 ; +FREQUENCY NET "clk_10_0" 9.700000 MHz ; +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +BANK 0 VCCIO 3.3 V; +BANK 1 VCCIO 3.3 V; +BANK 2 VCCIO 3.3 V; +BANK 3 VCCIO 3.3 V; +BANK 6 VCCIO 3.3 V; +BANK 7 VCCIO 3.3 V; +BANK 8 VCCIO 3.3 V; +######################################### +# I/O Pin Assignemnts: +######################################### +// Micro +LOCATE COMP "rstn" SITE "F1" ;// GSRN ping +LOCATE COMP "i2c_scl" SITE "B1" ; +LOCATE COMP "i2c_sda" SITE "C1" ; +LOCATE COMP "fpga_spics" SITE "H1" ; +LOCATE COMP "fpga_mclk" SITE "H2" ; +LOCATE COMP "fpga_mosi" SITE "G1" ; +LOCATE COMP "fpga_miso" SITE "F2" ; +LOCATE COMP "fpga_int" SITE "E2" ; +LOCATE COMP "uart_txd" SITE "D2" ; +LOCATE COMP "uart_rxd" SITE "E1" ; +LOCATE COMP "led[0]" SITE "P20" ; +LOCATE COMP "led[1]" SITE "M20" ; +LOCATE COMP "led[2]" SITE "M19" ; +// PHY +LOCATE COMP "phy_mdc" SITE "J1" ; +// PHY0 +LOCATE COMP "phy0_resetn" SITE "K2" ; +LOCATE COMP "phy0_mdio" SITE "L2" ; +LOCATE COMP "phy0_intn" SITE "K1" ; +LOCATE COMP "phy0_gpio[0]" SITE "M1" ; +LOCATE COMP "phy0_gpio[1]" SITE "L1" ; +// PHY1 +LOCATE COMP "phy1_resetn" SITE "N20" ; +LOCATE COMP "phy1_mdio" SITE "U20" ; +LOCATE COMP "phy1_intn" SITE "U19" ; +LOCATE COMP "phy1_gpio[0]" SITE "R20" ; +LOCATE COMP "phy1_gpio[1]" SITE "P19" ; + +// Arduino Expansion +LOCATE COMP "ard_sda" SITE "A19" ; +LOCATE COMP "ard_scl" SITE "B20" ; +LOCATE COMP "ard_rxd1" SITE "A18" ; +LOCATE COMP "ard_rxd2" SITE "A14" ; +LOCATE COMP "ard_rxd3" SITE "A7" ; +LOCATE COMP "ard_txd1" SITE "A17" ; +LOCATE COMP "ard_txd2" SITE "A10" ; +LOCATE COMP "ard_txd3" SITE "A6" ; +LOCATE COMP "pe0" SITE "A5" ; +LOCATE COMP "pe1" SITE "B5" ; +LOCATE COMP "pe3" SITE "B3" ; +LOCATE COMP "pe4" SITE "A4" ; +LOCATE COMP "pe5" SITE "B4" ; +LOCATE COMP "pg5" SITE "A3" ; +LOCATE COMP "ph3" SITE "A2" ; +LOCATE COMP "ph4" SITE "B2" ; + +// PHY2 + +LOCATE COMP "phy2_mdc" SITE "C20" ; +LOCATE COMP "phy2_mdio" SITE "D19" ; +LOCATE COMP "phy2_resetn" SITE "D20" ; + +//LOCATE COMP "pa[0]" SITE "C20" ; +//LOCATE COMP "pa[1]" SITE "D19" ; +//LOCATE COMP "pa[2]" SITE "D20" ; +LOCATE COMP "pa[3]" SITE "E19" ; +LOCATE COMP "pa[4]" SITE "E20" ; +LOCATE COMP "pa[5]" SITE "F19" ; +LOCATE COMP "pa[6]" SITE "F20" ; +LOCATE COMP "pa[7]" SITE "G20" ; +LOCATE COMP "pa[8]" SITE "G19" ; +LOCATE COMP "pa[9]" SITE "H20" ; + + +// V02 +LOCATE COMP "ftdi_tck_txd" SITE "R1" ; +LOCATE COMP "ftdi_tdi_rxd" SITE "T1" ; +LOCATE COMP "fpga_jtag_e" SITE "V1" ; +LOCATE COMP "fpga_gpio" SITE "N1" ; +IOBUF PORT "uart_txd" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "uart_rxd" IO_TYPE=LVCMOS33 ; +IOBUF PORT "i2c_scl" IO_TYPE=LVCMOS33 ; +IOBUF PORT "i2c_sda" IO_TYPE=LVCMOS33 OPENDRAIN=ON DRIVE=16 SLEWRATE=FAST ; +SYSCONFIG CONFIG_IOVOLTAGE=3.3 SLAVE_SPI_PORT=DISABLE MASTER_SPI_PORT=ENABLE SLAVE_PARALLEL_PORT=DISABLE CONFIG_MODE=JTAG BACKGROUND_RECONFIG=OFF ; +VOLTAGE 1.045 V; +USERCODE BIN "00000000000000000000000000000000" ; +BLOCK JTAGPATHS ; +IOBUF PORT "rstn" IO_TYPE=LVCMOS33 ; +IOBUF PORT "phy2_mdc" IO_TYPE=LVCMOS33 ; +IOBUF PORT "fpga_int" IO_TYPE=LVCMOS33 ; +IOBUF PORT "phy2_resetn" IO_TYPE=LVCMOS33 ; +IOBUF PORT "phy0_resetn" IO_TYPE=LVCMOS33 ; +IOBUF PORT "phy1_resetn" IO_TYPE=LVCMOS33 ; +IOBUF PORT "led[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "led[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "led[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "phy2_mdio" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "phy0_mdio" IO_TYPE=LVCMOS33 PULLMODE=UP OPENDRAIN=OFF ; +IOBUF PORT "phy1_mdio" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "ard_sda" IO_TYPE=LVCMOS33 ; +IOBUF PORT "ard_scl" IO_TYPE=LVCMOS33 ; +IOBUF PORT "ard_rxd1" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "ard_rxd2" IO_TYPE=LVCMOS33 ; +IOBUF PORT "ard_rxd3" IO_TYPE=LVCMOS33 ; +IOBUF PORT "ard_scl" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "ard_sda" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "ard_txd1" IO_TYPE=LVCMOS33 ; +IOBUF PORT "ard_txd2" IO_TYPE=LVCMOS33 ; +IOBUF PORT "ard_txd3" IO_TYPE=LVCMOS33 ; +IOBUF PORT "phy_mdc" IO_TYPE=LVCMOS33 ; +IOBUF PORT "fpga_miso" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "pe0" IO_TYPE=LVCMOS33 ; +IOBUF PORT "pe1" IO_TYPE=LVCMOS33 ; +IOBUF PORT "pe3" IO_TYPE=LVCMOS33 ; +IOBUF PORT "pe4" IO_TYPE=LVCMOS33 ; +IOBUF PORT "pe5" IO_TYPE=LVCMOS33 ; +IOBUF PORT "pg5" IO_TYPE=LVCMOS33 ; +IOBUF PORT "ph3" IO_TYPE=LVCMOS33 ; +IOBUF PORT "ph4" IO_TYPE=LVCMOS33 ; + +//IOBUF PORT "pa[0]" IO_TYPE=LVCMOS33 ; +//IOBUF PORT "pa[1]" IO_TYPE=LVCMOS33 ; +//IOBUF PORT "pa[2]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "pa[3]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "pa[4]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "pa[5]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "pa[6]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "pa[7]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "pa[8]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "pa[9]" IO_TYPE=LVCMOS33 ; + +# V02 +IOBUF PORT "ftdi_tck_txd" IO_TYPE=LVCMOS33 ; +IOBUF PORT "ftdi_tdi_rxd" IO_TYPE=LVCMOS33 ; +IOBUF PORT "fpga_jtag_e" IO_TYPE=LVCMOS33 ; +IOBUF PORT "fpga_gpio" IO_TYPE=LVCMOS33 ; +IOBUF PORT "phy1_intn" IO_TYPE=LVCMOS33 ; +IOBUF PORT "phy0_intn" IO_TYPE=LVCMOS33 ; +IOBUF PORT "fpga_mclk" IO_TYPE=LVCMOS33 ; +IOBUF PORT "fpga_spics" IO_TYPE=LVCMOS33 ; +IOBUF PORT "fpga_mosi" IO_TYPE=LVCMOS33 ; diff --git a/clarity/README b/clarity/README new file mode 100644 index 0000000..9d47733 --- /dev/null +++ b/clarity/README @@ -0,0 +1,3 @@ +This folder is generated by Clarity with some hand tweaks + +See https://mindchasers.com/dev/fpga-pcs-arch and forum posts related to PCS diff --git a/clarity/pcs/pcs.sbx b/clarity/pcs/pcs.sbx new file mode 100644 index 0000000..6941e9c --- /dev/null +++ b/clarity/pcs/pcs.sbx @@ -0,0 +1,7844 @@ +<!DOCTYPE pcs> +<lattice:project> + <spirit:component> + <spirit:vendor>LATTICE</spirit:vendor> + <spirit:library>LOCAL</spirit:library> + <spirit:name>pcs</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:fileSets> + <spirit:fileset> + <spirit:name>Diamond_Synthesis</spirit:name> + <spirit:group>synthesis</spirit:group> + <spirit:file> + <spirit:name>./pcs.v</spirit:name> + <spirit:fileType>verilogSource</spirit:fileType> + </spirit:file> + </spirit:fileset> + <spirit:fileset> + <spirit:name>Diamond_Simulation</spirit:name> + <spirit:group>simulation</spirit:group> + <spirit:file> + <spirit:name>./pcs.v</spirit:name> + <spirit:fileType>verilogSource</spirit:fileType> + </spirit:file> + </spirit:fileset> + </spirit:fileSets> + <spirit:componentGenerators/> + <spirit:model> + <spirit:views/> + <spirit:ports> + <spirit:port> + <spirit:name>refclk0_refclkn</spirit:name> + <spirit:displayName>refclk0_refclkn</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + <spirit:vendorExtensions> + <lattice:attributes> + <lattice:attribute lattice:name="exportFrom">refclk0.refclkn</lattice:attribute> + </lattice:attributes> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>refclk0_refclkp</spirit:name> + <spirit:displayName>refclk0_refclkp</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + <spirit:vendorExtensions> + <lattice:attributes> + <lattice:attribute lattice:name="exportFrom">refclk0.refclkp</lattice:attribute> + </lattice:attributes> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>sgmii0_ctc_del_s</spirit:name> + <spirit:displayName>sgmii0_ctc_del_s</spirit:displayName> + <spirit:wire> + <spirit:direction>out</spirit:direction> + </spirit:wire> + <spirit:vendorExtensions> + <lattice:attributes> + <lattice:attribute lattice:name="exportFrom">sgmii0.ctc_del_s</lattice:attribute> + </lattice:attributes> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>sgmii0_ctc_ins_s</spirit:name> + <spirit:displayName>sgmii0_ctc_ins_s</spirit:displayName> + <spirit:wire> + <spirit:direction>out</spirit:direction> + </spirit:wire> + <spirit:vendorExtensions> + <lattice:attributes> + <lattice:attribute lattice:name="exportFrom">sgmii0.ctc_ins_s</lattice:attribute> + </lattice:attributes> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>sgmii0_ctc_orun_s</spirit:name> + <spirit:displayName>sgmii0_ctc_orun_s</spirit:displayName> + <spirit:wire> + <spirit:direction>out</spirit:direction> + </spirit:wire> + <spirit:vendorExtensions> + <lattice:attributes> + <lattice:attribute lattice:name="exportFrom">sgmii0.ctc_orun_s</lattice:attribute> + </lattice:attributes> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>sgmii0_ctc_urun_s</spirit:name> + <spirit:displayName>sgmii0_ctc_urun_s</spirit:displayName> + <spirit:wire> + <spirit:direction>out</spirit:direction> + </spirit:wire> + <spirit:vendorExtensions> + <lattice:attributes> + <lattice:attribute lattice:name="exportFrom">sgmii0.ctc_urun_s</lattice:attribute> + </lattice:attributes> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>sgmii0_cyawstn</spirit:name> + <spirit:displayName>sgmii0_cyawstn</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + <spirit:vendorExtensions> + <lattice:attributes> + <lattice:attribute lattice:name="exportFrom">sgmii0.cyawstn</lattice:attribute> + </lattice:attributes> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>sgmii0_hdinn</spirit:name> + <spirit:displayName>sgmii0_hdinn</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + <spirit:vendorExtensions> + <lattice:attributes> + <lattice:attribute lattice:name="exportFrom">sgmii0.hdinn</lattice:attribute> + </lattice:attributes> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>sgmii0_hdinp</spirit:name> + <spirit:displayName>sgmii0_hdinp</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + <spirit:vendorExtensions> + <lattice:attributes> + <lattice:attribute lattice:name="exportFrom">sgmii0.hdinp</lattice:attribute> + </lattice:attributes> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>sgmii0_hdoutn</spirit:name> + <spirit:displayName>sgmii0_hdoutn</spirit:displayName> + <spirit:wire> + <spirit:direction>out</spirit:direction> + </spirit:wire> + <spirit:vendorExtensions> + <lattice:attributes> + <lattice:attribute lattice:name="exportFrom">sgmii0.hdoutn</lattice:attribute> + </lattice:attributes> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>sgmii0_hdoutp</spirit:name> + <spirit:displayName>sgmii0_hdoutp</spirit:displayName> + <spirit:wire> + <spirit:direction>out</spirit:direction> + </spirit:wire> + <spirit:vendorExtensions> + <lattice:attributes> + <lattice:attribute lattice:name="exportFrom">sgmii0.hdoutp</lattice:attribute> + </lattice:attributes> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>sgmii0_lsm_status_s</spirit:name> + <spirit:displayName>sgmii0_lsm_status_s</spirit:displayName> + <spirit:wire> + <spirit:direction>out</spirit:direction> + </spirit:wire> + <spirit:vendorExtensions> + <lattice:attributes> + <lattice:attribute lattice:name="exportFrom">sgmii0.lsm_status_s</lattice:attribute> + </lattice:attributes> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>sgmii0_pll_lol</spirit:name> + <spirit:displayName>sgmii0_pll_lol</spirit:displayName> + <spirit:wire> + <spirit:direction>out</spirit:direction> + </spirit:wire> + <spirit:vendorExtensions> + <lattice:attributes> + <lattice:attribute lattice:name="exportFrom">sgmii0.pll_lol</lattice:attribute> + </lattice:attributes> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>sgmii0_rst_dual_c</spirit:name> + <spirit:displayName>sgmii0_rst_dual_c</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + <spirit:vendorExtensions> + <lattice:attributes> + <lattice:attribute lattice:name="exportFrom">sgmii0.rst_dual_c</lattice:attribute> + </lattice:attributes> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>sgmii0_rx_cdr_lol_s</spirit:name> + <spirit:displayName>sgmii0_rx_cdr_lol_s</spirit:displayName> + <spirit:wire> + <spirit:direction>out</spirit:direction> + </spirit:wire> + <spirit:vendorExtensions> + <lattice:attributes> + <lattice:attribute lattice:name="exportFrom">sgmii0.rx_cdr_lol_s</lattice:attribute> + </lattice:attributes> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>sgmii0_rx_los_low_s</spirit:name> + <spirit:displayName>sgmii0_rx_los_low_s</spirit:displayName> + <spirit:wire> + <spirit:direction>out</spirit:direction> + </spirit:wire> + <spirit:vendorExtensions> + <lattice:attributes> + <lattice:attribute lattice:name="exportFrom">sgmii0.rx_los_low_s</lattice:attribute> + </lattice:attributes> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>sgmii0_rx_pcs_rst_c</spirit:name> + <spirit:displayName>sgmii0_rx_pcs_rst_c</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + <spirit:vendorExtensions> + <lattice:attributes> + <lattice:attribute lattice:name="exportFrom">sgmii0.rx_pcs_rst_c</lattice:attribute> + </lattice:attributes> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>sgmii0_rx_pwrup_c</spirit:name> + <spirit:displayName>sgmii0_rx_pwrup_c</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + <spirit:vendorExtensions> + <lattice:attributes> + <lattice:attribute lattice:name="exportFrom">sgmii0.rx_pwrup_c</lattice:attribute> + </lattice:attributes> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>sgmii0_rx_serdes_rst_c</spirit:name> + <spirit:displayName>sgmii0_rx_serdes_rst_c</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + <spirit:vendorExtensions> + <lattice:attributes> + <lattice:attribute lattice:name="exportFrom">sgmii0.rx_serdes_rst_c</lattice:attribute> + </lattice:attributes> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>sgmii0_sci_en</spirit:name> + <spirit:displayName>sgmii0_sci_en</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + <spirit:vendorExtensions> + <lattice:attributes> + <lattice:attribute lattice:name="exportFrom">sgmii0.sci_en</lattice:attribute> + </lattice:attributes> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>sgmii0_sci_en_dual</spirit:name> + <spirit:displayName>sgmii0_sci_en_dual</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + <spirit:vendorExtensions> + <lattice:attributes> + <lattice:attribute lattice:name="exportFrom">sgmii0.sci_en_dual</lattice:attribute> + </lattice:attributes> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>sgmii0_sci_int</spirit:name> + <spirit:displayName>sgmii0_sci_int</spirit:displayName> + <spirit:wire> + <spirit:direction>out</spirit:direction> + </spirit:wire> + <spirit:vendorExtensions> + <lattice:attributes> + <lattice:attribute lattice:name="exportFrom">sgmii0.sci_int</lattice:attribute> + </lattice:attributes> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>sgmii0_sci_rd</spirit:name> + <spirit:displayName>sgmii0_sci_rd</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + <spirit:vendorExtensions> + <lattice:attributes> + <lattice:attribute lattice:name="exportFrom">sgmii0.sci_rd</lattice:attribute> + </lattice:attributes> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>sgmii0_sci_sel</spirit:name> + <spirit:displayName>sgmii0_sci_sel</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + <spirit:vendorExtensions> + <lattice:attributes> + <lattice:attribute lattice:name="exportFrom">sgmii0.sci_sel</lattice:attribute> + </lattice:attributes> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>sgmii0_sci_sel_dual</spirit:name> + <spirit:displayName>sgmii0_sci_sel_dual</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + <spirit:vendorExtensions> + <lattice:attributes> + <lattice:attribute lattice:name="exportFrom">sgmii0.sci_sel_dual</lattice:attribute> + </lattice:attributes> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>sgmii0_sci_wrn</spirit:name> + <spirit:displayName>sgmii0_sci_wrn</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + <spirit:vendorExtensions> + <lattice:attributes> + <lattice:attribute lattice:name="exportFrom">sgmii0.sci_wrn</lattice:attribute> + </lattice:attributes> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>sgmii0_serdes_rst_dual_c</spirit:name> + <spirit:displayName>sgmii0_serdes_rst_dual_c</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + <spirit:vendorExtensions> + <lattice:attributes> + <lattice:attribute lattice:name="exportFrom">sgmii0.serdes_rst_dual_c</lattice:attribute> + </lattice:attributes> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>sgmii0_signal_detect_c</spirit:name> + <spirit:displayName>sgmii0_signal_detect_c</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + <spirit:vendorExtensions> + <lattice:attributes> + <lattice:attribute lattice:name="exportFrom">sgmii0.signal_detect_c</lattice:attribute> + </lattice:attributes> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>sgmii0_tx_pclk</spirit:name> + <spirit:displayName>sgmii0_tx_pclk</spirit:displayName> + <spirit:wire> + <spirit:direction>out</spirit:direction> + </spirit:wire> + <spirit:vendorExtensions> + <lattice:attributes> + <lattice:attribute lattice:name="exportFrom">sgmii0.tx_pclk</lattice:attribute> + </lattice:attributes> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>sgmii0_tx_pcs_rst_c</spirit:name> + <spirit:displayName>sgmii0_tx_pcs_rst_c</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + 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<lattice:lpckey>IO_TYPE</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">GbE</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>LEQ</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>LOOPBACK</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>LOSPORT</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>NUM_CHS</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>Order</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Big Endian [MSB:LSB]</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>PPORT_RX_RDY</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>PPORT_TX_RDY</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>PROTOCOL</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">GbE</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>PWAIT_RX_RDY</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">3000</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>PWAIT_TX_RDY</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">3000</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RCSRC</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>REFCLK_RATE</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">50.0000</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RSTSEQSEL</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RX8B10B</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXCOMMAA</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">1010000011</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXCOMMAB</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">0101111100</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXCOMMAM</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">1111111111</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXCOUPLING</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">AC</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXCTC</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXCTCBYTEN</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">0 00H</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXCTCBYTEN1</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">0 00H</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXCTCBYTEN2</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">1 BCH</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXCTCBYTEN3</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">0 50H</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXCTCMATCHPATTERN</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">M2-S2</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXDIFFTERM</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">50 ohms</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXFIFO_ENABLE</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXINVPOL</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Invert</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXLDR</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Off</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXLOSTHRESHOLD</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">4</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXLSM</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXSC</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">K28P5</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXWA</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Barrel Shift</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RX_DATA_WIDTH</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">8/10-Bit</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RX_FICLK_RATE</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">125.0000</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RX_LINE_RATE</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">1.2500</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RX_RATE_DIV</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Full Rate</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>SCIPORT</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>SOFTLOL</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>TX8B10B</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>TXAMPLITUDE</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">400</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>TXDEPOST</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>TXDEPRE</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>TXDIFFTERM</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">50 ohms</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>TXFIFO_ENABLE</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>TXINVPOL</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Invert</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>TXLDR</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Off</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>TXPLLLOLTHRESHOLD</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>TXPLLMULT</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">25X</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>TX_DATA_WIDTH</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">8/10-Bit</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>TX_FICLK_RATE</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">125.0000</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>TX_LINE_RATE</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">1.2500</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>TX_MAX_RATE</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">1.25</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>TX_RATE_DIV</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Full Rate</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>VHDL</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>Verilog</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcsection lattice:name="FilesGenerated"/> + <lattice:lpcentry> + <lattice:lpckey>sgmii0.pp</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">pp</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>sgmii0.sym</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">sym</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>sgmii0.tft</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">tft</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>sgmii0.txt</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">pcs_module</lattice:lpcvalue> + </lattice:lpcentry> + </lattice:lpc> + <lattice:groups> + <lattice:group> + <lattice:name>DCUCHANNEL</lattice:name> + <lattice:category>1</lattice:category> + <lattice:attributes> + <lattice:attribute lattice:name="GroupDrag">true</lattice:attribute> + <lattice:attribute lattice:name="GroupHide">false</lattice:attribute> + <lattice:attribute lattice:name="GroupType">DCUCHANNEL</lattice:attribute> + </lattice:attributes> + <lattice:elementref>Lane0</lattice:elementref> + </lattice:group> + </lattice:groups> + </spirit:vendorExtensions> + </spirit:componentRef> + </spirit:componentInstance> + <spirit:componentInstance> + <spirit:instanceName>sgmii1</spirit:instanceName> + <spirit:componentRef> + <spirit:vendor>Lattice Semiconductor Corporation</spirit:vendor> + <spirit:library>LEGACY</spirit:library> + <spirit:name>PCS</spirit:name> + <spirit:version>8.2</spirit:version> + <spirit:fileSets> + <spirit:fileset> + <spirit:name>Diamond_Simulation</spirit:name> + <spirit:group>simulation</spirit:group> + <spirit:file> + <spirit:name>./sgmii1/sgmii1.v</spirit:name> + <spirit:fileType>verilogSource</spirit:fileType> + </spirit:file> + </spirit:fileset> + <spirit:fileset> + <spirit:name>Diamond_Synthesis</spirit:name> + <spirit:group>synthesis</spirit:group> + <spirit:file> + <spirit:name>./sgmii1/sgmii1.v</spirit:name> + <spirit:fileType>verilogSource</spirit:fileType> + </spirit:file> + </spirit:fileset> + </spirit:fileSets> + <spirit:componentGenerators> + <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance"> + <spirit:name>Configuration</spirit:name> + <spirit:apiType>none</spirit:apiType> + <spirit:generatorExe>${sbp_path}/${instance}/generate_core.tcl</spirit:generatorExe> + <spirit:group>CONFIG</spirit:group> + </spirit:componentGenerator> + <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance"> + <spirit:name>CreateNGD</spirit:name> + <spirit:apiType>none</spirit:apiType> + <spirit:generatorExe>${sbp_path}/${instance}/generate_ngd.tcl</spirit:generatorExe> + <spirit:group>CONFIG</spirit:group> + </spirit:componentGenerator> + <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance"> + <spirit:name>Generation</spirit:name> + <spirit:apiType>none</spirit:apiType> + <spirit:generatorExe>${sbp_path}/${instance}/generate_core.tcl</spirit:generatorExe> + <spirit:group>GENERATE</spirit:group> + </spirit:componentGenerator> + </spirit:componentGenerators> + <spirit:model> + <spirit:views/> + <spirit:ports> + <spirit:port> + <spirit:name>ctc_del_s</spirit:name> + <spirit:displayName>ctc_del_s</spirit:displayName> + <spirit:wire> + <spirit:direction>out</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>ctc_ins_s</spirit:name> + <spirit:displayName>ctc_ins_s</spirit:displayName> + <spirit:wire> + <spirit:direction>out</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>ctc_orun_s</spirit:name> + <spirit:displayName>ctc_orun_s</spirit:displayName> + <spirit:wire> + <spirit:direction>out</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>ctc_urun_s</spirit:name> + <spirit:displayName>ctc_urun_s</spirit:displayName> + <spirit:wire> + <spirit:direction>out</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>cyawstn</spirit:name> + <spirit:displayName>cyawstn</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>hdinn</spirit:name> + <spirit:displayName>hdinn</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + <spirit:vendorExtensions> + <lattice:attributes> + <lattice:attribute lattice:name="PadPin">true</lattice:attribute> + </lattice:attributes> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>hdinp</spirit:name> + <spirit:displayName>hdinp</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + <spirit:vendorExtensions> + <lattice:attributes> + <lattice:attribute lattice:name="PadPin">true</lattice:attribute> + </lattice:attributes> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>hdoutn</spirit:name> + <spirit:displayName>hdoutn</spirit:displayName> + <spirit:wire> + <spirit:direction>out</spirit:direction> + </spirit:wire> + <spirit:vendorExtensions> + <lattice:attributes> + <lattice:attribute lattice:name="PadPin">true</lattice:attribute> + </lattice:attributes> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>hdoutp</spirit:name> + <spirit:displayName>hdoutp</spirit:displayName> + <spirit:wire> + <spirit:direction>out</spirit:direction> + </spirit:wire> + <spirit:vendorExtensions> + <lattice:attributes> + <lattice:attribute lattice:name="PadPin">true</lattice:attribute> + </lattice:attributes> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>lsm_status_s</spirit:name> + <spirit:displayName>lsm_status_s</spirit:displayName> + <spirit:wire> + <spirit:direction>out</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>pll_refclki</spirit:name> + <spirit:displayName>pll_refclki</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>rst_dual_c</spirit:name> + <spirit:displayName>rst_dual_c</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>rx_cdr_lol_s</spirit:name> + <spirit:displayName>rx_cdr_lol_s</spirit:displayName> + <spirit:wire> + <spirit:direction>out</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>rx_los_low_s</spirit:name> + <spirit:displayName>rx_los_low_s</spirit:displayName> + <spirit:wire> + <spirit:direction>out</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>rx_pcs_rst_c</spirit:name> + <spirit:displayName>rx_pcs_rst_c</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>rx_pwrup_c</spirit:name> + <spirit:displayName>rx_pwrup_c</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>rx_serdes_rst_c</spirit:name> + <spirit:displayName>rx_serdes_rst_c</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>rxrefclk</spirit:name> + <spirit:displayName>rxrefclk</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>sci_en</spirit:name> + <spirit:displayName>sci_en</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>sci_en_dual</spirit:name> + <spirit:displayName>sci_en_dual</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>sci_int</spirit:name> + <spirit:displayName>sci_int</spirit:displayName> + <spirit:wire> + <spirit:direction>out</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>sci_rd</spirit:name> + <spirit:displayName>sci_rd</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>sci_sel</spirit:name> + <spirit:displayName>sci_sel</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>sci_sel_dual</spirit:name> + <spirit:displayName>sci_sel_dual</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>sci_wrn</spirit:name> + <spirit:displayName>sci_wrn</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>serdes_pdb</spirit:name> + <spirit:displayName>serdes_pdb</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>serdes_rst_dual_c</spirit:name> + <spirit:displayName>serdes_rst_dual_c</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>signal_detect_c</spirit:name> + <spirit:displayName>signal_detect_c</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>tx_pclk</spirit:name> + <spirit:displayName>tx_pclk</spirit:displayName> + <spirit:wire> + <spirit:direction>out</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>tx_pcs_rst_c</spirit:name> + <spirit:displayName>tx_pcs_rst_c</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>tx_pwrup_c</spirit:name> + <spirit:displayName>tx_pwrup_c</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>tx_serdes_rst_c</spirit:name> + <spirit:displayName>tx_serdes_rst_c</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>txi_clk</spirit:name> + <spirit:displayName>txi_clk</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>rx_cv_err</spirit:name> + <spirit:displayName>rx_cv_err</spirit:displayName> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>0</spirit:right> + </spirit:vector> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>rx_disp_err</spirit:name> + <spirit:displayName>rx_disp_err</spirit:displayName> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>0</spirit:right> + </spirit:vector> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>rx_k</spirit:name> + <spirit:displayName>rx_k</spirit:displayName> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>0</spirit:right> + </spirit:vector> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>rxdata</spirit:name> + <spirit:displayName>rxdata</spirit:displayName> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>7</spirit:left> + <spirit:right>0</spirit:right> + </spirit:vector> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>sci_addr</spirit:name> + <spirit:displayName>sci_addr</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>5</spirit:left> + <spirit:right>0</spirit:right> + </spirit:vector> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>sci_rddata</spirit:name> + <spirit:displayName>sci_rddata</spirit:displayName> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>7</spirit:left> + <spirit:right>0</spirit:right> + </spirit:vector> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>sci_wrdata</spirit:name> + <spirit:displayName>sci_wrdata</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>7</spirit:left> + <spirit:right>0</spirit:right> + </spirit:vector> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>tx_disp_correct</spirit:name> + <spirit:displayName>tx_disp_correct</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>0</spirit:right> + </spirit:vector> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>tx_k</spirit:name> + <spirit:displayName>tx_k</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>0</spirit:right> + </spirit:vector> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>txdata</spirit:name> + <spirit:displayName>txdata</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>7</spirit:left> + <spirit:right>0</spirit:right> + </spirit:vector> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>xmit</spirit:name> + <spirit:displayName>xmit</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>0</spirit:right> + </spirit:vector> + </spirit:wire> + </spirit:port> + </spirit:ports> + </spirit:model> + <spirit:vendorExtensions> + <lattice:synthesis>synplify</lattice:synthesis> + <lattice:modified>2019-03-15.18:48:22</lattice:modified> + <lattice:attributes> + <lattice:attribute lattice:name="AddComponent">false</lattice:attribute> + <lattice:attribute lattice:name="BBox">false</lattice:attribute> + <lattice:attribute lattice:name="Change4to5">false</lattice:attribute> + <lattice:attribute lattice:name="ChangeConfig">false</lattice:attribute> + <lattice:attribute lattice:name="ChangeConnect">false</lattice:attribute> + <lattice:attribute lattice:name="ChangeDevice">false</lattice:attribute> + <lattice:attribute lattice:name="ChangeLocate">false</lattice:attribute> + <lattice:attribute lattice:name="ChangePack">false</lattice:attribute> + <lattice:attribute lattice:name="ChangePart">false</lattice:attribute> + <lattice:attribute lattice:name="ChangeSynthesis">false</lattice:attribute> + <lattice:attribute lattice:name="CoreType">LPM</lattice:attribute> + <lattice:attribute lattice:name="DCU_RXREFCLK">DCU0_EXTREF</lattice:attribute> + <lattice:attribute lattice:name="DCU_TXREFCLK">DCU0_EXTREF</lattice:attribute> + <lattice:attribute lattice:name="Migrate">false</lattice:attribute> + <lattice:attribute lattice:name="RemovedComponent">false</lattice:attribute> + </lattice:attributes> + <lattice:elements> + <lattice:element> + <lattice:name>Lane0</lattice:name> + <lattice:type>DCUCHANNEL</lattice:type> + <lattice:attributes> + <lattice:attribute lattice:name="ElementDrag">true</lattice:attribute> + <lattice:attribute lattice:name="ElementHide">false</lattice:attribute> + <lattice:attribute lattice:name="ElementType">DCUCHANNEL</lattice:attribute> + <lattice:attribute lattice:name="Locate">6</lattice:attribute> + </lattice:attributes> + </lattice:element> + </lattice:elements> + <lattice:lpc> + <lattice:lpcsection lattice:name="Device"/> + <lattice:lpcentry> + <lattice:lpckey>Family</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">ecp5um</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>OperatingCondition</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">COM</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>Package</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">CABGA381</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>PartName</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">LFE5UM-45F-8BG381C</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>PartType</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">LFE5UM-45F</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>SpeedGrade</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">8</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>Status</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">P</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcsection lattice:name="IP"/> + <lattice:lpcentry> + <lattice:lpckey>CoreName</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">PCS</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>CoreRevision</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">8.2</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>CoreStatus</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Demo</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>CoreType</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">LPM</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>Date</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">11/18/2018</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>ModuleName</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">sgmii1</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>ParameterFileVersion</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">1.0</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>SourceFormat</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">verilog</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>Time</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">17:42:50</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>VendorName</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Lattice Semiconductor Corporation</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcsection lattice:name="Parameters"/> + <lattice:lpcentry> + <lattice:lpckey>;ACHARA</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">0 00H</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>;ACHARB</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">0 00H</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>;ACHARM</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">0 00H</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>;RXMCAENABLE</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>CDRLOLACTION</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Full Recalibration</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>CDRLOLRANGE</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>CDR_MAX_RATE</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">1.25</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>CDR_MULT</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">25X</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>CDR_REF_RATE</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">50.0000</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>CH_MODE</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Rx and Tx</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>Destination</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Synplicity</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>EDIF</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>Expression</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">BusA(0 to 7)</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>IO</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>IO_TYPE</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">GbE</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>LEQ</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>LOOPBACK</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>LOSPORT</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>NUM_CHS</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>Order</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Big Endian [MSB:LSB]</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>PPORT_RX_RDY</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>PPORT_TX_RDY</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>PROTOCOL</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">GbE</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>PWAIT_RX_RDY</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">3000</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>PWAIT_TX_RDY</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">3000</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RCSRC</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>REFCLK_RATE</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">50.0000</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RSTSEQSEL</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RX8B10B</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXCOMMAA</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">1010000011</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXCOMMAB</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">0101111100</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXCOMMAM</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">1111111111</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXCOUPLING</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">AC</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXCTC</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXCTCBYTEN</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">0 00H</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXCTCBYTEN1</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">0 00H</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXCTCBYTEN2</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">1 BCH</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXCTCBYTEN3</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">0 50H</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXCTCMATCHPATTERN</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">M2-S2</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXDIFFTERM</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">50 ohms</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXFIFO_ENABLE</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXINVPOL</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Invert</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXLDR</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Off</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXLOSTHRESHOLD</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">4</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXLSM</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXSC</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">K28P5</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXWA</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Barrel Shift</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RX_DATA_WIDTH</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">8/10-Bit</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RX_FICLK_RATE</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">125.0000</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RX_LINE_RATE</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">1.2500</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RX_RATE_DIV</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Full Rate</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>SCIPORT</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>SOFTLOL</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>TX8B10B</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>TXAMPLITUDE</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">400</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>TXDEPOST</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>TXDEPRE</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>TXDIFFTERM</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">50 ohms</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>TXFIFO_ENABLE</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>TXINVPOL</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Invert</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>TXLDR</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Off</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>TXPLLLOLTHRESHOLD</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>TXPLLMULT</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">25X</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>TX_DATA_WIDTH</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">8/10-Bit</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>TX_FICLK_RATE</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">125.0000</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>TX_LINE_RATE</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">1.2500</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>TX_MAX_RATE</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">1.25</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>TX_RATE_DIV</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Full Rate</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>VHDL</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>Verilog</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcsection lattice:name="FilesGenerated"/> + <lattice:lpcentry> + <lattice:lpckey>sgmii1.pp</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">pp</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>sgmii1.sym</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">sym</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>sgmii1.tft</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">tft</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>sgmii1.txt</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">pcs_module</lattice:lpcvalue> + </lattice:lpcentry> + </lattice:lpc> + <lattice:groups> + <lattice:group> + <lattice:name>DCUCHANNEL</lattice:name> + <lattice:category>1</lattice:category> + <lattice:attributes> + <lattice:attribute lattice:name="GroupDrag">true</lattice:attribute> + <lattice:attribute lattice:name="GroupHide">false</lattice:attribute> + <lattice:attribute lattice:name="GroupType">DCUCHANNEL</lattice:attribute> + </lattice:attributes> + <lattice:elementref>Lane0</lattice:elementref> + </lattice:group> + </lattice:groups> + </spirit:vendorExtensions> + </spirit:componentRef> + </spirit:componentInstance> + <spirit:componentInstance> + <spirit:instanceName>sgmii2</spirit:instanceName> + <spirit:componentRef> + <spirit:vendor>Lattice Semiconductor Corporation</spirit:vendor> + <spirit:library>LEGACY</spirit:library> + <spirit:name>PCS</spirit:name> + <spirit:version>8.2</spirit:version> + <spirit:fileSets> + <spirit:fileset> + <spirit:name>Diamond_Simulation</spirit:name> + <spirit:group>simulation</spirit:group> + <spirit:file> + <spirit:name>./sgmii2/sgmii2.v</spirit:name> + <spirit:fileType>verilogSource</spirit:fileType> + </spirit:file> + <spirit:file> + <spirit:name>./sgmii2/sgmii2_softlogic.v</spirit:name> + <spirit:fileType>verilogSource</spirit:fileType> + </spirit:file> + </spirit:fileset> + <spirit:fileset> + <spirit:name>Diamond_Synthesis</spirit:name> + <spirit:group>synthesis</spirit:group> + <spirit:file> + <spirit:name>./sgmii2/sgmii2.v</spirit:name> + <spirit:fileType>verilogSource</spirit:fileType> + </spirit:file> + <spirit:file> + <spirit:name>./sgmii2/sgmii2_softlogic.v</spirit:name> + <spirit:fileType>verilogSource</spirit:fileType> + </spirit:file> + </spirit:fileset> + </spirit:fileSets> + <spirit:componentGenerators> + <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance"> + <spirit:name>Configuration</spirit:name> + <spirit:apiType>none</spirit:apiType> + <spirit:generatorExe>${sbp_path}/${instance}/generate_core.tcl</spirit:generatorExe> + <spirit:group>CONFIG</spirit:group> + </spirit:componentGenerator> + <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance"> + <spirit:name>CreateNGD</spirit:name> + <spirit:apiType>none</spirit:apiType> + <spirit:generatorExe>${sbp_path}/${instance}/generate_ngd.tcl</spirit:generatorExe> + <spirit:group>CONFIG</spirit:group> + </spirit:componentGenerator> + <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance"> + <spirit:name>Generation</spirit:name> + <spirit:apiType>none</spirit:apiType> + <spirit:generatorExe>${sbp_path}/${instance}/generate_core.tcl</spirit:generatorExe> + <spirit:group>GENERATE</spirit:group> + </spirit:componentGenerator> + </spirit:componentGenerators> + <spirit:model> + <spirit:views/> + <spirit:ports> + <spirit:port> + <spirit:name>ctc_del_s</spirit:name> + <spirit:displayName>ctc_del_s</spirit:displayName> + <spirit:wire> + <spirit:direction>out</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>ctc_ins_s</spirit:name> + <spirit:displayName>ctc_ins_s</spirit:displayName> + <spirit:wire> + <spirit:direction>out</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>ctc_orun_s</spirit:name> + <spirit:displayName>ctc_orun_s</spirit:displayName> + <spirit:wire> + <spirit:direction>out</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>ctc_urun_s</spirit:name> + <spirit:displayName>ctc_urun_s</spirit:displayName> + <spirit:wire> + <spirit:direction>out</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>cyawstn</spirit:name> + <spirit:displayName>cyawstn</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>hdinn</spirit:name> + <spirit:displayName>hdinn</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + <spirit:vendorExtensions> + <lattice:attributes> + <lattice:attribute lattice:name="PadPin">true</lattice:attribute> + </lattice:attributes> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>hdinp</spirit:name> + <spirit:displayName>hdinp</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + <spirit:vendorExtensions> + <lattice:attributes> + <lattice:attribute lattice:name="PadPin">true</lattice:attribute> + </lattice:attributes> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>hdoutn</spirit:name> + <spirit:displayName>hdoutn</spirit:displayName> + <spirit:wire> + <spirit:direction>out</spirit:direction> + </spirit:wire> + <spirit:vendorExtensions> + <lattice:attributes> + <lattice:attribute lattice:name="PadPin">true</lattice:attribute> + </lattice:attributes> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>hdoutp</spirit:name> + <spirit:displayName>hdoutp</spirit:displayName> + <spirit:wire> + <spirit:direction>out</spirit:direction> + </spirit:wire> + <spirit:vendorExtensions> + <lattice:attributes> + <lattice:attribute lattice:name="PadPin">true</lattice:attribute> + </lattice:attributes> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>lsm_status_s</spirit:name> + <spirit:displayName>lsm_status_s</spirit:displayName> + <spirit:wire> + <spirit:direction>out</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>pll_lol</spirit:name> + <spirit:displayName>pll_lol</spirit:displayName> + <spirit:wire> + <spirit:direction>out</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>pll_refclki</spirit:name> + <spirit:displayName>pll_refclki</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>rst_dual_c</spirit:name> + <spirit:displayName>rst_dual_c</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>rx_cdr_lol_s</spirit:name> + <spirit:displayName>rx_cdr_lol_s</spirit:displayName> + <spirit:wire> + <spirit:direction>out</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>rx_los_low_s</spirit:name> + <spirit:displayName>rx_los_low_s</spirit:displayName> + <spirit:wire> + <spirit:direction>out</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>rx_pcs_rst_c</spirit:name> + <spirit:displayName>rx_pcs_rst_c</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>rx_pwrup_c</spirit:name> + <spirit:displayName>rx_pwrup_c</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>rx_serdes_rst_c</spirit:name> + <spirit:displayName>rx_serdes_rst_c</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>rxrefclk</spirit:name> + <spirit:displayName>rxrefclk</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>sci_en</spirit:name> + <spirit:displayName>sci_en</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>sci_en_dual</spirit:name> + <spirit:displayName>sci_en_dual</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>sci_int</spirit:name> + <spirit:displayName>sci_int</spirit:displayName> + <spirit:wire> + <spirit:direction>out</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>sci_rd</spirit:name> + <spirit:displayName>sci_rd</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>sci_sel</spirit:name> + <spirit:displayName>sci_sel</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>sci_sel_dual</spirit:name> + <spirit:displayName>sci_sel_dual</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>sci_wrn</spirit:name> + <spirit:displayName>sci_wrn</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>serdes_pdb</spirit:name> + <spirit:displayName>serdes_pdb</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>serdes_rst_dual_c</spirit:name> + <spirit:displayName>serdes_rst_dual_c</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>signal_detect_c</spirit:name> + <spirit:displayName>signal_detect_c</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>sli_rst</spirit:name> + <spirit:displayName>sli_rst</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + <spirit:vendorExtensions> + <lattice:attributes> + <lattice:attribute lattice:name="Hide">true</lattice:attribute> + </lattice:attributes> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>tx_pclk</spirit:name> + <spirit:displayName>tx_pclk</spirit:displayName> + <spirit:wire> + <spirit:direction>out</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>tx_pcs_rst_c</spirit:name> + <spirit:displayName>tx_pcs_rst_c</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>tx_pwrup_c</spirit:name> + <spirit:displayName>tx_pwrup_c</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>tx_serdes_rst_c</spirit:name> + <spirit:displayName>tx_serdes_rst_c</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>txi_clk</spirit:name> + <spirit:displayName>txi_clk</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>rx_cv_err</spirit:name> + <spirit:displayName>rx_cv_err</spirit:displayName> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>0</spirit:right> + </spirit:vector> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>rx_disp_err</spirit:name> + <spirit:displayName>rx_disp_err</spirit:displayName> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>0</spirit:right> + </spirit:vector> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>rx_k</spirit:name> + <spirit:displayName>rx_k</spirit:displayName> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>0</spirit:right> + </spirit:vector> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>rxdata</spirit:name> + <spirit:displayName>rxdata</spirit:displayName> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>7</spirit:left> + <spirit:right>0</spirit:right> + </spirit:vector> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>sci_addr</spirit:name> + <spirit:displayName>sci_addr</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>5</spirit:left> + <spirit:right>0</spirit:right> + </spirit:vector> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>sci_rddata</spirit:name> + <spirit:displayName>sci_rddata</spirit:displayName> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>7</spirit:left> + <spirit:right>0</spirit:right> + </spirit:vector> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>sci_wrdata</spirit:name> + <spirit:displayName>sci_wrdata</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>7</spirit:left> + <spirit:right>0</spirit:right> + </spirit:vector> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>tx_disp_correct</spirit:name> + <spirit:displayName>tx_disp_correct</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>0</spirit:right> + </spirit:vector> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>tx_k</spirit:name> + <spirit:displayName>tx_k</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>0</spirit:right> + </spirit:vector> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>txdata</spirit:name> + <spirit:displayName>txdata</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>7</spirit:left> + <spirit:right>0</spirit:right> + </spirit:vector> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>xmit</spirit:name> + <spirit:displayName>xmit</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>0</spirit:right> + </spirit:vector> + </spirit:wire> + </spirit:port> + </spirit:ports> + </spirit:model> + <spirit:vendorExtensions> + <lattice:synthesis>synplify</lattice:synthesis> + <lattice:modified>2019-03-15.18:48:22</lattice:modified> + <lattice:attributes> + <lattice:attribute lattice:name="AddComponent">false</lattice:attribute> + <lattice:attribute lattice:name="BBox">false</lattice:attribute> + <lattice:attribute lattice:name="Change4to5">false</lattice:attribute> + <lattice:attribute lattice:name="ChangeConfig">false</lattice:attribute> + <lattice:attribute lattice:name="ChangeConnect">false</lattice:attribute> + <lattice:attribute lattice:name="ChangeDevice">false</lattice:attribute> + <lattice:attribute lattice:name="ChangeLocate">false</lattice:attribute> + <lattice:attribute lattice:name="ChangePack">false</lattice:attribute> + <lattice:attribute lattice:name="ChangePart">false</lattice:attribute> + <lattice:attribute lattice:name="ChangeSynthesis">false</lattice:attribute> + <lattice:attribute lattice:name="CoreType">LPM</lattice:attribute> + <lattice:attribute lattice:name="DCU_RXREFCLK">PRIMARY</lattice:attribute> + <lattice:attribute lattice:name="DCU_TXREFCLK">PRIMARY</lattice:attribute> + <lattice:attribute lattice:name="Migrate">false</lattice:attribute> + <lattice:attribute lattice:name="RemovedComponent">false</lattice:attribute> + </lattice:attributes> + <lattice:elements> + <lattice:element> + <lattice:name>Lane0</lattice:name> + <lattice:type>DCUCHANNEL</lattice:type> + <lattice:attributes> + <lattice:attribute lattice:name="ElementDrag">true</lattice:attribute> + <lattice:attribute lattice:name="ElementHide">false</lattice:attribute> + <lattice:attribute lattice:name="ElementType">DCUCHANNEL</lattice:attribute> + <lattice:attribute lattice:name="Locate">8</lattice:attribute> + </lattice:attributes> + </lattice:element> + </lattice:elements> + <lattice:lpc> + <lattice:lpcsection lattice:name="Device"/> + <lattice:lpcentry> + <lattice:lpckey>Family</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">ecp5um</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>OperatingCondition</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">COM</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>Package</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">CABGA381</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>PartName</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">LFE5UM-45F-8BG381C</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>PartType</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">LFE5UM-45F</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>SpeedGrade</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">8</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>Status</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">P</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcsection lattice:name="IP"/> + <lattice:lpcentry> + <lattice:lpckey>CoreName</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">PCS</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>CoreRevision</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">8.2</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>CoreStatus</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Demo</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>CoreType</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">LPM</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>Date</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">03/15/2019</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>ModuleName</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">sgmii2</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>ParameterFileVersion</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">1.0</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>SourceFormat</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">verilog</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>Time</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">18:46:19</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>VendorName</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Lattice Semiconductor Corporation</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcsection lattice:name="Parameters"/> + <lattice:lpcentry> + <lattice:lpckey>;ACHARA</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">0 00H</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>;ACHARB</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">0 00H</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>;ACHARM</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">0 00H</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>;RXMCAENABLE</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>CDRLOLACTION</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Full Recalibration</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>CDRLOLRANGE</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>CDR_MAX_RATE</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">1.25</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>CDR_MULT</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">25X</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>CDR_REF_RATE</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">50.0000</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>CH_MODE</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Rx and Tx</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>Destination</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Synplicity</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>EDIF</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>Expression</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">BusA(0 to 7)</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>IO</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>IO_TYPE</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">GbE</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>LEQ</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>LOOPBACK</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>LOSPORT</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>NUM_CHS</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>Order</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Big Endian [MSB:LSB]</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>PPORT_RX_RDY</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>PPORT_TX_RDY</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>PROTOCOL</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">GbE</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>PWAIT_RX_RDY</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">3000</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>PWAIT_TX_RDY</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">3000</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RCSRC</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>REFCLK_RATE</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">50.0000</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RSTSEQSEL</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RX8B10B</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXCOMMAA</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">1010000011</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXCOMMAB</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">0101111100</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXCOMMAM</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">1111111111</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXCOUPLING</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">AC</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXCTC</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXCTCBYTEN</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">0 00H</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXCTCBYTEN1</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">0 00H</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXCTCBYTEN2</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">1 BCH</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXCTCBYTEN3</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">0 50H</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXCTCMATCHPATTERN</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">M2-S2</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXDIFFTERM</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">50 ohms</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXFIFO_ENABLE</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXINVPOL</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Non-invert</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXLDR</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Off</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXLOSTHRESHOLD</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">4</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXLSM</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXSC</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">K28P5</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXWA</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Barrel Shift</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RX_DATA_WIDTH</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">8/10-Bit</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RX_FICLK_RATE</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">125.0000</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RX_LINE_RATE</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">1.2500</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RX_RATE_DIV</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Full Rate</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>SCIPORT</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>SOFTLOL</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>TX8B10B</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>TXAMPLITUDE</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">400</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>TXDEPOST</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>TXDEPRE</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>TXDIFFTERM</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">50 ohms</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>TXFIFO_ENABLE</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>TXINVPOL</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Non-invert</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>TXLDR</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Off</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>TXPLLLOLTHRESHOLD</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>TXPLLMULT</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">25X</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>TX_DATA_WIDTH</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">8/10-Bit</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>TX_FICLK_RATE</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">125.0000</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>TX_LINE_RATE</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">1.2500</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>TX_MAX_RATE</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">1.25</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>TX_RATE_DIV</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Full Rate</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>VHDL</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>Verilog</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcsection lattice:name="FilesGenerated"/> + <lattice:lpcentry> + <lattice:lpckey>sgmii2.pp</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">pp</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>sgmii2.sym</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">sym</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>sgmii2.tft</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">tft</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>sgmii2.txt</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">pcs_module</lattice:lpcvalue> + </lattice:lpcentry> + </lattice:lpc> + <lattice:groups> + <lattice:group> + <lattice:name>DCUCHANNEL</lattice:name> + <lattice:category>1</lattice:category> + <lattice:attributes> + <lattice:attribute lattice:name="GroupDrag">true</lattice:attribute> + <lattice:attribute lattice:name="GroupHide">false</lattice:attribute> + <lattice:attribute lattice:name="GroupType">DCUCHANNEL</lattice:attribute> + </lattice:attributes> + <lattice:elementref>Lane0</lattice:elementref> + </lattice:group> + </lattice:groups> + </spirit:vendorExtensions> + </spirit:componentRef> + </spirit:componentInstance> + <spirit:componentInstance> + <spirit:instanceName>sgmii3</spirit:instanceName> + <spirit:componentRef> + <spirit:vendor>Lattice Semiconductor Corporation</spirit:vendor> + <spirit:library>LEGACY</spirit:library> + <spirit:name>PCS</spirit:name> + <spirit:version>8.2</spirit:version> + <spirit:fileSets> + <spirit:fileset> + <spirit:name>Diamond_Simulation</spirit:name> + <spirit:group>simulation</spirit:group> + <spirit:file> + <spirit:name>./sgmii3/sgmii3.v</spirit:name> + <spirit:fileType>verilogSource</spirit:fileType> + </spirit:file> + </spirit:fileset> + <spirit:fileset> + <spirit:name>Diamond_Synthesis</spirit:name> + <spirit:group>synthesis</spirit:group> + <spirit:file> + <spirit:name>./sgmii3/sgmii3.v</spirit:name> + <spirit:fileType>verilogSource</spirit:fileType> + </spirit:file> + </spirit:fileset> + </spirit:fileSets> + <spirit:componentGenerators> + <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance"> + <spirit:name>Configuration</spirit:name> + <spirit:apiType>none</spirit:apiType> + <spirit:generatorExe>${sbp_path}/${instance}/generate_core.tcl</spirit:generatorExe> + <spirit:group>CONFIG</spirit:group> + </spirit:componentGenerator> + <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance"> + <spirit:name>CreateNGD</spirit:name> + <spirit:apiType>none</spirit:apiType> + <spirit:generatorExe>${sbp_path}/${instance}/generate_ngd.tcl</spirit:generatorExe> + <spirit:group>CONFIG</spirit:group> + </spirit:componentGenerator> + <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance"> + <spirit:name>Generation</spirit:name> + <spirit:apiType>none</spirit:apiType> + <spirit:generatorExe>${sbp_path}/${instance}/generate_core.tcl</spirit:generatorExe> + <spirit:group>GENERATE</spirit:group> + </spirit:componentGenerator> + </spirit:componentGenerators> + <spirit:model> + <spirit:views/> + <spirit:ports> + <spirit:port> + <spirit:name>ctc_del_s</spirit:name> + <spirit:displayName>ctc_del_s</spirit:displayName> + <spirit:wire> + <spirit:direction>out</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>ctc_ins_s</spirit:name> + <spirit:displayName>ctc_ins_s</spirit:displayName> + <spirit:wire> + <spirit:direction>out</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>ctc_orun_s</spirit:name> + <spirit:displayName>ctc_orun_s</spirit:displayName> + <spirit:wire> + <spirit:direction>out</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>ctc_urun_s</spirit:name> + <spirit:displayName>ctc_urun_s</spirit:displayName> + <spirit:wire> + <spirit:direction>out</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>cyawstn</spirit:name> + <spirit:displayName>cyawstn</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>hdinn</spirit:name> + <spirit:displayName>hdinn</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + <spirit:vendorExtensions> + <lattice:attributes> + <lattice:attribute lattice:name="PadPin">true</lattice:attribute> + </lattice:attributes> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>hdinp</spirit:name> + <spirit:displayName>hdinp</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + <spirit:vendorExtensions> + <lattice:attributes> + <lattice:attribute lattice:name="PadPin">true</lattice:attribute> + </lattice:attributes> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>hdoutn</spirit:name> + <spirit:displayName>hdoutn</spirit:displayName> + <spirit:wire> + <spirit:direction>out</spirit:direction> + </spirit:wire> + <spirit:vendorExtensions> + <lattice:attributes> + <lattice:attribute lattice:name="PadPin">true</lattice:attribute> + </lattice:attributes> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>hdoutp</spirit:name> + <spirit:displayName>hdoutp</spirit:displayName> + <spirit:wire> + <spirit:direction>out</spirit:direction> + </spirit:wire> + <spirit:vendorExtensions> + <lattice:attributes> + <lattice:attribute lattice:name="PadPin">true</lattice:attribute> + </lattice:attributes> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>lsm_status_s</spirit:name> + <spirit:displayName>lsm_status_s</spirit:displayName> + <spirit:wire> + <spirit:direction>out</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>pll_refclki</spirit:name> + <spirit:displayName>pll_refclki</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>rst_dual_c</spirit:name> + <spirit:displayName>rst_dual_c</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>rx_cdr_lol_s</spirit:name> + <spirit:displayName>rx_cdr_lol_s</spirit:displayName> + <spirit:wire> + <spirit:direction>out</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>rx_los_low_s</spirit:name> + <spirit:displayName>rx_los_low_s</spirit:displayName> + <spirit:wire> + <spirit:direction>out</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>rx_pcs_rst_c</spirit:name> + <spirit:displayName>rx_pcs_rst_c</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>rx_pwrup_c</spirit:name> + <spirit:displayName>rx_pwrup_c</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>rx_serdes_rst_c</spirit:name> + <spirit:displayName>rx_serdes_rst_c</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>rxrefclk</spirit:name> + <spirit:displayName>rxrefclk</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>sci_en</spirit:name> + <spirit:displayName>sci_en</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>sci_en_dual</spirit:name> + <spirit:displayName>sci_en_dual</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>sci_int</spirit:name> + <spirit:displayName>sci_int</spirit:displayName> + <spirit:wire> + <spirit:direction>out</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>sci_rd</spirit:name> + <spirit:displayName>sci_rd</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>sci_sel</spirit:name> + <spirit:displayName>sci_sel</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>sci_sel_dual</spirit:name> + <spirit:displayName>sci_sel_dual</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>sci_wrn</spirit:name> + <spirit:displayName>sci_wrn</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>serdes_pdb</spirit:name> + <spirit:displayName>serdes_pdb</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>serdes_rst_dual_c</spirit:name> + <spirit:displayName>serdes_rst_dual_c</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>signal_detect_c</spirit:name> + <spirit:displayName>signal_detect_c</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>tx_pclk</spirit:name> + <spirit:displayName>tx_pclk</spirit:displayName> + <spirit:wire> + <spirit:direction>out</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>tx_pcs_rst_c</spirit:name> + <spirit:displayName>tx_pcs_rst_c</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>tx_pwrup_c</spirit:name> + <spirit:displayName>tx_pwrup_c</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>tx_serdes_rst_c</spirit:name> + <spirit:displayName>tx_serdes_rst_c</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>txi_clk</spirit:name> + <spirit:displayName>txi_clk</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>rx_cv_err</spirit:name> + <spirit:displayName>rx_cv_err</spirit:displayName> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>0</spirit:right> + </spirit:vector> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>rx_disp_err</spirit:name> + <spirit:displayName>rx_disp_err</spirit:displayName> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>0</spirit:right> + </spirit:vector> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>rx_k</spirit:name> + <spirit:displayName>rx_k</spirit:displayName> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>0</spirit:right> + </spirit:vector> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>rxdata</spirit:name> + <spirit:displayName>rxdata</spirit:displayName> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>7</spirit:left> + <spirit:right>0</spirit:right> + </spirit:vector> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>sci_addr</spirit:name> + <spirit:displayName>sci_addr</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>5</spirit:left> + <spirit:right>0</spirit:right> + </spirit:vector> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>sci_rddata</spirit:name> + <spirit:displayName>sci_rddata</spirit:displayName> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>7</spirit:left> + <spirit:right>0</spirit:right> + </spirit:vector> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>sci_wrdata</spirit:name> + <spirit:displayName>sci_wrdata</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>7</spirit:left> + <spirit:right>0</spirit:right> + </spirit:vector> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>tx_disp_correct</spirit:name> + <spirit:displayName>tx_disp_correct</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>0</spirit:right> + </spirit:vector> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>tx_k</spirit:name> + <spirit:displayName>tx_k</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>0</spirit:right> + </spirit:vector> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>txdata</spirit:name> + <spirit:displayName>txdata</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>7</spirit:left> + <spirit:right>0</spirit:right> + </spirit:vector> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>xmit</spirit:name> + <spirit:displayName>xmit</spirit:displayName> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>0</spirit:right> + </spirit:vector> + </spirit:wire> + </spirit:port> + </spirit:ports> + </spirit:model> + <spirit:vendorExtensions> + <lattice:synthesis>synplify</lattice:synthesis> + <lattice:modified>2019-03-15.18:48:22</lattice:modified> + <lattice:attributes> + <lattice:attribute lattice:name="AddComponent">false</lattice:attribute> + <lattice:attribute lattice:name="BBox">false</lattice:attribute> + <lattice:attribute lattice:name="Change4to5">false</lattice:attribute> + <lattice:attribute lattice:name="ChangeConfig">false</lattice:attribute> + <lattice:attribute lattice:name="ChangeConnect">false</lattice:attribute> + <lattice:attribute lattice:name="ChangeDevice">false</lattice:attribute> + <lattice:attribute lattice:name="ChangeLocate">false</lattice:attribute> + <lattice:attribute lattice:name="ChangePack">false</lattice:attribute> + <lattice:attribute lattice:name="ChangePart">false</lattice:attribute> + <lattice:attribute lattice:name="ChangeSynthesis">false</lattice:attribute> + <lattice:attribute lattice:name="CoreType">LPM</lattice:attribute> + <lattice:attribute lattice:name="DCU_RXREFCLK">PRIMARY</lattice:attribute> + <lattice:attribute lattice:name="DCU_TXREFCLK">PRIMARY</lattice:attribute> + <lattice:attribute lattice:name="Migrate">false</lattice:attribute> + <lattice:attribute lattice:name="RemovedComponent">false</lattice:attribute> + </lattice:attributes> + <lattice:elements> + <lattice:element> + <lattice:name>Lane0</lattice:name> + <lattice:type>DCUCHANNEL</lattice:type> + <lattice:attributes> + <lattice:attribute lattice:name="ElementDrag">true</lattice:attribute> + <lattice:attribute lattice:name="ElementHide">false</lattice:attribute> + <lattice:attribute lattice:name="ElementType">DCUCHANNEL</lattice:attribute> + <lattice:attribute lattice:name="Locate">9</lattice:attribute> + </lattice:attributes> + </lattice:element> + </lattice:elements> + <lattice:lpc> + <lattice:lpcsection lattice:name="Device"/> + <lattice:lpcentry> + <lattice:lpckey>Family</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">ecp5um</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>OperatingCondition</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">COM</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>Package</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">CABGA381</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>PartName</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">LFE5UM-45F-8BG381C</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>PartType</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">LFE5UM-45F</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>SpeedGrade</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">8</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>Status</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">P</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcsection lattice:name="IP"/> + <lattice:lpcentry> + <lattice:lpckey>CoreName</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">PCS</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>CoreRevision</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">8.2</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>CoreStatus</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Demo</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>CoreType</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">LPM</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>Date</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">03/15/2019</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>ModuleName</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">sgmii3</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>ParameterFileVersion</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">1.0</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>SourceFormat</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">verilog</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>Time</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">18:46:48</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>VendorName</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Lattice Semiconductor Corporation</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcsection lattice:name="Parameters"/> + <lattice:lpcentry> + <lattice:lpckey>;ACHARA</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">0 00H</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>;ACHARB</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">0 00H</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>;ACHARM</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">0 00H</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>;RXMCAENABLE</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>CDRLOLACTION</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Full Recalibration</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>CDRLOLRANGE</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>CDR_MAX_RATE</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">1.25</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>CDR_MULT</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">25X</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>CDR_REF_RATE</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">50.0000</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>CH_MODE</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Rx and Tx</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>Destination</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Synplicity</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>EDIF</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>Expression</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">BusA(0 to 7)</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>IO</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>IO_TYPE</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">GbE</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>LEQ</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>LOOPBACK</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>LOSPORT</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>NUM_CHS</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>Order</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Big Endian [MSB:LSB]</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>PPORT_RX_RDY</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>PPORT_TX_RDY</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>PROTOCOL</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">GbE</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>PWAIT_RX_RDY</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">3000</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>PWAIT_TX_RDY</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">3000</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RCSRC</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>REFCLK_RATE</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">50.0000</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RSTSEQSEL</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RX8B10B</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXCOMMAA</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">1010000011</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXCOMMAB</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">0101111100</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXCOMMAM</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">1111111111</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXCOUPLING</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">AC</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXCTC</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXCTCBYTEN</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">0 00H</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXCTCBYTEN1</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">0 00H</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXCTCBYTEN2</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">1 BCH</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXCTCBYTEN3</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">0 50H</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXCTCMATCHPATTERN</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">M2-S2</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXDIFFTERM</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">50 ohms</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXFIFO_ENABLE</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXINVPOL</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Non-invert</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXLDR</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Off</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXLOSTHRESHOLD</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">4</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXLSM</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXSC</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">K28P5</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RXWA</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Barrel Shift</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RX_DATA_WIDTH</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">8/10-Bit</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RX_FICLK_RATE</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">125.0000</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RX_LINE_RATE</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">1.2500</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>RX_RATE_DIV</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Full Rate</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>SCIPORT</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>SOFTLOL</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>TX8B10B</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>TXAMPLITUDE</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">400</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>TXDEPOST</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>TXDEPRE</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>TXDIFFTERM</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">50 ohms</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>TXFIFO_ENABLE</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>TXINVPOL</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Non-invert</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>TXLDR</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Off</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>TXPLLLOLTHRESHOLD</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>TXPLLMULT</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">25X</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>TX_DATA_WIDTH</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">8/10-Bit</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>TX_FICLK_RATE</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">125.0000</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>TX_LINE_RATE</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">1.2500</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>TX_MAX_RATE</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">1.25</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>TX_RATE_DIV</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">Full Rate</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>VHDL</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>Verilog</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcsection lattice:name="FilesGenerated"/> + <lattice:lpcentry> + <lattice:lpckey>sgmii3.pp</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">pp</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>sgmii3.sym</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">sym</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>sgmii3.tft</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">tft</lattice:lpcvalue> + </lattice:lpcentry> + <lattice:lpcentry> + <lattice:lpckey>sgmii3.txt</lattice:lpckey> + <lattice:lpcvalue lattice:resolve="constant">pcs_module</lattice:lpcvalue> + </lattice:lpcentry> + </lattice:lpc> + <lattice:groups> + <lattice:group> + <lattice:name>DCUCHANNEL</lattice:name> + <lattice:category>1</lattice:category> + <lattice:attributes> + <lattice:attribute lattice:name="GroupDrag">true</lattice:attribute> + <lattice:attribute lattice:name="GroupHide">false</lattice:attribute> + <lattice:attribute lattice:name="GroupType">DCUCHANNEL</lattice:attribute> + </lattice:attributes> + <lattice:elementref>Lane0</lattice:elementref> + </lattice:group> + </lattice:groups> + </spirit:vendorExtensions> + </spirit:componentRef> + </spirit:componentInstance> + </spirit:componentInstances> + <spirit:adHocConnections> + <spirit:adHocConnection> + <spirit:name>sgmii0_sgmii1_cyawstn</spirit:name> + <spirit:displayName>sgmii0_sgmii1_cyawstn</spirit:displayName> + <spirit:description>sgmii0_sgmii1_cyawstn</spirit:description> + <spirit:vendorExtensions> + <lattice:attributes> + <lattice:attribute lattice:name="dualport">cyawstn</lattice:attribute> + <lattice:attribute lattice:name="primitive">DCU</lattice:attribute> + <lattice:attribute lattice:name="type">short</lattice:attribute> + </lattice:attributes> + </spirit:vendorExtensions> + <spirit:internalPortReference spirit:portRef="cyawstn" spirit:componentRef="sgmii0"/> + <spirit:internalPortReference spirit:portRef="cyawstn" spirit:componentRef="sgmii1"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>sgmii0_sgmii1_pll_refclki</spirit:name> + <spirit:displayName>sgmii0_sgmii1_pll_refclki</spirit:displayName> + <spirit:description>sgmii0_sgmii1_pll_refclki</spirit:description> + <spirit:vendorExtensions> + <lattice:attributes> + <lattice:attribute lattice:name="dualport">pll_refclki</lattice:attribute> + <lattice:attribute lattice:name="primitive">DCU</lattice:attribute> + <lattice:attribute lattice:name="type">short</lattice:attribute> + </lattice:attributes> + </spirit:vendorExtensions> + <spirit:internalPortReference spirit:portRef="pll_refclki" spirit:componentRef="sgmii0"/> + <spirit:internalPortReference spirit:portRef="pll_refclki" spirit:componentRef="sgmii1"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>sgmii0_sgmii1_sci_en_dual</spirit:name> + <spirit:displayName>sgmii0_sgmii1_sci_en_dual</spirit:displayName> + <spirit:description>sgmii0_sgmii1_sci_en_dual</spirit:description> + <spirit:vendorExtensions> + <lattice:attributes> + <lattice:attribute lattice:name="dualport">sci_en_dual</lattice:attribute> + <lattice:attribute lattice:name="primitive">DCU</lattice:attribute> + <lattice:attribute lattice:name="type">short</lattice:attribute> + </lattice:attributes> + </spirit:vendorExtensions> + <spirit:internalPortReference spirit:portRef="sci_en_dual" spirit:componentRef="sgmii0"/> + <spirit:internalPortReference spirit:portRef="sci_en_dual" spirit:componentRef="sgmii1"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>sgmii0_sgmii1_sci_int</spirit:name> + <spirit:displayName>sgmii0_sgmii1_sci_int</spirit:displayName> + <spirit:description>sgmii0_sgmii1_sci_int</spirit:description> + <spirit:vendorExtensions> + <lattice:attributes> + <lattice:attribute lattice:name="dualport">sci_int</lattice:attribute> + <lattice:attribute lattice:name="primitive">DCU</lattice:attribute> + <lattice:attribute lattice:name="type">short</lattice:attribute> + </lattice:attributes> + </spirit:vendorExtensions> + <spirit:internalPortReference spirit:portRef="sci_int" spirit:componentRef="sgmii0"/> + <spirit:internalPortReference spirit:portRef="sci_int" spirit:componentRef="sgmii1"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>sgmii0_sgmii1_sci_rd</spirit:name> + <spirit:displayName>sgmii0_sgmii1_sci_rd</spirit:displayName> + <spirit:description>sgmii0_sgmii1_sci_rd</spirit:description> + <spirit:vendorExtensions> + <lattice:attributes> + <lattice:attribute lattice:name="dualport">sci_rd</lattice:attribute> + <lattice:attribute lattice:name="primitive">DCU</lattice:attribute> + <lattice:attribute lattice:name="type">short</lattice:attribute> + </lattice:attributes> + </spirit:vendorExtensions> + <spirit:internalPortReference spirit:portRef="sci_rd" spirit:componentRef="sgmii0"/> + <spirit:internalPortReference spirit:portRef="sci_rd" spirit:componentRef="sgmii1"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>sgmii0_sgmii1_sci_sel_dual</spirit:name> + <spirit:displayName>sgmii0_sgmii1_sci_sel_dual</spirit:displayName> + <spirit:description>sgmii0_sgmii1_sci_sel_dual</spirit:description> + <spirit:vendorExtensions> + <lattice:attributes> + <lattice:attribute lattice:name="dualport">sci_sel_dual</lattice:attribute> + <lattice:attribute lattice:name="primitive">DCU</lattice:attribute> + <lattice:attribute lattice:name="type">short</lattice:attribute> + </lattice:attributes> + </spirit:vendorExtensions> + <spirit:internalPortReference spirit:portRef="sci_sel_dual" spirit:componentRef="sgmii0"/> + <spirit:internalPortReference spirit:portRef="sci_sel_dual" spirit:componentRef="sgmii1"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>sgmii0_sgmii1_sci_wrn</spirit:name> + <spirit:displayName>sgmii0_sgmii1_sci_wrn</spirit:displayName> + <spirit:description>sgmii0_sgmii1_sci_wrn</spirit:description> + <spirit:vendorExtensions> + <lattice:attributes> + <lattice:attribute lattice:name="dualport">sci_wrn</lattice:attribute> + <lattice:attribute lattice:name="primitive">DCU</lattice:attribute> + <lattice:attribute lattice:name="type">short</lattice:attribute> + </lattice:attributes> + </spirit:vendorExtensions> + <spirit:internalPortReference spirit:portRef="sci_wrn" spirit:componentRef="sgmii0"/> + <spirit:internalPortReference spirit:portRef="sci_wrn" spirit:componentRef="sgmii1"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>sgmii0_sgmii1_serdes_pdb</spirit:name> + <spirit:displayName>sgmii0_sgmii1_serdes_pdb</spirit:displayName> + <spirit:description>sgmii0_sgmii1_serdes_pdb</spirit:description> + <spirit:vendorExtensions> + <lattice:attributes> + <lattice:attribute lattice:name="dualport">serdes_pdb</lattice:attribute> + <lattice:attribute lattice:name="primitive">DCU</lattice:attribute> + <lattice:attribute lattice:name="type">short</lattice:attribute> + </lattice:attributes> + </spirit:vendorExtensions> + <spirit:internalPortReference spirit:portRef="serdes_pdb" spirit:componentRef="sgmii0"/> + <spirit:internalPortReference spirit:portRef="serdes_pdb" spirit:componentRef="sgmii1"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>sgmii3_sgmii2_cyawstn</spirit:name> + <spirit:displayName>sgmii3_sgmii2_cyawstn</spirit:displayName> + <spirit:description>sgmii3_sgmii2_cyawstn</spirit:description> + <spirit:vendorExtensions> + <lattice:attributes> + <lattice:attribute lattice:name="dualport">cyawstn</lattice:attribute> + <lattice:attribute lattice:name="primitive">DCU</lattice:attribute> + <lattice:attribute lattice:name="type">short</lattice:attribute> + </lattice:attributes> + </spirit:vendorExtensions> + <spirit:internalPortReference spirit:portRef="cyawstn" spirit:componentRef="sgmii3"/> + <spirit:internalPortReference spirit:portRef="cyawstn" spirit:componentRef="sgmii2"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>sgmii3_sgmii2_pll_refclki</spirit:name> + <spirit:displayName>sgmii3_sgmii2_pll_refclki</spirit:displayName> + <spirit:description>sgmii3_sgmii2_pll_refclki</spirit:description> + <spirit:vendorExtensions> + <lattice:attributes> + <lattice:attribute lattice:name="dualport">pll_refclki</lattice:attribute> + <lattice:attribute lattice:name="primitive">DCU</lattice:attribute> + <lattice:attribute lattice:name="type">short</lattice:attribute> + </lattice:attributes> + </spirit:vendorExtensions> + <spirit:internalPortReference spirit:portRef="pll_refclki" spirit:componentRef="sgmii3"/> + <spirit:internalPortReference spirit:portRef="pll_refclki" spirit:componentRef="sgmii2"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>sgmii3_sgmii2_sci_en_dual</spirit:name> + <spirit:displayName>sgmii3_sgmii2_sci_en_dual</spirit:displayName> + <spirit:description>sgmii3_sgmii2_sci_en_dual</spirit:description> + <spirit:vendorExtensions> + <lattice:attributes> + <lattice:attribute lattice:name="dualport">sci_en_dual</lattice:attribute> + <lattice:attribute lattice:name="primitive">DCU</lattice:attribute> + <lattice:attribute lattice:name="type">short</lattice:attribute> + </lattice:attributes> + </spirit:vendorExtensions> + <spirit:internalPortReference spirit:portRef="sci_en_dual" spirit:componentRef="sgmii3"/> + <spirit:internalPortReference spirit:portRef="sci_en_dual" spirit:componentRef="sgmii2"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>sgmii3_sgmii2_sci_int</spirit:name> + <spirit:displayName>sgmii3_sgmii2_sci_int</spirit:displayName> + <spirit:description>sgmii3_sgmii2_sci_int</spirit:description> + <spirit:vendorExtensions> + <lattice:attributes> + <lattice:attribute lattice:name="dualport">sci_int</lattice:attribute> + <lattice:attribute lattice:name="primitive">DCU</lattice:attribute> + <lattice:attribute lattice:name="type">short</lattice:attribute> + </lattice:attributes> + </spirit:vendorExtensions> + <spirit:internalPortReference spirit:portRef="sci_int" spirit:componentRef="sgmii3"/> + <spirit:internalPortReference spirit:portRef="sci_int" spirit:componentRef="sgmii2"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>sgmii3_sgmii2_sci_rd</spirit:name> + <spirit:displayName>sgmii3_sgmii2_sci_rd</spirit:displayName> + <spirit:description>sgmii3_sgmii2_sci_rd</spirit:description> + <spirit:vendorExtensions> + <lattice:attributes> + <lattice:attribute lattice:name="dualport">sci_rd</lattice:attribute> + <lattice:attribute lattice:name="primitive">DCU</lattice:attribute> + <lattice:attribute lattice:name="type">short</lattice:attribute> + </lattice:attributes> + </spirit:vendorExtensions> + <spirit:internalPortReference spirit:portRef="sci_rd" spirit:componentRef="sgmii3"/> + <spirit:internalPortReference spirit:portRef="sci_rd" spirit:componentRef="sgmii2"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>sgmii3_sgmii2_sci_sel_dual</spirit:name> + <spirit:displayName>sgmii3_sgmii2_sci_sel_dual</spirit:displayName> + <spirit:description>sgmii3_sgmii2_sci_sel_dual</spirit:description> + <spirit:vendorExtensions> + <lattice:attributes> + <lattice:attribute lattice:name="dualport">sci_sel_dual</lattice:attribute> + <lattice:attribute lattice:name="primitive">DCU</lattice:attribute> + <lattice:attribute lattice:name="type">short</lattice:attribute> + </lattice:attributes> + </spirit:vendorExtensions> + <spirit:internalPortReference spirit:portRef="sci_sel_dual" spirit:componentRef="sgmii3"/> + <spirit:internalPortReference spirit:portRef="sci_sel_dual" spirit:componentRef="sgmii2"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>sgmii3_sgmii2_sci_wrn</spirit:name> + <spirit:displayName>sgmii3_sgmii2_sci_wrn</spirit:displayName> + <spirit:description>sgmii3_sgmii2_sci_wrn</spirit:description> + <spirit:vendorExtensions> + <lattice:attributes> + <lattice:attribute lattice:name="dualport">sci_wrn</lattice:attribute> + <lattice:attribute lattice:name="primitive">DCU</lattice:attribute> + <lattice:attribute lattice:name="type">short</lattice:attribute> + </lattice:attributes> + </spirit:vendorExtensions> + <spirit:internalPortReference spirit:portRef="sci_wrn" spirit:componentRef="sgmii3"/> + <spirit:internalPortReference spirit:portRef="sci_wrn" spirit:componentRef="sgmii2"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>sgmii3_sgmii2_serdes_pdb</spirit:name> + <spirit:displayName>sgmii3_sgmii2_serdes_pdb</spirit:displayName> + <spirit:description>sgmii3_sgmii2_serdes_pdb</spirit:description> + <spirit:vendorExtensions> + <lattice:attributes> + <lattice:attribute lattice:name="dualport">serdes_pdb</lattice:attribute> + <lattice:attribute lattice:name="primitive">DCU</lattice:attribute> + <lattice:attribute lattice:name="type">short</lattice:attribute> + </lattice:attributes> + </spirit:vendorExtensions> + <spirit:internalPortReference spirit:portRef="serdes_pdb" spirit:componentRef="sgmii3"/> + <spirit:internalPortReference spirit:portRef="serdes_pdb" spirit:componentRef="sgmii2"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>sgmii0_sgmii1_sci_addr</spirit:name> + <spirit:displayName>sgmii0_sgmii1_sci_addr</spirit:displayName> + <spirit:description>sgmii0_sgmii1_sci_addr</spirit:description> + <spirit:vendorExtensions> + <lattice:attributes> + <lattice:attribute lattice:name="dualport">sgmii0_sgmii1_sci_addr</lattice:attribute> + <lattice:attribute lattice:name="primitive">DCU</lattice:attribute> + <lattice:attribute lattice:name="type">short</lattice:attribute> + </lattice:attributes> + </spirit:vendorExtensions> + <spirit:internalPortReference spirit:right="0" spirit:portRef="sci_addr" spirit:componentRef="sgmii0" spirit:left="5"/> + <spirit:internalPortReference spirit:right="0" spirit:portRef="sci_addr" spirit:componentRef="sgmii1" spirit:left="5"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>sgmii0_sgmii1_sci_rddata</spirit:name> + <spirit:displayName>sgmii0_sgmii1_sci_rddata</spirit:displayName> + <spirit:description>sgmii0_sgmii1_sci_rddata</spirit:description> + <spirit:vendorExtensions> + <lattice:attributes> + <lattice:attribute lattice:name="dualport">sgmii0_sgmii1_sci_rddata</lattice:attribute> + <lattice:attribute lattice:name="primitive">DCU</lattice:attribute> + <lattice:attribute lattice:name="type">short</lattice:attribute> + </lattice:attributes> + </spirit:vendorExtensions> + <spirit:internalPortReference spirit:right="0" spirit:portRef="sci_rddata" spirit:componentRef="sgmii0" spirit:left="7"/> + <spirit:internalPortReference spirit:right="0" spirit:portRef="sci_rddata" spirit:componentRef="sgmii1" spirit:left="7"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>sgmii0_sgmii1_sci_wrdata</spirit:name> + <spirit:displayName>sgmii0_sgmii1_sci_wrdata</spirit:displayName> + <spirit:description>sgmii0_sgmii1_sci_wrdata</spirit:description> + <spirit:vendorExtensions> + <lattice:attributes> + <lattice:attribute lattice:name="dualport">sgmii0_sgmii1_sci_wrdata</lattice:attribute> + <lattice:attribute lattice:name="primitive">DCU</lattice:attribute> + <lattice:attribute lattice:name="type">short</lattice:attribute> + </lattice:attributes> + </spirit:vendorExtensions> + <spirit:internalPortReference spirit:right="0" spirit:portRef="sci_wrdata" spirit:componentRef="sgmii0" spirit:left="7"/> + <spirit:internalPortReference spirit:right="0" spirit:portRef="sci_wrdata" spirit:componentRef="sgmii1" spirit:left="7"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>sgmii3_sgmii2_sci_addr</spirit:name> + <spirit:displayName>sgmii3_sgmii2_sci_addr</spirit:displayName> + <spirit:description>sgmii3_sgmii2_sci_addr</spirit:description> + <spirit:vendorExtensions> + <lattice:attributes> + <lattice:attribute lattice:name="dualport">sgmii3_sgmii2_sci_addr</lattice:attribute> + <lattice:attribute lattice:name="primitive">DCU</lattice:attribute> + <lattice:attribute lattice:name="type">short</lattice:attribute> + </lattice:attributes> + </spirit:vendorExtensions> + <spirit:internalPortReference spirit:right="0" spirit:portRef="sci_addr" spirit:componentRef="sgmii3" spirit:left="5"/> + <spirit:internalPortReference spirit:right="0" spirit:portRef="sci_addr" spirit:componentRef="sgmii2" spirit:left="5"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>sgmii3_sgmii2_sci_rddata</spirit:name> + <spirit:displayName>sgmii3_sgmii2_sci_rddata</spirit:displayName> + <spirit:description>sgmii3_sgmii2_sci_rddata</spirit:description> + <spirit:vendorExtensions> + <lattice:attributes> + <lattice:attribute lattice:name="dualport">sgmii3_sgmii2_sci_rddata</lattice:attribute> + <lattice:attribute lattice:name="primitive">DCU</lattice:attribute> + <lattice:attribute lattice:name="type">short</lattice:attribute> + </lattice:attributes> + </spirit:vendorExtensions> + <spirit:internalPortReference spirit:right="0" spirit:portRef="sci_rddata" spirit:componentRef="sgmii3" spirit:left="7"/> + <spirit:internalPortReference spirit:right="0" spirit:portRef="sci_rddata" spirit:componentRef="sgmii2" spirit:left="7"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>sgmii3_sgmii2_sci_wrdata</spirit:name> + <spirit:displayName>sgmii3_sgmii2_sci_wrdata</spirit:displayName> + <spirit:description>sgmii3_sgmii2_sci_wrdata</spirit:description> + <spirit:vendorExtensions> + <lattice:attributes> + <lattice:attribute lattice:name="dualport">sgmii3_sgmii2_sci_wrdata</lattice:attribute> + <lattice:attribute lattice:name="primitive">DCU</lattice:attribute> + <lattice:attribute lattice:name="type">short</lattice:attribute> + </lattice:attributes> + </spirit:vendorExtensions> + <spirit:internalPortReference spirit:right="0" spirit:portRef="sci_wrdata" spirit:componentRef="sgmii3" spirit:left="7"/> + <spirit:internalPortReference spirit:right="0" spirit:portRef="sci_wrdata" spirit:componentRef="sgmii2" spirit:left="7"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>refclk0_refclkn</spirit:name> + <spirit:displayName>refclk0_refclkn</spirit:displayName> + <spirit:vendorExtensions> + <lattice:attributes> + <lattice:attribute lattice:name="export">sys_yes</lattice:attribute> + </lattice:attributes> + </spirit:vendorExtensions> + <spirit:internalPortReference spirit:portRef="refclkn" spirit:componentRef="refclk0"/> + <spirit:externalPortReference spirit:portRef="refclk0_refclkn"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>refclk0_refclko</spirit:name> + <spirit:displayName>refclk0_refclko</spirit:displayName> + <spirit:description>refclk0_refclko</spirit:description> + <spirit:vendorExtensions> + <lattice:attributes> + <lattice:attribute lattice:name="export">sys_no</lattice:attribute> + <lattice:attribute lattice:name="type">internal</lattice:attribute> + </lattice:attributes> + </spirit:vendorExtensions> + <spirit:internalPortReference spirit:portRef="refclko" spirit:componentRef="refclk0"/> + <spirit:internalPortReference spirit:portRef="rxrefclk" spirit:componentRef="sgmii2"/> + <spirit:internalPortReference spirit:portRef="rxrefclk" spirit:componentRef="sgmii1"/> + <spirit:internalPortReference spirit:portRef="rxrefclk" spirit:componentRef="sgmii0"/> + <spirit:internalPortReference spirit:portRef="pll_refclki" spirit:componentRef="sgmii0"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>refclk0_refclkp</spirit:name> + <spirit:displayName>refclk0_refclkp</spirit:displayName> + <spirit:vendorExtensions> + <lattice:attributes> + <lattice:attribute lattice:name="export">sys_yes</lattice:attribute> + </lattice:attributes> + </spirit:vendorExtensions> + <spirit:internalPortReference spirit:portRef="refclkp" spirit:componentRef="refclk0"/> + <spirit:externalPortReference spirit:portRef="refclk0_refclkp"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>sgmii0_ctc_del_s</spirit:name> + <spirit:displayName>sgmii0_ctc_del_s</spirit:displayName> + <spirit:internalPortReference spirit:portRef="ctc_del_s" spirit:componentRef="sgmii0"/> + <spirit:externalPortReference spirit:portRef="sgmii0_ctc_del_s"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>sgmii0_ctc_ins_s</spirit:name> + <spirit:displayName>sgmii0_ctc_ins_s</spirit:displayName> + <spirit:internalPortReference spirit:portRef="ctc_ins_s" spirit:componentRef="sgmii0"/> + <spirit:externalPortReference spirit:portRef="sgmii0_ctc_ins_s"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>sgmii0_ctc_orun_s</spirit:name> + <spirit:displayName>sgmii0_ctc_orun_s</spirit:displayName> + <spirit:internalPortReference spirit:portRef="ctc_orun_s" spirit:componentRef="sgmii0"/> + <spirit:externalPortReference spirit:portRef="sgmii0_ctc_orun_s"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>sgmii0_ctc_urun_s</spirit:name> + <spirit:displayName>sgmii0_ctc_urun_s</spirit:displayName> + <spirit:internalPortReference spirit:portRef="ctc_urun_s" spirit:componentRef="sgmii0"/> + <spirit:externalPortReference spirit:portRef="sgmii0_ctc_urun_s"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>sgmii0_cyawstn</spirit:name> + <spirit:displayName>sgmii0_cyawstn</spirit:displayName> + <spirit:internalPortReference spirit:portRef="cyawstn" spirit:componentRef="sgmii0"/> + <spirit:externalPortReference spirit:portRef="sgmii0_cyawstn"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>sgmii0_hdinn</spirit:name> + <spirit:displayName>sgmii0_hdinn</spirit:displayName> + <spirit:vendorExtensions> + <lattice:attributes> + <lattice:attribute lattice:name="export">sys_yes</lattice:attribute> + </lattice:attributes> + </spirit:vendorExtensions> + <spirit:internalPortReference spirit:portRef="hdinn" spirit:componentRef="sgmii0"/> + <spirit:externalPortReference spirit:portRef="sgmii0_hdinn"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>sgmii0_hdinp</spirit:name> + <spirit:displayName>sgmii0_hdinp</spirit:displayName> + <spirit:vendorExtensions> + <lattice:attributes> + <lattice:attribute lattice:name="export">sys_yes</lattice:attribute> + </lattice:attributes> + </spirit:vendorExtensions> + <spirit:internalPortReference spirit:portRef="hdinp" spirit:componentRef="sgmii0"/> + <spirit:externalPortReference spirit:portRef="sgmii0_hdinp"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>sgmii0_hdoutn</spirit:name> + <spirit:displayName>sgmii0_hdoutn</spirit:displayName> + <spirit:vendorExtensions> + <lattice:attributes> + <lattice:attribute lattice:name="export">sys_yes</lattice:attribute> + </lattice:attributes> + </spirit:vendorExtensions> + <spirit:internalPortReference spirit:portRef="hdoutn" spirit:componentRef="sgmii0"/> + <spirit:externalPortReference spirit:portRef="sgmii0_hdoutn"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>sgmii0_hdoutp</spirit:name> + <spirit:displayName>sgmii0_hdoutp</spirit:displayName> + <spirit:vendorExtensions> + <lattice:attributes> + <lattice:attribute lattice:name="export">sys_yes</lattice:attribute> + </lattice:attributes> + </spirit:vendorExtensions> + <spirit:internalPortReference spirit:portRef="hdoutp" spirit:componentRef="sgmii0"/> + <spirit:externalPortReference spirit:portRef="sgmii0_hdoutp"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>sgmii0_lsm_status_s</spirit:name> + <spirit:displayName>sgmii0_lsm_status_s</spirit:displayName> + <spirit:internalPortReference spirit:portRef="lsm_status_s" spirit:componentRef="sgmii0"/> + <spirit:externalPortReference spirit:portRef="sgmii0_lsm_status_s"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + 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<spirit:name>sgmii2_txdata[3]</spirit:name> + <spirit:displayName>sgmii2_txdata[3]</spirit:displayName> + <spirit:externalPortReference spirit:portRef="sgmii2_txdata[3]"/> + <spirit:internalPortReference spirit:portRef="txdata[3]" spirit:componentRef="sgmii2"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>sgmii2_txdata[4]</spirit:name> + <spirit:displayName>sgmii2_txdata[4]</spirit:displayName> + <spirit:externalPortReference spirit:portRef="sgmii2_txdata[4]"/> + <spirit:internalPortReference spirit:portRef="txdata[4]" spirit:componentRef="sgmii2"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>sgmii2_txdata[5]</spirit:name> + <spirit:displayName>sgmii2_txdata[5]</spirit:displayName> + <spirit:externalPortReference spirit:portRef="sgmii2_txdata[5]"/> + <spirit:internalPortReference spirit:portRef="txdata[5]" spirit:componentRef="sgmii2"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>sgmii2_txdata[6]</spirit:name> + <spirit:displayName>sgmii2_txdata[6]</spirit:displayName> + <spirit:externalPortReference spirit:portRef="sgmii2_txdata[6]"/> + <spirit:internalPortReference spirit:portRef="txdata[6]" spirit:componentRef="sgmii2"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>sgmii2_txdata[7]</spirit:name> + <spirit:displayName>sgmii2_txdata[7]</spirit:displayName> + <spirit:externalPortReference spirit:portRef="sgmii2_txdata[7]"/> + <spirit:internalPortReference spirit:portRef="txdata[7]" spirit:componentRef="sgmii2"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>sgmii2_xmit</spirit:name> + <spirit:displayName>sgmii2_xmit</spirit:displayName> + <spirit:internalPortReference spirit:right="0" spirit:portRef="xmit" spirit:componentRef="sgmii2" spirit:left="0"/> + <spirit:externalPortReference spirit:right="0" spirit:portRef="sgmii2_xmit" spirit:left="0"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>sgmii2_xmit[0]</spirit:name> + <spirit:displayName>sgmii2_xmit[0]</spirit:displayName> + <spirit:externalPortReference spirit:portRef="sgmii2_xmit[0]"/> + <spirit:internalPortReference spirit:portRef="xmit[0]" spirit:componentRef="sgmii2"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>sgmii3_rx_cv_err</spirit:name> + <spirit:displayName>sgmii3_rx_cv_err</spirit:displayName> + <spirit:internalPortReference spirit:right="0" spirit:portRef="rx_cv_err" spirit:componentRef="sgmii3" spirit:left="0"/> + <spirit:externalPortReference spirit:right="0" spirit:portRef="sgmii3_rx_cv_err" spirit:left="0"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>sgmii3_rx_cv_err[0]</spirit:name> + <spirit:displayName>sgmii3_rx_cv_err[0]</spirit:displayName> + <spirit:internalPortReference spirit:portRef="rx_cv_err[0]" spirit:componentRef="sgmii3"/> + <spirit:externalPortReference spirit:portRef="sgmii3_rx_cv_err[0]"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>sgmii3_rx_disp_err</spirit:name> + <spirit:displayName>sgmii3_rx_disp_err</spirit:displayName> + <spirit:internalPortReference spirit:right="0" spirit:portRef="rx_disp_err" spirit:componentRef="sgmii3" spirit:left="0"/> + <spirit:externalPortReference spirit:right="0" spirit:portRef="sgmii3_rx_disp_err" spirit:left="0"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>sgmii3_rx_disp_err[0]</spirit:name> + <spirit:displayName>sgmii3_rx_disp_err[0]</spirit:displayName> + <spirit:internalPortReference spirit:portRef="rx_disp_err[0]" spirit:componentRef="sgmii3"/> + <spirit:externalPortReference spirit:portRef="sgmii3_rx_disp_err[0]"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>sgmii3_rx_k</spirit:name> + <spirit:displayName>sgmii3_rx_k</spirit:displayName> + <spirit:internalPortReference spirit:right="0" spirit:portRef="rx_k" spirit:componentRef="sgmii3" spirit:left="0"/> + <spirit:externalPortReference spirit:right="0" spirit:portRef="sgmii3_rx_k" spirit:left="0"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>sgmii3_rx_k[0]</spirit:name> + <spirit:displayName>sgmii3_rx_k[0]</spirit:displayName> + <spirit:internalPortReference spirit:portRef="rx_k[0]" spirit:componentRef="sgmii3"/> + <spirit:externalPortReference spirit:portRef="sgmii3_rx_k[0]"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>sgmii3_rxdata</spirit:name> + <spirit:displayName>sgmii3_rxdata</spirit:displayName> + <spirit:internalPortReference spirit:right="0" spirit:portRef="rxdata" spirit:componentRef="sgmii3" spirit:left="7"/> + <spirit:externalPortReference spirit:right="0" spirit:portRef="sgmii3_rxdata" spirit:left="7"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>sgmii3_rxdata[0]</spirit:name> + <spirit:displayName>sgmii3_rxdata[0]</spirit:displayName> + <spirit:internalPortReference spirit:portRef="rxdata[0]" spirit:componentRef="sgmii3"/> + <spirit:externalPortReference spirit:portRef="sgmii3_rxdata[0]"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>sgmii3_rxdata[1]</spirit:name> + <spirit:displayName>sgmii3_rxdata[1]</spirit:displayName> + <spirit:internalPortReference spirit:portRef="rxdata[1]" spirit:componentRef="sgmii3"/> + <spirit:externalPortReference spirit:portRef="sgmii3_rxdata[1]"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>sgmii3_rxdata[2]</spirit:name> + <spirit:displayName>sgmii3_rxdata[2]</spirit:displayName> + <spirit:internalPortReference spirit:portRef="rxdata[2]" spirit:componentRef="sgmii3"/> + <spirit:externalPortReference spirit:portRef="sgmii3_rxdata[2]"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>sgmii3_rxdata[3]</spirit:name> + <spirit:displayName>sgmii3_rxdata[3]</spirit:displayName> + <spirit:internalPortReference spirit:portRef="rxdata[3]" spirit:componentRef="sgmii3"/> + <spirit:externalPortReference spirit:portRef="sgmii3_rxdata[3]"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>sgmii3_rxdata[4]</spirit:name> + <spirit:displayName>sgmii3_rxdata[4]</spirit:displayName> + <spirit:internalPortReference spirit:portRef="rxdata[4]" spirit:componentRef="sgmii3"/> + <spirit:externalPortReference spirit:portRef="sgmii3_rxdata[4]"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>sgmii3_rxdata[5]</spirit:name> + <spirit:displayName>sgmii3_rxdata[5]</spirit:displayName> + <spirit:internalPortReference spirit:portRef="rxdata[5]" spirit:componentRef="sgmii3"/> + <spirit:externalPortReference spirit:portRef="sgmii3_rxdata[5]"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>sgmii3_rxdata[6]</spirit:name> + <spirit:displayName>sgmii3_rxdata[6]</spirit:displayName> + <spirit:internalPortReference spirit:portRef="rxdata[6]" spirit:componentRef="sgmii3"/> + <spirit:externalPortReference spirit:portRef="sgmii3_rxdata[6]"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>sgmii3_rxdata[7]</spirit:name> + <spirit:displayName>sgmii3_rxdata[7]</spirit:displayName> + <spirit:internalPortReference spirit:portRef="rxdata[7]" spirit:componentRef="sgmii3"/> + <spirit:externalPortReference spirit:portRef="sgmii3_rxdata[7]"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>sgmii3_tx_disp_correct</spirit:name> + <spirit:displayName>sgmii3_tx_disp_correct</spirit:displayName> + <spirit:internalPortReference spirit:right="0" spirit:portRef="tx_disp_correct" spirit:componentRef="sgmii3" spirit:left="0"/> + <spirit:externalPortReference spirit:right="0" spirit:portRef="sgmii3_tx_disp_correct" spirit:left="0"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>sgmii3_tx_disp_correct[0]</spirit:name> + <spirit:displayName>sgmii3_tx_disp_correct[0]</spirit:displayName> + <spirit:externalPortReference spirit:portRef="sgmii3_tx_disp_correct[0]"/> + <spirit:internalPortReference spirit:portRef="tx_disp_correct[0]" spirit:componentRef="sgmii3"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>sgmii3_tx_k</spirit:name> + <spirit:displayName>sgmii3_tx_k</spirit:displayName> + <spirit:internalPortReference spirit:right="0" spirit:portRef="tx_k" spirit:componentRef="sgmii3" spirit:left="0"/> + <spirit:externalPortReference spirit:right="0" spirit:portRef="sgmii3_tx_k" spirit:left="0"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>sgmii3_tx_k[0]</spirit:name> + <spirit:displayName>sgmii3_tx_k[0]</spirit:displayName> + <spirit:externalPortReference spirit:portRef="sgmii3_tx_k[0]"/> + <spirit:internalPortReference spirit:portRef="tx_k[0]" spirit:componentRef="sgmii3"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>sgmii3_txdata</spirit:name> + <spirit:displayName>sgmii3_txdata</spirit:displayName> + <spirit:internalPortReference spirit:right="0" spirit:portRef="txdata" spirit:componentRef="sgmii3" spirit:left="7"/> + <spirit:externalPortReference spirit:right="0" spirit:portRef="sgmii3_txdata" spirit:left="7"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>sgmii3_txdata[0]</spirit:name> + <spirit:displayName>sgmii3_txdata[0]</spirit:displayName> + <spirit:externalPortReference spirit:portRef="sgmii3_txdata[0]"/> + <spirit:internalPortReference spirit:portRef="txdata[0]" spirit:componentRef="sgmii3"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>sgmii3_txdata[1]</spirit:name> + <spirit:displayName>sgmii3_txdata[1]</spirit:displayName> + <spirit:externalPortReference spirit:portRef="sgmii3_txdata[1]"/> + <spirit:internalPortReference spirit:portRef="txdata[1]" spirit:componentRef="sgmii3"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>sgmii3_txdata[2]</spirit:name> + <spirit:displayName>sgmii3_txdata[2]</spirit:displayName> + <spirit:externalPortReference spirit:portRef="sgmii3_txdata[2]"/> + <spirit:internalPortReference spirit:portRef="txdata[2]" spirit:componentRef="sgmii3"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>sgmii3_txdata[3]</spirit:name> + <spirit:displayName>sgmii3_txdata[3]</spirit:displayName> + <spirit:externalPortReference spirit:portRef="sgmii3_txdata[3]"/> + <spirit:internalPortReference spirit:portRef="txdata[3]" spirit:componentRef="sgmii3"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>sgmii3_txdata[4]</spirit:name> + <spirit:displayName>sgmii3_txdata[4]</spirit:displayName> + <spirit:externalPortReference spirit:portRef="sgmii3_txdata[4]"/> + <spirit:internalPortReference spirit:portRef="txdata[4]" spirit:componentRef="sgmii3"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>sgmii3_txdata[5]</spirit:name> + <spirit:displayName>sgmii3_txdata[5]</spirit:displayName> + <spirit:externalPortReference spirit:portRef="sgmii3_txdata[5]"/> + <spirit:internalPortReference spirit:portRef="txdata[5]" spirit:componentRef="sgmii3"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>sgmii3_txdata[6]</spirit:name> + <spirit:displayName>sgmii3_txdata[6]</spirit:displayName> + <spirit:externalPortReference spirit:portRef="sgmii3_txdata[6]"/> + <spirit:internalPortReference spirit:portRef="txdata[6]" spirit:componentRef="sgmii3"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>sgmii3_txdata[7]</spirit:name> + <spirit:displayName>sgmii3_txdata[7]</spirit:displayName> + <spirit:externalPortReference spirit:portRef="sgmii3_txdata[7]"/> + <spirit:internalPortReference spirit:portRef="txdata[7]" spirit:componentRef="sgmii3"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>sgmii3_xmit</spirit:name> + <spirit:displayName>sgmii3_xmit</spirit:displayName> + <spirit:internalPortReference spirit:right="0" spirit:portRef="xmit" spirit:componentRef="sgmii3" spirit:left="0"/> + <spirit:externalPortReference spirit:right="0" spirit:portRef="sgmii3_xmit" spirit:left="0"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>sgmii3_xmit[0]</spirit:name> + <spirit:displayName>sgmii3_xmit[0]</spirit:displayName> + <spirit:externalPortReference spirit:portRef="sgmii3_xmit[0]"/> + <spirit:internalPortReference spirit:portRef="xmit[0]" spirit:componentRef="sgmii3"/> + </spirit:adHocConnection> + </spirit:adHocConnections> + </spirit:design> +</lattice:project> diff --git a/clarity/pcs/pcs.v b/clarity/pcs/pcs.v new file mode 100644 index 0000000..40bad95 --- /dev/null +++ b/clarity/pcs/pcs.v @@ -0,0 +1,320 @@ +/* synthesis translate_off*/ +`define SBP_SIMULATION +/* synthesis translate_on*/ +`ifndef SBP_SIMULATION +`define SBP_SYNTHESIS +`endif + +// +// Verific Verilog Description of module pcs +// +module pcs (sgmii0_rx_cv_err, sgmii0_rx_disp_err, sgmii0_rx_k, sgmii0_rxdata, + sgmii0_sci_addr, sgmii0_sci_rddata, sgmii0_sci_wrdata, sgmii0_tx_disp_correct, + sgmii0_tx_k, sgmii0_txdata, sgmii0_xmit, sgmii1_rx_cv_err, + sgmii1_rx_disp_err, sgmii1_rx_k, sgmii1_rxdata, sgmii1_tx_disp_correct, + sgmii1_tx_k, sgmii1_txdata, sgmii1_xmit, sgmii2_rx_cv_err, + sgmii2_rx_disp_err, sgmii2_rx_k, sgmii2_rxdata, sgmii2_sci_addr, + sgmii2_sci_rddata, sgmii2_sci_wrdata, sgmii2_tx_disp_correct, + sgmii2_tx_k, sgmii2_txdata, sgmii2_xmit, sgmii3_rx_cv_err, + sgmii3_rx_disp_err, sgmii3_rx_k, sgmii3_rxdata, sgmii3_tx_disp_correct, + sgmii3_tx_k, sgmii3_txdata, sgmii3_xmit, refclk0_refclkn, + refclk0_refclkp, sgmii0_ctc_del_s, sgmii0_ctc_ins_s, sgmii0_ctc_orun_s, + sgmii0_ctc_urun_s, sgmii0_cyawstn, sgmii0_hdinn, sgmii0_hdinp, + sgmii0_hdoutn, sgmii0_hdoutp, sgmii0_lsm_status_s, sgmii0_pll_lol, + sgmii0_rst_dual_c, sgmii0_rx_cdr_lol_s, sgmii0_rx_los_low_s, + sgmii0_rx_pcs_rst_c, sgmii0_rx_pwrup_c, sgmii0_rx_serdes_rst_c, + sgmii0_sci_en, sgmii0_sci_en_dual, sgmii0_sci_int, sgmii0_sci_rd, + sgmii0_sci_sel, sgmii0_sci_sel_dual, sgmii0_sci_wrn, sgmii0_serdes_rst_dual_c, + sgmii0_signal_detect_c, sgmii0_tx_pclk, sgmii0_tx_pcs_rst_c, + sgmii0_tx_pwrup_c, sgmii0_tx_serdes_rst_c, sgmii0_txi_clk, + sgmii1_ctc_del_s, sgmii1_ctc_ins_s, sgmii1_ctc_orun_s, sgmii1_ctc_urun_s, + sgmii1_hdinn, sgmii1_hdinp, sgmii1_hdoutn, sgmii1_hdoutp, + sgmii1_lsm_status_s, sgmii1_rst_dual_c, sgmii1_rx_cdr_lol_s, + sgmii1_rx_los_low_s, sgmii1_rx_pcs_rst_c, sgmii1_rx_pwrup_c, + sgmii1_rx_serdes_rst_c, sgmii1_sci_en, sgmii1_sci_sel, sgmii1_serdes_pdb, + sgmii1_serdes_rst_dual_c, sgmii1_signal_detect_c, sgmii1_tx_pclk, + sgmii1_tx_pcs_rst_c, sgmii1_tx_pwrup_c, sgmii1_tx_serdes_rst_c, + sgmii1_txi_clk, sgmii2_ctc_del_s, sgmii2_ctc_ins_s, sgmii2_ctc_orun_s, + sgmii2_ctc_urun_s, sgmii2_cyawstn, sgmii2_hdinn, sgmii2_hdinp, + sgmii2_hdoutn, sgmii2_hdoutp, sgmii2_lsm_status_s, sgmii2_pll_lol, + sgmii2_rst_dual_c, sgmii2_rx_cdr_lol_s, sgmii2_rx_los_low_s, + sgmii2_rx_pcs_rst_c, sgmii2_rx_pwrup_c, sgmii2_rx_serdes_rst_c, + sgmii2_sci_en, sgmii2_sci_en_dual, sgmii2_sci_int, sgmii2_sci_rd, + sgmii2_sci_sel, sgmii2_sci_sel_dual, sgmii2_sci_wrn, sgmii2_serdes_pdb, + sgmii2_serdes_rst_dual_c, sgmii2_signal_detect_c, sgmii2_tx_pclk, + sgmii2_tx_pcs_rst_c, sgmii2_tx_pwrup_c, sgmii2_tx_serdes_rst_c, + sgmii2_txi_clk, sgmii3_ctc_del_s, sgmii3_ctc_ins_s, sgmii3_ctc_orun_s, + sgmii3_ctc_urun_s, sgmii3_hdinn, sgmii3_hdinp, sgmii3_hdoutn, + sgmii3_hdoutp, sgmii3_lsm_status_s, sgmii3_rst_dual_c, + sgmii3_rx_cdr_lol_s, sgmii3_rx_los_low_s, sgmii3_rx_pcs_rst_c, + sgmii3_rx_pwrup_c, sgmii3_rx_serdes_rst_c, + sgmii3_sci_sel, sgmii3_serdes_rst_dual_c, sgmii3_signal_detect_c, + sgmii3_tx_pclk, sgmii3_tx_pcs_rst_c, sgmii3_tx_pwrup_c, sgmii3_tx_serdes_rst_c, + sgmii3_txi_clk, refclk0_refclko) /* synthesis sbp_module=true */ ; + output [0:0]sgmii0_rx_cv_err; + output [0:0]sgmii0_rx_disp_err; + output [0:0]sgmii0_rx_k; + output [7:0]sgmii0_rxdata; + input [5:0]sgmii0_sci_addr; + output [7:0]sgmii0_sci_rddata; + input [7:0]sgmii0_sci_wrdata; + input [0:0]sgmii0_tx_disp_correct; + input [0:0]sgmii0_tx_k; + input [7:0]sgmii0_txdata; + input [0:0]sgmii0_xmit; + output [0:0]sgmii1_rx_cv_err; + output [0:0]sgmii1_rx_disp_err; + output [0:0]sgmii1_rx_k; + output [7:0]sgmii1_rxdata; + input [0:0]sgmii1_tx_disp_correct; + input [0:0]sgmii1_tx_k; + input [7:0]sgmii1_txdata; + input [0:0]sgmii1_xmit; + output [0:0]sgmii2_rx_cv_err; + output [0:0]sgmii2_rx_disp_err; + output [0:0]sgmii2_rx_k; + output [7:0]sgmii2_rxdata; + input [5:0]sgmii2_sci_addr; + output [7:0]sgmii2_sci_rddata; + input [7:0]sgmii2_sci_wrdata; + input [0:0]sgmii2_tx_disp_correct; + input [0:0]sgmii2_tx_k; + input [7:0]sgmii2_txdata; + input [0:0]sgmii2_xmit; + output [0:0]sgmii3_rx_cv_err; + output [0:0]sgmii3_rx_disp_err; + output [0:0]sgmii3_rx_k; + output [7:0]sgmii3_rxdata; + input [0:0]sgmii3_tx_disp_correct; + input [0:0]sgmii3_tx_k; + input [7:0]sgmii3_txdata; + input [0:0]sgmii3_xmit; + input refclk0_refclkn; + input refclk0_refclkp; + output sgmii0_ctc_del_s; + output sgmii0_ctc_ins_s; + output sgmii0_ctc_orun_s; + output sgmii0_ctc_urun_s; + input sgmii0_cyawstn; + input sgmii0_hdinn; + input sgmii0_hdinp; + output sgmii0_hdoutn; + output sgmii0_hdoutp; + output sgmii0_lsm_status_s; + output sgmii0_pll_lol; + input sgmii0_rst_dual_c; + output sgmii0_rx_cdr_lol_s; + output sgmii0_rx_los_low_s; + input sgmii0_rx_pcs_rst_c; + input sgmii0_rx_pwrup_c; + input sgmii0_rx_serdes_rst_c; + input sgmii0_sci_en; + input sgmii0_sci_en_dual; + output sgmii0_sci_int; + input sgmii0_sci_rd; + input sgmii0_sci_sel; + input sgmii0_sci_sel_dual; + input sgmii0_sci_wrn; + input sgmii0_serdes_rst_dual_c; + input sgmii0_signal_detect_c; + output sgmii0_tx_pclk; + input sgmii0_tx_pcs_rst_c; + input sgmii0_tx_pwrup_c; + input sgmii0_tx_serdes_rst_c; + input sgmii0_txi_clk; + output sgmii1_ctc_del_s; + output sgmii1_ctc_ins_s; + output sgmii1_ctc_orun_s; + output sgmii1_ctc_urun_s; + input sgmii1_hdinn; + input sgmii1_hdinp; + output sgmii1_hdoutn; + output sgmii1_hdoutp; + output sgmii1_lsm_status_s; + input sgmii1_rst_dual_c; + output sgmii1_rx_cdr_lol_s; + output sgmii1_rx_los_low_s; + input sgmii1_rx_pcs_rst_c; + input sgmii1_rx_pwrup_c; + input sgmii1_rx_serdes_rst_c; + input sgmii1_sci_en; + input sgmii1_sci_sel; + input sgmii1_serdes_pdb; + input sgmii1_serdes_rst_dual_c; + input sgmii1_signal_detect_c; + output sgmii1_tx_pclk; + input sgmii1_tx_pcs_rst_c; + input sgmii1_tx_pwrup_c; + input sgmii1_tx_serdes_rst_c; + input sgmii1_txi_clk; + output sgmii2_ctc_del_s; + output sgmii2_ctc_ins_s; + output sgmii2_ctc_orun_s; + output sgmii2_ctc_urun_s; + input sgmii2_cyawstn; + input sgmii2_hdinn; + input sgmii2_hdinp; + output sgmii2_hdoutn; + output sgmii2_hdoutp; + output sgmii2_lsm_status_s; + output sgmii2_pll_lol; + input sgmii2_rst_dual_c; + output sgmii2_rx_cdr_lol_s; + output sgmii2_rx_los_low_s; + input sgmii2_rx_pcs_rst_c; + input sgmii2_rx_pwrup_c; + input sgmii2_rx_serdes_rst_c; + input sgmii2_sci_en; + input sgmii2_sci_en_dual; + output sgmii2_sci_int; + input sgmii2_sci_rd; + input sgmii2_sci_sel; + input sgmii2_sci_sel_dual; + input sgmii2_sci_wrn; + input sgmii2_serdes_pdb; + input sgmii2_serdes_rst_dual_c; + input sgmii2_signal_detect_c; + output sgmii2_tx_pclk; + input sgmii2_tx_pcs_rst_c; + input sgmii2_tx_pwrup_c; + input sgmii2_tx_serdes_rst_c; + input sgmii2_txi_clk; + output sgmii3_ctc_del_s; + output sgmii3_ctc_ins_s; + output sgmii3_ctc_orun_s; + output sgmii3_ctc_urun_s; + input sgmii3_hdinn; + input sgmii3_hdinp; + output sgmii3_hdoutn; + output sgmii3_hdoutp; + output sgmii3_lsm_status_s; + input sgmii3_rst_dual_c; + output sgmii3_rx_cdr_lol_s; + output sgmii3_rx_los_low_s; + input sgmii3_rx_pcs_rst_c; + input sgmii3_rx_pwrup_c; + input sgmii3_rx_serdes_rst_c; + input sgmii3_sci_sel; + input sgmii3_serdes_rst_dual_c; + input sgmii3_signal_detect_c; + output sgmii3_tx_pclk; + input sgmii3_tx_pcs_rst_c; + input sgmii3_tx_pwrup_c; + input sgmii3_tx_serdes_rst_c; + input sgmii3_txi_clk; + + + output refclk0_refclko; + wire [7:0]i_sgmii0_sci_rddata; + wire [7:0]i_sgmii1_sci_rddata; + wire [7:0]o_sgmii1_sci_rddata; + wire [7:0]i_sgmii2_sci_rddata; + wire [7:0]o_sgmii2_sci_rddata; + wire [7:0]i_sgmii3_sci_rddata; + + wire i_sgmii0_sci_int, i_sgmii1_sci_int, o_sgmii1_sci_int, i_sgmii2_sci_int, + o_sgmii2_sci_int, i_sgmii3_sci_int, sli_rst_wire0, sli_rst_wire2; + + assign sli_rst_wire0 = sgmii0_serdes_rst_dual_c || sgmii0_tx_serdes_rst_c || (!sgmii1_serdes_pdb) || (!sgmii0_tx_pwrup_c) || (!sgmii1_tx_pwrup_c); + assign sli_rst_wire2 = sgmii2_serdes_rst_dual_c || sgmii2_tx_serdes_rst_c || (!sgmii2_serdes_pdb) || (!sgmii2_tx_pwrup_c) || (!sgmii3_tx_pwrup_c); + /* synthesis translate_off*/ + `define sbx_mux + /* synthesis translate_on*/ + `ifdef sbx_mux + assign o_sgmii1_sci_rddata = sgmii1_sci_sel ? i_sgmii1_sci_rddata : 8'b0; + assign sgmii0_sci_rddata = sgmii0_sci_sel ? i_sgmii0_sci_rddata : o_sgmii1_sci_rddata; + assign o_sgmii2_sci_rddata = sgmii2_sci_sel ? i_sgmii2_sci_rddata : 8'b0; + assign sgmii2_sci_rddata = sgmii3_sci_sel ? i_sgmii3_sci_rddata : o_sgmii2_sci_rddata; + assign o_sgmii1_sci_int = sgmii1_sci_sel ? i_sgmii1_sci_int : 0; + assign sgmii0_sci_int = sgmii0_sci_sel ? i_sgmii0_sci_int : o_sgmii1_sci_int; + assign o_sgmii2_sci_int = sgmii2_sci_sel ? i_sgmii2_sci_int : 0; + assign sgmii2_sci_int = sgmii3_sci_sel ? i_sgmii3_sci_int : o_sgmii2_sci_int; + `else + assign sgmii0_sci_rddata = i_sgmii0_sci_rddata; + assign sgmii2_sci_rddata = i_sgmii3_sci_rddata; + assign sgmii0_sci_int = i_sgmii0_sci_int; + assign sgmii2_sci_int = i_sgmii3_sci_int; + `endif + refclk0 refclk0_inst (.refclkn(refclk0_refclkn), .refclko(refclk0_refclko), + .refclkp(refclk0_refclkp)); + sgmii0 sgmii0_inst (.rx_cv_err({sgmii0_rx_cv_err}), .rx_disp_err({sgmii0_rx_disp_err}), + .rx_k({sgmii0_rx_k}), .rxdata({sgmii0_rxdata}), .sci_addr({sgmii0_sci_addr}), + .sci_rddata({i_sgmii0_sci_rddata}), .sci_wrdata({sgmii0_sci_wrdata}), + .tx_disp_correct({sgmii0_tx_disp_correct}), .tx_k({sgmii0_tx_k}), + .txdata({sgmii0_txdata}), .xmit({sgmii0_xmit}), .ctc_del_s(sgmii0_ctc_del_s), + .ctc_ins_s(sgmii0_ctc_ins_s), .ctc_orun_s(sgmii0_ctc_orun_s), + .ctc_urun_s(sgmii0_ctc_urun_s), .cyawstn(sgmii0_cyawstn), .hdinn(sgmii0_hdinn), + .hdinp(sgmii0_hdinp), .hdoutn(sgmii0_hdoutn), .hdoutp(sgmii0_hdoutp), + .lsm_status_s(sgmii0_lsm_status_s), .pll_lol(sgmii0_pll_lol), + .pll_refclki(refclk0_refclko), .rst_dual_c(sgmii0_rst_dual_c), + .rx_cdr_lol_s(sgmii0_rx_cdr_lol_s), .rx_los_low_s(sgmii0_rx_los_low_s), + .rx_pcs_rst_c(sgmii0_rx_pcs_rst_c), .rx_pwrup_c(sgmii0_rx_pwrup_c), + .rx_serdes_rst_c(sgmii0_rx_serdes_rst_c), .rxrefclk(refclk0_refclko), + .sci_en(sgmii0_sci_en), .sci_en_dual(sgmii0_sci_en_dual), .sci_int(i_sgmii0_sci_int), + .sci_rd(sgmii0_sci_rd), .sci_sel(sgmii0_sci_sel), .sci_sel_dual(sgmii0_sci_sel_dual), + .sci_wrn(sgmii0_sci_wrn), .serdes_pdb(sgmii1_serdes_pdb), .serdes_rst_dual_c(sgmii0_serdes_rst_dual_c), + .signal_detect_c(sgmii0_signal_detect_c), .sli_rst(sli_rst_wire0), + .tx_pclk(sgmii0_tx_pclk), .tx_pcs_rst_c(sgmii0_tx_pcs_rst_c), + .tx_pwrup_c(sgmii0_tx_pwrup_c), .tx_serdes_rst_c(sgmii0_tx_serdes_rst_c), + .txi_clk(sgmii0_txi_clk)); + sgmii1 sgmii1_inst (.rx_cv_err({sgmii1_rx_cv_err}), .rx_disp_err({sgmii1_rx_disp_err}), + .rx_k({sgmii1_rx_k}), .rxdata({sgmii1_rxdata}), .sci_addr({sgmii0_sci_addr}), + .sci_rddata({i_sgmii1_sci_rddata}), .sci_wrdata({sgmii0_sci_wrdata}), + .tx_disp_correct({sgmii1_tx_disp_correct}), .tx_k({sgmii1_tx_k}), + .txdata({sgmii1_txdata}), .xmit({sgmii1_xmit}), .ctc_del_s(sgmii1_ctc_del_s), + .ctc_ins_s(sgmii1_ctc_ins_s), .ctc_orun_s(sgmii1_ctc_orun_s), + .ctc_urun_s(sgmii1_ctc_urun_s), .cyawstn(sgmii0_cyawstn), .hdinn(sgmii1_hdinn), + .hdinp(sgmii1_hdinp), .hdoutn(sgmii1_hdoutn), .hdoutp(sgmii1_hdoutp), + .lsm_status_s(sgmii1_lsm_status_s), .pll_refclki(refclk0_refclko), + .rst_dual_c(sgmii1_rst_dual_c), .rx_cdr_lol_s(sgmii1_rx_cdr_lol_s), + .rx_los_low_s(sgmii1_rx_los_low_s), .rx_pcs_rst_c(sgmii1_rx_pcs_rst_c), + .rx_pwrup_c(sgmii1_rx_pwrup_c), .rx_serdes_rst_c(sgmii1_rx_serdes_rst_c), + .rxrefclk(refclk0_refclko), .sci_en(sgmii1_sci_en), .sci_en_dual(sgmii0_sci_en_dual), + .sci_int(i_sgmii1_sci_int), .sci_rd(sgmii0_sci_rd), .sci_sel(sgmii1_sci_sel), + .sci_sel_dual(sgmii0_sci_sel_dual), .sci_wrn(sgmii0_sci_wrn), + .serdes_pdb(sgmii1_serdes_pdb), .serdes_rst_dual_c(sgmii1_serdes_rst_dual_c), + .signal_detect_c(sgmii1_signal_detect_c), .tx_pclk(sgmii1_tx_pclk), + .tx_pcs_rst_c(sgmii1_tx_pcs_rst_c), .tx_pwrup_c(sgmii1_tx_pwrup_c), + .tx_serdes_rst_c(sgmii1_tx_serdes_rst_c), .txi_clk(sgmii1_txi_clk)); + sgmii2 sgmii2_inst (.rx_cv_err({sgmii2_rx_cv_err}), .rx_disp_err({sgmii2_rx_disp_err}), + .rx_k({sgmii2_rx_k}), .rxdata({sgmii2_rxdata}), .sci_addr({sgmii2_sci_addr}), + .sci_rddata({i_sgmii2_sci_rddata}), .sci_wrdata({sgmii2_sci_wrdata}), + .tx_disp_correct({sgmii2_tx_disp_correct}), .tx_k({sgmii2_tx_k}), + .txdata({sgmii2_txdata}), .xmit({sgmii2_xmit}), .ctc_del_s(sgmii2_ctc_del_s), + .ctc_ins_s(sgmii2_ctc_ins_s), .ctc_orun_s(sgmii2_ctc_orun_s), + .ctc_urun_s(sgmii2_ctc_urun_s), .cyawstn(sgmii2_cyawstn), .hdinn(sgmii2_hdinn), + .hdinp(sgmii2_hdinp), .hdoutn(sgmii2_hdoutn), .hdoutp(sgmii2_hdoutp), + .lsm_status_s(sgmii2_lsm_status_s), .pll_lol(sgmii2_pll_lol), + .pll_refclki(refclk0_refclko), .rst_dual_c(sgmii2_rst_dual_c), + .rx_cdr_lol_s(sgmii2_rx_cdr_lol_s), .rx_los_low_s(sgmii2_rx_los_low_s), + .rx_pcs_rst_c(sgmii2_rx_pcs_rst_c), .rx_pwrup_c(sgmii2_rx_pwrup_c), + .rx_serdes_rst_c(sgmii2_rx_serdes_rst_c), .rxrefclk(refclk0_refclko), + .sci_en(sgmii2_sci_en), .sci_en_dual(sgmii2_sci_en_dual), .sci_int(i_sgmii2_sci_int), + .sci_rd(sgmii2_sci_rd), .sci_sel(sgmii2_sci_sel), .sci_sel_dual(sgmii2_sci_sel_dual), + .sci_wrn(sgmii2_sci_wrn), .serdes_pdb(sgmii2_serdes_pdb), .serdes_rst_dual_c(sgmii2_serdes_rst_dual_c), + .signal_detect_c(sgmii2_signal_detect_c), .sli_rst(sli_rst_wire2), + .tx_pclk(sgmii2_tx_pclk), .tx_pcs_rst_c(sgmii2_tx_pcs_rst_c), + .tx_pwrup_c(sgmii2_tx_pwrup_c), .tx_serdes_rst_c(sgmii2_tx_serdes_rst_c), + .txi_clk(sgmii2_txi_clk)); + sgmii3 sgmii3_inst (.rx_cv_err({sgmii3_rx_cv_err}), .rx_disp_err({sgmii3_rx_disp_err}), + .rx_k({sgmii3_rx_k}), .rxdata({sgmii3_rxdata}), .sci_addr({sgmii2_sci_addr}), + .sci_rddata({i_sgmii3_sci_rddata}), .sci_wrdata({sgmii2_sci_wrdata}), + .tx_disp_correct({sgmii3_tx_disp_correct}), .tx_k({sgmii3_tx_k}), + .txdata({sgmii3_txdata}), .xmit({sgmii3_xmit}), .ctc_del_s(sgmii3_ctc_del_s), + .ctc_ins_s(sgmii3_ctc_ins_s), .ctc_orun_s(sgmii3_ctc_orun_s), + .ctc_urun_s(sgmii3_ctc_urun_s), .cyawstn(sgmii2_cyawstn), .hdinn(sgmii3_hdinn), + .hdinp(sgmii3_hdinp), .hdoutn(sgmii3_hdoutn), .hdoutp(sgmii3_hdoutp), + .lsm_status_s(sgmii3_lsm_status_s), .pll_refclki(refclk0_refclko), + .rst_dual_c(sgmii3_rst_dual_c), .rx_cdr_lol_s(sgmii3_rx_cdr_lol_s), + .rx_los_low_s(sgmii3_rx_los_low_s), .rx_pcs_rst_c(sgmii3_rx_pcs_rst_c), + .rx_pwrup_c(sgmii3_rx_pwrup_c), .rx_serdes_rst_c(sgmii3_rx_serdes_rst_c), + .rxrefclk(refclk0_refclko), .sci_en(sgmii2_sci_en), .sci_en_dual(sgmii2_sci_en_dual), + .sci_int(i_sgmii3_sci_int), .sci_rd(sgmii2_sci_rd), .sci_sel(sgmii3_sci_sel), + .sci_sel_dual(sgmii2_sci_sel_dual), .sci_wrn(sgmii2_sci_wrn), + .serdes_pdb(sgmii2_serdes_pdb), .serdes_rst_dual_c(sgmii3_serdes_rst_dual_c), + .signal_detect_c(sgmii3_signal_detect_c), .tx_pclk(sgmii3_tx_pclk), + .tx_pcs_rst_c(sgmii3_tx_pcs_rst_c), .tx_pwrup_c(sgmii3_tx_pwrup_c), + .tx_serdes_rst_c(sgmii3_tx_serdes_rst_c), .txi_clk(sgmii3_txi_clk)); + +endmodule + diff --git a/clarity/pcs/pcs_tmpl.v b/clarity/pcs/pcs_tmpl.v new file mode 100644 index 0000000..b181d80 --- /dev/null +++ b/clarity/pcs/pcs_tmpl.v @@ -0,0 +1,44 @@ +//Verilog instantiation template + +pcs _inst (.sgmii1_rx_cv_err(), .sgmii1_rx_disp_err(), .sgmii1_rx_k(), + .sgmii1_rxdata(), .sgmii1_tx_disp_correct(), .sgmii1_tx_k(), .sgmii1_txdata(), + .sgmii1_xmit(), .sgmii1_ctc_del_s(), .sgmii1_ctc_ins_s(), .sgmii1_ctc_orun_s(), + .sgmii1_ctc_urun_s(), .sgmii1_hdinn(), .sgmii1_hdinp(), .sgmii1_hdoutn(), + .sgmii1_hdoutp(), .sgmii1_lsm_status_s(), .sgmii1_rst_dual_c(), .sgmii1_rx_cdr_lol_s(), + .sgmii1_rx_los_low_s(), .sgmii1_rx_pcs_rst_c(), .sgmii1_rx_pwrup_c(), + .sgmii1_rx_serdes_rst_c(), .sgmii1_sci_en(), .sgmii1_sci_sel(), .sgmii1_serdes_pdb(), + .sgmii1_serdes_rst_dual_c(), .sgmii1_signal_detect_c(), .sgmii1_tx_pclk(), + .sgmii1_tx_pcs_rst_c(), .sgmii1_tx_pwrup_c(), .sgmii1_tx_serdes_rst_c(), + .sgmii1_txi_clk(), .sgmii2_rx_cv_err(), .sgmii2_rx_disp_err(), .sgmii2_rx_k(), + .sgmii2_rxdata(), .sgmii2_tx_disp_correct(), .sgmii2_tx_k(), .sgmii2_txdata(), + .sgmii2_xmit(), .sgmii2_ctc_del_s(), .sgmii2_ctc_ins_s(), .sgmii2_ctc_orun_s(), + .sgmii2_ctc_urun_s(), .sgmii2_hdinn(), .sgmii2_hdinp(), .sgmii2_hdoutn(), + .sgmii2_hdoutp(), .sgmii2_lsm_status_s(), .sgmii2_pll_lol(), .sgmii2_rst_dual_c(), + .sgmii2_rx_cdr_lol_s(), .sgmii2_rx_los_low_s(), .sgmii2_rx_pcs_rst_c(), + .sgmii2_rx_pwrup_c(), .sgmii2_rx_serdes_rst_c(), .sgmii2_sci_en(), + .sgmii2_sci_sel(), .sgmii2_serdes_rst_dual_c(), .sgmii2_signal_detect_c(), + .sgmii2_tx_pclk(), .sgmii2_tx_pcs_rst_c(), .sgmii2_tx_pwrup_c(), .sgmii2_tx_serdes_rst_c(), + .sgmii2_txi_clk(), .sgmii2_sci_addr(), .sgmii2_sci_wrdata(), .sgmii3_rx_cv_err(), + .sgmii3_rx_disp_err(), .sgmii3_rx_k(), .sgmii3_rxdata(), .sgmii3_tx_disp_correct(), + .sgmii3_tx_k(), .sgmii3_txdata(), .sgmii3_xmit(), .sgmii2_cyawstn(), + .sgmii2_sci_en_dual(), .sgmii2_sci_rd(), .sgmii2_sci_sel_dual(), .sgmii2_sci_wrn(), + .sgmii2_serdes_pdb(), .sgmii3_ctc_del_s(), .sgmii3_ctc_ins_s(), .sgmii3_ctc_orun_s(), + .sgmii3_ctc_urun_s(), .sgmii3_hdinn(), .sgmii3_hdinp(), .sgmii3_hdoutn(), + .sgmii3_hdoutp(), .sgmii3_lsm_status_s(), .sgmii3_pll_refclki(), .sgmii3_rst_dual_c(), + .sgmii3_rx_cdr_lol_s(), .sgmii3_rx_los_low_s(), .sgmii3_rx_pcs_rst_c(), + .sgmii3_rx_pwrup_c(), .sgmii3_rx_serdes_rst_c(), .sgmii3_rxrefclk(), + .sgmii3_sci_en(), .sgmii3_sci_sel(), .sgmii3_serdes_rst_dual_c(), + .sgmii3_signal_detect_c(), .sgmii3_tx_pclk(), .sgmii3_tx_pcs_rst_c(), + .sgmii3_tx_pwrup_c(), .sgmii3_tx_serdes_rst_c(), .sgmii3_txi_clk(), + .refclk0_refclkn(), .refclk0_refclkp(), .sgmii0_rx_cv_err(), .sgmii0_rx_disp_err(), + .sgmii0_rx_k(), .sgmii0_rxdata(), .sgmii0_sci_addr(), .sgmii0_sci_wrdata(), + .sgmii0_tx_disp_correct(), .sgmii0_tx_k(), .sgmii0_txdata(), .sgmii0_xmit(), + .sgmii0_ctc_del_s(), .sgmii0_ctc_ins_s(), .sgmii0_ctc_orun_s(), .sgmii0_ctc_urun_s(), + .sgmii0_cyawstn(), .sgmii0_hdinn(), .sgmii0_hdinp(), .sgmii0_hdoutn(), + .sgmii0_hdoutp(), .sgmii0_lsm_status_s(), .sgmii0_pll_lol(), .sgmii0_rst_dual_c(), + .sgmii0_rx_cdr_lol_s(), .sgmii0_rx_los_low_s(), .sgmii0_rx_pcs_rst_c(), + .sgmii0_rx_pwrup_c(), .sgmii0_rx_serdes_rst_c(), .sgmii0_sci_en(), + .sgmii0_sci_en_dual(), .sgmii0_sci_rd(), .sgmii0_sci_sel(), .sgmii0_sci_sel_dual(), + .sgmii0_sci_wrn(), .sgmii0_serdes_rst_dual_c(), .sgmii0_signal_detect_c(), + .sgmii0_tx_pclk(), .sgmii0_tx_pcs_rst_c(), .sgmii0_tx_pwrup_c(), .sgmii0_tx_serdes_rst_c(), + .sgmii0_txi_clk());
\ No newline at end of file diff --git a/clarity/pcs/refclk0/refclk0.fdc b/clarity/pcs/refclk0/refclk0.fdc new file mode 100644 index 0000000..6fbcac9 --- /dev/null +++ b/clarity/pcs/refclk0/refclk0.fdc @@ -0,0 +1,2 @@ +###==== Start Configuration + diff --git a/clarity/pcs/refclk0/refclk0.lpc b/clarity/pcs/refclk0/refclk0.lpc new file mode 100644 index 0000000..4e2184e --- /dev/null +++ b/clarity/pcs/refclk0/refclk0.lpc @@ -0,0 +1,31 @@ +[Device] +Family=ecp5um +OperatingCondition=COM +Package=CABGA381 +PartName=LFE5UM-45F-8BG381C +PartType=LFE5UM-45F +SpeedGrade=8 +Status=P +[IP] +CoreName=EXTREF +CoreRevision=1.1 +CoreStatus=Demo +CoreType=LPM +Date=10/17/2017 +ModuleName=refclk0 +ParameterFileVersion=1.0 +SourceFormat=verilog +Time=18:21:09 +VendorName=Lattice Semiconductor Corporation +[Parameters] +Destination=Synplicity +EDIF=1 +EXTREFDCBIAS=Disabled +EXTREFTERMRES=50 ohms +Expression=BusA(0 to 7) +IO=0 +Order=Big Endian [MSB:LSB] +VHDL=0 +Verilog=1 +[SYSTEMPNR] +EXTREF=DCU0 diff --git a/clarity/pcs/refclk0/refclk0.v b/clarity/pcs/refclk0/refclk0.v new file mode 100644 index 0000000..7fe46e2 --- /dev/null +++ b/clarity/pcs/refclk0/refclk0.v @@ -0,0 +1,20 @@ +// Verilog netlist produced by program ASBGen: Ports rev. 2.30, Attr. rev. 2.65 +// Netlist written on Tue Oct 17 18:22:54 2017 +// +// Verilog Description of module refclk0 +// + +`timescale 1ns/1ps +module refclk0 (refclkp, refclkn, refclko); + input refclkp; + input refclkn; + output refclko; + + + EXTREFB EXTREF0_inst (.REFCLKP(refclkp), .REFCLKN(refclkn), .REFCLKO(refclko)) /* synthesis LOC=EXTREF0 */ ; + defparam EXTREF0_inst.REFCK_PWDNB = "0b1"; + defparam EXTREF0_inst.REFCK_RTERM = "0b1"; + defparam EXTREF0_inst.REFCK_DCBIAS_EN = "0b0"; + +endmodule + diff --git a/clarity/pcs/sgmii0/sgmii0.fdc b/clarity/pcs/sgmii0/sgmii0.fdc new file mode 100644 index 0000000..292bc0f --- /dev/null +++ b/clarity/pcs/sgmii0/sgmii0.fdc @@ -0,0 +1,3 @@ +###==== Start Generation + +define_attribute {i:Lane0} {loc} {DCU0_CH0} diff --git a/clarity/pcs/sgmii0/sgmii0.lpc b/clarity/pcs/sgmii0/sgmii0.lpc new file mode 100644 index 0000000..0aea3d2 --- /dev/null +++ b/clarity/pcs/sgmii0/sgmii0.lpc @@ -0,0 +1,97 @@ +[Device] +Family=ecp5um +OperatingCondition=COM +Package=CABGA381 +PartName=LFE5UM-45F-8BG381C +PartType=LFE5UM-45F +SpeedGrade=8 +Status=P +[IP] +CoreName=PCS +CoreRevision=8.2 +CoreStatus=Demo +CoreType=LPM +Date=02/08/2019 +ModuleName=sgmii0 +ParameterFileVersion=1.0 +SourceFormat=verilog +Time=18:42:05 +VendorName=Lattice Semiconductor Corporation +[Parameters] +;ACHARA=0 00H +;ACHARB=0 00H +;ACHARM=0 00H +;RXMCAENABLE=Disabled +CDRLOLACTION=Full Recalibration +CDRLOLRANGE=0 +CDR_MAX_RATE=1.25 +CDR_MULT=25X +CDR_REF_RATE=50.0000 +CH_MODE=Rx and Tx +Destination=Synplicity +EDIF=1 +Expression=BusA(0 to 7) +IO=0 +IO_TYPE=GbE +LEQ=0 +LOOPBACK=Disabled +LOSPORT=Enabled +NUM_CHS=1 +Order=Big Endian [MSB:LSB] +PPORT_RX_RDY=Disabled +PPORT_TX_RDY=Disabled +PROTOCOL=GbE +PWAIT_RX_RDY=3000 +PWAIT_TX_RDY=3000 +RCSRC=Disabled +REFCLK_RATE=50.0000 +RSTSEQSEL=Disabled +RX8B10B=Enabled +RXCOMMAA=1010000011 +RXCOMMAB=0101111100 +RXCOMMAM=1111111111 +RXCOUPLING=AC +RXCTC=Enabled +RXCTCBYTEN=0 00H +RXCTCBYTEN1=0 00H +RXCTCBYTEN2=1 BCH +RXCTCBYTEN3=0 50H +RXCTCMATCHPATTERN=M2-S2 +RXDIFFTERM=50 ohms +RXFIFO_ENABLE=Enabled +RXINVPOL=Invert +RXLDR=Off +RXLOSTHRESHOLD=4 +RXLSM=Enabled +RXSC=K28P5 +RXWA=Barrel Shift +RX_DATA_WIDTH=8/10-Bit +RX_FICLK_RATE=125.0000 +RX_LINE_RATE=1.2500 +RX_RATE_DIV=Full Rate +SCIPORT=Enabled +SOFTLOL=Enabled +TX8B10B=Enabled +TXAMPLITUDE=400 +TXDEPOST=Disabled +TXDEPRE=Disabled +TXDIFFTERM=50 ohms +TXFIFO_ENABLE=Enabled +TXINVPOL=Invert +TXLDR=Off +TXPLLLOLTHRESHOLD=0 +TXPLLMULT=25X +TX_DATA_WIDTH=8/10-Bit +TX_FICLK_RATE=125.0000 +TX_LINE_RATE=1.2500 +TX_MAX_RATE=1.25 +TX_RATE_DIV=Full Rate +VHDL=0 +Verilog=1 +[FilesGenerated] +sgmii0.pp=pp +sgmii0.sym=sym +sgmii0.tft=tft +sgmii0.txt=pcs_module +[SYSTEMPNR] +LN0=DCU0_CH0 diff --git a/clarity/pcs/sgmii0/sgmii0.v b/clarity/pcs/sgmii0/sgmii0.v new file mode 100644 index 0000000..e2b5903 --- /dev/null +++ b/clarity/pcs/sgmii0/sgmii0.v @@ -0,0 +1,439 @@ +// Verilog netlist produced by program ASBGen: Ports rev. 2.30, Attr. rev. 2.70 +// Netlist written on Sun Nov 18 17:44:07 2018 +// +// Verilog Description of module sgmii0 +// + +`timescale 1ns/1ps +module sgmii0 (hdoutp, hdoutn, hdinp, hdinn, rxrefclk, + tx_pclk, txi_clk, txdata, tx_k, xmit, tx_disp_correct, + rxdata, rx_k, rx_disp_err, rx_cv_err, signal_detect_c, + rx_los_low_s, lsm_status_s, ctc_urun_s, ctc_orun_s, rx_cdr_lol_s, + ctc_ins_s, ctc_del_s, tx_pcs_rst_c, rx_pcs_rst_c, rx_serdes_rst_c, + tx_pwrup_c, rx_pwrup_c, sci_wrdata, sci_addr, sci_rddata, + sci_en_dual, sci_sel_dual, sci_en, sci_sel, sci_rd, sci_wrn, + sci_int, cyawstn, rst_dual_c, serdes_rst_dual_c, serdes_pdb, + tx_serdes_rst_c, pll_refclki, sli_rst, pll_lol); + output hdoutp; + output hdoutn; + input hdinp; + input hdinn; + input rxrefclk; + output tx_pclk; + input txi_clk; + input [7:0]txdata; + input [0:0]tx_k; + input [0:0]xmit; + input [0:0]tx_disp_correct; + output [7:0]rxdata; + output [0:0]rx_k; + output [0:0]rx_disp_err; + output [0:0]rx_cv_err; + input signal_detect_c; + output rx_los_low_s; + output lsm_status_s; + output ctc_urun_s; + output ctc_orun_s; + output rx_cdr_lol_s; + output ctc_ins_s; + output ctc_del_s; + input tx_pcs_rst_c; + input rx_pcs_rst_c; + input rx_serdes_rst_c; + input tx_pwrup_c; + input rx_pwrup_c; + input [7:0]sci_wrdata; + input [5:0]sci_addr; + output [7:0]sci_rddata; + input sci_en_dual; + input sci_sel_dual; + input sci_en; + input sci_sel; + input sci_rd; + input sci_wrn; + output sci_int; + input cyawstn; + input rst_dual_c; + input serdes_rst_dual_c; + input serdes_pdb; + input tx_serdes_rst_c; + input pll_refclki; + input sli_rst; + output pll_lol; + + + wire n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, + n12, n13, n14, n15, n16, n17, n18, n19, n20, n21, + n22, n23, n24, n25, n26, n27, n28, n29, n30, n31, + n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, + n42, n43, n46, n47, n48, n49, n50, n51, n52, n53, + n54, n55, n56, n57, n58, n59, n60, n61, n62, n63, + n64, n65, n66, n67, n68, n69, n70, n71, n72, n73, + n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, + n84, n85, n86, n87, n88, n89, n90, n91, n92, n93, + n94, n95, n96, n97, n98, n99, n100, n101, _Z; + + DCUA DCU0_inst (.CH0_HDINP(hdinp), .CH1_HDINP(1'b0), .CH0_HDINN(hdinn), + .CH1_HDINN(1'b0), .D_TXBIT_CLKP_FROM_ND(1'b0), .D_TXBIT_CLKN_FROM_ND(1'b0), + .D_SYNC_ND(1'b0), .D_TXPLL_LOL_FROM_ND(1'b0), .CH0_RX_REFCLK(rxrefclk), + .CH1_RX_REFCLK(1'b0), .CH0_FF_RXI_CLK(tx_pclk), .CH1_FF_RXI_CLK(1'b1), + .CH0_FF_TXI_CLK(txi_clk), .CH1_FF_TXI_CLK(1'b1), .CH0_FF_EBRD_CLK(tx_pclk), + .CH1_FF_EBRD_CLK(1'b1), .CH0_FF_TX_D_0(txdata[0]), .CH1_FF_TX_D_0(1'b0), + .CH0_FF_TX_D_1(txdata[1]), .CH1_FF_TX_D_1(1'b0), .CH0_FF_TX_D_2(txdata[2]), + .CH1_FF_TX_D_2(1'b0), .CH0_FF_TX_D_3(txdata[3]), .CH1_FF_TX_D_3(1'b0), + .CH0_FF_TX_D_4(txdata[4]), .CH1_FF_TX_D_4(1'b0), .CH0_FF_TX_D_5(txdata[5]), + .CH1_FF_TX_D_5(1'b0), .CH0_FF_TX_D_6(txdata[6]), .CH1_FF_TX_D_6(1'b0), + .CH0_FF_TX_D_7(txdata[7]), .CH1_FF_TX_D_7(1'b0), .CH0_FF_TX_D_8(tx_k[0]), + .CH1_FF_TX_D_8(1'b0), .CH0_FF_TX_D_9(1'b0), .CH1_FF_TX_D_9(1'b0), + .CH0_FF_TX_D_10(xmit[0]), .CH1_FF_TX_D_10(1'b0), .CH0_FF_TX_D_11(tx_disp_correct[0]), + .CH1_FF_TX_D_11(1'b0), .CH0_FF_TX_D_12(1'b0), .CH1_FF_TX_D_12(1'b0), + .CH0_FF_TX_D_13(1'b0), .CH1_FF_TX_D_13(1'b0), .CH0_FF_TX_D_14(1'b0), + .CH1_FF_TX_D_14(1'b0), .CH0_FF_TX_D_15(1'b0), .CH1_FF_TX_D_15(1'b0), + .CH0_FF_TX_D_16(1'b0), .CH1_FF_TX_D_16(1'b0), .CH0_FF_TX_D_17(1'b0), + .CH1_FF_TX_D_17(1'b0), .CH0_FF_TX_D_18(1'b0), .CH1_FF_TX_D_18(1'b0), + .CH0_FF_TX_D_19(1'b0), .CH1_FF_TX_D_19(1'b0), .CH0_FF_TX_D_20(1'b0), + .CH1_FF_TX_D_20(1'b0), .CH0_FF_TX_D_21(1'b0), .CH1_FF_TX_D_21(1'b0), + .CH0_FF_TX_D_22(1'b0), .CH1_FF_TX_D_22(1'b0), .CH0_FF_TX_D_23(1'b0), + .CH1_FF_TX_D_23(1'b0), .CH0_FFC_EI_EN(1'b0), .CH1_FFC_EI_EN(1'b0), + .CH0_FFC_PCIE_DET_EN(1'b0), .CH1_FFC_PCIE_DET_EN(1'b0), .CH0_FFC_PCIE_CT(1'b0), + .CH1_FFC_PCIE_CT(1'b0), .CH0_FFC_SB_INV_RX(1'b0), .CH1_FFC_SB_INV_RX(1'b0), + .CH0_FFC_ENABLE_CGALIGN(1'b0), .CH1_FFC_ENABLE_CGALIGN(1'b0), .CH0_FFC_SIGNAL_DETECT(signal_detect_c), + .CH1_FFC_SIGNAL_DETECT(1'b0), .CH0_FFC_FB_LOOPBACK(1'b0), .CH1_FFC_FB_LOOPBACK(1'b0), + .CH0_FFC_SB_PFIFO_LP(1'b0), .CH1_FFC_SB_PFIFO_LP(1'b0), .CH0_FFC_PFIFO_CLR(1'b0), + .CH1_FFC_PFIFO_CLR(1'b0), .CH0_FFC_RATE_MODE_RX(1'b0), .CH1_FFC_RATE_MODE_RX(1'b0), + .CH0_FFC_RATE_MODE_TX(1'b0), .CH1_FFC_RATE_MODE_TX(1'b0), .CH0_FFC_DIV11_MODE_RX(1'b0), + .CH1_FFC_DIV11_MODE_RX(1'b0), .CH0_FFC_DIV11_MODE_TX(1'b0), .CH1_FFC_DIV11_MODE_TX(1'b0), + .CH0_FFC_RX_GEAR_MODE(1'b0), .CH1_FFC_RX_GEAR_MODE(1'b0), .CH0_FFC_TX_GEAR_MODE(1'b0), + .CH1_FFC_TX_GEAR_MODE(1'b0), .CH0_FFC_LDR_CORE2TX_EN(1'b0), .CH1_FFC_LDR_CORE2TX_EN(1'b0), + .CH0_FFC_LANE_TX_RST(tx_pcs_rst_c), .CH1_FFC_LANE_TX_RST(1'b0), + .CH0_FFC_LANE_RX_RST(rx_pcs_rst_c), .CH1_FFC_LANE_RX_RST(1'b0), + .CH0_FFC_RRST(rx_serdes_rst_c), .CH1_FFC_RRST(1'b0), .CH0_FFC_TXPWDNB(tx_pwrup_c), + .CH1_FFC_TXPWDNB(1'b0), .CH0_FFC_RXPWDNB(rx_pwrup_c), .CH1_FFC_RXPWDNB(1'b0), + .CH0_LDR_CORE2TX(1'b0), .CH1_LDR_CORE2TX(1'b0), .D_SCIWDATA0(sci_wrdata[0]), + .D_SCIWDATA1(sci_wrdata[1]), .D_SCIWDATA2(sci_wrdata[2]), .D_SCIWDATA3(sci_wrdata[3]), + .D_SCIWDATA4(sci_wrdata[4]), .D_SCIWDATA5(sci_wrdata[5]), .D_SCIWDATA6(sci_wrdata[6]), + .D_SCIWDATA7(sci_wrdata[7]), .D_SCIADDR0(sci_addr[0]), .D_SCIADDR1(sci_addr[1]), + .D_SCIADDR2(sci_addr[2]), .D_SCIADDR3(sci_addr[3]), .D_SCIADDR4(sci_addr[4]), + .D_SCIADDR5(sci_addr[5]), .D_SCIENAUX(sci_en_dual), .D_SCISELAUX(sci_sel_dual), + .CH0_SCIEN(sci_en), .CH1_SCIEN(1'b0), .CH0_SCISEL(sci_sel), .CH1_SCISEL(1'b0), + .D_SCIRD(sci_rd), .D_SCIWSTN(sci_wrn), .D_CYAWSTN(cyawstn), .D_FFC_SYNC_TOGGLE(1'b0), + .D_FFC_DUAL_RST(rst_dual_c), .D_FFC_MACRO_RST(serdes_rst_dual_c), + .D_FFC_MACROPDB(serdes_pdb), .D_FFC_TRST(tx_serdes_rst_c), .CH0_FFC_CDR_EN_BITSLIP(1'b0), + .CH1_FFC_CDR_EN_BITSLIP(1'b0), .D_SCAN_ENABLE(1'b0), .D_SCAN_IN_0(1'b0), + .D_SCAN_IN_1(1'b0), .D_SCAN_IN_2(1'b0), .D_SCAN_IN_3(1'b0), .D_SCAN_IN_4(1'b0), + .D_SCAN_IN_5(1'b0), .D_SCAN_IN_6(1'b0), .D_SCAN_IN_7(1'b0), .D_SCAN_MODE(1'b0), + .D_SCAN_RESET(1'b0), .D_CIN0(1'b0), .D_CIN1(1'b0), .D_CIN2(1'b0), + .D_CIN3(1'b0), .D_CIN4(1'b0), .D_CIN5(1'b0), .D_CIN6(1'b0), + .D_CIN7(1'b0), .D_CIN8(1'b0), .D_CIN9(1'b0), .D_CIN10(1'b0), + .D_CIN11(1'b0), .CH0_HDOUTP(hdoutp), .CH1_HDOUTP(n47), .CH0_HDOUTN(hdoutn), + .CH1_HDOUTN(n48), .D_TXBIT_CLKP_TO_ND(n1), .D_TXBIT_CLKN_TO_ND(n2), + .D_SYNC_PULSE2ND(n3), .D_TXPLL_LOL_TO_ND(n4), .CH0_FF_RX_F_CLK(n5), + .CH1_FF_RX_F_CLK(n49), .CH0_FF_RX_H_CLK(n6), .CH1_FF_RX_H_CLK(n50), + .CH0_FF_TX_F_CLK(n7), .CH1_FF_TX_F_CLK(n51), .CH0_FF_TX_H_CLK(n8), + .CH1_FF_TX_H_CLK(n52), .CH0_FF_RX_PCLK(n9), .CH1_FF_RX_PCLK(n53), + .CH0_FF_TX_PCLK(tx_pclk), .CH1_FF_TX_PCLK(n54), .CH0_FF_RX_D_0(rxdata[0]), + .CH1_FF_RX_D_0(n55), .CH0_FF_RX_D_1(rxdata[1]), .CH1_FF_RX_D_1(n56), + .CH0_FF_RX_D_2(rxdata[2]), .CH1_FF_RX_D_2(n57), .CH0_FF_RX_D_3(rxdata[3]), + .CH1_FF_RX_D_3(n58), .CH0_FF_RX_D_4(rxdata[4]), .CH1_FF_RX_D_4(n59), + .CH0_FF_RX_D_5(rxdata[5]), .CH1_FF_RX_D_5(n60), .CH0_FF_RX_D_6(rxdata[6]), + .CH1_FF_RX_D_6(n61), .CH0_FF_RX_D_7(rxdata[7]), .CH1_FF_RX_D_7(n62), + .CH0_FF_RX_D_8(rx_k[0]), .CH1_FF_RX_D_8(n63), .CH0_FF_RX_D_9(rx_disp_err[0]), + .CH1_FF_RX_D_9(n64), .CH0_FF_RX_D_10(rx_cv_err[0]), .CH1_FF_RX_D_10(n65), + .CH0_FF_RX_D_11(n10), .CH1_FF_RX_D_11(n66), .CH0_FF_RX_D_12(n67), + .CH1_FF_RX_D_12(n68), .CH0_FF_RX_D_13(n69), .CH1_FF_RX_D_13(n70), + .CH0_FF_RX_D_14(n71), .CH1_FF_RX_D_14(n72), .CH0_FF_RX_D_15(n73), + .CH1_FF_RX_D_15(n74), .CH0_FF_RX_D_16(n75), .CH1_FF_RX_D_16(n76), + .CH0_FF_RX_D_17(n77), .CH1_FF_RX_D_17(n78), .CH0_FF_RX_D_18(n79), + .CH1_FF_RX_D_18(n80), .CH0_FF_RX_D_19(n81), .CH1_FF_RX_D_19(n82), + .CH0_FF_RX_D_20(n83), .CH1_FF_RX_D_20(n84), .CH0_FF_RX_D_21(n85), + .CH1_FF_RX_D_21(n86), .CH0_FF_RX_D_22(n87), .CH1_FF_RX_D_22(n88), + .CH0_FF_RX_D_23(n11), .CH1_FF_RX_D_23(n89), .CH0_FFS_PCIE_DONE(n12), + .CH1_FFS_PCIE_DONE(n90), .CH0_FFS_PCIE_CON(n13), .CH1_FFS_PCIE_CON(n91), + .CH0_FFS_RLOS(rx_los_low_s), .CH1_FFS_RLOS(n92), .CH0_FFS_LS_SYNC_STATUS(lsm_status_s), + .CH1_FFS_LS_SYNC_STATUS(n93), .CH0_FFS_CC_UNDERRUN(ctc_urun_s), + .CH1_FFS_CC_UNDERRUN(n94), .CH0_FFS_CC_OVERRUN(ctc_orun_s), .CH1_FFS_CC_OVERRUN(n95), + .CH0_FFS_RXFBFIFO_ERROR(n14), .CH1_FFS_RXFBFIFO_ERROR(n96), .CH0_FFS_TXFBFIFO_ERROR(n15), + .CH1_FFS_TXFBFIFO_ERROR(n97), .CH0_FFS_RLOL(rx_cdr_lol_s), .CH1_FFS_RLOL(n98), + .CH0_FFS_SKP_ADDED(ctc_ins_s), .CH1_FFS_SKP_ADDED(n99), .CH0_FFS_SKP_DELETED(ctc_del_s), + .CH1_FFS_SKP_DELETED(n100), .CH0_LDR_RX2CORE(n101), .CH1_LDR_RX2CORE(_Z), + .D_SCIRDATA0(sci_rddata[0]), .D_SCIRDATA1(sci_rddata[1]), .D_SCIRDATA2(sci_rddata[2]), + .D_SCIRDATA3(sci_rddata[3]), .D_SCIRDATA4(sci_rddata[4]), .D_SCIRDATA5(sci_rddata[5]), + .D_SCIRDATA6(sci_rddata[6]), .D_SCIRDATA7(sci_rddata[7]), .D_SCIINT(sci_int), + .D_SCAN_OUT_0(n16), .D_SCAN_OUT_1(n17), .D_SCAN_OUT_2(n18), .D_SCAN_OUT_3(n19), + .D_SCAN_OUT_4(n20), .D_SCAN_OUT_5(n21), .D_SCAN_OUT_6(n22), .D_SCAN_OUT_7(n23), + .D_COUT0(n24), .D_COUT1(n25), .D_COUT2(n26), .D_COUT3(n27), + .D_COUT4(n28), .D_COUT5(n29), .D_COUT6(n30), .D_COUT7(n31), + .D_COUT8(n32), .D_COUT9(n33), .D_COUT10(n34), .D_COUT11(n35), + .D_COUT12(n36), .D_COUT13(n37), .D_COUT14(n38), .D_COUT15(n39), + .D_COUT16(n40), .D_COUT17(n41), .D_COUT18(n42), .D_COUT19(n43), + .D_REFCLKI(pll_refclki), .D_FFS_PLOL(pll_lol)) /* synthesis LOC=DCU0 CHAN=CH0 */ ; + defparam DCU0_inst.D_MACROPDB = "0b1"; + defparam DCU0_inst.D_IB_PWDNB = "0b1"; + defparam DCU0_inst.D_XGE_MODE = "0b0"; + defparam DCU0_inst.D_LOW_MARK = "0d4"; + defparam DCU0_inst.D_HIGH_MARK = "0d12"; + defparam DCU0_inst.D_BUS8BIT_SEL = "0b0"; + defparam DCU0_inst.D_CDR_LOL_SET = "0b00"; + defparam DCU0_inst.D_TXPLL_PWDNB = "0b1"; + defparam DCU0_inst.D_BITCLK_LOCAL_EN = "0b1"; + defparam DCU0_inst.D_BITCLK_ND_EN = "0b0"; + defparam DCU0_inst.D_BITCLK_FROM_ND_EN = "0b0"; + defparam DCU0_inst.D_SYNC_LOCAL_EN = "0b1"; + defparam DCU0_inst.D_SYNC_ND_EN = "0b0"; + defparam DCU0_inst.CH0_UC_MODE = "0b0"; + defparam DCU0_inst.CH0_PCIE_MODE = "0b0"; + defparam DCU0_inst.CH0_RIO_MODE = "0b0"; + defparam DCU0_inst.CH0_WA_MODE = "0b0"; + defparam DCU0_inst.CH0_INVERT_RX = "0b1"; + defparam DCU0_inst.CH0_INVERT_TX = "0b1"; + defparam DCU0_inst.CH0_PRBS_SELECTION = "0b0"; + defparam DCU0_inst.CH0_GE_AN_ENABLE = "0b0"; + defparam DCU0_inst.CH0_PRBS_LOCK = "0b0"; + defparam DCU0_inst.CH0_PRBS_ENABLE = "0b0"; + defparam DCU0_inst.CH0_ENABLE_CG_ALIGN = "0b1"; + defparam DCU0_inst.CH0_TX_GEAR_MODE = "0b0"; + defparam DCU0_inst.CH0_RX_GEAR_MODE = "0b0"; + defparam DCU0_inst.CH0_PCS_DET_TIME_SEL = "0b00"; + defparam DCU0_inst.CH0_PCIE_EI_EN = "0b0"; + defparam DCU0_inst.CH0_TX_GEAR_BYPASS = "0b0"; + defparam DCU0_inst.CH0_ENC_BYPASS = "0b0"; + defparam DCU0_inst.CH0_SB_BYPASS = "0b0"; + defparam DCU0_inst.CH0_RX_SB_BYPASS = "0b0"; + defparam DCU0_inst.CH0_WA_BYPASS = "0b0"; + defparam DCU0_inst.CH0_DEC_BYPASS = "0b0"; + defparam DCU0_inst.CH0_CTC_BYPASS = "0b0"; + defparam DCU0_inst.CH0_RX_GEAR_BYPASS = "0b0"; + defparam DCU0_inst.CH0_LSM_DISABLE = "0b0"; + defparam DCU0_inst.CH0_MATCH_2_ENABLE = "0b1"; + defparam DCU0_inst.CH0_MATCH_4_ENABLE = "0b0"; + defparam DCU0_inst.CH0_MIN_IPG_CNT = "0b11"; + defparam DCU0_inst.CH0_CC_MATCH_1 = "0x000"; + defparam DCU0_inst.CH0_CC_MATCH_2 = "0x000"; + defparam DCU0_inst.CH0_CC_MATCH_3 = "0x1BC"; + defparam DCU0_inst.CH0_CC_MATCH_4 = "0x050"; + defparam DCU0_inst.CH0_UDF_COMMA_MASK = "0x3ff"; + defparam DCU0_inst.CH0_UDF_COMMA_A = "0x283"; + defparam DCU0_inst.CH0_UDF_COMMA_B = "0x17C"; + defparam DCU0_inst.CH0_RX_DCO_CK_DIV = "0b010"; + defparam DCU0_inst.CH0_RCV_DCC_EN = "0b0"; + defparam DCU0_inst.CH0_TPWDNB = "0b1"; + defparam DCU0_inst.CH0_RATE_MODE_TX = "0b0"; + defparam DCU0_inst.CH0_RTERM_TX = "0d19"; + defparam DCU0_inst.CH0_TX_CM_SEL = "0b00"; + defparam DCU0_inst.CH0_TDRV_PRE_EN = "0b0"; + defparam DCU0_inst.CH0_TDRV_SLICE0_SEL = "0b00"; + defparam DCU0_inst.CH0_TDRV_SLICE1_SEL = "0b00"; + defparam DCU0_inst.CH0_TDRV_SLICE2_SEL = "0b01"; + defparam DCU0_inst.CH0_TDRV_SLICE3_SEL = "0b01"; + defparam DCU0_inst.CH0_TDRV_SLICE4_SEL = "0b00"; + defparam DCU0_inst.CH0_TDRV_SLICE5_SEL = "0b00"; + defparam DCU0_inst.CH0_TDRV_SLICE0_CUR = "0b000"; + defparam DCU0_inst.CH0_TDRV_SLICE1_CUR = "0b000"; + defparam DCU0_inst.CH0_TDRV_SLICE2_CUR = "0b11"; + defparam DCU0_inst.CH0_TDRV_SLICE3_CUR = "0b00"; + defparam DCU0_inst.CH0_TDRV_SLICE4_CUR = "0b00"; + defparam DCU0_inst.CH0_TDRV_SLICE5_CUR = "0b00"; + defparam DCU0_inst.CH0_TDRV_DAT_SEL = "0b00"; + defparam DCU0_inst.CH0_TX_DIV11_SEL = "0b0"; + defparam DCU0_inst.CH0_RPWDNB = "0b1"; + defparam DCU0_inst.CH0_RATE_MODE_RX = "0b0"; + defparam DCU0_inst.CH0_RX_DIV11_SEL = "0b0"; + defparam DCU0_inst.CH0_SEL_SD_RX_CLK = "0b0"; + defparam DCU0_inst.CH0_FF_RX_H_CLK_EN = "0b0"; + defparam DCU0_inst.CH0_FF_RX_F_CLK_DIS = "0b0"; + defparam DCU0_inst.CH0_FF_TX_H_CLK_EN = "0b0"; + defparam DCU0_inst.CH0_FF_TX_F_CLK_DIS = "0b0"; + defparam DCU0_inst.CH0_TDRV_POST_EN = "0b0"; + defparam DCU0_inst.CH0_TX_POST_SIGN = "0b0"; + defparam DCU0_inst.CH0_TX_PRE_SIGN = "0b0"; + defparam DCU0_inst.CH0_REQ_LVL_SET = "0b00"; + defparam DCU0_inst.CH0_REQ_EN = "0b1"; + defparam DCU0_inst.CH0_RTERM_RX = "0d22"; + defparam DCU0_inst.CH0_RXTERM_CM = "0b11"; + defparam DCU0_inst.CH0_PDEN_SEL = "0b1"; + defparam DCU0_inst.CH0_RXIN_CM = "0b11"; + defparam DCU0_inst.CH0_LEQ_OFFSET_SEL = "0b0"; + defparam DCU0_inst.CH0_LEQ_OFFSET_TRIM = "0b000"; + defparam DCU0_inst.CH0_RLOS_SEL = "0b1"; + defparam DCU0_inst.CH0_RX_LOS_LVL = "0b100"; + defparam DCU0_inst.CH0_RX_LOS_CEQ = "0b11"; + defparam DCU0_inst.CH0_RX_LOS_HYST_EN = "0b0"; + defparam DCU0_inst.CH0_RX_LOS_EN = "0b1"; + defparam DCU0_inst.CH0_LDR_RX2CORE_SEL = "0b0"; + defparam DCU0_inst.CH0_LDR_CORE2TX_SEL = "0b0"; + defparam DCU0_inst.D_TX_MAX_RATE = "1.25"; + defparam DCU0_inst.CH0_CDR_MAX_RATE = "1.25"; + defparam DCU0_inst.CH0_TXAMPLITUDE = "0d400"; + defparam DCU0_inst.CH0_TXDEPRE = "DISABLED"; + defparam DCU0_inst.CH0_TXDEPOST = "DISABLED"; + defparam DCU0_inst.CH0_PROTOCOL = "GBE"; + defparam DCU0_inst.D_ISETLOS = "0d0"; + defparam DCU0_inst.D_SETIRPOLY_AUX = "0b00"; + defparam DCU0_inst.D_SETICONST_AUX = "0b00"; + defparam DCU0_inst.D_SETIRPOLY_CH = "0b00"; + defparam DCU0_inst.D_SETICONST_CH = "0b00"; + defparam DCU0_inst.D_REQ_ISET = "0b000"; + defparam DCU0_inst.D_PD_ISET = "0b00"; + defparam DCU0_inst.D_DCO_CALIB_TIME_SEL = "0b00"; + defparam DCU0_inst.CH0_CDR_CNT4SEL = "0b00"; + defparam DCU0_inst.CH0_CDR_CNT8SEL = "0b00"; + defparam DCU0_inst.CH0_DCOATDCFG = "0b00"; + defparam DCU0_inst.CH0_DCOATDDLY = "0b00"; + defparam DCU0_inst.CH0_DCOBYPSATD = "0b1"; + defparam DCU0_inst.CH0_DCOCALDIV = "0b001"; + defparam DCU0_inst.CH0_DCOCTLGI = "0b010"; + defparam DCU0_inst.CH0_DCODISBDAVOID = "0b0"; + defparam DCU0_inst.CH0_DCOFLTDAC = "0b01"; + defparam DCU0_inst.CH0_DCOFTNRG = "0b110"; + defparam DCU0_inst.CH0_DCOIOSTUNE = "0b000"; + defparam DCU0_inst.CH0_DCOITUNE = "0b00"; + defparam DCU0_inst.CH0_DCOITUNE4LSB = "0b111"; + defparam DCU0_inst.CH0_DCOIUPDNX2 = "0b1"; + defparam DCU0_inst.CH0_DCONUOFLSB = "0b101"; + defparam DCU0_inst.CH0_DCOSCALEI = "0b00"; + defparam DCU0_inst.CH0_DCOSTARTVAL = "0b000"; + defparam DCU0_inst.CH0_DCOSTEP = "0b00"; + defparam DCU0_inst.CH0_BAND_THRESHOLD = "0d0"; + defparam DCU0_inst.CH0_AUTO_FACQ_EN = "0b1"; + defparam DCU0_inst.CH0_AUTO_CALIB_EN = "0b1"; + defparam DCU0_inst.CH0_CALIB_CK_MODE = "0b0"; + defparam DCU0_inst.CH0_REG_BAND_OFFSET = "0d0"; + defparam DCU0_inst.CH0_REG_BAND_SEL = "0d0"; + defparam DCU0_inst.CH0_REG_IDAC_SEL = "0d0"; + defparam DCU0_inst.CH0_REG_IDAC_EN = "0b0"; + defparam DCU0_inst.D_CMUSETISCL4VCO = "0b000"; + defparam DCU0_inst.D_CMUSETI4VCO = "0b00"; + defparam DCU0_inst.D_CMUSETINITVCT = "0b00"; + defparam DCU0_inst.D_CMUSETZGM = "0b000"; + defparam DCU0_inst.D_CMUSETP2AGM = "0b000"; + defparam DCU0_inst.D_CMUSETP1GM = "0b000"; + defparam DCU0_inst.D_CMUSETI4CPZ = "0d3"; + defparam DCU0_inst.D_CMUSETI4CPP = "0d3"; + defparam DCU0_inst.D_CMUSETICP4Z = "0b101"; + defparam DCU0_inst.D_CMUSETICP4P = "0b01"; + defparam DCU0_inst.D_CMUSETBIASI = "0b00"; + defparam DCU0_inst.D_SETPLLRC = "0d1"; + defparam DCU0_inst.CH0_RX_RATE_SEL = "0d8"; + defparam DCU0_inst.D_REFCK_MODE = "0b100"; + defparam DCU0_inst.D_TX_VCO_CK_DIV = "0b010"; + defparam DCU0_inst.D_PLL_LOL_SET = "0b00"; + defparam DCU0_inst.D_RG_EN = "0b0"; + defparam DCU0_inst.D_RG_SET = "0b00"; + assign n1 = 1'bz; + assign n2 = 1'bz; + assign n3 = 1'bz; + assign n4 = 1'bz; + assign n5 = 1'bz; + assign n6 = 1'bz; + assign n7 = 1'bz; + assign n8 = 1'bz; + assign n9 = 1'bz; + assign n10 = 1'bz; + assign n11 = 1'bz; + assign n12 = 1'bz; + assign n13 = 1'bz; + assign n14 = 1'bz; + assign n15 = 1'bz; + assign n16 = 1'bz; + assign n17 = 1'bz; + assign n18 = 1'bz; + assign n19 = 1'bz; + assign n20 = 1'bz; + assign n21 = 1'bz; + assign n22 = 1'bz; + assign n23 = 1'bz; + assign n24 = 1'bz; + assign n25 = 1'bz; + assign n26 = 1'bz; + assign n27 = 1'bz; + assign n28 = 1'bz; + assign n29 = 1'bz; + assign n30 = 1'bz; + assign n31 = 1'bz; + assign n32 = 1'bz; + assign n33 = 1'bz; + assign n34 = 1'bz; + assign n35 = 1'bz; + assign n36 = 1'bz; + assign n37 = 1'bz; + assign n38 = 1'bz; + assign n39 = 1'bz; + assign n40 = 1'bz; + assign n41 = 1'bz; + assign n42 = 1'bz; + assign n43 = 1'bz; + assign n46 = 1'bz; + assign n47 = 1'bz; + assign n48 = 1'bz; + assign n49 = 1'bz; + assign n50 = 1'bz; + assign n51 = 1'bz; + assign n52 = 1'bz; + assign n53 = 1'bz; + assign n54 = 1'bz; + assign n55 = 1'bz; + assign n56 = 1'bz; + assign n57 = 1'bz; + assign n58 = 1'bz; + assign n59 = 1'bz; + assign n60 = 1'bz; + assign n61 = 1'bz; + assign n62 = 1'bz; + assign n63 = 1'bz; + assign n64 = 1'bz; + assign n65 = 1'bz; + assign n66 = 1'bz; + assign n67 = 1'bz; + assign n68 = 1'bz; + assign n69 = 1'bz; + assign n70 = 1'bz; + assign n71 = 1'bz; + assign n72 = 1'bz; + assign n73 = 1'bz; + assign n74 = 1'bz; + assign n75 = 1'bz; + assign n76 = 1'bz; + assign n77 = 1'bz; + assign n78 = 1'bz; + assign n79 = 1'bz; + assign n80 = 1'bz; + assign n81 = 1'bz; + assign n82 = 1'bz; + assign n83 = 1'bz; + assign n84 = 1'bz; + assign n85 = 1'bz; + assign n86 = 1'bz; + assign n87 = 1'bz; + assign n88 = 1'bz; + assign n89 = 1'bz; + assign n90 = 1'bz; + assign n91 = 1'bz; + assign n92 = 1'bz; + assign n93 = 1'bz; + assign n94 = 1'bz; + assign n95 = 1'bz; + assign n96 = 1'bz; + assign n97 = 1'bz; + assign n98 = 1'bz; + assign n99 = 1'bz; + assign n100 = 1'bz; + assign n101 = 1'bz; + assign _Z = 1'bz; + sgmii0sll_core sll_inst (.sli_rst(sli_rst), .sli_refclk(pll_refclki), + .sli_pclk(tx_pclk), .sli_div2_rate(1'b0), .sli_div11_rate(1'b0), + .sli_gear_mode(1'b0), .sli_cpri_mode({3'b000}), .sli_pcie_mode(1'b0), + .slo_plol()); + defparam sll_inst.PPROTOCOL = "GBE"; + defparam sll_inst.PLOL_SETTING = 0; + defparam sll_inst.PDYN_RATE_CTRL = "DISABLED"; + defparam sll_inst.PPCIE_MAX_RATE = "2.5"; + defparam sll_inst.PDIFF_VAL_LOCK = 98; + defparam sll_inst.PDIFF_VAL_UNLOCK = 196; + defparam sll_inst.PPCLK_TC = 327680; + defparam sll_inst.PDIFF_DIV11_VAL_LOCK = 0; + defparam sll_inst.PDIFF_DIV11_VAL_UNLOCK = 0; + defparam sll_inst.PPCLK_DIV11_TC = 0; + +endmodule + + diff --git a/clarity/pcs/sgmii0/sgmii0_softlogic.v b/clarity/pcs/sgmii0/sgmii0_softlogic.v new file mode 100644 index 0000000..74972ff --- /dev/null +++ b/clarity/pcs/sgmii0/sgmii0_softlogic.v @@ -0,0 +1,1060 @@ + +// =========================================================================== +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< +// --------------------------------------------------------------------------- +// Copyright (c) 2015 by Lattice Semiconductor Corporation +// ALL RIGHTS RESERVED +// ------------------------------------------------------------------ +// +// Permission: +// +// Lattice SG Pte. Ltd. grants permission to use this code +// pursuant to the terms of the Lattice Reference Design License Agreement. +// +// +// Disclaimer: +// +// This VHDL or Verilog source code is intended as a design reference +// which illustrates how these types of functions can be implemented. +// It is the user's responsibility to verify their design for +// consistency and functionality through the use of formal +// verification methods. Lattice provides no warranty +// regarding the use or functionality of this code. +// +// --------------------------------------------------------------------------- +// +// Lattice SG Pte. Ltd. +// 101 Thomson Road, United Square #07-02 +// Singapore 307591 +// +// +// TEL: 1-800-Lattice (USA and Canada) +// +65-6631-2000 (Singapore) +// +1-503-268-8001 (other locations) +// +// web: http://www.latticesemi.com/ +// email: techsupport@latticesemi.com +// +// --------------------------------------------------------------------------- +// +// ============================================================================= +// FILE DETAILS +// Project : SLL - Soft Loss Of Lock(LOL) Logic +// File : sll_core.v +// Title : Top-level file for SLL +// Dependencies : 1. +// : 2. +// Description : +// ============================================================================= +// REVISION HISTORY +// Version : 1.0 +// Author(s) : AV +// Mod. Date : March 2, 2015 +// Changes Made : Initial Creation +// ============================================================================= +// REVISION HISTORY +// Version : 1.1 +// Author(s) : AV +// Mod. Date : June 8, 2015 +// Changes Made : Following updates were made +// : 1. Changed all the PLOL status logic and FSM to run +// : on sli_refclk. +// : 2. Added the HB logic for presence of tx_pclk +// : 3. Changed the lparam assignment scheme for +// : simulation purposes. +// ============================================================================= +// REVISION HISTORY +// Version : 1.2 +// Author(s) : AV +// Mod. Date : June 24, 2015 +// Changes Made : Updated the gearing logic for SDI dynamic rate change +// ============================================================================= +// REVISION HISTORY +// Version : 1.3 +// Author(s) : AV +// Mod. Date : July 14, 2015 +// Changes Made : Added the logic for dynamic rate change in CPRI +// ============================================================================= +// REVISION HISTORY +// Version : 1.4 +// Author(s) : AV +// Mod. Date : August 21, 2015 +// Changes Made : Added the logic for dynamic rate change of 5G CPRI & +// PCIe. +// ============================================================================= +// REVISION HISTORY +// Version : 1.5 +// Author(s) : ES/EB +// Mod. Date : March 21, 2017 +// Changes Made : 1. Added pdiff_sync signal to syncrhonize pcount_diff +// : to sli_refclk. +// : 2. Updated terminal count logic for PCIe 5G +// : 3. Modified checking of pcount_diff in SLL state +// : machine to cover actual count +// : (from 16-bits to 22-bits) +// ============================================================================= +// REVISION HISTORY +// Version : 1.6 +// Author(s) : ES +// Mod. Date : April 19, 2017 +// Changes Made : 1. Added registered lock and unlock signal from +// pdiff_sync to totally decouple pcount_diff from +// SLL state machine. +// : 2. Modified LPCLK_TC_4 to 1:1 clock ratio when CPRI +// is operating @ 4.9125Gbps data rate. +// ============================================================================= +`timescale 1ns/10ps + +module sgmii0sll_core ( + //Reset and Clock inputs + sli_rst, //Active high asynchronous reset input + sli_refclk, //Refclk input to the Tx PLL + sli_pclk, //Tx pclk output from the PCS + + //Control inputs + sli_div2_rate, //Divide by 2 control; 0 - Full rate; 1 - Half rate + sli_div11_rate, //Divide by 11 control; 0 - Full rate; 1 - Div by 11 + sli_gear_mode, //Gear mode control for PCS; 0 - 8/10; 1- 16/20 + sli_cpri_mode, //Mode of operation specific to CPRI protocol + sli_pcie_mode, //Mode of operation specific to PCIe mode (2.5G or 5G) + + //LOL Output + slo_plol //Tx PLL Loss of Lock output to the user logic + ); + +// Inputs +input sli_rst; +input sli_refclk; +input sli_pclk; +input sli_div2_rate; +input sli_div11_rate; +input sli_gear_mode; +input [2:0] sli_cpri_mode; +input sli_pcie_mode; + +// Outputs +output slo_plol; + + +// Parameters +parameter PPROTOCOL = "PCIE"; //Protocol selected by the User +parameter PLOL_SETTING = 0; //PLL LOL setting. Possible values are 0,1,2,3 +parameter PDYN_RATE_CTRL = "DISABLED"; //PCS Dynamic Rate control +parameter PPCIE_MAX_RATE = "2.5"; //PCIe max data rate +parameter PDIFF_VAL_LOCK = 20; //Differential count value for Lock +parameter PDIFF_VAL_UNLOCK = 39; //Differential count value for Unlock +parameter PPCLK_TC = 65535; //Terminal count value for counter running on sli_pclk +parameter PDIFF_DIV11_VAL_LOCK = 3; //Differential count value for Lock for SDI Div11 +parameter PDIFF_DIV11_VAL_UNLOCK = 3; //Differential count value for Unlock for SDI Div11 +parameter PPCLK_DIV11_TC = 2383; //Terminal count value (SDI Div11) for counter running on sli_pclk + + +// Local Parameters +localparam [1:0] LPLL_LOSS_ST = 2'b00; //PLL Loss state +localparam [1:0] LPLL_PRELOSS_ST = 2'b01; //PLL Pre-Loss state +localparam [1:0] LPLL_PRELOCK_ST = 2'b10; //PLL Pre-Lock state +localparam [1:0] LPLL_LOCK_ST = 2'b11; //PLL Lock state +`ifdef RSL_SIM_MODE +localparam [15:0] LRCLK_TC = 16'd63; //Terminal count value for counter running on sli_refclk +`else +localparam [15:0] LRCLK_TC = 16'd65535; //Terminal count value for counter running on sli_refclk +`endif +localparam [15:0] LRCLK_TC_PUL_WIDTH = 16'd50; //Pulse width for the Refclk terminal count pulse +localparam [7:0] LHB_WAIT_CNT = 8'd255; //Wait count for the Heartbeat signal + +// Local Parameters related to the CPRI dynamic modes +// Terminal count values for the four CPRI modes +localparam LPCLK_TC_0 = 32768; +localparam LPCLK_TC_1 = 65536; +localparam LPCLK_TC_2 = 131072; +localparam LPCLK_TC_3 = 163840; +localparam LPCLK_TC_4 = 65536; + +// Lock values count values for the four CPRI modes and four PLOL settings (4x5) +// CPRI rate mode 0 CPRI rate mode 1 CPRI rate mode 2 CPRI rate mode 3 CPRI rate mode 4 +localparam LPDIFF_LOCK_00 = 9; localparam LPDIFF_LOCK_10 = 19; localparam LPDIFF_LOCK_20 = 39; localparam LPDIFF_LOCK_30 = 49; localparam LPDIFF_LOCK_40 = 19; +localparam LPDIFF_LOCK_01 = 9; localparam LPDIFF_LOCK_11 = 19; localparam LPDIFF_LOCK_21 = 39; localparam LPDIFF_LOCK_31 = 49; localparam LPDIFF_LOCK_41 = 19; +localparam LPDIFF_LOCK_02 = 49; localparam LPDIFF_LOCK_12 = 98; localparam LPDIFF_LOCK_22 = 196; localparam LPDIFF_LOCK_32 = 245; localparam LPDIFF_LOCK_42 = 98; +localparam LPDIFF_LOCK_03 = 131; localparam LPDIFF_LOCK_13 = 262; localparam LPDIFF_LOCK_23 = 524; localparam LPDIFF_LOCK_33 = 655; localparam LPDIFF_LOCK_43 = 262; + +// Unlock values count values for the four CPRI modes and four PLOL settings (4x5) +// CPRI rate mode 0 CPRI rate mode 1 CPRI rate mode 2 CPRI rate mode 3 CPRI rate mode 4 +localparam LPDIFF_UNLOCK_00 = 19; localparam LPDIFF_UNLOCK_10 = 39; localparam LPDIFF_UNLOCK_20 = 78; localparam LPDIFF_UNLOCK_30 = 98; localparam LPDIFF_UNLOCK_40 = 39; +localparam LPDIFF_UNLOCK_01 = 65; localparam LPDIFF_UNLOCK_11 = 131; localparam LPDIFF_UNLOCK_21 = 262; localparam LPDIFF_UNLOCK_31 = 327; localparam LPDIFF_UNLOCK_41 = 131; +localparam LPDIFF_UNLOCK_02 = 72; localparam LPDIFF_UNLOCK_12 = 144; localparam LPDIFF_UNLOCK_22 = 288; localparam LPDIFF_UNLOCK_32 = 360; localparam LPDIFF_UNLOCK_42 = 144; +localparam LPDIFF_UNLOCK_03 = 196; localparam LPDIFF_UNLOCK_13 = 393; localparam LPDIFF_UNLOCK_23 = 786; localparam LPDIFF_UNLOCK_33 = 983; localparam LPDIFF_UNLOCK_43 = 393; + +// Input and Output reg and wire declarations +wire sli_rst; +wire sli_refclk; +wire sli_pclk; +wire sli_div2_rate; +wire sli_div11_rate; +wire sli_gear_mode; +wire [2:0] sli_cpri_mode; +wire sli_pcie_mode; +wire slo_plol; + +//-------------- Internal signals reg and wire declarations -------------------- + +//Signals running on sli_refclk +reg [15:0] rcount; //16-bit Counter +reg rtc_pul; //Terminal count pulse +reg rtc_pul_p1; //Terminal count pulse pipeline +reg rtc_ctrl; //Terminal count pulse control + +reg [7:0] rhb_wait_cnt; //Heartbeat wait counter + +//Heatbeat synchronization and pipeline registers +wire rhb_sync; +reg rhb_sync_p2; +reg rhb_sync_p1; + +//Pipeling registers for dynamic control mode +wire rgear; +wire rdiv2; +wire rdiv11; +reg rgear_p1; +reg rdiv2_p1; +reg rdiv11_p1; + +reg rstat_pclk; //Pclk presence/absence status + +reg [21:0] rcount_tc; //Tx_pclk terminal count register +reg [15:0] rdiff_comp_lock; //Differential comparison value for Lock +reg [15:0] rdiff_comp_unlock; //Differential compariosn value for Unlock + +wire rpcie_mode; //PCIe mode signal synchronized to refclk +reg rpcie_mode_p1; //PCIe mode pipeline register + +wire rcpri_mod_ch_sync; //CPRI mode change synchronized to refclk +reg rcpri_mod_ch_p1; //CPRI mode change pipeline register +reg rcpri_mod_ch_p2; //CPRI mode change pipeline register +reg rcpri_mod_ch_st; //CPRI mode change status + +reg [1:0] sll_state; //Current-state register for LOL FSM + +reg pll_lock; //PLL Lock signal + +//Signals running on sli_pclk +//Synchronization and pipeline registers +wire ppul_sync; +reg ppul_sync_p1; +reg ppul_sync_p2; +reg ppul_sync_p3; + +wire pdiff_sync; +reg pdiff_sync_p1; + +reg [21:0] pcount; //22-bit counter +reg [21:0] pcount_diff; //Differential value between Tx_pclk counter and theoritical value + +//Heartbeat counter and heartbeat signal running on pclk +reg [2:0] phb_cnt; +reg phb; + +//CPRI dynamic mode releated signals +reg [2:0] pcpri_mode; +reg pcpri_mod_ch; + +//Assignment scheme changed mainly for simulation purpose +wire [15:0] LRCLK_TC_w; +assign LRCLK_TC_w = LRCLK_TC; + +reg unlock; +reg lock; + +//Heartbeat synchronization +sync # (.PDATA_RST_VAL(0)) phb_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (phb), + .data_out(rhb_sync) + ); + + +//Terminal count pulse synchronization +sync # (.PDATA_RST_VAL(0)) rtc_sync_inst ( + .clk (sli_pclk), + .rst (sli_rst), + .data_in (rtc_pul), + .data_out(ppul_sync) + ); + +//Differential value logic update synchronization +sync # (.PDATA_RST_VAL(0)) pdiff_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (ppul_sync), + .data_out(pdiff_sync) + ); + +//Gear mode synchronization +sync # (.PDATA_RST_VAL(0)) gear_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (sli_gear_mode), + .data_out(rgear) + ); + +//Div2 synchronization +sync # (.PDATA_RST_VAL(0)) div2_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (sli_div2_rate), + .data_out(rdiv2) + ); + +//Div11 synchronization +sync # (.PDATA_RST_VAL(0)) div11_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (sli_div11_rate), + .data_out(rdiv11) + ); + +//CPRI mode change synchronization +sync # (.PDATA_RST_VAL(0)) cpri_mod_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (pcpri_mod_ch), + .data_out(rcpri_mod_ch_sync) + ); + +//PCIe mode change synchronization +sync # (.PDATA_RST_VAL(0)) pcie_mod_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (sli_pcie_mode), + .data_out(rpcie_mode) + ); + +// ============================================================================= +// Synchronized Lock/Unlock signals +// ============================================================================= +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + unlock <= 1'b0; + lock <= 1'b0; + pdiff_sync_p1 <= 1'b0; + end + else begin + pdiff_sync_p1 <= pdiff_sync; + if (unlock) begin + unlock <= ~pdiff_sync && pdiff_sync_p1 ? 1'b0 : unlock; + end + else begin + unlock <= pdiff_sync ? (pcount_diff[21:0] > {6'd0, rdiff_comp_unlock}) : 1'b0; + end + if (lock) begin + lock <= ~pdiff_sync && pdiff_sync_p1 ? 1'b0 : lock; + end + else begin + lock <= pdiff_sync ? (pcount_diff[21:0] <= {6'd0, rdiff_comp_lock}) : 1'b0; + end + end +end + +// ============================================================================= +// Refclk Counter, pulse generation logic and Heartbeat monitor logic +// ============================================================================= +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rcount <= 16'd0; + rtc_pul <= 1'b0; + rtc_ctrl <= 1'b0; + rtc_pul_p1 <= 1'b0; + end + else begin + //Counter logic + if ((rgear_p1^rgear == 1'b1) || (rdiv2_p1^rdiv2 == 1'b1) || (rdiv11_p1^rdiv11 == 1'b1) || (rcpri_mod_ch_p1^rcpri_mod_ch_p2 == 1'b1) || (rpcie_mode_p1^rpcie_mode == 1'b1)) begin + if (rtc_ctrl == 1'b1) begin + rcount <= LRCLK_TC_PUL_WIDTH; + end + end + else begin + if (rcount != LRCLK_TC_w) begin + rcount <= rcount + 1; + end + else begin + rcount <= 16'd0; + end + end + + //Pulse control logic + if (rcount == LRCLK_TC_w - 1) begin + rtc_ctrl <= 1'b1; + end + + //Pulse Generation logic + if (rtc_ctrl == 1'b1) begin + if ((rcount == LRCLK_TC_w) || (rcount < LRCLK_TC_PUL_WIDTH)) begin + rtc_pul <= 1'b1; + end + else begin + rtc_pul <= 1'b0; + end + end + + rtc_pul_p1 <= rtc_pul; + end +end + + +// ============================================================================= +// Heartbeat synchronization & monitor logic and Dynamic mode pipeline logic +// ============================================================================= +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rhb_sync_p1 <= 1'b0; + rhb_sync_p2 <= 1'b0; + rhb_wait_cnt <= 8'd0; + rstat_pclk <= 1'b0; + rgear_p1 <= 1'b0; + rdiv2_p1 <= 1'b0; + rdiv11_p1 <= 1'b0; + rcpri_mod_ch_p1 <= 1'b0; + rcpri_mod_ch_p2 <= 1'b0; + rcpri_mod_ch_st <= 1'b0; + rpcie_mode_p1 <= 1'b0; + + end + else begin + //Pipeline stages for the Heartbeat + rhb_sync_p1 <= rhb_sync; + rhb_sync_p2 <= rhb_sync_p1; + + //Pipeline stages of the Dynamic rate control signals + rgear_p1 <= rgear; + rdiv2_p1 <= rdiv2; + rdiv11_p1 <= rdiv11; + + //Pipeline stage for PCIe mode + rpcie_mode_p1 <= rpcie_mode; + + //Pipeline stage for CPRI mode change + rcpri_mod_ch_p1 <= rcpri_mod_ch_sync; + rcpri_mod_ch_p2 <= rcpri_mod_ch_p1; + + //CPRI mode change status logic + if (rcpri_mod_ch_p1^rcpri_mod_ch_sync == 1'b1) begin + rcpri_mod_ch_st <= 1'b1; + end + + //Heartbeat wait counter and monitor logic + if (rtc_ctrl == 1'b1) begin + if (rhb_sync_p1 == 1'b1 && rhb_sync_p2 == 1'b0) begin + rhb_wait_cnt <= 8'd0; + rstat_pclk <= 1'b1; + end + else if (rhb_wait_cnt == LHB_WAIT_CNT) begin + rhb_wait_cnt <= 8'd0; + rstat_pclk <= 1'b0; + end + else begin + rhb_wait_cnt <= rhb_wait_cnt + 1; + end + end + end +end + + +// ============================================================================= +// Pipleline registers for the TC pulse and CPRI mode change logic +// ============================================================================= +always @(posedge sli_pclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + ppul_sync_p1 <= 1'b0; + ppul_sync_p2 <= 1'b0; + ppul_sync_p3 <= 1'b0; + pcpri_mode <= 3'b0; + pcpri_mod_ch <= 1'b0; + end + else begin + ppul_sync_p1 <= ppul_sync; + ppul_sync_p2 <= ppul_sync_p1; + ppul_sync_p3 <= ppul_sync_p2; + + //CPRI mode change logic + pcpri_mode <= sli_cpri_mode; + + if (pcpri_mode != sli_cpri_mode) begin + pcpri_mod_ch <= ~pcpri_mod_ch; + end + end +end + + +// ============================================================================= +// Terminal count logic +// ============================================================================= + +//For SDI protocol with Dynamic rate control enabled +generate +if ((PDYN_RATE_CTRL == "ENABLED") && (PPROTOCOL == "SDI")) begin +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rcount_tc <= 22'd0; + rdiff_comp_lock <= 16'd0; + rdiff_comp_unlock <= 16'd0; + end + else begin + //Terminal count logic + //Div by 11 is enabled + if (rdiv11 == 1'b1) begin + //Gear mode is 16/20 + if (rgear == 1'b1) begin + rcount_tc <= PPCLK_DIV11_TC; + rdiff_comp_lock <= PDIFF_DIV11_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_DIV11_VAL_UNLOCK; + end + else begin + rcount_tc <= {PPCLK_DIV11_TC[20:0], 1'b0}; + rdiff_comp_lock <= {PDIFF_DIV11_VAL_LOCK[14:0], 1'b0}; + rdiff_comp_unlock <= {PDIFF_DIV11_VAL_UNLOCK[14:0], 1'b0}; + end + end + //Div by 2 is enabled + else if (rdiv2 == 1'b1) begin + //Gear mode is 16/20 + if (rgear == 1'b1) begin + rcount_tc <= {1'b0,PPCLK_TC[21:1]}; + rdiff_comp_lock <= {1'b0,PDIFF_VAL_LOCK[15:1]}; + rdiff_comp_unlock <= {1'b0,PDIFF_VAL_UNLOCK[15:1]}; + end + else begin + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end + end + //Both div by 11 and div by 2 are disabled + else begin + //Gear mode is 16/20 + if (rgear == 1'b1) begin + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end + else begin + rcount_tc <= {PPCLK_TC[20:0],1'b0}; + rdiff_comp_lock <= {PDIFF_VAL_LOCK[14:0],1'b0}; + rdiff_comp_unlock <= {PDIFF_VAL_UNLOCK[14:0],1'b0}; + end + end + end +end +end +endgenerate + +//For G8B10B protocol with Dynamic rate control enabled +generate +if ((PDYN_RATE_CTRL == "ENABLED") && (PPROTOCOL == "G8B10B")) begin +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rcount_tc <= 22'd0; + rdiff_comp_lock <= 16'd0; + rdiff_comp_unlock <= 16'd0; + end + else begin + //Terminal count logic + //Div by 2 is enabled + if (rdiv2 == 1'b1) begin + rcount_tc <= {1'b0,PPCLK_TC[21:1]}; + rdiff_comp_lock <= {1'b0,PDIFF_VAL_LOCK[15:1]}; + rdiff_comp_unlock <= {1'b0,PDIFF_VAL_UNLOCK[15:1]}; + end + else begin + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end + end +end +end +endgenerate + + +//For CPRI protocol with Dynamic rate control is disabled +generate +if ((PDYN_RATE_CTRL == "DISABLED") && (PPROTOCOL == "CPRI")) begin +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rcount_tc <= 22'd0; + rdiff_comp_lock <= 16'd0; + rdiff_comp_unlock <= 16'd0; + end + else begin + //Terminal count logic for CPRI protocol + //Only if there is a change in the rate mode from the default + if (rcpri_mod_ch_st == 1'b1) begin + if (rcpri_mod_ch_p1^rcpri_mod_ch_p2 == 1'b1) begin + case(sli_cpri_mode) + 3'd0 : begin //For 0.6Gbps + rcount_tc <= LPCLK_TC_0; + case(PLOL_SETTING) + 'd0 : begin + rdiff_comp_lock <= LPDIFF_LOCK_00; + rdiff_comp_unlock <= LPDIFF_UNLOCK_00; + end + + 'd1 : begin + rdiff_comp_lock <= LPDIFF_LOCK_01; + rdiff_comp_unlock <= LPDIFF_UNLOCK_01; + end + + 'd2 : begin + rdiff_comp_lock <= LPDIFF_LOCK_02; + rdiff_comp_unlock <= LPDIFF_UNLOCK_02; + end + + 'd3 : begin + rdiff_comp_lock <= LPDIFF_LOCK_03; + rdiff_comp_unlock <= LPDIFF_UNLOCK_03; + end + + default : begin + rdiff_comp_lock <= LPDIFF_LOCK_00; + rdiff_comp_unlock <= LPDIFF_UNLOCK_00; + end + endcase + end + + 3'd1 : begin //For 1.2Gbps + rcount_tc <= LPCLK_TC_1; + case(PLOL_SETTING) + 'd0 : begin + rdiff_comp_lock <= LPDIFF_LOCK_10; + rdiff_comp_unlock <= LPDIFF_UNLOCK_10; + end + + 'd1 : begin + rdiff_comp_lock <= LPDIFF_LOCK_11; + rdiff_comp_unlock <= LPDIFF_UNLOCK_11; + end + + 'd2 : begin + rdiff_comp_lock <= LPDIFF_LOCK_12; + rdiff_comp_unlock <= LPDIFF_UNLOCK_12; + end + + 'd3 : begin + rdiff_comp_lock <= LPDIFF_LOCK_13; + rdiff_comp_unlock <= LPDIFF_UNLOCK_13; + end + + default : begin + rdiff_comp_lock <= LPDIFF_LOCK_10; + rdiff_comp_unlock <= LPDIFF_UNLOCK_10; + end + endcase + end + + 3'd2 : begin //For 2.4Gbps + rcount_tc <= LPCLK_TC_2; + case(PLOL_SETTING) + 'd0 : begin + rdiff_comp_lock <= LPDIFF_LOCK_20; + rdiff_comp_unlock <= LPDIFF_UNLOCK_20; + end + + 'd1 : begin + rdiff_comp_lock <= LPDIFF_LOCK_21; + rdiff_comp_unlock <= LPDIFF_UNLOCK_21; + end + + 'd2 : begin + rdiff_comp_lock <= LPDIFF_LOCK_22; + rdiff_comp_unlock <= LPDIFF_UNLOCK_22; + end + + 'd3 : begin + rdiff_comp_lock <= LPDIFF_LOCK_23; + rdiff_comp_unlock <= LPDIFF_UNLOCK_23; + end + + default : begin + rdiff_comp_lock <= LPDIFF_LOCK_20; + rdiff_comp_unlock <= LPDIFF_UNLOCK_20; + end + endcase + end + + 3'd3 : begin //For 3.07Gbps + rcount_tc <= LPCLK_TC_3; + case(PLOL_SETTING) + 'd0 : begin + rdiff_comp_lock <= LPDIFF_LOCK_30; + rdiff_comp_unlock <= LPDIFF_UNLOCK_30; + end + + 'd1 : begin + rdiff_comp_lock <= LPDIFF_LOCK_31; + rdiff_comp_unlock <= LPDIFF_UNLOCK_31; + end + + 'd2 : begin + rdiff_comp_lock <= LPDIFF_LOCK_32; + rdiff_comp_unlock <= LPDIFF_UNLOCK_32; + end + + 'd3 : begin + rdiff_comp_lock <= LPDIFF_LOCK_33; + rdiff_comp_unlock <= LPDIFF_UNLOCK_33; + end + endcase + end + + 3'd4 : begin //For 4.9125bps + rcount_tc <= LPCLK_TC_4; + case(PLOL_SETTING) + 'd0 : begin + rdiff_comp_lock <= LPDIFF_LOCK_40; + rdiff_comp_unlock <= LPDIFF_UNLOCK_40; + end + + 'd1 : begin + rdiff_comp_lock <= LPDIFF_LOCK_41; + rdiff_comp_unlock <= LPDIFF_UNLOCK_41; + end + + 'd2 : begin + rdiff_comp_lock <= LPDIFF_LOCK_42; + rdiff_comp_unlock <= LPDIFF_UNLOCK_42; + end + + 'd3 : begin + rdiff_comp_lock <= LPDIFF_LOCK_43; + rdiff_comp_unlock <= LPDIFF_UNLOCK_43; + end + + default : begin + rdiff_comp_lock <= LPDIFF_LOCK_40; + rdiff_comp_unlock <= LPDIFF_UNLOCK_40; + end + endcase + end + + default : begin + rcount_tc <= LPCLK_TC_0; + rdiff_comp_lock <= LPDIFF_LOCK_00; + rdiff_comp_unlock <= LPDIFF_UNLOCK_00; + end + endcase + end + end + else begin + //If there is no change in the CPRI rate mode from default + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end + end +end +end +endgenerate + +//For PCIe protocol with Dynamic rate control disabled +generate +if ((PDYN_RATE_CTRL == "DISABLED") && (PPROTOCOL == "PCIE")) begin +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rcount_tc <= 22'd0; + rdiff_comp_lock <= 16'd0; + rdiff_comp_unlock <= 16'd0; + end + else begin + //Terminal count logic + if (PPCIE_MAX_RATE == "2.5") begin + //2.5G mode is enabled + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end + else begin + //5G mode is enabled + if (rpcie_mode == 1'b1) begin + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end + else begin + //2.5G mode is enabled + rcount_tc <= {1'b0,PPCLK_TC[21:1]}; + rdiff_comp_lock <= {1'b0,PDIFF_VAL_LOCK[15:1]}; + rdiff_comp_unlock <= {1'b0,PDIFF_VAL_UNLOCK[15:1]}; + end + end + end +end +end +endgenerate + +//For all protocols other than CPRI & PCIe +generate +if ((PDYN_RATE_CTRL == "DISABLED") && ((PPROTOCOL != "CPRI") && (PPROTOCOL != "PCIE"))) begin +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rcount_tc <= 22'd0; + rdiff_comp_lock <= 16'd0; + rdiff_comp_unlock <= 16'd0; + end + else begin + //Terminal count logic for all protocols other than CPRI & PCIe + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end +end +end +endgenerate + + +// ============================================================================= +// Tx_pclk counter, Heartbeat and Differential value logic +// ============================================================================= +always @(posedge sli_pclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + pcount <= 22'd0; + pcount_diff <= 22'd65535; + phb_cnt <= 3'd0; + phb <= 1'b0; + end + else begin + //Counter logic + if (ppul_sync_p1 == 1'b1 && ppul_sync_p2 == 1'b0) begin + pcount <= 22'd0; + end + else begin + pcount <= pcount + 1; + end + + //Heartbeat logic + phb_cnt <= phb_cnt + 1; + + if ((phb_cnt < 3'd4) && (phb_cnt >= 3'd0)) begin + phb <= 1'b1; + end + else begin + phb <= 1'b0; + end + + //Differential value logic + if (ppul_sync_p1 == 1'b1 && ppul_sync_p2 == 1'b0) begin + pcount_diff <= rcount_tc + ~(pcount) + 1; + end + else if (ppul_sync_p2 == 1'b1 && ppul_sync_p3 == 1'b0) begin + if (pcount_diff[21] == 1'b1) begin + pcount_diff <= ~(pcount_diff) + 1; + end + end + end +end + + +// ============================================================================= +// State transition logic for SLL FSM +// ============================================================================= +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + sll_state <= LPLL_LOSS_ST; + end + else begin + //Reasons to declare an immediate loss - Absence of Tx_pclk, Dynamic rate change for SDI or CPRI + if ((rstat_pclk == 1'b0) || (rgear_p1^rgear == 1'b1) || (rdiv2_p1^rdiv2 == 1'b1) || + (rdiv11_p1^rdiv11 == 1'b1) || (rcpri_mod_ch_p1^rcpri_mod_ch_p2 == 1'b1) || (rpcie_mode_p1^rpcie_mode == 1'b1)) begin + sll_state <= LPLL_LOSS_ST; + end + else begin + case(sll_state) + LPLL_LOSS_ST : begin + if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin + if (unlock) begin + sll_state <= LPLL_LOSS_ST; + end + else if (lock) begin + if (PLOL_SETTING == 2'd0) begin + sll_state <= LPLL_PRELOCK_ST; + end + else begin + sll_state <= LPLL_LOCK_ST; + end + end + end + end + + LPLL_LOCK_ST : begin + if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin + if (lock) begin + sll_state <= LPLL_LOCK_ST; + end + else begin + if (PLOL_SETTING == 2'd0) begin + sll_state <= LPLL_LOSS_ST; + end + else begin + sll_state <= LPLL_PRELOSS_ST; + end + end + end + end + + LPLL_PRELOCK_ST : begin + if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin + if (lock) begin + sll_state <= LPLL_LOCK_ST; + end + else begin + sll_state <= LPLL_PRELOSS_ST; + end + end + end + + LPLL_PRELOSS_ST : begin + if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin + if (unlock) begin + sll_state <= LPLL_PRELOSS_ST; + end + else if (lock) begin + sll_state <= LPLL_LOCK_ST; + end + end + end + + default: begin + sll_state <= LPLL_LOSS_ST; + end + endcase + end + end +end + + +// ============================================================================= +// Logic for Tx PLL Lock +// ============================================================================= +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + pll_lock <= 1'b0; + end + else begin + case(sll_state) + LPLL_LOSS_ST : begin + pll_lock <= 1'b0; + end + + LPLL_LOCK_ST : begin + pll_lock <= 1'b1; + end + + LPLL_PRELOSS_ST : begin + pll_lock <= 1'b0; + end + + default: begin + pll_lock <= 1'b0; + end + endcase + end +end + +assign slo_plol = ~(pll_lock); + +endmodule + + +// =========================================================================== +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< +// --------------------------------------------------------------------------- +// Copyright (c) 2015 by Lattice Semiconductor Corporation +// ALL RIGHTS RESERVED +// ------------------------------------------------------------------ +// +// Permission: +// +// Lattice SG Pte. Ltd. grants permission to use this code +// pursuant to the terms of the Lattice Reference Design License Agreement. +// +// +// Disclaimer: +// +// This VHDL or Verilog source code is intended as a design reference +// which illustrates how these types of functions can be implemented. +// It is the user's responsibility to verify their design for +// consistency and functionality through the use of formal +// verification methods. Lattice provides no warranty +// regarding the use or functionality of this code. +// +// --------------------------------------------------------------------------- +// +// Lattice SG Pte. Ltd. +// 101 Thomson Road, United Square #07-02 +// Singapore 307591 +// +// +// TEL: 1-800-Lattice (USA and Canada) +// +65-6631-2000 (Singapore) +// +1-503-268-8001 (other locations) +// +// web: http://www.latticesemi.com/ +// email: techsupport@latticesemi.com +// +// --------------------------------------------------------------------------- +// +// ============================================================================= +// FILE DETAILS +// Project : Synchronizer Logic +// File : sync.v +// Title : Synchronizer module +// Description : +// ============================================================================= +// REVISION HISTORY +// Version : 1.0 +// Author(s) : AV +// Mod. Date : July 7, 2015 +// Changes Made : Initial Creation +// ----------------------------------------------------------------------------- +// Version : 1.1 +// Author(s) : EB +// Mod. Date : March 21, 2017 +// Changes Made : +// ============================================================================= + +`ifndef PCS_SYNC_MODULE +`define PCS_SYNC_MODULE +module sync ( + clk, + rst, + data_in, + data_out + ); + +input clk; //Clock in which the async data needs to be synchronized to +input rst; //Active high reset +input data_in; //Asynchronous data +output data_out; //Synchronized data + +parameter PDATA_RST_VAL = 0; //Reset value for the registers + +reg data_p1; +reg data_p2; + +// ============================================================================= +// Synchronization logic +// ============================================================================= +always @(posedge clk or posedge rst) begin + if (rst == 1'b1) begin + data_p1 <= PDATA_RST_VAL; + data_p2 <= PDATA_RST_VAL; + end + else begin + data_p1 <= data_in; + data_p2 <= data_p1; + end +end + +assign data_out = data_p2; + +endmodule +`endif + diff --git a/clarity/pcs/sgmii1/sgmii1.fdc b/clarity/pcs/sgmii1/sgmii1.fdc new file mode 100644 index 0000000..c667056 --- /dev/null +++ b/clarity/pcs/sgmii1/sgmii1.fdc @@ -0,0 +1,3 @@ +###==== Start Generation + +define_attribute {i:Lane0} {loc} {DCU0_CH1} diff --git a/clarity/pcs/sgmii1/sgmii1.lpc b/clarity/pcs/sgmii1/sgmii1.lpc new file mode 100644 index 0000000..ac31555 --- /dev/null +++ b/clarity/pcs/sgmii1/sgmii1.lpc @@ -0,0 +1,97 @@ +[Device] +Family=ecp5um +OperatingCondition=COM +Package=CABGA381 +PartName=LFE5UM-45F-8BG381C +PartType=LFE5UM-45F +SpeedGrade=8 +Status=P +[IP] +CoreName=PCS +CoreRevision=8.2 +CoreStatus=Demo +CoreType=LPM +Date=11/18/2018 +ModuleName=sgmii1 +ParameterFileVersion=1.0 +SourceFormat=verilog +Time=17:42:50 +VendorName=Lattice Semiconductor Corporation +[Parameters] +;ACHARA=0 00H +;ACHARB=0 00H +;ACHARM=0 00H +;RXMCAENABLE=Disabled +CDRLOLACTION=Full Recalibration +CDRLOLRANGE=0 +CDR_MAX_RATE=1.25 +CDR_MULT=25X +CDR_REF_RATE=50.0000 +CH_MODE=Rx and Tx +Destination=Synplicity +EDIF=1 +Expression=BusA(0 to 7) +IO=0 +IO_TYPE=GbE +LEQ=0 +LOOPBACK=Disabled +LOSPORT=Enabled +NUM_CHS=1 +Order=Big Endian [MSB:LSB] +PPORT_RX_RDY=Disabled +PPORT_TX_RDY=Disabled +PROTOCOL=GbE +PWAIT_RX_RDY=3000 +PWAIT_TX_RDY=3000 +RCSRC=Disabled +REFCLK_RATE=50.0000 +RSTSEQSEL=Disabled +RX8B10B=Enabled +RXCOMMAA=1010000011 +RXCOMMAB=0101111100 +RXCOMMAM=1111111111 +RXCOUPLING=AC +RXCTC=Enabled +RXCTCBYTEN=0 00H +RXCTCBYTEN1=0 00H +RXCTCBYTEN2=1 BCH +RXCTCBYTEN3=0 50H +RXCTCMATCHPATTERN=M2-S2 +RXDIFFTERM=50 ohms +RXFIFO_ENABLE=Enabled +RXINVPOL=Invert +RXLDR=Off +RXLOSTHRESHOLD=4 +RXLSM=Enabled +RXSC=K28P5 +RXWA=Barrel Shift +RX_DATA_WIDTH=8/10-Bit +RX_FICLK_RATE=125.0000 +RX_LINE_RATE=1.2500 +RX_RATE_DIV=Full Rate +SCIPORT=Enabled +SOFTLOL=Disabled +TX8B10B=Enabled +TXAMPLITUDE=400 +TXDEPOST=Disabled +TXDEPRE=Disabled +TXDIFFTERM=50 ohms +TXFIFO_ENABLE=Enabled +TXINVPOL=Invert +TXLDR=Off +TXPLLLOLTHRESHOLD=0 +TXPLLMULT=25X +TX_DATA_WIDTH=8/10-Bit +TX_FICLK_RATE=125.0000 +TX_LINE_RATE=1.2500 +TX_MAX_RATE=1.25 +TX_RATE_DIV=Full Rate +VHDL=0 +Verilog=1 +[FilesGenerated] +sgmii1.pp=pp +sgmii1.sym=sym +sgmii1.tft=tft +sgmii1.txt=pcs_module +[SYSTEMPNR] +LN0=DCU0_CH1 diff --git a/clarity/pcs/sgmii1/sgmii1.v b/clarity/pcs/sgmii1/sgmii1.v new file mode 100644 index 0000000..648808a --- /dev/null +++ b/clarity/pcs/sgmii1/sgmii1.v @@ -0,0 +1,422 @@ +// Verilog netlist produced by program ASBGen: Ports rev. 2.30, Attr. rev. 2.70 +// Netlist written on Sun Nov 18 17:44:07 2018 +// +// Verilog Description of module sgmii1 +// + +`timescale 1ns/1ps +module sgmii1 (hdoutp, hdoutn, hdinp, hdinn, rxrefclk, + tx_pclk, txi_clk, txdata, tx_k, xmit, tx_disp_correct, + rxdata, rx_k, rx_disp_err, rx_cv_err, signal_detect_c, + rx_los_low_s, lsm_status_s, ctc_urun_s, ctc_orun_s, rx_cdr_lol_s, + ctc_ins_s, ctc_del_s, tx_pcs_rst_c, rx_pcs_rst_c, rx_serdes_rst_c, + tx_pwrup_c, rx_pwrup_c, sci_wrdata, sci_addr, sci_rddata, + sci_en_dual, sci_sel_dual, sci_en, sci_sel, sci_rd, sci_wrn, + sci_int, cyawstn, rst_dual_c, serdes_rst_dual_c, serdes_pdb, + tx_serdes_rst_c, pll_refclki); + output hdoutp; + output hdoutn; + input hdinp; + input hdinn; + input rxrefclk; + output tx_pclk; + input txi_clk; + input [7:0]txdata; + input [0:0]tx_k; + input [0:0]xmit; + input [0:0]tx_disp_correct; + output [7:0]rxdata; + output [0:0]rx_k; + output [0:0]rx_disp_err; + output [0:0]rx_cv_err; + input signal_detect_c; + output rx_los_low_s; + output lsm_status_s; + output ctc_urun_s; + output ctc_orun_s; + output rx_cdr_lol_s; + output ctc_ins_s; + output ctc_del_s; + input tx_pcs_rst_c; + input rx_pcs_rst_c; + input rx_serdes_rst_c; + input tx_pwrup_c; + input rx_pwrup_c; + input [7:0]sci_wrdata; + input [5:0]sci_addr; + output [7:0]sci_rddata; + input sci_en_dual; + input sci_sel_dual; + input sci_en; + input sci_sel; + input sci_rd; + input sci_wrn; + output sci_int; + input cyawstn; + input rst_dual_c; + input serdes_rst_dual_c; + input serdes_pdb; + input tx_serdes_rst_c; + input pll_refclki; + + + wire n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, + n12, n13, n14, n15, n16, n17, n18, n19, n20, n21, + n22, n23, n24, n25, n26, n27, n28, n29, n30, n31, + n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, + n42, n43, n46, n47, n48, n49, n50, n51, n52, n53, + n54, n55, n56, n57, n58, n59, n60, n61, n62, n63, + n64, n65, n66, n67, n68, n69, n70, n71, n72, n73, + n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, + n84, n85, n86, n87, n88, n89, n90, n91, n92, n93, + n94, n95, n96, n97, n98, n99, n100, n101, _Z; + + DCUA DCU0_inst (.CH0_HDINP(1'b0), .CH1_HDINP(hdinp), .CH0_HDINN(1'b0), + .CH1_HDINN(hdinn), .D_TXBIT_CLKP_FROM_ND(1'b0), .D_TXBIT_CLKN_FROM_ND(1'b0), + .D_SYNC_ND(1'b0), .D_TXPLL_LOL_FROM_ND(1'b0), .CH0_RX_REFCLK(1'b0), + .CH1_RX_REFCLK(rxrefclk), .CH0_FF_RXI_CLK(1'b1), .CH1_FF_RXI_CLK(tx_pclk), + .CH0_FF_TXI_CLK(1'b1), .CH1_FF_TXI_CLK(txi_clk), .CH0_FF_EBRD_CLK(1'b1), + .CH1_FF_EBRD_CLK(tx_pclk), .CH0_FF_TX_D_0(1'b0), .CH1_FF_TX_D_0(txdata[0]), + .CH0_FF_TX_D_1(1'b0), .CH1_FF_TX_D_1(txdata[1]), .CH0_FF_TX_D_2(1'b0), + .CH1_FF_TX_D_2(txdata[2]), .CH0_FF_TX_D_3(1'b0), .CH1_FF_TX_D_3(txdata[3]), + .CH0_FF_TX_D_4(1'b0), .CH1_FF_TX_D_4(txdata[4]), .CH0_FF_TX_D_5(1'b0), + .CH1_FF_TX_D_5(txdata[5]), .CH0_FF_TX_D_6(1'b0), .CH1_FF_TX_D_6(txdata[6]), + .CH0_FF_TX_D_7(1'b0), .CH1_FF_TX_D_7(txdata[7]), .CH0_FF_TX_D_8(1'b0), + .CH1_FF_TX_D_8(tx_k[0]), .CH0_FF_TX_D_9(1'b0), .CH1_FF_TX_D_9(1'b0), + .CH0_FF_TX_D_10(1'b0), .CH1_FF_TX_D_10(xmit[0]), .CH0_FF_TX_D_11(1'b0), + .CH1_FF_TX_D_11(tx_disp_correct[0]), .CH0_FF_TX_D_12(1'b0), .CH1_FF_TX_D_12(1'b0), + .CH0_FF_TX_D_13(1'b0), .CH1_FF_TX_D_13(1'b0), .CH0_FF_TX_D_14(1'b0), + .CH1_FF_TX_D_14(1'b0), .CH0_FF_TX_D_15(1'b0), .CH1_FF_TX_D_15(1'b0), + .CH0_FF_TX_D_16(1'b0), .CH1_FF_TX_D_16(1'b0), .CH0_FF_TX_D_17(1'b0), + .CH1_FF_TX_D_17(1'b0), .CH0_FF_TX_D_18(1'b0), .CH1_FF_TX_D_18(1'b0), + .CH0_FF_TX_D_19(1'b0), .CH1_FF_TX_D_19(1'b0), .CH0_FF_TX_D_20(1'b0), + .CH1_FF_TX_D_20(1'b0), .CH0_FF_TX_D_21(1'b0), .CH1_FF_TX_D_21(1'b0), + .CH0_FF_TX_D_22(1'b0), .CH1_FF_TX_D_22(1'b0), .CH0_FF_TX_D_23(1'b0), + .CH1_FF_TX_D_23(1'b0), .CH0_FFC_EI_EN(1'b0), .CH1_FFC_EI_EN(1'b0), + .CH0_FFC_PCIE_DET_EN(1'b0), .CH1_FFC_PCIE_DET_EN(1'b0), .CH0_FFC_PCIE_CT(1'b0), + .CH1_FFC_PCIE_CT(1'b0), .CH0_FFC_SB_INV_RX(1'b0), .CH1_FFC_SB_INV_RX(1'b0), + .CH0_FFC_ENABLE_CGALIGN(1'b0), .CH1_FFC_ENABLE_CGALIGN(1'b0), .CH0_FFC_SIGNAL_DETECT(1'b0), + .CH1_FFC_SIGNAL_DETECT(signal_detect_c), .CH0_FFC_FB_LOOPBACK(1'b0), + .CH1_FFC_FB_LOOPBACK(1'b0), .CH0_FFC_SB_PFIFO_LP(1'b0), .CH1_FFC_SB_PFIFO_LP(1'b0), + .CH0_FFC_PFIFO_CLR(1'b0), .CH1_FFC_PFIFO_CLR(1'b0), .CH0_FFC_RATE_MODE_RX(1'b0), + .CH1_FFC_RATE_MODE_RX(1'b0), .CH0_FFC_RATE_MODE_TX(1'b0), .CH1_FFC_RATE_MODE_TX(1'b0), + .CH0_FFC_DIV11_MODE_RX(1'b0), .CH1_FFC_DIV11_MODE_RX(1'b0), .CH0_FFC_DIV11_MODE_TX(1'b0), + .CH1_FFC_DIV11_MODE_TX(1'b0), .CH0_FFC_RX_GEAR_MODE(1'b0), .CH1_FFC_RX_GEAR_MODE(1'b0), + .CH0_FFC_TX_GEAR_MODE(1'b0), .CH1_FFC_TX_GEAR_MODE(1'b0), .CH0_FFC_LDR_CORE2TX_EN(1'b0), + .CH1_FFC_LDR_CORE2TX_EN(1'b0), .CH0_FFC_LANE_TX_RST(1'b0), .CH1_FFC_LANE_TX_RST(tx_pcs_rst_c), + .CH0_FFC_LANE_RX_RST(1'b0), .CH1_FFC_LANE_RX_RST(rx_pcs_rst_c), + .CH0_FFC_RRST(1'b0), .CH1_FFC_RRST(rx_serdes_rst_c), .CH0_FFC_TXPWDNB(1'b0), + .CH1_FFC_TXPWDNB(tx_pwrup_c), .CH0_FFC_RXPWDNB(1'b0), .CH1_FFC_RXPWDNB(rx_pwrup_c), + .CH0_LDR_CORE2TX(1'b0), .CH1_LDR_CORE2TX(1'b0), .D_SCIWDATA0(sci_wrdata[0]), + .D_SCIWDATA1(sci_wrdata[1]), .D_SCIWDATA2(sci_wrdata[2]), .D_SCIWDATA3(sci_wrdata[3]), + .D_SCIWDATA4(sci_wrdata[4]), .D_SCIWDATA5(sci_wrdata[5]), .D_SCIWDATA6(sci_wrdata[6]), + .D_SCIWDATA7(sci_wrdata[7]), .D_SCIADDR0(sci_addr[0]), .D_SCIADDR1(sci_addr[1]), + .D_SCIADDR2(sci_addr[2]), .D_SCIADDR3(sci_addr[3]), .D_SCIADDR4(sci_addr[4]), + .D_SCIADDR5(sci_addr[5]), .D_SCIENAUX(sci_en_dual), .D_SCISELAUX(sci_sel_dual), + .CH0_SCIEN(1'b0), .CH1_SCIEN(sci_en), .CH0_SCISEL(1'b0), .CH1_SCISEL(sci_sel), + .D_SCIRD(sci_rd), .D_SCIWSTN(sci_wrn), .D_CYAWSTN(cyawstn), .D_FFC_SYNC_TOGGLE(1'b0), + .D_FFC_DUAL_RST(rst_dual_c), .D_FFC_MACRO_RST(serdes_rst_dual_c), + .D_FFC_MACROPDB(serdes_pdb), .D_FFC_TRST(tx_serdes_rst_c), .CH0_FFC_CDR_EN_BITSLIP(1'b0), + .CH1_FFC_CDR_EN_BITSLIP(1'b0), .D_SCAN_ENABLE(1'b0), .D_SCAN_IN_0(1'b0), + .D_SCAN_IN_1(1'b0), .D_SCAN_IN_2(1'b0), .D_SCAN_IN_3(1'b0), .D_SCAN_IN_4(1'b0), + .D_SCAN_IN_5(1'b0), .D_SCAN_IN_6(1'b0), .D_SCAN_IN_7(1'b0), .D_SCAN_MODE(1'b0), + .D_SCAN_RESET(1'b0), .D_CIN0(1'b0), .D_CIN1(1'b0), .D_CIN2(1'b0), + .D_CIN3(1'b0), .D_CIN4(1'b0), .D_CIN5(1'b0), .D_CIN6(1'b0), + .D_CIN7(1'b0), .D_CIN8(1'b0), .D_CIN9(1'b0), .D_CIN10(1'b0), + .D_CIN11(1'b0), .CH0_HDOUTP(n47), .CH1_HDOUTP(hdoutp), .CH0_HDOUTN(n48), + .CH1_HDOUTN(hdoutn), .D_TXBIT_CLKP_TO_ND(n1), .D_TXBIT_CLKN_TO_ND(n2), + .D_SYNC_PULSE2ND(n3), .D_TXPLL_LOL_TO_ND(n4), .CH0_FF_RX_F_CLK(n49), + .CH1_FF_RX_F_CLK(n5), .CH0_FF_RX_H_CLK(n50), .CH1_FF_RX_H_CLK(n6), + .CH0_FF_TX_F_CLK(n51), .CH1_FF_TX_F_CLK(n7), .CH0_FF_TX_H_CLK(n52), + .CH1_FF_TX_H_CLK(n8), .CH0_FF_RX_PCLK(n53), .CH1_FF_RX_PCLK(n9), + .CH0_FF_TX_PCLK(n54), .CH1_FF_TX_PCLK(tx_pclk), .CH0_FF_RX_D_0(n55), + .CH1_FF_RX_D_0(rxdata[0]), .CH0_FF_RX_D_1(n56), .CH1_FF_RX_D_1(rxdata[1]), + .CH0_FF_RX_D_2(n57), .CH1_FF_RX_D_2(rxdata[2]), .CH0_FF_RX_D_3(n58), + .CH1_FF_RX_D_3(rxdata[3]), .CH0_FF_RX_D_4(n59), .CH1_FF_RX_D_4(rxdata[4]), + .CH0_FF_RX_D_5(n60), .CH1_FF_RX_D_5(rxdata[5]), .CH0_FF_RX_D_6(n61), + .CH1_FF_RX_D_6(rxdata[6]), .CH0_FF_RX_D_7(n62), .CH1_FF_RX_D_7(rxdata[7]), + .CH0_FF_RX_D_8(n63), .CH1_FF_RX_D_8(rx_k[0]), .CH0_FF_RX_D_9(n64), + .CH1_FF_RX_D_9(rx_disp_err[0]), .CH0_FF_RX_D_10(n65), .CH1_FF_RX_D_10(rx_cv_err[0]), + .CH0_FF_RX_D_11(n66), .CH1_FF_RX_D_11(n10), .CH0_FF_RX_D_12(n67), + .CH1_FF_RX_D_12(n68), .CH0_FF_RX_D_13(n69), .CH1_FF_RX_D_13(n70), + .CH0_FF_RX_D_14(n71), .CH1_FF_RX_D_14(n72), .CH0_FF_RX_D_15(n73), + .CH1_FF_RX_D_15(n74), .CH0_FF_RX_D_16(n75), .CH1_FF_RX_D_16(n76), + .CH0_FF_RX_D_17(n77), .CH1_FF_RX_D_17(n78), .CH0_FF_RX_D_18(n79), + .CH1_FF_RX_D_18(n80), .CH0_FF_RX_D_19(n81), .CH1_FF_RX_D_19(n82), + .CH0_FF_RX_D_20(n83), .CH1_FF_RX_D_20(n84), .CH0_FF_RX_D_21(n85), + .CH1_FF_RX_D_21(n86), .CH0_FF_RX_D_22(n87), .CH1_FF_RX_D_22(n88), + .CH0_FF_RX_D_23(n89), .CH1_FF_RX_D_23(n11), .CH0_FFS_PCIE_DONE(n90), + .CH1_FFS_PCIE_DONE(n12), .CH0_FFS_PCIE_CON(n91), .CH1_FFS_PCIE_CON(n13), + .CH0_FFS_RLOS(n92), .CH1_FFS_RLOS(rx_los_low_s), .CH0_FFS_LS_SYNC_STATUS(n93), + .CH1_FFS_LS_SYNC_STATUS(lsm_status_s), .CH0_FFS_CC_UNDERRUN(n94), + .CH1_FFS_CC_UNDERRUN(ctc_urun_s), .CH0_FFS_CC_OVERRUN(n95), .CH1_FFS_CC_OVERRUN(ctc_orun_s), + .CH0_FFS_RXFBFIFO_ERROR(n96), .CH1_FFS_RXFBFIFO_ERROR(n14), .CH0_FFS_TXFBFIFO_ERROR(n97), + .CH1_FFS_TXFBFIFO_ERROR(n15), .CH0_FFS_RLOL(n98), .CH1_FFS_RLOL(rx_cdr_lol_s), + .CH0_FFS_SKP_ADDED(n99), .CH1_FFS_SKP_ADDED(ctc_ins_s), .CH0_FFS_SKP_DELETED(n100), + .CH1_FFS_SKP_DELETED(ctc_del_s), .CH0_LDR_RX2CORE(n101), .CH1_LDR_RX2CORE(_Z), + .D_SCIRDATA0(sci_rddata[0]), .D_SCIRDATA1(sci_rddata[1]), .D_SCIRDATA2(sci_rddata[2]), + .D_SCIRDATA3(sci_rddata[3]), .D_SCIRDATA4(sci_rddata[4]), .D_SCIRDATA5(sci_rddata[5]), + .D_SCIRDATA6(sci_rddata[6]), .D_SCIRDATA7(sci_rddata[7]), .D_SCIINT(sci_int), + .D_SCAN_OUT_0(n16), .D_SCAN_OUT_1(n17), .D_SCAN_OUT_2(n18), .D_SCAN_OUT_3(n19), + .D_SCAN_OUT_4(n20), .D_SCAN_OUT_5(n21), .D_SCAN_OUT_6(n22), .D_SCAN_OUT_7(n23), + .D_COUT0(n24), .D_COUT1(n25), .D_COUT2(n26), .D_COUT3(n27), + .D_COUT4(n28), .D_COUT5(n29), .D_COUT6(n30), .D_COUT7(n31), + .D_COUT8(n32), .D_COUT9(n33), .D_COUT10(n34), .D_COUT11(n35), + .D_COUT12(n36), .D_COUT13(n37), .D_COUT14(n38), .D_COUT15(n39), + .D_COUT16(n40), .D_COUT17(n41), .D_COUT18(n42), .D_COUT19(n43), + .D_REFCLKI(pll_refclki), .D_FFS_PLOL(n46)) /* synthesis LOC=DCU0 CHAN=CH1 */ ; + defparam DCU0_inst.D_MACROPDB = "0b1"; + defparam DCU0_inst.D_IB_PWDNB = "0b1"; + defparam DCU0_inst.D_XGE_MODE = "0b0"; + defparam DCU0_inst.D_LOW_MARK = "0d4"; + defparam DCU0_inst.D_HIGH_MARK = "0d12"; + defparam DCU0_inst.D_BUS8BIT_SEL = "0b0"; + defparam DCU0_inst.D_CDR_LOL_SET = "0b00"; + defparam DCU0_inst.D_TXPLL_PWDNB = "0b1"; + defparam DCU0_inst.D_BITCLK_LOCAL_EN = "0b1"; + defparam DCU0_inst.D_BITCLK_ND_EN = "0b0"; + defparam DCU0_inst.D_BITCLK_FROM_ND_EN = "0b0"; + defparam DCU0_inst.D_SYNC_LOCAL_EN = "0b1"; + defparam DCU0_inst.D_SYNC_ND_EN = "0b0"; + defparam DCU0_inst.CH1_UC_MODE = "0b0"; + defparam DCU0_inst.CH1_PCIE_MODE = "0b0"; + defparam DCU0_inst.CH1_RIO_MODE = "0b0"; + defparam DCU0_inst.CH1_WA_MODE = "0b0"; + defparam DCU0_inst.CH1_INVERT_RX = "0b1"; + defparam DCU0_inst.CH1_INVERT_TX = "0b1"; + defparam DCU0_inst.CH1_PRBS_SELECTION = "0b0"; + defparam DCU0_inst.CH1_GE_AN_ENABLE = "0b0"; + defparam DCU0_inst.CH1_PRBS_LOCK = "0b0"; + defparam DCU0_inst.CH1_PRBS_ENABLE = "0b0"; + defparam DCU0_inst.CH1_ENABLE_CG_ALIGN = "0b1"; + defparam DCU0_inst.CH1_TX_GEAR_MODE = "0b0"; + defparam DCU0_inst.CH1_RX_GEAR_MODE = "0b0"; + defparam DCU0_inst.CH1_PCS_DET_TIME_SEL = "0b00"; + defparam DCU0_inst.CH1_PCIE_EI_EN = "0b0"; + defparam DCU0_inst.CH1_TX_GEAR_BYPASS = "0b0"; + defparam DCU0_inst.CH1_ENC_BYPASS = "0b0"; + defparam DCU0_inst.CH1_SB_BYPASS = "0b0"; + defparam DCU0_inst.CH1_RX_SB_BYPASS = "0b0"; + defparam DCU0_inst.CH1_WA_BYPASS = "0b0"; + defparam DCU0_inst.CH1_DEC_BYPASS = "0b0"; + defparam DCU0_inst.CH1_CTC_BYPASS = "0b0"; + defparam DCU0_inst.CH1_RX_GEAR_BYPASS = "0b0"; + defparam DCU0_inst.CH1_LSM_DISABLE = "0b0"; + defparam DCU0_inst.CH1_MATCH_2_ENABLE = "0b1"; + defparam DCU0_inst.CH1_MATCH_4_ENABLE = "0b0"; + defparam DCU0_inst.CH1_MIN_IPG_CNT = "0b11"; + defparam DCU0_inst.CH1_CC_MATCH_1 = "0x000"; + defparam DCU0_inst.CH1_CC_MATCH_2 = "0x000"; + defparam DCU0_inst.CH1_CC_MATCH_3 = "0x1BC"; + defparam DCU0_inst.CH1_CC_MATCH_4 = "0x050"; + defparam DCU0_inst.CH1_UDF_COMMA_MASK = "0x3ff"; + defparam DCU0_inst.CH1_UDF_COMMA_A = "0x283"; + defparam DCU0_inst.CH1_UDF_COMMA_B = "0x17C"; + defparam DCU0_inst.CH1_RX_DCO_CK_DIV = "0b010"; + defparam DCU0_inst.CH1_RCV_DCC_EN = "0b0"; + defparam DCU0_inst.CH1_TPWDNB = "0b1"; + defparam DCU0_inst.CH1_RATE_MODE_TX = "0b0"; + defparam DCU0_inst.CH1_RTERM_TX = "0d19"; + defparam DCU0_inst.CH1_TX_CM_SEL = "0b00"; + defparam DCU0_inst.CH1_TDRV_PRE_EN = "0b0"; + defparam DCU0_inst.CH1_TDRV_SLICE0_SEL = "0b00"; + defparam DCU0_inst.CH1_TDRV_SLICE1_SEL = "0b00"; + defparam DCU0_inst.CH1_TDRV_SLICE2_SEL = "0b01"; + defparam DCU0_inst.CH1_TDRV_SLICE3_SEL = "0b01"; + defparam DCU0_inst.CH1_TDRV_SLICE4_SEL = "0b00"; + defparam DCU0_inst.CH1_TDRV_SLICE5_SEL = "0b00"; + defparam DCU0_inst.CH1_TDRV_SLICE0_CUR = "0b000"; + defparam DCU0_inst.CH1_TDRV_SLICE1_CUR = "0b000"; + defparam DCU0_inst.CH1_TDRV_SLICE2_CUR = "0b11"; + defparam DCU0_inst.CH1_TDRV_SLICE3_CUR = "0b00"; + defparam DCU0_inst.CH1_TDRV_SLICE4_CUR = "0b00"; + defparam DCU0_inst.CH1_TDRV_SLICE5_CUR = "0b00"; + defparam DCU0_inst.CH1_TDRV_DAT_SEL = "0b00"; + defparam DCU0_inst.CH1_TX_DIV11_SEL = "0b0"; + defparam DCU0_inst.CH1_RPWDNB = "0b1"; + defparam DCU0_inst.CH1_RATE_MODE_RX = "0b0"; + defparam DCU0_inst.CH1_RX_DIV11_SEL = "0b0"; + defparam DCU0_inst.CH1_SEL_SD_RX_CLK = "0b0"; + defparam DCU0_inst.CH1_FF_RX_H_CLK_EN = "0b0"; + defparam DCU0_inst.CH1_FF_RX_F_CLK_DIS = "0b0"; + defparam DCU0_inst.CH1_FF_TX_H_CLK_EN = "0b0"; + defparam DCU0_inst.CH1_FF_TX_F_CLK_DIS = "0b0"; + defparam DCU0_inst.CH1_TDRV_POST_EN = "0b0"; + defparam DCU0_inst.CH1_TX_POST_SIGN = "0b0"; + defparam DCU0_inst.CH1_TX_PRE_SIGN = "0b0"; + defparam DCU0_inst.CH1_REQ_LVL_SET = "0b00"; + defparam DCU0_inst.CH1_REQ_EN = "0b1"; + defparam DCU0_inst.CH1_RTERM_RX = "0d22"; + defparam DCU0_inst.CH1_RXTERM_CM = "0b11"; + defparam DCU0_inst.CH1_PDEN_SEL = "0b1"; + defparam DCU0_inst.CH1_RXIN_CM = "0b11"; + defparam DCU0_inst.CH1_LEQ_OFFSET_SEL = "0b0"; + defparam DCU0_inst.CH1_LEQ_OFFSET_TRIM = "0b000"; + defparam DCU0_inst.CH1_RLOS_SEL = "0b1"; + defparam DCU0_inst.CH1_RX_LOS_LVL = "0b100"; + defparam DCU0_inst.CH1_RX_LOS_CEQ = "0b11"; + defparam DCU0_inst.CH1_RX_LOS_HYST_EN = "0b0"; + defparam DCU0_inst.CH1_RX_LOS_EN = "0b1"; + defparam DCU0_inst.CH1_LDR_RX2CORE_SEL = "0b0"; + defparam DCU0_inst.CH1_LDR_CORE2TX_SEL = "0b0"; + defparam DCU0_inst.D_TX_MAX_RATE = "1.25"; + defparam DCU0_inst.CH1_CDR_MAX_RATE = "1.25"; + defparam DCU0_inst.CH1_TXAMPLITUDE = "0d400"; + defparam DCU0_inst.CH1_TXDEPRE = "DISABLED"; + defparam DCU0_inst.CH1_TXDEPOST = "DISABLED"; + defparam DCU0_inst.CH1_PROTOCOL = "GBE"; + defparam DCU0_inst.D_ISETLOS = "0d0"; + defparam DCU0_inst.D_SETIRPOLY_AUX = "0b00"; + defparam DCU0_inst.D_SETICONST_AUX = "0b00"; + defparam DCU0_inst.D_SETIRPOLY_CH = "0b00"; + defparam DCU0_inst.D_SETICONST_CH = "0b00"; + defparam DCU0_inst.D_REQ_ISET = "0b000"; + defparam DCU0_inst.D_PD_ISET = "0b00"; + defparam DCU0_inst.D_DCO_CALIB_TIME_SEL = "0b00"; + defparam DCU0_inst.CH1_CDR_CNT4SEL = "0b00"; + defparam DCU0_inst.CH1_CDR_CNT8SEL = "0b00"; + defparam DCU0_inst.CH1_DCOATDCFG = "0b00"; + defparam DCU0_inst.CH1_DCOATDDLY = "0b00"; + defparam DCU0_inst.CH1_DCOBYPSATD = "0b1"; + defparam DCU0_inst.CH1_DCOCALDIV = "0b001"; + defparam DCU0_inst.CH1_DCOCTLGI = "0b010"; + defparam DCU0_inst.CH1_DCODISBDAVOID = "0b0"; + defparam DCU0_inst.CH1_DCOFLTDAC = "0b01"; + defparam DCU0_inst.CH1_DCOFTNRG = "0b110"; + defparam DCU0_inst.CH1_DCOIOSTUNE = "0b000"; + defparam DCU0_inst.CH1_DCOITUNE = "0b00"; + defparam DCU0_inst.CH1_DCOITUNE4LSB = "0b111"; + defparam DCU0_inst.CH1_DCOIUPDNX2 = "0b1"; + defparam DCU0_inst.CH1_DCONUOFLSB = "0b101"; + defparam DCU0_inst.CH1_DCOSCALEI = "0b00"; + defparam DCU0_inst.CH1_DCOSTARTVAL = "0b000"; + defparam DCU0_inst.CH1_DCOSTEP = "0b00"; + defparam DCU0_inst.CH1_BAND_THRESHOLD = "0d0"; + defparam DCU0_inst.CH1_AUTO_FACQ_EN = "0b1"; + defparam DCU0_inst.CH1_AUTO_CALIB_EN = "0b1"; + defparam DCU0_inst.CH1_CALIB_CK_MODE = "0b0"; + defparam DCU0_inst.CH1_REG_BAND_OFFSET = "0d0"; + defparam DCU0_inst.CH1_REG_BAND_SEL = "0d0"; + defparam DCU0_inst.CH1_REG_IDAC_SEL = "0d0"; + defparam DCU0_inst.CH1_REG_IDAC_EN = "0b0"; + defparam DCU0_inst.D_CMUSETISCL4VCO = "0b000"; + defparam DCU0_inst.D_CMUSETI4VCO = "0b00"; + defparam DCU0_inst.D_CMUSETINITVCT = "0b00"; + defparam DCU0_inst.D_CMUSETZGM = "0b000"; + defparam DCU0_inst.D_CMUSETP2AGM = "0b000"; + defparam DCU0_inst.D_CMUSETP1GM = "0b000"; + defparam DCU0_inst.D_CMUSETI4CPZ = "0d3"; + defparam DCU0_inst.D_CMUSETI4CPP = "0d3"; + defparam DCU0_inst.D_CMUSETICP4Z = "0b101"; + defparam DCU0_inst.D_CMUSETICP4P = "0b01"; + defparam DCU0_inst.D_CMUSETBIASI = "0b00"; + defparam DCU0_inst.D_SETPLLRC = "0d1"; + defparam DCU0_inst.CH1_RX_RATE_SEL = "0d8"; + defparam DCU0_inst.D_REFCK_MODE = "0b100"; + defparam DCU0_inst.D_TX_VCO_CK_DIV = "0b010"; + defparam DCU0_inst.D_PLL_LOL_SET = "0b00"; + defparam DCU0_inst.D_RG_EN = "0b0"; + defparam DCU0_inst.D_RG_SET = "0b00"; + assign n1 = 1'bz; + assign n2 = 1'bz; + assign n3 = 1'bz; + assign n4 = 1'bz; + assign n5 = 1'bz; + assign n6 = 1'bz; + assign n7 = 1'bz; + assign n8 = 1'bz; + assign n9 = 1'bz; + assign n10 = 1'bz; + assign n11 = 1'bz; + assign n12 = 1'bz; + assign n13 = 1'bz; + assign n14 = 1'bz; + assign n15 = 1'bz; + assign n16 = 1'bz; + assign n17 = 1'bz; + assign n18 = 1'bz; + assign n19 = 1'bz; + assign n20 = 1'bz; + assign n21 = 1'bz; + assign n22 = 1'bz; + assign n23 = 1'bz; + assign n24 = 1'bz; + assign n25 = 1'bz; + assign n26 = 1'bz; + assign n27 = 1'bz; + assign n28 = 1'bz; + assign n29 = 1'bz; + assign n30 = 1'bz; + assign n31 = 1'bz; + assign n32 = 1'bz; + assign n33 = 1'bz; + assign n34 = 1'bz; + assign n35 = 1'bz; + assign n36 = 1'bz; + assign n37 = 1'bz; + assign n38 = 1'bz; + assign n39 = 1'bz; + assign n40 = 1'bz; + assign n41 = 1'bz; + assign n42 = 1'bz; + assign n43 = 1'bz; + assign n46 = 1'bz; + assign n47 = 1'bz; + assign n48 = 1'bz; + assign n49 = 1'bz; + assign n50 = 1'bz; + assign n51 = 1'bz; + assign n52 = 1'bz; + assign n53 = 1'bz; + assign n54 = 1'bz; + assign n55 = 1'bz; + assign n56 = 1'bz; + assign n57 = 1'bz; + assign n58 = 1'bz; + assign n59 = 1'bz; + assign n60 = 1'bz; + assign n61 = 1'bz; + assign n62 = 1'bz; + assign n63 = 1'bz; + assign n64 = 1'bz; + assign n65 = 1'bz; + assign n66 = 1'bz; + assign n67 = 1'bz; + assign n68 = 1'bz; + assign n69 = 1'bz; + assign n70 = 1'bz; + assign n71 = 1'bz; + assign n72 = 1'bz; + assign n73 = 1'bz; + assign n74 = 1'bz; + assign n75 = 1'bz; + assign n76 = 1'bz; + assign n77 = 1'bz; + assign n78 = 1'bz; + assign n79 = 1'bz; + assign n80 = 1'bz; + assign n81 = 1'bz; + assign n82 = 1'bz; + assign n83 = 1'bz; + assign n84 = 1'bz; + assign n85 = 1'bz; + assign n86 = 1'bz; + assign n87 = 1'bz; + assign n88 = 1'bz; + assign n89 = 1'bz; + assign n90 = 1'bz; + assign n91 = 1'bz; + assign n92 = 1'bz; + assign n93 = 1'bz; + assign n94 = 1'bz; + assign n95 = 1'bz; + assign n96 = 1'bz; + assign n97 = 1'bz; + assign n98 = 1'bz; + assign n99 = 1'bz; + assign n100 = 1'bz; + assign n101 = 1'bz; + assign _Z = 1'bz; + +endmodule + diff --git a/clarity/pcs/sgmii2/sgmii2.fdc b/clarity/pcs/sgmii2/sgmii2.fdc new file mode 100644 index 0000000..29b09af --- /dev/null +++ b/clarity/pcs/sgmii2/sgmii2.fdc @@ -0,0 +1,3 @@ +###==== Start Generation + +define_attribute {i:Lane0} {loc} {DCU1_CH0} diff --git a/clarity/pcs/sgmii2/sgmii2.lpc b/clarity/pcs/sgmii2/sgmii2.lpc new file mode 100644 index 0000000..5e8a34b --- /dev/null +++ b/clarity/pcs/sgmii2/sgmii2.lpc @@ -0,0 +1,97 @@ +[Device] +Family=ecp5um +OperatingCondition=COM +Package=CABGA381 +PartName=LFE5UM-45F-8BG381C +PartType=LFE5UM-45F +SpeedGrade=8 +Status=P +[IP] +CoreName=PCS +CoreRevision=8.2 +CoreStatus=Demo +CoreType=LPM +Date=03/15/2019 +ModuleName=sgmii2 +ParameterFileVersion=1.0 +SourceFormat=verilog +Time=18:46:19 +VendorName=Lattice Semiconductor Corporation +[Parameters] +;ACHARA=0 00H +;ACHARB=0 00H +;ACHARM=0 00H +;RXMCAENABLE=Disabled +CDRLOLACTION=Full Recalibration +CDRLOLRANGE=0 +CDR_MAX_RATE=1.25 +CDR_MULT=25X +CDR_REF_RATE=50.0000 +CH_MODE=Rx and Tx +Destination=Synplicity +EDIF=1 +Expression=BusA(0 to 7) +IO=0 +IO_TYPE=GbE +LEQ=0 +LOOPBACK=Disabled +LOSPORT=Enabled +NUM_CHS=1 +Order=Big Endian [MSB:LSB] +PPORT_RX_RDY=Disabled +PPORT_TX_RDY=Disabled +PROTOCOL=GbE +PWAIT_RX_RDY=3000 +PWAIT_TX_RDY=3000 +RCSRC=Disabled +REFCLK_RATE=50.0000 +RSTSEQSEL=Disabled +RX8B10B=Enabled +RXCOMMAA=1010000011 +RXCOMMAB=0101111100 +RXCOMMAM=1111111111 +RXCOUPLING=AC +RXCTC=Enabled +RXCTCBYTEN=0 00H +RXCTCBYTEN1=0 00H +RXCTCBYTEN2=1 BCH +RXCTCBYTEN3=0 50H +RXCTCMATCHPATTERN=M2-S2 +RXDIFFTERM=50 ohms +RXFIFO_ENABLE=Enabled +RXINVPOL=Non-invert +RXLDR=Off +RXLOSTHRESHOLD=4 +RXLSM=Enabled +RXSC=K28P5 +RXWA=Barrel Shift +RX_DATA_WIDTH=8/10-Bit +RX_FICLK_RATE=125.0000 +RX_LINE_RATE=1.2500 +RX_RATE_DIV=Full Rate +SCIPORT=Enabled +SOFTLOL=Enabled +TX8B10B=Enabled +TXAMPLITUDE=400 +TXDEPOST=Disabled +TXDEPRE=Disabled +TXDIFFTERM=50 ohms +TXFIFO_ENABLE=Enabled +TXINVPOL=Non-invert +TXLDR=Off +TXPLLLOLTHRESHOLD=0 +TXPLLMULT=25X +TX_DATA_WIDTH=8/10-Bit +TX_FICLK_RATE=125.0000 +TX_LINE_RATE=1.2500 +TX_MAX_RATE=1.25 +TX_RATE_DIV=Full Rate +VHDL=0 +Verilog=1 +[FilesGenerated] +sgmii2.pp=pp +sgmii2.sym=sym +sgmii2.tft=tft +sgmii2.txt=pcs_module +[SYSTEMPNR] +LN0=DCU1_CH0 diff --git a/clarity/pcs/sgmii2/sgmii2.v b/clarity/pcs/sgmii2/sgmii2.v new file mode 100644 index 0000000..77abaf2 --- /dev/null +++ b/clarity/pcs/sgmii2/sgmii2.v @@ -0,0 +1,439 @@ +// Verilog netlist produced by program ASBGen: Ports rev. 2.30, Attr. rev. 2.70 +// Netlist written on Fri Mar 15 18:48:22 2019 +// +// Verilog Description of module sgmii2 +// + +`timescale 1ns/1ps +module sgmii2 (hdoutp, hdoutn, hdinp, hdinn, rxrefclk, + tx_pclk, txi_clk, txdata, tx_k, xmit, tx_disp_correct, + rxdata, rx_k, rx_disp_err, rx_cv_err, signal_detect_c, + rx_los_low_s, lsm_status_s, ctc_urun_s, ctc_orun_s, rx_cdr_lol_s, + ctc_ins_s, ctc_del_s, tx_pcs_rst_c, rx_pcs_rst_c, rx_serdes_rst_c, + tx_pwrup_c, rx_pwrup_c, sci_wrdata, sci_addr, sci_rddata, + sci_en_dual, sci_sel_dual, sci_en, sci_sel, sci_rd, sci_wrn, + sci_int, cyawstn, rst_dual_c, serdes_rst_dual_c, serdes_pdb, + tx_serdes_rst_c, pll_refclki, sli_rst, pll_lol); + output hdoutp; + output hdoutn; + input hdinp; + input hdinn; + input rxrefclk; + output tx_pclk; + input txi_clk; + input [7:0]txdata; + input [0:0]tx_k; + input [0:0]xmit; + input [0:0]tx_disp_correct; + output [7:0]rxdata; + output [0:0]rx_k; + output [0:0]rx_disp_err; + output [0:0]rx_cv_err; + input signal_detect_c; + output rx_los_low_s; + output lsm_status_s; + output ctc_urun_s; + output ctc_orun_s; + output rx_cdr_lol_s; + output ctc_ins_s; + output ctc_del_s; + input tx_pcs_rst_c; + input rx_pcs_rst_c; + input rx_serdes_rst_c; + input tx_pwrup_c; + input rx_pwrup_c; + input [7:0]sci_wrdata; + input [5:0]sci_addr; + output [7:0]sci_rddata; + input sci_en_dual; + input sci_sel_dual; + input sci_en; + input sci_sel; + input sci_rd; + input sci_wrn; + output sci_int; + input cyawstn; + input rst_dual_c; + input serdes_rst_dual_c; + input serdes_pdb; + input tx_serdes_rst_c; + input pll_refclki; + input sli_rst; + output pll_lol; + + + wire n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, + n12, n13, n14, n15, n16, n17, n18, n19, n20, n21, + n22, n23, n24, n25, n26, n27, n28, n29, n30, n31, + n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, + n42, n43, n46, n47, n48, n49, n50, n51, n52, n53, + n54, n55, n56, n57, n58, n59, n60, n61, n62, n63, + n64, n65, n66, n67, n68, n69, n70, n71, n72, n73, + n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, + n84, n85, n86, n87, n88, n89, n90, n91, n92, n93, + n94, n95, n96, n97, n98, n99, n100, n101, _Z; + + DCUA DCU1_inst (.CH0_HDINP(hdinp), .CH1_HDINP(1'b0), .CH0_HDINN(hdinn), + .CH1_HDINN(1'b0), .D_TXBIT_CLKP_FROM_ND(1'b0), .D_TXBIT_CLKN_FROM_ND(1'b0), + .D_SYNC_ND(1'b0), .D_TXPLL_LOL_FROM_ND(1'b0), .CH0_RX_REFCLK(rxrefclk), + .CH1_RX_REFCLK(1'b0), .CH0_FF_RXI_CLK(tx_pclk), .CH1_FF_RXI_CLK(1'b1), + .CH0_FF_TXI_CLK(txi_clk), .CH1_FF_TXI_CLK(1'b1), .CH0_FF_EBRD_CLK(tx_pclk), + .CH1_FF_EBRD_CLK(1'b1), .CH0_FF_TX_D_0(txdata[0]), .CH1_FF_TX_D_0(1'b0), + .CH0_FF_TX_D_1(txdata[1]), .CH1_FF_TX_D_1(1'b0), .CH0_FF_TX_D_2(txdata[2]), + .CH1_FF_TX_D_2(1'b0), .CH0_FF_TX_D_3(txdata[3]), .CH1_FF_TX_D_3(1'b0), + .CH0_FF_TX_D_4(txdata[4]), .CH1_FF_TX_D_4(1'b0), .CH0_FF_TX_D_5(txdata[5]), + .CH1_FF_TX_D_5(1'b0), .CH0_FF_TX_D_6(txdata[6]), .CH1_FF_TX_D_6(1'b0), + .CH0_FF_TX_D_7(txdata[7]), .CH1_FF_TX_D_7(1'b0), .CH0_FF_TX_D_8(tx_k[0]), + .CH1_FF_TX_D_8(1'b0), .CH0_FF_TX_D_9(1'b0), .CH1_FF_TX_D_9(1'b0), + .CH0_FF_TX_D_10(xmit[0]), .CH1_FF_TX_D_10(1'b0), .CH0_FF_TX_D_11(tx_disp_correct[0]), + .CH1_FF_TX_D_11(1'b0), .CH0_FF_TX_D_12(1'b0), .CH1_FF_TX_D_12(1'b0), + .CH0_FF_TX_D_13(1'b0), .CH1_FF_TX_D_13(1'b0), .CH0_FF_TX_D_14(1'b0), + .CH1_FF_TX_D_14(1'b0), .CH0_FF_TX_D_15(1'b0), .CH1_FF_TX_D_15(1'b0), + .CH0_FF_TX_D_16(1'b0), .CH1_FF_TX_D_16(1'b0), .CH0_FF_TX_D_17(1'b0), + .CH1_FF_TX_D_17(1'b0), .CH0_FF_TX_D_18(1'b0), .CH1_FF_TX_D_18(1'b0), + .CH0_FF_TX_D_19(1'b0), .CH1_FF_TX_D_19(1'b0), .CH0_FF_TX_D_20(1'b0), + .CH1_FF_TX_D_20(1'b0), .CH0_FF_TX_D_21(1'b0), .CH1_FF_TX_D_21(1'b0), + .CH0_FF_TX_D_22(1'b0), .CH1_FF_TX_D_22(1'b0), .CH0_FF_TX_D_23(1'b0), + .CH1_FF_TX_D_23(1'b0), .CH0_FFC_EI_EN(1'b0), .CH1_FFC_EI_EN(1'b0), + .CH0_FFC_PCIE_DET_EN(1'b0), .CH1_FFC_PCIE_DET_EN(1'b0), .CH0_FFC_PCIE_CT(1'b0), + .CH1_FFC_PCIE_CT(1'b0), .CH0_FFC_SB_INV_RX(1'b0), .CH1_FFC_SB_INV_RX(1'b0), + .CH0_FFC_ENABLE_CGALIGN(1'b0), .CH1_FFC_ENABLE_CGALIGN(1'b0), .CH0_FFC_SIGNAL_DETECT(signal_detect_c), + .CH1_FFC_SIGNAL_DETECT(1'b0), .CH0_FFC_FB_LOOPBACK(1'b0), .CH1_FFC_FB_LOOPBACK(1'b0), + .CH0_FFC_SB_PFIFO_LP(1'b0), .CH1_FFC_SB_PFIFO_LP(1'b0), .CH0_FFC_PFIFO_CLR(1'b0), + .CH1_FFC_PFIFO_CLR(1'b0), .CH0_FFC_RATE_MODE_RX(1'b0), .CH1_FFC_RATE_MODE_RX(1'b0), + .CH0_FFC_RATE_MODE_TX(1'b0), .CH1_FFC_RATE_MODE_TX(1'b0), .CH0_FFC_DIV11_MODE_RX(1'b0), + .CH1_FFC_DIV11_MODE_RX(1'b0), .CH0_FFC_DIV11_MODE_TX(1'b0), .CH1_FFC_DIV11_MODE_TX(1'b0), + .CH0_FFC_RX_GEAR_MODE(1'b0), .CH1_FFC_RX_GEAR_MODE(1'b0), .CH0_FFC_TX_GEAR_MODE(1'b0), + .CH1_FFC_TX_GEAR_MODE(1'b0), .CH0_FFC_LDR_CORE2TX_EN(1'b0), .CH1_FFC_LDR_CORE2TX_EN(1'b0), + .CH0_FFC_LANE_TX_RST(tx_pcs_rst_c), .CH1_FFC_LANE_TX_RST(1'b0), + .CH0_FFC_LANE_RX_RST(rx_pcs_rst_c), .CH1_FFC_LANE_RX_RST(1'b0), + .CH0_FFC_RRST(rx_serdes_rst_c), .CH1_FFC_RRST(1'b0), .CH0_FFC_TXPWDNB(tx_pwrup_c), + .CH1_FFC_TXPWDNB(1'b0), .CH0_FFC_RXPWDNB(rx_pwrup_c), .CH1_FFC_RXPWDNB(1'b0), + .CH0_LDR_CORE2TX(1'b0), .CH1_LDR_CORE2TX(1'b0), .D_SCIWDATA0(sci_wrdata[0]), + .D_SCIWDATA1(sci_wrdata[1]), .D_SCIWDATA2(sci_wrdata[2]), .D_SCIWDATA3(sci_wrdata[3]), + .D_SCIWDATA4(sci_wrdata[4]), .D_SCIWDATA5(sci_wrdata[5]), .D_SCIWDATA6(sci_wrdata[6]), + .D_SCIWDATA7(sci_wrdata[7]), .D_SCIADDR0(sci_addr[0]), .D_SCIADDR1(sci_addr[1]), + .D_SCIADDR2(sci_addr[2]), .D_SCIADDR3(sci_addr[3]), .D_SCIADDR4(sci_addr[4]), + .D_SCIADDR5(sci_addr[5]), .D_SCIENAUX(sci_en_dual), .D_SCISELAUX(sci_sel_dual), + .CH0_SCIEN(sci_en), .CH1_SCIEN(1'b0), .CH0_SCISEL(sci_sel), .CH1_SCISEL(1'b0), + .D_SCIRD(sci_rd), .D_SCIWSTN(sci_wrn), .D_CYAWSTN(cyawstn), .D_FFC_SYNC_TOGGLE(1'b0), + .D_FFC_DUAL_RST(rst_dual_c), .D_FFC_MACRO_RST(serdes_rst_dual_c), + .D_FFC_MACROPDB(serdes_pdb), .D_FFC_TRST(tx_serdes_rst_c), .CH0_FFC_CDR_EN_BITSLIP(1'b0), + .CH1_FFC_CDR_EN_BITSLIP(1'b0), .D_SCAN_ENABLE(1'b0), .D_SCAN_IN_0(1'b0), + .D_SCAN_IN_1(1'b0), .D_SCAN_IN_2(1'b0), .D_SCAN_IN_3(1'b0), .D_SCAN_IN_4(1'b0), + .D_SCAN_IN_5(1'b0), .D_SCAN_IN_6(1'b0), .D_SCAN_IN_7(1'b0), .D_SCAN_MODE(1'b0), + .D_SCAN_RESET(1'b0), .D_CIN0(1'b0), .D_CIN1(1'b0), .D_CIN2(1'b0), + .D_CIN3(1'b0), .D_CIN4(1'b0), .D_CIN5(1'b0), .D_CIN6(1'b0), + .D_CIN7(1'b0), .D_CIN8(1'b0), .D_CIN9(1'b0), .D_CIN10(1'b0), + .D_CIN11(1'b0), .CH0_HDOUTP(hdoutp), .CH1_HDOUTP(n47), .CH0_HDOUTN(hdoutn), + .CH1_HDOUTN(n48), .D_TXBIT_CLKP_TO_ND(n1), .D_TXBIT_CLKN_TO_ND(n2), + .D_SYNC_PULSE2ND(n3), .D_TXPLL_LOL_TO_ND(n4), .CH0_FF_RX_F_CLK(n5), + .CH1_FF_RX_F_CLK(n49), .CH0_FF_RX_H_CLK(n6), .CH1_FF_RX_H_CLK(n50), + .CH0_FF_TX_F_CLK(n7), .CH1_FF_TX_F_CLK(n51), .CH0_FF_TX_H_CLK(n8), + .CH1_FF_TX_H_CLK(n52), .CH0_FF_RX_PCLK(n9), .CH1_FF_RX_PCLK(n53), + .CH0_FF_TX_PCLK(tx_pclk), .CH1_FF_TX_PCLK(n54), .CH0_FF_RX_D_0(rxdata[0]), + .CH1_FF_RX_D_0(n55), .CH0_FF_RX_D_1(rxdata[1]), .CH1_FF_RX_D_1(n56), + .CH0_FF_RX_D_2(rxdata[2]), .CH1_FF_RX_D_2(n57), .CH0_FF_RX_D_3(rxdata[3]), + .CH1_FF_RX_D_3(n58), .CH0_FF_RX_D_4(rxdata[4]), .CH1_FF_RX_D_4(n59), + .CH0_FF_RX_D_5(rxdata[5]), .CH1_FF_RX_D_5(n60), .CH0_FF_RX_D_6(rxdata[6]), + .CH1_FF_RX_D_6(n61), .CH0_FF_RX_D_7(rxdata[7]), .CH1_FF_RX_D_7(n62), + .CH0_FF_RX_D_8(rx_k[0]), .CH1_FF_RX_D_8(n63), .CH0_FF_RX_D_9(rx_disp_err[0]), + .CH1_FF_RX_D_9(n64), .CH0_FF_RX_D_10(rx_cv_err[0]), .CH1_FF_RX_D_10(n65), + .CH0_FF_RX_D_11(n10), .CH1_FF_RX_D_11(n66), .CH0_FF_RX_D_12(n67), + .CH1_FF_RX_D_12(n68), .CH0_FF_RX_D_13(n69), .CH1_FF_RX_D_13(n70), + .CH0_FF_RX_D_14(n71), .CH1_FF_RX_D_14(n72), .CH0_FF_RX_D_15(n73), + .CH1_FF_RX_D_15(n74), .CH0_FF_RX_D_16(n75), .CH1_FF_RX_D_16(n76), + .CH0_FF_RX_D_17(n77), .CH1_FF_RX_D_17(n78), .CH0_FF_RX_D_18(n79), + .CH1_FF_RX_D_18(n80), .CH0_FF_RX_D_19(n81), .CH1_FF_RX_D_19(n82), + .CH0_FF_RX_D_20(n83), .CH1_FF_RX_D_20(n84), .CH0_FF_RX_D_21(n85), + .CH1_FF_RX_D_21(n86), .CH0_FF_RX_D_22(n87), .CH1_FF_RX_D_22(n88), + .CH0_FF_RX_D_23(n11), .CH1_FF_RX_D_23(n89), .CH0_FFS_PCIE_DONE(n12), + .CH1_FFS_PCIE_DONE(n90), .CH0_FFS_PCIE_CON(n13), .CH1_FFS_PCIE_CON(n91), + .CH0_FFS_RLOS(rx_los_low_s), .CH1_FFS_RLOS(n92), .CH0_FFS_LS_SYNC_STATUS(lsm_status_s), + .CH1_FFS_LS_SYNC_STATUS(n93), .CH0_FFS_CC_UNDERRUN(ctc_urun_s), + .CH1_FFS_CC_UNDERRUN(n94), .CH0_FFS_CC_OVERRUN(ctc_orun_s), .CH1_FFS_CC_OVERRUN(n95), + .CH0_FFS_RXFBFIFO_ERROR(n14), .CH1_FFS_RXFBFIFO_ERROR(n96), .CH0_FFS_TXFBFIFO_ERROR(n15), + .CH1_FFS_TXFBFIFO_ERROR(n97), .CH0_FFS_RLOL(rx_cdr_lol_s), .CH1_FFS_RLOL(n98), + .CH0_FFS_SKP_ADDED(ctc_ins_s), .CH1_FFS_SKP_ADDED(n99), .CH0_FFS_SKP_DELETED(ctc_del_s), + .CH1_FFS_SKP_DELETED(n100), .CH0_LDR_RX2CORE(n101), .CH1_LDR_RX2CORE(_Z), + .D_SCIRDATA0(sci_rddata[0]), .D_SCIRDATA1(sci_rddata[1]), .D_SCIRDATA2(sci_rddata[2]), + .D_SCIRDATA3(sci_rddata[3]), .D_SCIRDATA4(sci_rddata[4]), .D_SCIRDATA5(sci_rddata[5]), + .D_SCIRDATA6(sci_rddata[6]), .D_SCIRDATA7(sci_rddata[7]), .D_SCIINT(sci_int), + .D_SCAN_OUT_0(n16), .D_SCAN_OUT_1(n17), .D_SCAN_OUT_2(n18), .D_SCAN_OUT_3(n19), + .D_SCAN_OUT_4(n20), .D_SCAN_OUT_5(n21), .D_SCAN_OUT_6(n22), .D_SCAN_OUT_7(n23), + .D_COUT0(n24), .D_COUT1(n25), .D_COUT2(n26), .D_COUT3(n27), + .D_COUT4(n28), .D_COUT5(n29), .D_COUT6(n30), .D_COUT7(n31), + .D_COUT8(n32), .D_COUT9(n33), .D_COUT10(n34), .D_COUT11(n35), + .D_COUT12(n36), .D_COUT13(n37), .D_COUT14(n38), .D_COUT15(n39), + .D_COUT16(n40), .D_COUT17(n41), .D_COUT18(n42), .D_COUT19(n43), + .D_REFCLKI(pll_refclki), .D_FFS_PLOL(pll_lol)) /* synthesis LOC=DCU1 CHAN=CH0 */ ; + defparam DCU1_inst.D_MACROPDB = "0b1"; + defparam DCU1_inst.D_IB_PWDNB = "0b1"; + defparam DCU1_inst.D_XGE_MODE = "0b0"; + defparam DCU1_inst.D_LOW_MARK = "0d4"; + defparam DCU1_inst.D_HIGH_MARK = "0d12"; + defparam DCU1_inst.D_BUS8BIT_SEL = "0b0"; + defparam DCU1_inst.D_CDR_LOL_SET = "0b00"; + defparam DCU1_inst.D_TXPLL_PWDNB = "0b1"; + defparam DCU1_inst.D_BITCLK_LOCAL_EN = "0b1"; + defparam DCU1_inst.D_BITCLK_ND_EN = "0b0"; + defparam DCU1_inst.D_BITCLK_FROM_ND_EN = "0b0"; + defparam DCU1_inst.D_SYNC_LOCAL_EN = "0b1"; + defparam DCU1_inst.D_SYNC_ND_EN = "0b0"; + defparam DCU1_inst.CH0_UC_MODE = "0b0"; + defparam DCU1_inst.CH0_PCIE_MODE = "0b0"; + defparam DCU1_inst.CH0_RIO_MODE = "0b0"; + defparam DCU1_inst.CH0_WA_MODE = "0b0"; + defparam DCU1_inst.CH0_INVERT_RX = "0b0"; + defparam DCU1_inst.CH0_INVERT_TX = "0b0"; + defparam DCU1_inst.CH0_PRBS_SELECTION = "0b0"; + defparam DCU1_inst.CH0_GE_AN_ENABLE = "0b0"; + defparam DCU1_inst.CH0_PRBS_LOCK = "0b0"; + defparam DCU1_inst.CH0_PRBS_ENABLE = "0b0"; + defparam DCU1_inst.CH0_ENABLE_CG_ALIGN = "0b1"; + defparam DCU1_inst.CH0_TX_GEAR_MODE = "0b0"; + defparam DCU1_inst.CH0_RX_GEAR_MODE = "0b0"; + defparam DCU1_inst.CH0_PCS_DET_TIME_SEL = "0b00"; + defparam DCU1_inst.CH0_PCIE_EI_EN = "0b0"; + defparam DCU1_inst.CH0_TX_GEAR_BYPASS = "0b0"; + defparam DCU1_inst.CH0_ENC_BYPASS = "0b0"; + defparam DCU1_inst.CH0_SB_BYPASS = "0b0"; + defparam DCU1_inst.CH0_RX_SB_BYPASS = "0b0"; + defparam DCU1_inst.CH0_WA_BYPASS = "0b0"; + defparam DCU1_inst.CH0_DEC_BYPASS = "0b0"; + defparam DCU1_inst.CH0_CTC_BYPASS = "0b0"; + defparam DCU1_inst.CH0_RX_GEAR_BYPASS = "0b0"; + defparam DCU1_inst.CH0_LSM_DISABLE = "0b0"; + defparam DCU1_inst.CH0_MATCH_2_ENABLE = "0b1"; + defparam DCU1_inst.CH0_MATCH_4_ENABLE = "0b0"; + defparam DCU1_inst.CH0_MIN_IPG_CNT = "0b11"; + defparam DCU1_inst.CH0_CC_MATCH_1 = "0x000"; + defparam DCU1_inst.CH0_CC_MATCH_2 = "0x000"; + defparam DCU1_inst.CH0_CC_MATCH_3 = "0x1BC"; + defparam DCU1_inst.CH0_CC_MATCH_4 = "0x050"; + defparam DCU1_inst.CH0_UDF_COMMA_MASK = "0x3ff"; + defparam DCU1_inst.CH0_UDF_COMMA_A = "0x283"; + defparam DCU1_inst.CH0_UDF_COMMA_B = "0x17C"; + defparam DCU1_inst.CH0_RX_DCO_CK_DIV = "0b010"; + defparam DCU1_inst.CH0_RCV_DCC_EN = "0b0"; + defparam DCU1_inst.CH0_TPWDNB = "0b1"; + defparam DCU1_inst.CH0_RATE_MODE_TX = "0b0"; + defparam DCU1_inst.CH0_RTERM_TX = "0d19"; + defparam DCU1_inst.CH0_TX_CM_SEL = "0b00"; + defparam DCU1_inst.CH0_TDRV_PRE_EN = "0b0"; + defparam DCU1_inst.CH0_TDRV_SLICE0_SEL = "0b00"; + defparam DCU1_inst.CH0_TDRV_SLICE1_SEL = "0b00"; + defparam DCU1_inst.CH0_TDRV_SLICE2_SEL = "0b01"; + defparam DCU1_inst.CH0_TDRV_SLICE3_SEL = "0b01"; + defparam DCU1_inst.CH0_TDRV_SLICE4_SEL = "0b00"; + defparam DCU1_inst.CH0_TDRV_SLICE5_SEL = "0b00"; + defparam DCU1_inst.CH0_TDRV_SLICE0_CUR = "0b000"; + defparam DCU1_inst.CH0_TDRV_SLICE1_CUR = "0b000"; + defparam DCU1_inst.CH0_TDRV_SLICE2_CUR = "0b11"; + defparam DCU1_inst.CH0_TDRV_SLICE3_CUR = "0b00"; + defparam DCU1_inst.CH0_TDRV_SLICE4_CUR = "0b00"; + defparam DCU1_inst.CH0_TDRV_SLICE5_CUR = "0b00"; + defparam DCU1_inst.CH0_TDRV_DAT_SEL = "0b00"; + defparam DCU1_inst.CH0_TX_DIV11_SEL = "0b0"; + defparam DCU1_inst.CH0_RPWDNB = "0b1"; + defparam DCU1_inst.CH0_RATE_MODE_RX = "0b0"; + defparam DCU1_inst.CH0_RX_DIV11_SEL = "0b0"; + defparam DCU1_inst.CH0_SEL_SD_RX_CLK = "0b0"; + defparam DCU1_inst.CH0_FF_RX_H_CLK_EN = "0b0"; + defparam DCU1_inst.CH0_FF_RX_F_CLK_DIS = "0b0"; + defparam DCU1_inst.CH0_FF_TX_H_CLK_EN = "0b0"; + defparam DCU1_inst.CH0_FF_TX_F_CLK_DIS = "0b0"; + defparam DCU1_inst.CH0_TDRV_POST_EN = "0b0"; + defparam DCU1_inst.CH0_TX_POST_SIGN = "0b0"; + defparam DCU1_inst.CH0_TX_PRE_SIGN = "0b0"; + defparam DCU1_inst.CH0_REQ_LVL_SET = "0b00"; + defparam DCU1_inst.CH0_REQ_EN = "0b1"; + defparam DCU1_inst.CH0_RTERM_RX = "0d22"; + defparam DCU1_inst.CH0_RXTERM_CM = "0b11"; + defparam DCU1_inst.CH0_PDEN_SEL = "0b1"; + defparam DCU1_inst.CH0_RXIN_CM = "0b11"; + defparam DCU1_inst.CH0_LEQ_OFFSET_SEL = "0b0"; + defparam DCU1_inst.CH0_LEQ_OFFSET_TRIM = "0b000"; + defparam DCU1_inst.CH0_RLOS_SEL = "0b1"; + defparam DCU1_inst.CH0_RX_LOS_LVL = "0b100"; + defparam DCU1_inst.CH0_RX_LOS_CEQ = "0b11"; + defparam DCU1_inst.CH0_RX_LOS_HYST_EN = "0b0"; + defparam DCU1_inst.CH0_RX_LOS_EN = "0b1"; + defparam DCU1_inst.CH0_LDR_RX2CORE_SEL = "0b0"; + defparam DCU1_inst.CH0_LDR_CORE2TX_SEL = "0b0"; + defparam DCU1_inst.D_TX_MAX_RATE = "1.25"; + defparam DCU1_inst.CH0_CDR_MAX_RATE = "1.25"; + defparam DCU1_inst.CH0_TXAMPLITUDE = "0d400"; + defparam DCU1_inst.CH0_TXDEPRE = "DISABLED"; + defparam DCU1_inst.CH0_TXDEPOST = "DISABLED"; + defparam DCU1_inst.CH0_PROTOCOL = "GBE"; + defparam DCU1_inst.D_ISETLOS = "0d0"; + defparam DCU1_inst.D_SETIRPOLY_AUX = "0b00"; + defparam DCU1_inst.D_SETICONST_AUX = "0b00"; + defparam DCU1_inst.D_SETIRPOLY_CH = "0b00"; + defparam DCU1_inst.D_SETICONST_CH = "0b00"; + defparam DCU1_inst.D_REQ_ISET = "0b000"; + defparam DCU1_inst.D_PD_ISET = "0b00"; + defparam DCU1_inst.D_DCO_CALIB_TIME_SEL = "0b00"; + defparam DCU1_inst.CH0_CDR_CNT4SEL = "0b00"; + defparam DCU1_inst.CH0_CDR_CNT8SEL = "0b00"; + defparam DCU1_inst.CH0_DCOATDCFG = "0b00"; + defparam DCU1_inst.CH0_DCOATDDLY = "0b00"; + defparam DCU1_inst.CH0_DCOBYPSATD = "0b1"; + defparam DCU1_inst.CH0_DCOCALDIV = "0b001"; + defparam DCU1_inst.CH0_DCOCTLGI = "0b010"; + defparam DCU1_inst.CH0_DCODISBDAVOID = "0b0"; + defparam DCU1_inst.CH0_DCOFLTDAC = "0b01"; + defparam DCU1_inst.CH0_DCOFTNRG = "0b110"; + defparam DCU1_inst.CH0_DCOIOSTUNE = "0b000"; + defparam DCU1_inst.CH0_DCOITUNE = "0b00"; + defparam DCU1_inst.CH0_DCOITUNE4LSB = "0b111"; + defparam DCU1_inst.CH0_DCOIUPDNX2 = "0b1"; + defparam DCU1_inst.CH0_DCONUOFLSB = "0b101"; + defparam DCU1_inst.CH0_DCOSCALEI = "0b00"; + defparam DCU1_inst.CH0_DCOSTARTVAL = "0b000"; + defparam DCU1_inst.CH0_DCOSTEP = "0b00"; + defparam DCU1_inst.CH0_BAND_THRESHOLD = "0d0"; + defparam DCU1_inst.CH0_AUTO_FACQ_EN = "0b1"; + defparam DCU1_inst.CH0_AUTO_CALIB_EN = "0b1"; + defparam DCU1_inst.CH0_CALIB_CK_MODE = "0b0"; + defparam DCU1_inst.CH0_REG_BAND_OFFSET = "0d0"; + defparam DCU1_inst.CH0_REG_BAND_SEL = "0d0"; + defparam DCU1_inst.CH0_REG_IDAC_SEL = "0d0"; + defparam DCU1_inst.CH0_REG_IDAC_EN = "0b0"; + defparam DCU1_inst.D_CMUSETISCL4VCO = "0b000"; + defparam DCU1_inst.D_CMUSETI4VCO = "0b00"; + defparam DCU1_inst.D_CMUSETINITVCT = "0b00"; + defparam DCU1_inst.D_CMUSETZGM = "0b000"; + defparam DCU1_inst.D_CMUSETP2AGM = "0b000"; + defparam DCU1_inst.D_CMUSETP1GM = "0b000"; + defparam DCU1_inst.D_CMUSETI4CPZ = "0d3"; + defparam DCU1_inst.D_CMUSETI4CPP = "0d3"; + defparam DCU1_inst.D_CMUSETICP4Z = "0b101"; + defparam DCU1_inst.D_CMUSETICP4P = "0b01"; + defparam DCU1_inst.D_CMUSETBIASI = "0b00"; + defparam DCU1_inst.D_SETPLLRC = "0d1"; + defparam DCU1_inst.CH0_RX_RATE_SEL = "0d8"; + defparam DCU1_inst.D_REFCK_MODE = "0b100"; + defparam DCU1_inst.D_TX_VCO_CK_DIV = "0b010"; + defparam DCU1_inst.D_PLL_LOL_SET = "0b00"; + defparam DCU1_inst.D_RG_EN = "0b0"; + defparam DCU1_inst.D_RG_SET = "0b00"; + assign n1 = 1'bz; + assign n2 = 1'bz; + assign n3 = 1'bz; + assign n4 = 1'bz; + assign n5 = 1'bz; + assign n6 = 1'bz; + assign n7 = 1'bz; + assign n8 = 1'bz; + assign n9 = 1'bz; + assign n10 = 1'bz; + assign n11 = 1'bz; + assign n12 = 1'bz; + assign n13 = 1'bz; + assign n14 = 1'bz; + assign n15 = 1'bz; + assign n16 = 1'bz; + assign n17 = 1'bz; + assign n18 = 1'bz; + assign n19 = 1'bz; + assign n20 = 1'bz; + assign n21 = 1'bz; + assign n22 = 1'bz; + assign n23 = 1'bz; + assign n24 = 1'bz; + assign n25 = 1'bz; + assign n26 = 1'bz; + assign n27 = 1'bz; + assign n28 = 1'bz; + assign n29 = 1'bz; + assign n30 = 1'bz; + assign n31 = 1'bz; + assign n32 = 1'bz; + assign n33 = 1'bz; + assign n34 = 1'bz; + assign n35 = 1'bz; + assign n36 = 1'bz; + assign n37 = 1'bz; + assign n38 = 1'bz; + assign n39 = 1'bz; + assign n40 = 1'bz; + assign n41 = 1'bz; + assign n42 = 1'bz; + assign n43 = 1'bz; + assign n46 = 1'bz; + assign n47 = 1'bz; + assign n48 = 1'bz; + assign n49 = 1'bz; + assign n50 = 1'bz; + assign n51 = 1'bz; + assign n52 = 1'bz; + assign n53 = 1'bz; + assign n54 = 1'bz; + assign n55 = 1'bz; + assign n56 = 1'bz; + assign n57 = 1'bz; + assign n58 = 1'bz; + assign n59 = 1'bz; + assign n60 = 1'bz; + assign n61 = 1'bz; + assign n62 = 1'bz; + assign n63 = 1'bz; + assign n64 = 1'bz; + assign n65 = 1'bz; + assign n66 = 1'bz; + assign n67 = 1'bz; + assign n68 = 1'bz; + assign n69 = 1'bz; + assign n70 = 1'bz; + assign n71 = 1'bz; + assign n72 = 1'bz; + assign n73 = 1'bz; + assign n74 = 1'bz; + assign n75 = 1'bz; + assign n76 = 1'bz; + assign n77 = 1'bz; + assign n78 = 1'bz; + assign n79 = 1'bz; + assign n80 = 1'bz; + assign n81 = 1'bz; + assign n82 = 1'bz; + assign n83 = 1'bz; + assign n84 = 1'bz; + assign n85 = 1'bz; + assign n86 = 1'bz; + assign n87 = 1'bz; + assign n88 = 1'bz; + assign n89 = 1'bz; + assign n90 = 1'bz; + assign n91 = 1'bz; + assign n92 = 1'bz; + assign n93 = 1'bz; + assign n94 = 1'bz; + assign n95 = 1'bz; + assign n96 = 1'bz; + assign n97 = 1'bz; + assign n98 = 1'bz; + assign n99 = 1'bz; + assign n100 = 1'bz; + assign n101 = 1'bz; + assign _Z = 1'bz; + sgmii2sll_core sll_inst (.sli_rst(sli_rst), .sli_refclk(pll_refclki), + .sli_pclk(tx_pclk), .sli_div2_rate(1'b0), .sli_div11_rate(1'b0), + .sli_gear_mode(1'b0), .sli_cpri_mode({3'b000}), .sli_pcie_mode(1'b0), + .slo_plol()); + defparam sll_inst.PPROTOCOL = "GBE"; + defparam sll_inst.PLOL_SETTING = 0; + defparam sll_inst.PDYN_RATE_CTRL = "DISABLED"; + defparam sll_inst.PPCIE_MAX_RATE = "2.5"; + defparam sll_inst.PDIFF_VAL_LOCK = 98; + defparam sll_inst.PDIFF_VAL_UNLOCK = 196; + defparam sll_inst.PPCLK_TC = 327680; + defparam sll_inst.PDIFF_DIV11_VAL_LOCK = 0; + defparam sll_inst.PDIFF_DIV11_VAL_UNLOCK = 0; + defparam sll_inst.PPCLK_DIV11_TC = 0; + +endmodule + + diff --git a/clarity/pcs/sgmii2/sgmii2_softlogic.v b/clarity/pcs/sgmii2/sgmii2_softlogic.v new file mode 100644 index 0000000..5346253 --- /dev/null +++ b/clarity/pcs/sgmii2/sgmii2_softlogic.v @@ -0,0 +1,1060 @@ + +// =========================================================================== +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< +// --------------------------------------------------------------------------- +// Copyright (c) 2015 by Lattice Semiconductor Corporation +// ALL RIGHTS RESERVED +// ------------------------------------------------------------------ +// +// Permission: +// +// Lattice SG Pte. Ltd. grants permission to use this code +// pursuant to the terms of the Lattice Reference Design License Agreement. +// +// +// Disclaimer: +// +// This VHDL or Verilog source code is intended as a design reference +// which illustrates how these types of functions can be implemented. +// It is the user's responsibility to verify their design for +// consistency and functionality through the use of formal +// verification methods. Lattice provides no warranty +// regarding the use or functionality of this code. +// +// --------------------------------------------------------------------------- +// +// Lattice SG Pte. Ltd. +// 101 Thomson Road, United Square #07-02 +// Singapore 307591 +// +// +// TEL: 1-800-Lattice (USA and Canada) +// +65-6631-2000 (Singapore) +// +1-503-268-8001 (other locations) +// +// web: http://www.latticesemi.com/ +// email: techsupport@latticesemi.com +// +// --------------------------------------------------------------------------- +// +// ============================================================================= +// FILE DETAILS +// Project : SLL - Soft Loss Of Lock(LOL) Logic +// File : sll_core.v +// Title : Top-level file for SLL +// Dependencies : 1. +// : 2. +// Description : +// ============================================================================= +// REVISION HISTORY +// Version : 1.0 +// Author(s) : AV +// Mod. Date : March 2, 2015 +// Changes Made : Initial Creation +// ============================================================================= +// REVISION HISTORY +// Version : 1.1 +// Author(s) : AV +// Mod. Date : June 8, 2015 +// Changes Made : Following updates were made +// : 1. Changed all the PLOL status logic and FSM to run +// : on sli_refclk. +// : 2. Added the HB logic for presence of tx_pclk +// : 3. Changed the lparam assignment scheme for +// : simulation purposes. +// ============================================================================= +// REVISION HISTORY +// Version : 1.2 +// Author(s) : AV +// Mod. Date : June 24, 2015 +// Changes Made : Updated the gearing logic for SDI dynamic rate change +// ============================================================================= +// REVISION HISTORY +// Version : 1.3 +// Author(s) : AV +// Mod. Date : July 14, 2015 +// Changes Made : Added the logic for dynamic rate change in CPRI +// ============================================================================= +// REVISION HISTORY +// Version : 1.4 +// Author(s) : AV +// Mod. Date : August 21, 2015 +// Changes Made : Added the logic for dynamic rate change of 5G CPRI & +// PCIe. +// ============================================================================= +// REVISION HISTORY +// Version : 1.5 +// Author(s) : ES/EB +// Mod. Date : March 21, 2017 +// Changes Made : 1. Added pdiff_sync signal to syncrhonize pcount_diff +// : to sli_refclk. +// : 2. Updated terminal count logic for PCIe 5G +// : 3. Modified checking of pcount_diff in SLL state +// : machine to cover actual count +// : (from 16-bits to 22-bits) +// ============================================================================= +// REVISION HISTORY +// Version : 1.6 +// Author(s) : ES +// Mod. Date : April 19, 2017 +// Changes Made : 1. Added registered lock and unlock signal from +// pdiff_sync to totally decouple pcount_diff from +// SLL state machine. +// : 2. Modified LPCLK_TC_4 to 1:1 clock ratio when CPRI +// is operating @ 4.9125Gbps data rate. +// ============================================================================= +`timescale 1ns/10ps + +module sgmii2sll_core ( + //Reset and Clock inputs + sli_rst, //Active high asynchronous reset input + sli_refclk, //Refclk input to the Tx PLL + sli_pclk, //Tx pclk output from the PCS + + //Control inputs + sli_div2_rate, //Divide by 2 control; 0 - Full rate; 1 - Half rate + sli_div11_rate, //Divide by 11 control; 0 - Full rate; 1 - Div by 11 + sli_gear_mode, //Gear mode control for PCS; 0 - 8/10; 1- 16/20 + sli_cpri_mode, //Mode of operation specific to CPRI protocol + sli_pcie_mode, //Mode of operation specific to PCIe mode (2.5G or 5G) + + //LOL Output + slo_plol //Tx PLL Loss of Lock output to the user logic + ); + +// Inputs +input sli_rst; +input sli_refclk; +input sli_pclk; +input sli_div2_rate; +input sli_div11_rate; +input sli_gear_mode; +input [2:0] sli_cpri_mode; +input sli_pcie_mode; + +// Outputs +output slo_plol; + + +// Parameters +parameter PPROTOCOL = "PCIE"; //Protocol selected by the User +parameter PLOL_SETTING = 0; //PLL LOL setting. Possible values are 0,1,2,3 +parameter PDYN_RATE_CTRL = "DISABLED"; //PCS Dynamic Rate control +parameter PPCIE_MAX_RATE = "2.5"; //PCIe max data rate +parameter PDIFF_VAL_LOCK = 20; //Differential count value for Lock +parameter PDIFF_VAL_UNLOCK = 39; //Differential count value for Unlock +parameter PPCLK_TC = 65535; //Terminal count value for counter running on sli_pclk +parameter PDIFF_DIV11_VAL_LOCK = 3; //Differential count value for Lock for SDI Div11 +parameter PDIFF_DIV11_VAL_UNLOCK = 3; //Differential count value for Unlock for SDI Div11 +parameter PPCLK_DIV11_TC = 2383; //Terminal count value (SDI Div11) for counter running on sli_pclk + + +// Local Parameters +localparam [1:0] LPLL_LOSS_ST = 2'b00; //PLL Loss state +localparam [1:0] LPLL_PRELOSS_ST = 2'b01; //PLL Pre-Loss state +localparam [1:0] LPLL_PRELOCK_ST = 2'b10; //PLL Pre-Lock state +localparam [1:0] LPLL_LOCK_ST = 2'b11; //PLL Lock state +`ifdef RSL_SIM_MODE +localparam [15:0] LRCLK_TC = 16'd63; //Terminal count value for counter running on sli_refclk +`else +localparam [15:0] LRCLK_TC = 16'd65535; //Terminal count value for counter running on sli_refclk +`endif +localparam [15:0] LRCLK_TC_PUL_WIDTH = 16'd50; //Pulse width for the Refclk terminal count pulse +localparam [7:0] LHB_WAIT_CNT = 8'd255; //Wait count for the Heartbeat signal + +// Local Parameters related to the CPRI dynamic modes +// Terminal count values for the four CPRI modes +localparam LPCLK_TC_0 = 32768; +localparam LPCLK_TC_1 = 65536; +localparam LPCLK_TC_2 = 131072; +localparam LPCLK_TC_3 = 163840; +localparam LPCLK_TC_4 = 65536; + +// Lock values count values for the four CPRI modes and four PLOL settings (4x5) +// CPRI rate mode 0 CPRI rate mode 1 CPRI rate mode 2 CPRI rate mode 3 CPRI rate mode 4 +localparam LPDIFF_LOCK_00 = 9; localparam LPDIFF_LOCK_10 = 19; localparam LPDIFF_LOCK_20 = 39; localparam LPDIFF_LOCK_30 = 49; localparam LPDIFF_LOCK_40 = 19; +localparam LPDIFF_LOCK_01 = 9; localparam LPDIFF_LOCK_11 = 19; localparam LPDIFF_LOCK_21 = 39; localparam LPDIFF_LOCK_31 = 49; localparam LPDIFF_LOCK_41 = 19; +localparam LPDIFF_LOCK_02 = 49; localparam LPDIFF_LOCK_12 = 98; localparam LPDIFF_LOCK_22 = 196; localparam LPDIFF_LOCK_32 = 245; localparam LPDIFF_LOCK_42 = 98; +localparam LPDIFF_LOCK_03 = 131; localparam LPDIFF_LOCK_13 = 262; localparam LPDIFF_LOCK_23 = 524; localparam LPDIFF_LOCK_33 = 655; localparam LPDIFF_LOCK_43 = 262; + +// Unlock values count values for the four CPRI modes and four PLOL settings (4x5) +// CPRI rate mode 0 CPRI rate mode 1 CPRI rate mode 2 CPRI rate mode 3 CPRI rate mode 4 +localparam LPDIFF_UNLOCK_00 = 19; localparam LPDIFF_UNLOCK_10 = 39; localparam LPDIFF_UNLOCK_20 = 78; localparam LPDIFF_UNLOCK_30 = 98; localparam LPDIFF_UNLOCK_40 = 39; +localparam LPDIFF_UNLOCK_01 = 65; localparam LPDIFF_UNLOCK_11 = 131; localparam LPDIFF_UNLOCK_21 = 262; localparam LPDIFF_UNLOCK_31 = 327; localparam LPDIFF_UNLOCK_41 = 131; +localparam LPDIFF_UNLOCK_02 = 72; localparam LPDIFF_UNLOCK_12 = 144; localparam LPDIFF_UNLOCK_22 = 288; localparam LPDIFF_UNLOCK_32 = 360; localparam LPDIFF_UNLOCK_42 = 144; +localparam LPDIFF_UNLOCK_03 = 196; localparam LPDIFF_UNLOCK_13 = 393; localparam LPDIFF_UNLOCK_23 = 786; localparam LPDIFF_UNLOCK_33 = 983; localparam LPDIFF_UNLOCK_43 = 393; + +// Input and Output reg and wire declarations +wire sli_rst; +wire sli_refclk; +wire sli_pclk; +wire sli_div2_rate; +wire sli_div11_rate; +wire sli_gear_mode; +wire [2:0] sli_cpri_mode; +wire sli_pcie_mode; +wire slo_plol; + +//-------------- Internal signals reg and wire declarations -------------------- + +//Signals running on sli_refclk +reg [15:0] rcount; //16-bit Counter +reg rtc_pul; //Terminal count pulse +reg rtc_pul_p1; //Terminal count pulse pipeline +reg rtc_ctrl; //Terminal count pulse control + +reg [7:0] rhb_wait_cnt; //Heartbeat wait counter + +//Heatbeat synchronization and pipeline registers +wire rhb_sync; +reg rhb_sync_p2; +reg rhb_sync_p1; + +//Pipeling registers for dynamic control mode +wire rgear; +wire rdiv2; +wire rdiv11; +reg rgear_p1; +reg rdiv2_p1; +reg rdiv11_p1; + +reg rstat_pclk; //Pclk presence/absence status + +reg [21:0] rcount_tc; //Tx_pclk terminal count register +reg [15:0] rdiff_comp_lock; //Differential comparison value for Lock +reg [15:0] rdiff_comp_unlock; //Differential compariosn value for Unlock + +wire rpcie_mode; //PCIe mode signal synchronized to refclk +reg rpcie_mode_p1; //PCIe mode pipeline register + +wire rcpri_mod_ch_sync; //CPRI mode change synchronized to refclk +reg rcpri_mod_ch_p1; //CPRI mode change pipeline register +reg rcpri_mod_ch_p2; //CPRI mode change pipeline register +reg rcpri_mod_ch_st; //CPRI mode change status + +reg [1:0] sll_state; //Current-state register for LOL FSM + +reg pll_lock; //PLL Lock signal + +//Signals running on sli_pclk +//Synchronization and pipeline registers +wire ppul_sync; +reg ppul_sync_p1; +reg ppul_sync_p2; +reg ppul_sync_p3; + +wire pdiff_sync; +reg pdiff_sync_p1; + +reg [21:0] pcount; //22-bit counter +reg [21:0] pcount_diff; //Differential value between Tx_pclk counter and theoritical value + +//Heartbeat counter and heartbeat signal running on pclk +reg [2:0] phb_cnt; +reg phb; + +//CPRI dynamic mode releated signals +reg [2:0] pcpri_mode; +reg pcpri_mod_ch; + +//Assignment scheme changed mainly for simulation purpose +wire [15:0] LRCLK_TC_w; +assign LRCLK_TC_w = LRCLK_TC; + +reg unlock; +reg lock; + +//Heartbeat synchronization +sync # (.PDATA_RST_VAL(0)) phb_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (phb), + .data_out(rhb_sync) + ); + + +//Terminal count pulse synchronization +sync # (.PDATA_RST_VAL(0)) rtc_sync_inst ( + .clk (sli_pclk), + .rst (sli_rst), + .data_in (rtc_pul), + .data_out(ppul_sync) + ); + +//Differential value logic update synchronization +sync # (.PDATA_RST_VAL(0)) pdiff_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (ppul_sync), + .data_out(pdiff_sync) + ); + +//Gear mode synchronization +sync # (.PDATA_RST_VAL(0)) gear_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (sli_gear_mode), + .data_out(rgear) + ); + +//Div2 synchronization +sync # (.PDATA_RST_VAL(0)) div2_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (sli_div2_rate), + .data_out(rdiv2) + ); + +//Div11 synchronization +sync # (.PDATA_RST_VAL(0)) div11_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (sli_div11_rate), + .data_out(rdiv11) + ); + +//CPRI mode change synchronization +sync # (.PDATA_RST_VAL(0)) cpri_mod_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (pcpri_mod_ch), + .data_out(rcpri_mod_ch_sync) + ); + +//PCIe mode change synchronization +sync # (.PDATA_RST_VAL(0)) pcie_mod_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (sli_pcie_mode), + .data_out(rpcie_mode) + ); + +// ============================================================================= +// Synchronized Lock/Unlock signals +// ============================================================================= +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + unlock <= 1'b0; + lock <= 1'b0; + pdiff_sync_p1 <= 1'b0; + end + else begin + pdiff_sync_p1 <= pdiff_sync; + if (unlock) begin + unlock <= ~pdiff_sync && pdiff_sync_p1 ? 1'b0 : unlock; + end + else begin + unlock <= pdiff_sync ? (pcount_diff[21:0] > {6'd0, rdiff_comp_unlock}) : 1'b0; + end + if (lock) begin + lock <= ~pdiff_sync && pdiff_sync_p1 ? 1'b0 : lock; + end + else begin + lock <= pdiff_sync ? (pcount_diff[21:0] <= {6'd0, rdiff_comp_lock}) : 1'b0; + end + end +end + +// ============================================================================= +// Refclk Counter, pulse generation logic and Heartbeat monitor logic +// ============================================================================= +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rcount <= 16'd0; + rtc_pul <= 1'b0; + rtc_ctrl <= 1'b0; + rtc_pul_p1 <= 1'b0; + end + else begin + //Counter logic + if ((rgear_p1^rgear == 1'b1) || (rdiv2_p1^rdiv2 == 1'b1) || (rdiv11_p1^rdiv11 == 1'b1) || (rcpri_mod_ch_p1^rcpri_mod_ch_p2 == 1'b1) || (rpcie_mode_p1^rpcie_mode == 1'b1)) begin + if (rtc_ctrl == 1'b1) begin + rcount <= LRCLK_TC_PUL_WIDTH; + end + end + else begin + if (rcount != LRCLK_TC_w) begin + rcount <= rcount + 1; + end + else begin + rcount <= 16'd0; + end + end + + //Pulse control logic + if (rcount == LRCLK_TC_w - 1) begin + rtc_ctrl <= 1'b1; + end + + //Pulse Generation logic + if (rtc_ctrl == 1'b1) begin + if ((rcount == LRCLK_TC_w) || (rcount < LRCLK_TC_PUL_WIDTH)) begin + rtc_pul <= 1'b1; + end + else begin + rtc_pul <= 1'b0; + end + end + + rtc_pul_p1 <= rtc_pul; + end +end + + +// ============================================================================= +// Heartbeat synchronization & monitor logic and Dynamic mode pipeline logic +// ============================================================================= +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rhb_sync_p1 <= 1'b0; + rhb_sync_p2 <= 1'b0; + rhb_wait_cnt <= 8'd0; + rstat_pclk <= 1'b0; + rgear_p1 <= 1'b0; + rdiv2_p1 <= 1'b0; + rdiv11_p1 <= 1'b0; + rcpri_mod_ch_p1 <= 1'b0; + rcpri_mod_ch_p2 <= 1'b0; + rcpri_mod_ch_st <= 1'b0; + rpcie_mode_p1 <= 1'b0; + + end + else begin + //Pipeline stages for the Heartbeat + rhb_sync_p1 <= rhb_sync; + rhb_sync_p2 <= rhb_sync_p1; + + //Pipeline stages of the Dynamic rate control signals + rgear_p1 <= rgear; + rdiv2_p1 <= rdiv2; + rdiv11_p1 <= rdiv11; + + //Pipeline stage for PCIe mode + rpcie_mode_p1 <= rpcie_mode; + + //Pipeline stage for CPRI mode change + rcpri_mod_ch_p1 <= rcpri_mod_ch_sync; + rcpri_mod_ch_p2 <= rcpri_mod_ch_p1; + + //CPRI mode change status logic + if (rcpri_mod_ch_p1^rcpri_mod_ch_sync == 1'b1) begin + rcpri_mod_ch_st <= 1'b1; + end + + //Heartbeat wait counter and monitor logic + if (rtc_ctrl == 1'b1) begin + if (rhb_sync_p1 == 1'b1 && rhb_sync_p2 == 1'b0) begin + rhb_wait_cnt <= 8'd0; + rstat_pclk <= 1'b1; + end + else if (rhb_wait_cnt == LHB_WAIT_CNT) begin + rhb_wait_cnt <= 8'd0; + rstat_pclk <= 1'b0; + end + else begin + rhb_wait_cnt <= rhb_wait_cnt + 1; + end + end + end +end + + +// ============================================================================= +// Pipleline registers for the TC pulse and CPRI mode change logic +// ============================================================================= +always @(posedge sli_pclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + ppul_sync_p1 <= 1'b0; + ppul_sync_p2 <= 1'b0; + ppul_sync_p3 <= 1'b0; + pcpri_mode <= 3'b0; + pcpri_mod_ch <= 1'b0; + end + else begin + ppul_sync_p1 <= ppul_sync; + ppul_sync_p2 <= ppul_sync_p1; + ppul_sync_p3 <= ppul_sync_p2; + + //CPRI mode change logic + pcpri_mode <= sli_cpri_mode; + + if (pcpri_mode != sli_cpri_mode) begin + pcpri_mod_ch <= ~pcpri_mod_ch; + end + end +end + + +// ============================================================================= +// Terminal count logic +// ============================================================================= + +//For SDI protocol with Dynamic rate control enabled +generate +if ((PDYN_RATE_CTRL == "ENABLED") && (PPROTOCOL == "SDI")) begin +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rcount_tc <= 22'd0; + rdiff_comp_lock <= 16'd0; + rdiff_comp_unlock <= 16'd0; + end + else begin + //Terminal count logic + //Div by 11 is enabled + if (rdiv11 == 1'b1) begin + //Gear mode is 16/20 + if (rgear == 1'b1) begin + rcount_tc <= PPCLK_DIV11_TC; + rdiff_comp_lock <= PDIFF_DIV11_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_DIV11_VAL_UNLOCK; + end + else begin + rcount_tc <= {PPCLK_DIV11_TC[20:0], 1'b0}; + rdiff_comp_lock <= {PDIFF_DIV11_VAL_LOCK[14:0], 1'b0}; + rdiff_comp_unlock <= {PDIFF_DIV11_VAL_UNLOCK[14:0], 1'b0}; + end + end + //Div by 2 is enabled + else if (rdiv2 == 1'b1) begin + //Gear mode is 16/20 + if (rgear == 1'b1) begin + rcount_tc <= {1'b0,PPCLK_TC[21:1]}; + rdiff_comp_lock <= {1'b0,PDIFF_VAL_LOCK[15:1]}; + rdiff_comp_unlock <= {1'b0,PDIFF_VAL_UNLOCK[15:1]}; + end + else begin + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end + end + //Both div by 11 and div by 2 are disabled + else begin + //Gear mode is 16/20 + if (rgear == 1'b1) begin + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end + else begin + rcount_tc <= {PPCLK_TC[20:0],1'b0}; + rdiff_comp_lock <= {PDIFF_VAL_LOCK[14:0],1'b0}; + rdiff_comp_unlock <= {PDIFF_VAL_UNLOCK[14:0],1'b0}; + end + end + end +end +end +endgenerate + +//For G8B10B protocol with Dynamic rate control enabled +generate +if ((PDYN_RATE_CTRL == "ENABLED") && (PPROTOCOL == "G8B10B")) begin +alway |