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+// Verilog netlist produced by program ASBGen: Ports rev. 2.30, Attr. rev. 2.65
+// Netlist written on Tue Oct 17 18:22:54 2017
+//
+// Verilog Description of module refclk0
+//
+
+`timescale 1ns/1ps
+module refclk0 (refclkp, refclkn, refclko);
+ input refclkp;
+ input refclkn;
+ output refclko;
+
+
+ EXTREFB EXTREF0_inst (.REFCLKP(refclkp), .REFCLKN(refclkn), .REFCLKO(refclko)) /* synthesis LOC=EXTREF0 */ ;
+ defparam EXTREF0_inst.REFCK_PWDNB = "0b1";
+ defparam EXTREF0_inst.REFCK_RTERM = "0b1";
+ defparam EXTREF0_inst.REFCK_DCBIAS_EN = "0b0";
+
+endmodule
+

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