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privateisland
darsena
gpio
master
pkt_gen
Open Source FPGA Verilog Project for Networking
Private Island Networks Inc.
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Commit message
Author
Age
darsena
manu: prune and rename to make current
Private Island Networks
13 months
gpio
project: add gpio revision to support daughter board I/O renaming
Private Island Networks Inc.
5 weeks
master
sim: update sim related files for website article https://privateisland.tech/...
Private Island Networks Inc
6 weeks
pkt_gen
sim: upddate mpf project file, tb, and sim scripts to support first pass pkt_gen
Private Island Networks Inc
6 weeks
Age
Commit message
Author
2025-07-03
manu: prune and rename to make current
darsena
Private Island Networks
2023-12-27
drop_fifo: fix up logic when packets are dropped
Private Island Networks Inc
2021-06-30
controller: rm i2c_fifo_priority because it is no longer used
mindchasers
2021-06-30
top/controller: re i2c_fifo_priority because it is no longer used
mindchasers
2021-03-02
top: remap shield I/O to use GPIO rather than specific names, default is now ...
mindchasers
2021-03-02
ecp5um: include this Lattice file for easy reference
mindchasers
2021-03-02
update project file
mindchasers
2021-03-02
switch: add tx_src_sel
mindchasers
2021-03-02
spi: fix write bug
mindchasers
2021-03-02
pkt_filter: add wire for match
mindchasers
[...]
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