diff options
| author | Private Island Networks Inc. <opensource@privateisland.tech> | 2026-07-06 14:00:38 -0400 |
|---|---|---|
| committer | Private Island Networks Inc. <opensource@privateisland.tech> | 2026-07-06 14:00:38 -0400 |
| commit | 510f3c7286c3c325f6ba6a61e43e3141f6e0df25 (patch) | |
| tree | bb44a7927d199b20171a01bb2fcc0bd6afaf9da8 | |
| parent | 3f27dd29f10ade4ec76cdda0459fdf0464b19a7e (diff) | |
project: add gpio revision to support daughter board I/O renaminggpio
4 files changed, 1614 insertions, 12 deletions
diff --git a/manufacturer/altera/cyclone10_lp/betsy.qpf b/manufacturer/altera/cyclone10_lp/betsy.qpf index c6aaaba..9d77a60 100644 --- a/manufacturer/altera/cyclone10_lp/betsy.qpf +++ b/manufacturer/altera/cyclone10_lp/betsy.qpf @@ -1,31 +1,32 @@ # -------------------------------------------------------------------------- # # -# Copyright (C) 2023 Intel Corporation. All rights reserved. -# Your use of Intel Corporation's design tools, logic functions +# Copyright (C) 2025 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions # and other software and tools, and any partner logic # functions, and any output files from any of the foregoing # (including device programming or simulation files), and any # associated documentation or information are expressly subject -# to the terms and conditions of the Intel Program License -# Subscription Agreement, the Intel Quartus Prime License Agreement, -# the Intel FPGA IP License Agreement, or other applicable license +# to the terms and conditions of the Altera Program License +# Subscription Agreement, the Altera Quartus Prime License Agreement, +# the Altera IP License Agreement, or other applicable license # agreement, including, without limitation, that your use is for # the sole purpose of programming logic devices manufactured by -# Intel and sold by Intel or its authorized distributors. Please -# refer to the applicable agreement for further details, at -# https://fpgasoftware.intel.com/eula. +# Altera and sold by Altera or its authorized distributors. Please +# refer to the Altera Software License Subscription Agreements +# on the Quartus Prime software download page. # # -------------------------------------------------------------------------- # # # Quartus Prime -# Version 23.1std.0 Build 991 11/28/2023 Patches 0.02std SC Lite Edition -# Date created = 13:02:56 May 09, 2024 +# Version 25.1std.0 Build 1129 10/21/2025 SC Standard Edition +# Date created = 13:39:14 July 06, 2026 # # -------------------------------------------------------------------------- # -QUARTUS_VERSION = "23.1" -DATE = "13:02:56 May 09, 2024" +QUARTUS_VERSION = "25.1" +DATE = "13:39:14 July 06, 2026" # Revisions +PROJECT_REVISION = "betsy_gpio" PROJECT_REVISION = "betsy" diff --git a/manufacturer/altera/cyclone10_lp/betsy_gpio.qsf b/manufacturer/altera/cyclone10_lp/betsy_gpio.qsf new file mode 100644 index 0000000..3ca429f --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/betsy_gpio.qsf @@ -0,0 +1,793 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2020 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details, at +# https://fpgasoftware.intel.com/eula. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition +# Date created = 00:31:06 February 23, 2021 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# betsy_gpio_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone 10 LP" +set_global_assignment -name DEVICE 10CL025YU256I7G +set_global_assignment -name TOP_LEVEL_ENTITY betsy +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 25.1STD.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:52:46 JUNE 30, 2026" +set_global_assignment -name LAST_QUARTUS_VERSION "25.1std.0 Standard Edition" +set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40" +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 +set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 256 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V +set_global_assignment -name EDA_SIMULATION_TOOL "Questa Altera FPGA (Verilog)" +set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name ENABLE_OCT_DONE OFF +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall +set_global_assignment -name ENABLE_SIGNALTAP ON +set_global_assignment -name USE_SIGNALTAP_FILE brds/betsy/betsy.stp +set_global_assignment -name USE_CONFIGURATION_DEVICE ON +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE MT25QL128 +set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" + +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_betsy + +# Set Directive for GPIO +set_global_assignment -name VERILOG_MACRO "GPIO_PRESENT=1" + + + +# Bank 1 Configuration, Sheet 6 +set_location_assignment PIN_E1 -to flash_dqs +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to flash_dqs +#set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to flash_dqs + +set_location_assignment PIN_B1 -to flash_d[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to flash_d[4] + +set_location_assignment PIN_C1 -to flash_d[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to flash_d[0] + +set_location_assignment PIN_D2 -to flash_seln +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to flash_seln + +set_location_assignment PIN_G1 -to rstn +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to rstn + +set_location_assignment PIN_H1 -to flash_clk +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to flash_clk + +set_location_assignment PIN_H2 -to flash_d[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to flash_d[1] + +# JTAG is defined in bank 1. Can this be supported in user mode? + + +# Bank 2 RGMII 0, Sheet 3 +set_location_assignment PIN_M1 -to phy0_rx_clk +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy0_rx_clk + +set_location_assignment PIN_J2 -to phy0_tx_ctl +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy0_tx_ctl + +set_location_assignment PIN_J1 -to phy0_rx_ctl +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy0_rx_ctl + +set_location_assignment PIN_K2 -to phy0_rx_d[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy0_rx_d[2] + +set_location_assignment PIN_K1 -to phy0_rx_d[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy0_rx_d[3] + +set_location_assignment PIN_L2 -to phy0_rx_d[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy0_rx_d[0] + +set_location_assignment PIN_L1 -to phy0_rx_d[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy0_rx_d[1] + +# L3 + +set_location_assignment PIN_N2 -to phy0_intn +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy0_intn + +set_location_assignment PIN_N1 -to phy0_rstn +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy0_rstn + +# K5 +# L4 + +set_location_assignment PIN_R1 -to phy0_gpio[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy0_gpio[0] + +# P2 + +set_location_assignment PIN_P1 -to phy0_gpio[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy0_gpio[1] + + +# Bank 3 RGMII 0, Sheet 3 +set_location_assignment PIN_T8 -to phy0_clk +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy0_clk + +# N3 +# P3 + +set_location_assignment PIN_R3 -to phy0_tx_d[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy0_tx_d[1] + +set_location_assignment PIN_T3 -to phy0_tx_d[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy0_tx_d[0] + +set_location_assignment PIN_T2 -to phy0_tx_clk +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy0_tx_clk + +set_location_assignment PIN_R4 -to phy0_tx_d[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy0_tx_d[3] + +set_location_assignment PIN_T4 -to phy0_tx_d[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy0_tx_d[2] + +# N5 +# N6 +# M6 +# P6 +# M7 +# R5 +# T5 +# R6 + +set_location_assignment PIN_T6 -to phy0_mdio +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy0_mdio + +# L7 +# R7 + +set_location_assignment PIN_T7 -to phy0_mdc +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy0_mdc + +# L8 +# M8 +# N8 +# P8 + +# Bank 4, RGMII 1, Sheet 4 +set_location_assignment PIN_T9 -to phy1_rx_clk +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy1_rx_clk + +set_location_assignment PIN_T10 -to phy1_rx_d[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy1_rx_d[3] + +set_location_assignment PIN_T11 -to phy1_rx_d[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy1_rx_d[2] + +set_location_assignment PIN_T12 -to phy1_rx_d[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy1_rx_d[1] + +set_location_assignment PIN_P9 -to phy1_gpio[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy1_gpio[0] + +set_location_assignment PIN_R13 -to phy1_rx_ctl +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy1_rx_ctl + +set_location_assignment PIN_T13 -to phy1_rx_d[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy1_rx_d[0] + +set_location_assignment PIN_T14 -to phy1_tx_ctl +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy1_tx_ctl + +set_location_assignment PIN_T15 -to phy1_tx_clk +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy1_tx_clk + +set_location_assignment PIN_P14 -to phy1_rstn +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy1_rstn + + +# Bank 5, RGMII 1, Sheet 4 +set_location_assignment PIN_P15 -to phy1_clk +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy1_clk + +set_location_assignment PIN_P16 -to phy1_tx_d[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy1_tx_d[1] + +set_location_assignment PIN_R16 -to phy1_tx_d[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy1_tx_d[0] + +set_location_assignment PIN_N16 -to phy1_tx_d[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy1_tx_d[3] + +set_location_assignment PIN_N15 -to phy1_tx_d[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy1_tx_d[2] + +set_location_assignment PIN_L16 -to phy1_mdio +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy1_mdio + +set_location_assignment PIN_L15 -to phy1_intn +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy1_intn + +set_location_assignment PIN_K16 -to phy1_mdc +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy1_mdc + +set_location_assignment PIN_K15 -to phy1_gpio[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to phy1_gpio[1] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio[15] + +set_location_assignment PIN_J15 -to gpio[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio[14] + + +# Bank 6, RGMII 2, Sheet 5 +#set_location_assignment PIN_E16 -to gpio[8] +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio[8] + +set_location_assignment PIN_G16 -to gpio[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio[12] + +set_location_assignment PIN_G15 -to gpio[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio[13] + +set_location_assignment PIN_F16 -to gpio[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio[10] + +set_location_assignment PIN_F15 -to gpio[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio[11] + +set_location_assignment PIN_B16 -to gpio[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio[6] + +set_location_assignment PIN_D16 -to gpio[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio[9] + +set_location_assignment PIN_D15 -to gpio[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio[16] + +set_location_assignment PIN_C16 -to gpio[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio[7] + +# Bank 7, RGMII 2, Sheet 5 +set_location_assignment PIN_A13 -to gpio[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio[3] + +set_location_assignment PIN_A14 -to gpio[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio[4] + +set_location_assignment PIN_B14 -to gpio[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio[17] + +set_location_assignment PIN_A12 -to gpio[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio[2] + +set_location_assignment PIN_A11 -to gpio[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio[0] + +set_location_assignment PIN_A15 -to gpio[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio[5] + +set_location_assignment PIN_A10 -to gpio[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio[1] + +# Bank 8 + +set_location_assignment PIN_A7 -to fpga_led[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to fpga_led[2] + +set_location_assignment PIN_A6 -to fpga_led[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to fpga_led[1] + +set_location_assignment PIN_A5 -to fpga_led[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to fpga_led[0] + +set_location_assignment PIN_A4 -to flash_d[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to flash_d[7] + +set_location_assignment PIN_B4 -to flash_d[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to flash_d[5] + +set_location_assignment PIN_A2 -to flash_d[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to flash_d[2] + +set_location_assignment PIN_A3 -to flash_d[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to flash_d[6] + +set_location_assignment PIN_B3 -to flash_d[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to flash_d[3] + + + + + + +set_location_assignment PIN_A8 -to clk_i +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to clk_i +set_global_assignment -name SDC_FILE betsy.sdc +set_global_assignment -name SIGNALTAP_FILE brds/betsy/betsy.stp +set_global_assignment -name VERILOG_FILE src/betsy.v +set_global_assignment -name VERILOG_FILE ../../../src/cam.v +set_global_assignment -name VERILOG_FILE ../../../src/controller.v +set_global_assignment -name VERILOG_FILE ../../../src/cont_params.v +set_global_assignment -name VERILOG_FILE ../../../src/dpram_inf.v +set_global_assignment -name VERILOG_FILE ../../../src/drop_fifo.v +set_global_assignment -name VERILOG_FILE ../../../src/ethernet_params.v +set_global_assignment -name VERILOG_FILE ../../../src/fcs.v +set_global_assignment -name VERILOG_FILE ../../../src/half_fifo.v +set_global_assignment -name VERILOG_FILE ../../../src/ipv4_rx.v +set_global_assignment -name VERILOG_FILE ../../../src/ipv4_rx_c.v +set_global_assignment -name VERILOG_FILE ../../../src/ipv4_tx_c.v +set_global_assignment -name VERILOG_FILE ../../../src/ipv4_tx_mle.v +set_global_assignment -name VERILOG_FILE ../../../src/mac_rgmii.v +set_global_assignment -name VERILOG_FILE ../../../src/ml_engine.v +set_global_assignment -name VERILOG_FILE ../../../src/mdio.v +set_global_assignment -name VERILOG_FILE ../../../src/mdio_cont.v +set_global_assignment -name VERILOG_FILE ../../../src/mdio_data_ti.v +set_global_assignment -name VERILOG_FILE ../../../src/pkt_filter.v +set_global_assignment -name VERILOG_FILE ../../../src/rgmii_params.v +set_global_assignment -name VERILOG_FILE ../../../src/switch.v +set_global_assignment -name VERILOG_FILE ../../../src/sync_fifo.v +set_global_assignment -name VERILOG_FILE ../../../src/udp_rx.v +set_global_assignment -name VERILOG_FILE ../../../src/udp_rx_c.v +set_global_assignment -name QIP_FILE ip/ddrio/ddrio.qip +set_global_assignment -name QIP_FILE ip/rgmii_rxd/ddri.qip +set_global_assignment -name QIP_FILE ip/pll/pll.qip +set_global_assignment -name QIP_FILE ip/rgmii_txd/ddro.qip +set_global_assignment -name VERILOG_TEST_BENCH_FILE sim/src/tb.sv + +set_global_assignment -name SLD_NODE_CREATOR_ID 110 -section_id tst_controller +set_global_assignment -name SLD_NODE_ENTITY_NAME sld_signaltap -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_clk -to "pll:pll_0|c0" -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_RAM_BLOCK_TYPE=AUTO" -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_INFO=805334538" -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_POWER_UP_TRIGGER=0" -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH=0" -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ATTRIBUTE_MEM_MODE=OFF" -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_FLOW_USE_GENERATED=0" -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_BITS=11" -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_BUFFER_FULL_STOP=1" -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_CURRENT_RESOURCE_WIDTH=1" -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INCREMENTAL_ROUTING=1" -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[4] -to tst_controller|gnd -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[6] -to tst_controller|gnd -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[10] -to tst_controller|gnd -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[15] -to tst_controller|gnd -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[16] -to tst_controller|gnd -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[17] -to tst_controller|gnd -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[25] -to tst_controller|vcc -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL=1" -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_IN_ENABLED=0" -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_PIPELINE=0" -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_RAM_PIPELINE=0" -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_COUNTER_PIPELINE=0" -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=basic,1," -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=0" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[0] -to "controller:controller_0|gpio_direction[0]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[0] -to "controller:controller_0|gpio_direction[0]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[1] -to "controller:controller_0|gpio_direction[10]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[1] -to "controller:controller_0|gpio_direction[10]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[2] -to "controller:controller_0|gpio_direction[11]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[2] -to "controller:controller_0|gpio_direction[11]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[3] -to "controller:controller_0|gpio_direction[12]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[3] -to "controller:controller_0|gpio_direction[12]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[4] -to "controller:controller_0|gpio_direction[13]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[4] -to "controller:controller_0|gpio_direction[13]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[5] -to "controller:controller_0|gpio_direction[14]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[5] -to "controller:controller_0|gpio_direction[14]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[6] -to "controller:controller_0|gpio_direction[15]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[6] -to "controller:controller_0|gpio_direction[15]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[7] -to "controller:controller_0|gpio_direction[16]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[7] -to "controller:controller_0|gpio_direction[16]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[8] -to "controller:controller_0|gpio_direction[17]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[8] -to "controller:controller_0|gpio_direction[17]" -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[11] -to tst_controller|gnd -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[21] -to tst_controller|gnd -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[30] -to tst_controller|gnd -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[1] -to tst_controller|vcc -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SEGMENT_SIZE=256" -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SAMPLE_DEPTH=256" -section_id tst_controller +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[5] -to tst_controller|gnd -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[19] -to tst_controller|gnd -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[7] -to tst_controller|vcc -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[9] -to "controller:controller_0|gpio_direction[1]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[10] -to "controller:controller_0|gpio_direction[2]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[11] -to "controller:controller_0|gpio_direction[3]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[12] -to "controller:controller_0|gpio_direction[4]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[13] -to "controller:controller_0|gpio_direction[5]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[14] -to "controller:controller_0|gpio_direction[6]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[15] -to "controller:controller_0|gpio_direction[7]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[16] -to "controller:controller_0|gpio_direction[8]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[17] -to "controller:controller_0|gpio_direction[9]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[18] -to "controller:controller_0|gpio_out[0]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[19] -to "controller:controller_0|gpio_out[10]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[20] -to "controller:controller_0|gpio_out[11]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[21] -to "controller:controller_0|gpio_out[12]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[22] -to "controller:controller_0|gpio_out[13]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[23] -to "controller:controller_0|gpio_out[14]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[24] -to "controller:controller_0|gpio_out[15]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[25] -to "controller:controller_0|gpio_out[16]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[26] -to "controller:controller_0|gpio_out[17]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[27] -to "controller:controller_0|gpio_out[1]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[28] -to "controller:controller_0|gpio_out[2]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[29] -to "controller:controller_0|gpio_out[3]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[30] -to "controller:controller_0|gpio_out[4]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[31] -to "controller:controller_0|gpio_out[5]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[32] -to "controller:controller_0|gpio_out[6]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[33] -to "controller:controller_0|gpio_out[7]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[34] -to "controller:controller_0|gpio_out[8]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[35] -to "controller:controller_0|gpio_out[9]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[36] -to "controller:controller_0|gpio_out_en[0]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[37] -to "controller:controller_0|gpio_out_en[10]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[38] -to "controller:controller_0|gpio_out_en[11]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[39] -to "controller:controller_0|gpio_out_en[12]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[40] -to "controller:controller_0|gpio_out_en[13]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[41] -to "controller:controller_0|gpio_out_en[14]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[42] -to "controller:controller_0|gpio_out_en[15]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[43] -to "controller:controller_0|gpio_out_en[16]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[44] -to "controller:controller_0|gpio_out_en[17]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[45] -to "controller:controller_0|gpio_out_en[1]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[46] -to "controller:controller_0|gpio_out_en[2]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[47] -to "controller:controller_0|gpio_out_en[3]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[48] -to "controller:controller_0|gpio_out_en[4]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[49] -to "controller:controller_0|gpio_out_en[5]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[50] -to "controller:controller_0|gpio_out_en[6]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[51] -to "controller:controller_0|gpio_out_en[7]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[52] -to "controller:controller_0|gpio_out_en[8]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[53] -to "controller:controller_0|gpio_out_en[9]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[54] -to "controller:controller_0|gpio_value[0]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[55] -to "controller:controller_0|gpio_value[10]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[56] -to "controller:controller_0|gpio_value[11]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[57] -to "controller:controller_0|gpio_value[12]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[58] -to "controller:controller_0|gpio_value[13]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[59] -to "controller:controller_0|gpio_value[14]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[60] -to "controller:controller_0|gpio_value[15]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[61] -to "controller:controller_0|gpio_value[16]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[62] -to "controller:controller_0|gpio_value[17]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[63] -to "controller:controller_0|gpio_value[1]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[64] -to "controller:controller_0|gpio_value[2]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[65] -to "controller:controller_0|gpio_value[3]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[66] -to "controller:controller_0|gpio_value[4]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[67] -to "controller:controller_0|gpio_value[5]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[68] -to "controller:controller_0|gpio_value[6]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[69] -to "controller:controller_0|gpio_value[7]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[70] -to "controller:controller_0|gpio_value[8]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[71] -to "controller:controller_0|gpio_value[9]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[72] -to "controller:controller_0|msg_addr_ro" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[73] -to "controller:controller_0|msg_addr_valid" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[74] -to "controller:controller_0|msg_error" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[75] -to "controller:controller_0|rx_cnt[0]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[76] -to "controller:controller_0|rx_cnt[1]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[77] -to "controller:controller_0|rx_cnt[2]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[78] -to "controller:controller_0|rx_cnt[3]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[79] -to "controller:controller_0|rx_cnt[4]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[80] -to "controller:controller_0|rx_fifo_int" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[81] -to "controller:controller_0|rx_fifo_int_acked" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[82] -to "controller:controller_0|rx_fifo_int_m1" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[83] -to "controller:controller_0|rx_fifo_int_m2" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[84] -to "controller:controller_0|rx_msg_captured" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[85] -to "controller:controller_0|rx_msg_cnt[0]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[86] -to "controller:controller_0|rx_msg_cnt[10]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[87] -to "controller:controller_0|rx_msg_cnt[11]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[88] -to "controller:controller_0|rx_msg_cnt[12]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[89] -to "controller:controller_0|rx_msg_cnt[13]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[90] -to "controller:controller_0|rx_msg_cnt[14]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[91] -to "controller:controller_0|rx_msg_cnt[15]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[92] -to "controller:controller_0|rx_msg_cnt[1]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[93] -to "controller:controller_0|rx_msg_cnt[2]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[94] -to "controller:controller_0|rx_msg_cnt[3]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[95] -to "controller:controller_0|rx_msg_cnt[4]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[96] -to "controller:controller_0|rx_msg_cnt[5]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[97] -to "controller:controller_0|rx_msg_cnt[6]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[98] -to "controller:controller_0|rx_msg_cnt[7]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[99] -to "controller:controller_0|rx_msg_cnt[8]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[100] -to "controller:controller_0|rx_msg_cnt[9]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[101] -to "controller:controller_0|rx_rd_active" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[102] -to "controller:controller_0|rx_rd_ptr[0]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[103] -to "controller:controller_0|rx_rd_ptr[10]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[104] -to "controller:controller_0|rx_rd_ptr[1]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[105] -to "controller:controller_0|rx_rd_ptr[2]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[106] -to "controller:controller_0|rx_rd_ptr[3]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[107] -to "controller:controller_0|rx_rd_ptr[4]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[108] -to "controller:controller_0|rx_rd_ptr[5]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[109] -to "controller:controller_0|rx_rd_ptr[6]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[110] -to "controller:controller_0|rx_rd_ptr[7]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[111] -to "controller:controller_0|rx_rd_ptr[8]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[112] -to "controller:controller_0|rx_rd_ptr[9]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[113] -to "controller:controller_0|rx_wr_ptr[0]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[114] -to "controller:controller_0|rx_wr_ptr[10]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[115] -to "controller:controller_0|rx_wr_ptr[1]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[116] -to "controller:controller_0|rx_wr_ptr[2]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[117] -to "controller:controller_0|rx_wr_ptr[3]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[118] -to "controller:controller_0|rx_wr_ptr[4]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[119] -to "controller:controller_0|rx_wr_ptr[5]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[120] -to "controller:controller_0|rx_wr_ptr[6]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[121] -to "controller:controller_0|rx_wr_ptr[7]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[122] -to "controller:controller_0|rx_wr_ptr[8]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[123] -to "controller:controller_0|rx_wr_ptr[9]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[9] -to "controller:controller_0|gpio_direction[1]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[10] -to "controller:controller_0|gpio_direction[2]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[11] -to "controller:controller_0|gpio_direction[3]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[12] -to "controller:controller_0|gpio_direction[4]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[13] -to "controller:controller_0|gpio_direction[5]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[14] -to "controller:controller_0|gpio_direction[6]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[15] -to "controller:controller_0|gpio_direction[7]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[16] -to "controller:controller_0|gpio_direction[8]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[17] -to "controller:controller_0|gpio_direction[9]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[18] -to "controller:controller_0|gpio_out[0]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[19] -to "controller:controller_0|gpio_out[10]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[20] -to "controller:controller_0|gpio_out[11]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[21] -to "controller:controller_0|gpio_out[12]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[22] -to "controller:controller_0|gpio_out[13]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[23] -to "controller:controller_0|gpio_out[14]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[24] -to "controller:controller_0|gpio_out[15]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[25] -to "controller:controller_0|gpio_out[16]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[26] -to "controller:controller_0|gpio_out[17]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[27] -to "controller:controller_0|gpio_out[1]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[28] -to "controller:controller_0|gpio_out[2]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[29] -to "controller:controller_0|gpio_out[3]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[30] -to "controller:controller_0|gpio_out[4]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[31] -to "controller:controller_0|gpio_out[5]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[32] -to "controller:controller_0|gpio_out[6]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[33] -to "controller:controller_0|gpio_out[7]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[34] -to "controller:controller_0|gpio_out[8]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[35] -to "controller:controller_0|gpio_out[9]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[36] -to "controller:controller_0|gpio_out_en[0]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[37] -to "controller:controller_0|gpio_out_en[10]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[38] -to "controller:controller_0|gpio_out_en[11]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[39] -to "controller:controller_0|gpio_out_en[12]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[40] -to "controller:controller_0|gpio_out_en[13]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[41] -to "controller:controller_0|gpio_out_en[14]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[42] -to "controller:controller_0|gpio_out_en[15]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[43] -to "controller:controller_0|gpio_out_en[16]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[44] -to "controller:controller_0|gpio_out_en[17]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[45] -to "controller:controller_0|gpio_out_en[1]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[46] -to "controller:controller_0|gpio_out_en[2]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[47] -to "controller:controller_0|gpio_out_en[3]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[48] -to "controller:controller_0|gpio_out_en[4]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[49] -to "controller:controller_0|gpio_out_en[5]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[50] -to "controller:controller_0|gpio_out_en[6]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[51] -to "controller:controller_0|gpio_out_en[7]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[52] -to "controller:controller_0|gpio_out_en[8]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[53] -to "controller:controller_0|gpio_out_en[9]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[54] -to "controller:controller_0|gpio_value[0]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[55] -to "controller:controller_0|gpio_value[10]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[56] -to "controller:controller_0|gpio_value[11]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[57] -to "controller:controller_0|gpio_value[12]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[58] -to "controller:controller_0|gpio_value[13]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[59] -to "controller:controller_0|gpio_value[14]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[60] -to "controller:controller_0|gpio_value[15]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[61] -to "controller:controller_0|gpio_value[16]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[62] -to "controller:controller_0|gpio_value[17]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[63] -to "controller:controller_0|gpio_value[1]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[64] -to "controller:controller_0|gpio_value[2]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[65] -to "controller:controller_0|gpio_value[3]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[66] -to "controller:controller_0|gpio_value[4]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[67] -to "controller:controller_0|gpio_value[5]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[68] -to "controller:controller_0|gpio_value[6]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[69] -to "controller:controller_0|gpio_value[7]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[70] -to "controller:controller_0|gpio_value[8]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[71] -to "controller:controller_0|gpio_value[9]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[72] -to "controller:controller_0|msg_addr[0]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[73] -to "controller:controller_0|msg_addr[10]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[74] -to "controller:controller_0|msg_addr[11]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[75] -to "controller:controller_0|msg_addr[12]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[76] -to "controller:controller_0|msg_addr[13]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[77] -to "controller:controller_0|msg_addr[14]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[78] -to "controller:controller_0|msg_addr[15]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[79] -to "controller:controller_0|msg_addr[1]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[80] -to "controller:controller_0|msg_addr[2]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[81] -to "controller:controller_0|msg_addr[3]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[82] -to "controller:controller_0|msg_addr[4]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[83] -to "controller:controller_0|msg_addr[5]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[84] -to "controller:controller_0|msg_addr[6]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[85] -to "controller:controller_0|msg_addr[7]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[86] -to "controller:controller_0|msg_addr[8]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[87] -to "controller:controller_0|msg_addr[9]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[88] -to "controller:controller_0|msg_addr_ro" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[89] -to "controller:controller_0|msg_addr_valid" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[90] -to "controller:controller_0|msg_data[0]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[91] -to "controller:controller_0|msg_data[10]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[92] -to "controller:controller_0|msg_data[11]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[93] -to "controller:controller_0|msg_data[12]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[94] -to "controller:controller_0|msg_data[13]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[95] -to "controller:controller_0|msg_data[14]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[96] -to "controller:controller_0|msg_data[15]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[97] -to "controller:controller_0|msg_data[16]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[98] -to "controller:controller_0|msg_data[17]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[99] -to "controller:controller_0|msg_data[18]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[100] -to "controller:controller_0|msg_data[19]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[101] -to "controller:controller_0|msg_data[1]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[102] -to "controller:controller_0|msg_data[20]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[103] -to "controller:controller_0|msg_data[21]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[104] -to "controller:controller_0|msg_data[22]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[105] -to "controller:controller_0|msg_data[23]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[106] -to "controller:controller_0|msg_data[24]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[107] -to "controller:controller_0|msg_data[25]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[108] -to "controller:controller_0|msg_data[26]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[109] -to "controller:controller_0|msg_data[27]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[110] -to "controller:controller_0|msg_data[28]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[111] -to "controller:controller_0|msg_data[29]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[112] -to "controller:controller_0|msg_data[2]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[113] -to "controller:controller_0|msg_data[30]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[114] -to "controller:controller_0|msg_data[31]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[115] -to "controller:controller_0|msg_data[3]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[116] -to "controller:controller_0|msg_data[4]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[117] -to "controller:controller_0|msg_data[5]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[118] -to "controller:controller_0|msg_data[6]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[119] -to "controller:controller_0|msg_data[7]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[120] -to "controller:controller_0|msg_data[8]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[121] -to "controller:controller_0|msg_data[9]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[122] -to "controller:controller_0|msg_error" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[123] -to "controller:controller_0|msg_response[0]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[124] -to "controller:controller_0|msg_response[10]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[125] -to "controller:controller_0|msg_response[11]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[126] -to "controller:controller_0|msg_response[12]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[127] -to "controller:controller_0|msg_response[13]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[128] -to "controller:controller_0|msg_response[14]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[129] -to "controller:controller_0|msg_response[15]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[130] -to "controller:controller_0|msg_response[16]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[131] -to "controller:controller_0|msg_response[17]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[132] -to "controller:controller_0|msg_response[18]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[133] -to "controller:controller_0|msg_response[19]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[134] -to "controller:controller_0|msg_response[1]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[135] -to "controller:controller_0|msg_response[20]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[136] -to "controller:controller_0|msg_response[21]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[137] -to "controller:controller_0|msg_response[22]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[138] -to "controller:controller_0|msg_response[23]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[139] -to "controller:controller_0|msg_response[24]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[140] -to "controller:controller_0|msg_response[25]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[141] -to "controller:controller_0|msg_response[26]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[142] -to "controller:controller_0|msg_response[27]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[143] -to "controller:controller_0|msg_response[28]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[144] -to "controller:controller_0|msg_response[29]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[145] -to "controller:controller_0|msg_response[2]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[146] -to "controller:controller_0|msg_response[30]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[147] -to "controller:controller_0|msg_response[31]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[148] -to "controller:controller_0|msg_response[3]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[149] -to "controller:controller_0|msg_response[4]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[150] -to "controller:controller_0|msg_response[5]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[151] -to "controller:controller_0|msg_response[6]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[152] -to "controller:controller_0|msg_response[7]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[153] -to "controller:controller_0|msg_response[8]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[154] -to "controller:controller_0|msg_response[9]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[155] -to "controller:controller_0|msg_token[0]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[156] -to "controller:controller_0|msg_token[1]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[157] -to "controller:controller_0|msg_token[2]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[158] -to "controller:controller_0|msg_token[3]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[159] -to "controller:controller_0|msg_token[4]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[160] -to "controller:controller_0|msg_token[5]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[161] -to "controller:controller_0|msg_token[6]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[162] -to "controller:controller_0|msg_token[7]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[163] -to "controller:controller_0|msg_type[0]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[164] -to "controller:controller_0|msg_type[1]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[165] -to "controller:controller_0|msg_type[2]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[166] -to "controller:controller_0|msg_type[3]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[167] -to "controller:controller_0|msg_type[4]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[168] -to "controller:controller_0|msg_type[5]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[169] -to "controller:controller_0|msg_type[6]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[170] -to "controller:controller_0|msg_type[7]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[171] -to "controller:controller_0|rx_cnt[0]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[172] -to "controller:controller_0|rx_cnt[1]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[173] -to "controller:controller_0|rx_cnt[2]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[174] -to "controller:controller_0|rx_cnt[3]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[175] -to "controller:controller_0|rx_cnt[4]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[176] -to "controller:controller_0|rx_fifo_int" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[177] -to "controller:controller_0|rx_fifo_int_acked" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[178] -to "controller:controller_0|rx_fifo_int_m1" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[179] -to "controller:controller_0|rx_fifo_int_m2" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[180] -to "controller:controller_0|rx_msg_captured" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[181] -to "controller:controller_0|rx_msg_cnt[0]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[182] -to "controller:controller_0|rx_msg_cnt[10]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[183] -to "controller:controller_0|rx_msg_cnt[11]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[184] -to "controller:controller_0|rx_msg_cnt[12]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[185] -to "controller:controller_0|rx_msg_cnt[13]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[186] -to "controller:controller_0|rx_msg_cnt[14]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[187] -to "controller:controller_0|rx_msg_cnt[15]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[188] -to "controller:controller_0|rx_msg_cnt[1]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[189] -to "controller:controller_0|rx_msg_cnt[2]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[190] -to "controller:controller_0|rx_msg_cnt[3]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[191] -to "controller:controller_0|rx_msg_cnt[4]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[192] -to "controller:controller_0|rx_msg_cnt[5]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[193] -to "controller:controller_0|rx_msg_cnt[6]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[194] -to "controller:controller_0|rx_msg_cnt[7]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[195] -to "controller:controller_0|rx_msg_cnt[8]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[196] -to "controller:controller_0|rx_msg_cnt[9]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[197] -to "controller:controller_0|rx_rd_active" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[198] -to "controller:controller_0|rx_rd_ptr[0]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[199] -to "controller:controller_0|rx_rd_ptr[10]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[200] -to "controller:controller_0|rx_rd_ptr[1]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[201] -to "controller:controller_0|rx_rd_ptr[2]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[202] -to "controller:controller_0|rx_rd_ptr[3]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[203] -to "controller:controller_0|rx_rd_ptr[4]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[204] -to "controller:controller_0|rx_rd_ptr[5]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[205] -to "controller:controller_0|rx_rd_ptr[6]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[206] -to "controller:controller_0|rx_rd_ptr[7]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[207] -to "controller:controller_0|rx_rd_ptr[8]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[208] -to "controller:controller_0|rx_rd_ptr[9]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[209] -to "controller:controller_0|rx_wr_ptr[0]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[210] -to "controller:controller_0|rx_wr_ptr[10]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[211] -to "controller:controller_0|rx_wr_ptr[1]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[212] -to "controller:controller_0|rx_wr_ptr[2]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[213] -to "controller:controller_0|rx_wr_ptr[3]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[214] -to "controller:controller_0|rx_wr_ptr[4]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[215] -to "controller:controller_0|rx_wr_ptr[5]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[216] -to "controller:controller_0|rx_wr_ptr[6]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[217] -to "controller:controller_0|rx_wr_ptr[7]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[218] -to "controller:controller_0|rx_wr_ptr[8]" -section_id tst_controller +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[219] -to "controller:controller_0|rx_wr_ptr[9]" -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_DATA_BITS=220" -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_BITS=124" -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_BITS=220" -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK=0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" -section_id tst_controller +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK_LENGTH=394" -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[0] -to tst_controller|gnd -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[2] -to tst_controller|gnd -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[3] -to tst_controller|gnd -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[8] -to tst_controller|gnd -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[9] -to tst_controller|vcc -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[12] -to tst_controller|gnd -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[13] -to tst_controller|vcc -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[14] -to tst_controller|gnd -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[18] -to tst_controller|vcc -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[20] -to tst_controller|gnd -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[22] -to tst_controller|vcc -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[23] -to tst_controller|gnd -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[24] -to tst_controller|vcc -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[26] -to tst_controller|gnd -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[27] -to tst_controller|gnd -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[28] -to tst_controller|vcc -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[29] -to tst_controller|vcc -section_id tst_controller +set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[31] -to tst_controller|gnd -section_id tst_controller +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio +set_global_assignment -name SLD_FILE db/betsy_auto_stripped.stp +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file diff --git a/manufacturer/altera/cyclone10_lp/betsy_gpio_assignment_defaults.qdf b/manufacturer/altera/cyclone10_lp/betsy_gpio_assignment_defaults.qdf new file mode 100644 index 0000000..b0bacd2 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/betsy_gpio_assignment_defaults.qdf @@ -0,0 +1,806 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2022 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details, at +# https://fpgasoftware.intel.com/eula. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition +# Date created = 12:01:56 May 07, 2023 +# +# -------------------------------------------------------------------------- # +# +# Note: +# +# 1) Do not modify this file. This file was generated +# automatically by the Quartus Prime software and is used +# to preserve global assignments across Quartus Prime versions. +# +# -------------------------------------------------------------------------- # + +set_global_assignment -name IP_COMPONENT_REPORT_HIERARCHY Off +set_global_assignment -name IP_COMPONENT_INTERNAL Off +set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On +set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off +set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off +set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db +set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off +set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off +set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off +set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off +set_global_assignment -name HC_OUTPUT_DIR hc_output +set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off +set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off +set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On +set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off +set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings" +set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On +set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On +set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off +set_global_assignment -name REVISION_TYPE Base -family "Arria V" +set_global_assignment -name REVISION_TYPE Base -family "Stratix V" +set_global_assignment -name REVISION_TYPE Base -family "Arria V GZ" +set_global_assignment -name REVISION_TYPE Base -family "Cyclone V" +set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle" +set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On +set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On +set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On +set_global_assignment -name DO_COMBINED_ANALYSIS Off +set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT Off +set_global_assignment -name ENABLE_HPS_INTERNAL_TIMING Off +set_global_assignment -name EMIF_SOC_PHYCLK_ADVANCE_MODELING Off +set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN Off +set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On +set_global_assignment -name TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria V" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone 10 LP" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "MAX 10" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix IV" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone IV E" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria 10" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS Off -family "MAX V" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix V" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria V GZ" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS Off -family "MAX II" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria II GX" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria II GZ" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone IV GX" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone V" +set_global_assignment -name TIMING_ANALYZER_DO_REPORT_TIMING Off +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone 10 LP" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "MAX 10" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria 10" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V" +set_global_assignment -name TIMING_ANALYZER_REPORT_NUM_WORST_CASE_TIMING_PATHS 100 +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria V" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone 10 LP" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "MAX 10" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone IV E" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix IV" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria 10" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL Off -family "MAX V" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix V" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria V GZ" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL Off -family "MAX II" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GX" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GZ" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone IV GX" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone V" +set_global_assignment -name OPTIMIZATION_MODE Balanced +set_global_assignment -name ALLOW_REGISTER_MERGING On +set_global_assignment -name ALLOW_REGISTER_DUPLICATION On +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria V" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON -family "Cyclone 10 LP" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX 10" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Stratix IV" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone IV E" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON -family "Arria 10" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX V" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Stratix V" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria V GZ" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX II" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria II GX" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria II GZ" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone IV GX" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone V" +set_global_assignment -name MUX_RESTRUCTURE Auto +set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off +set_global_assignment -name ENABLE_IP_DEBUG Off +set_global_assignment -name SAVE_DISK_SPACE On +set_global_assignment -name OCP_HW_EVAL Enable +set_global_assignment -name DEVICE_FILTER_PACKAGE Any +set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any +set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>" +set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001 +set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993 +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name TRUE_WYSIWYG_FLOW Off +set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off +set_global_assignment -name STATE_MACHINE_PROCESSING Auto +set_global_assignment -name SAFE_STATE_MACHINE Off +set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On +set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On +set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off +set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000 +set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250 +set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On +set_global_assignment -name PARALLEL_SYNTHESIS On +set_global_assignment -name DSP_BLOCK_BALANCING Auto +set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)" +set_global_assignment -name NOT_GATE_PUSH_BACK On +set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On +set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off +set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On +set_global_assignment -name IGNORE_CARRY_BUFFERS Off +set_global_assignment -name IGNORE_CASCADE_BUFFERS Off +set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off +set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off +set_global_assignment -name IGNORE_LCELL_BUFFERS Off +set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO +set_global_assignment -name IGNORE_SOFT_BUFFERS On +set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off +set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off +set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On +set_global_assignment -name AUTO_GLOBAL_OE_MAX On +set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On +set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off +set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut +set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed +set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name ALLOW_XOR_GATE_USAGE On +set_global_assignment -name AUTO_LCELL_INSERTION On +set_global_assignment -name CARRY_CHAIN_LENGTH 48 +set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32 +set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32 +set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48 +set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70 +set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70 +set_global_assignment -name CASCADE_CHAIN_LENGTH 2 +set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16 +set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4 +set_global_assignment -name AUTO_CARRY_CHAINS On +set_global_assignment -name AUTO_CASCADE_CHAINS On +set_global_assignment -name AUTO_PARALLEL_EXPANDERS On +set_global_assignment -name AUTO_OPEN_DRAIN_PINS On +set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off +set_global_assignment -name AUTO_ROM_RECOGNITION On +set_global_assignment -name AUTO_RAM_RECOGNITION On +set_global_assignment -name AUTO_DSP_RECOGNITION On +set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto +set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto +set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On +set_global_assignment -name STRICT_RAM_RECOGNITION Off +set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On +set_global_assignment -name FORCE_SYNCH_CLEAR Off +set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On +set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off +set_global_assignment -name AUTO_RESOURCE_SHARING Off +set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off +set_global_assignment -name MAX7000_FANIN_PER_CELL 100 +set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On +set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)" +set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)" +set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)" +set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off +set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone 10 LP" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "MAX 10" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria 10" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX" +set_global_assignment -name REPORT_PARAMETER_SETTINGS On +set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On +set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On +set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone 10 LP" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX 10" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria 10" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V" +set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation" +set_global_assignment -name HDL_MESSAGE_LEVEL Level2 +set_global_assignment -name USE_HIGH_SPEED_ADDER Auto +set_global_assignment -name NUMBER_OF_PROTECTED_REGISTERS_REPORTED 100 +set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000 +set_global_assignment -name NUMBER_OF_SYNTHESIS_MIGRATION_ROWS 5000 +set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS Off +set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000 +set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100 +set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On +set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off +set_global_assignment -name BLOCK_DESIGN_NAMING Auto +set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off +set_global_assignment -name SYNTHESIS_EFFORT Auto +set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On +set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off +set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium +set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone 10 LP" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "MAX 10" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria 10" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX" +set_global_assignment -name MAX_LABS "-1 (Unlimited)" +set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On +set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)" +set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On +set_global_assignment -name PRPOF_ID Off +set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING Off +set_global_assignment -name REPORT_PARAMETER_SETTINGS_PRO On +set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS_PRO On +set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE Off +set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off +set_global_assignment -name AUTO_MERGE_PLLS On +set_global_assignment -name IGNORE_MODE_FOR_MERGE Off +set_global_assignment -name TXPMA_SLEW_RATE Low +set_global_assignment -name ADCE_ENABLED Auto +set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal +set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off +set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0 +set_global_assignment -name PHYSICAL_SYNTHESIS Off +set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off +set_global_assignment -name DEVICE AUTO +set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off +set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off +set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On +set_global_assignment -name ENABLE_NCEO_OUTPUT Off +set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name STRATIXIII_UPDATE_MODE Standard +set_global_assignment -name STRATIX_UPDATE_MODE Standard +set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image" +set_global_assignment -name CVP_MODE Off +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria 10" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Stratix V" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V GZ" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Cyclone V" +set_global_assignment -name VID_OPERATION_MODE "PMBus Slave" +set_global_assignment -name USE_CONF_DONE AUTO +set_global_assignment -name USE_PWRMGT_SCL AUTO +set_global_assignment -name USE_PWRMGT_SDA AUTO +set_global_assignment -name USE_PWRMGT_ALERT AUTO +set_global_assignment -name USE_INIT_DONE AUTO +set_global_assignment -name USE_CVP_CONFDONE AUTO +set_global_assignment -name USE_SEU_ERROR AUTO +set_global_assignment -name RESERVE_AVST_CLK_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_VALID_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration" +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name USER_START_UP_CLOCK Off +set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND Off +set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off +set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS On +set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION On +set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC +set_global_assignment -name ENABLE_VREFA_PIN Off +set_global_assignment -name ENABLE_VREFB_PIN Off +set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off +set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off +set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off +set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground" +set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off +set_global_assignment -name INIT_DONE_OPEN_DRAIN On +set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name ENABLE_CONFIGURATION_PINS On +set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off +set_global_assignment -name ENABLE_NCE_PIN Off +set_global_assignment -name ENABLE_BOOT_SEL_PIN On +set_global_assignment -name CRC_ERROR_CHECKING Off +set_global_assignment -name INTERNAL_SCRUBBING Off +set_global_assignment -name PR_ERROR_OPEN_DRAIN On +set_global_assignment -name PR_READY_OPEN_DRAIN On +set_global_assignment -name ENABLE_CVP_CONFDONE Off +set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On +set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone 10 LP" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "MAX 10" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone 10 LP" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "MAX 10" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V" +set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix IV" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix V" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria V GZ" +set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0 +set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation" +set_global_assignment -name OPTIMIZE_SSN Off +set_global_assignment -name OPTIMIZE_TIMING "Normal compilation" +set_global_assignment -name ECO_OPTIMIZE_TIMING Off +set_global_assignment -name ECO_REGENERATE_REPORT Off +set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal +set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically +set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically +set_global_assignment -name SEED 1 +set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION OFF +set_global_assignment -name RESERVE_ROUTING_OUTPUT_FLEXIBILITY Off +set_global_assignment -name SLOW_SLEW_RATE Off +set_global_assignment -name PCI_IO Off +set_global_assignment -name TURBO_BIT On +set_global_assignment -name WEAK_PULL_UP_RESISTOR Off +set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off +set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off +set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On +set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto +set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto +set_global_assignment -name NORMAL_LCELL_INSERT On +set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone 10 LP" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX 10" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix IV" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV E" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria 10" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX II" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V GZ" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GX" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GZ" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV GX" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone V" +set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF +set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off +set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off +set_global_assignment -name AUTO_TURBO_BIT ON +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off +set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off +set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On +set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off +set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off +set_global_assignment -name FITTER_EFFORT "Auto Fit" +set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal +set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto +set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto +set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off +set_global_assignment -name AUTO_GLOBAL_CLOCK On +set_global_assignment -name AUTO_GLOBAL_OE On +set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On +set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic +set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off +set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up" +set_global_assignment -name ENABLE_HOLD_BACK_OFF On +set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto +set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off +set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Auto +set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On +set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone 10 LP" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "MAX 10" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V" +set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX" +set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off +set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On +set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off +set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off +set_global_assignment -name PR_DONE_OPEN_DRAIN On +set_global_assignment -name NCEO_OPEN_DRAIN On +set_global_assignment -name ENABLE_CRC_ERROR_PIN Off +set_global_assignment -name ENABLE_PR_PINS Off +set_global_assignment -name RESERVE_PR_PINS Off +set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS Off +set_global_assignment -name PR_PINS_OPEN_DRAIN Off +set_global_assignment -name CLAMPING_DIODE Off +set_global_assignment -name TRI_STATE_SPI_PINS Off +set_global_assignment -name UNUSED_TSD_PINS_GND Off +set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off +set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off +set_global_assignment -name ALM_REGISTER_PACKING_EFFORT Medium +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION Off -family "Stratix IV" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria 10" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix V" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V GZ" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Cyclone V" +set_global_assignment -name RELATIVE_NEUTRON_FLUX 1.0 +set_global_assignment -name SEU_FIT_REPORT Off +set_global_assignment -name HYPER_RETIMER Off -family "Arria 10" +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX "-1" +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR Auto +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION Auto +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS On +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS On +set_global_assignment -name EDA_SIMULATION_TOOL "<None>" +set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<None>" +set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "<None>" +set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "<None>" +set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "<None>" +set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "<None>" +set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<None>" +set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>" +set_global_assignment -name EDA_RESYNTHESIS_TOOL "<None>" +set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On +set_global_assignment -name COMPRESSION_MODE Off +set_global_assignment -name CLOCK_SOURCE Internal +set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz" +set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1 +set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off +set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF +set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F +set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name USE_CHECKSUM_AS_USERCODE On +set_global_assignment -name SECURITY_BIT Off +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone 10 LP" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX 10" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX" +set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto +set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE "PV3102 or EM1130" +set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 0000000 +set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "Auto discovery" +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 0 +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_B 0 +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 0 +set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto +set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto +set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto +set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On +set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off +set_global_assignment -name GENERATE_TTF_FILE Off +set_global_assignment -name GENERATE_RBF_FILE Off +set_global_assignment -name GENERATE_HEX_FILE Off +set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0 +set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal" +set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off +set_global_assignment -name AUTO_RESTART_CONFIGURATION On +set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off +set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off +set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone 10 LP" +set_global_assignment -name ENABLE_OCT_DONE On -family "MAX 10" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV E" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria 10" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Stratix V" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V GZ" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria II GX" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV GX" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone V" +set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF +set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off +set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off +set_global_assignment -name ENABLE_ADV_SEU_DETECTION Off +set_global_assignment -name POR_SCHEME "Instant ON" +set_global_assignment -name EN_USER_IO_WEAK_PULLUP On +set_global_assignment -name EN_SPI_IO_WEAK_PULLUP On +set_global_assignment -name POF_VERIFY_PROTECT Off +set_global_assignment -name ENABLE_SPI_MODE_CHECK Off +set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK On +set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off +set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0 +set_global_assignment -name GENERATE_PMSF_FILES On +set_global_assignment -name START_TIME 0ns +set_global_assignment -name SIMULATION_MODE TIMING +set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off +set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On +set_global_assignment -name SETUP_HOLD_DETECTION Off +set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off +set_global_assignment -name CHECK_OUTPUTS Off +set_global_assignment -name SIMULATION_COVERAGE On +set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name GLITCH_DETECTION Off +set_global_assignment -name GLITCH_INTERVAL 1ns +set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off +set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On +set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off +set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On +set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE +set_global_assignment -name SIMULATION_NETLIST_VIEWER Off +set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT +set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT +set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off +set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO +set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO +set_global_assignment -name DRC_TOP_FANOUT 50 +set_global_assignment -name DRC_FANOUT_EXCEEDING 30 +set_global_assignment -name DRC_GATED_CLOCK_FEED 30 +set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY +set_global_assignment -name ENABLE_DRC_SETTINGS Off +set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25 +set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10 +set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30 +set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2 +set_global_assignment -name MERGE_HEX_FILE Off +set_global_assignment -name GENERATE_SVF_FILE Off +set_global_assignment -name GENERATE_ISC_FILE Off +set_global_assignment -name GENERATE_JAM_FILE Off +set_global_assignment -name GENERATE_JBC_FILE Off +set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On +set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off +set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off +set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off +set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off +set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On +set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off +set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state" +set_global_assignment -name HPS_EARLY_IO_RELEASE Off +set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off +set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off +set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_USE_PVA On +set_global_assignment -name POWER_USE_INPUT_FILE "No File" +set_global_assignment -name POWER_USE_INPUT_FILES Off +set_global_assignment -name POWER_VCD_FILTER_GLITCHES On +set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off +set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off +set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL +set_global_assignment -name POWER_AUTO_COMPUTE_TJ On +set_global_assignment -name POWER_TJ_VALUE 25 +set_global_assignment -name POWER_USE_TA_VALUE 25 +set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off +set_global_assignment -name POWER_BOARD_TEMPERATURE 25 +set_global_assignment -name POWER_HPS_ENABLE Off +set_global_assignment -name POWER_HPS_PROC_FREQ 0.0 +set_global_assignment -name ENABLE_SMART_VOLTAGE_ID Off +set_global_assignment -name IGNORE_PARTITIONS Off +set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off +set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On +set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End" +set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On +set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On +set_global_assignment -name RTLV_GROUP_RELATED_NODES On +set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off +set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off +set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On +set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On +set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On +set_global_assignment -name EQC_BBOX_MERGE On +set_global_assignment -name EQC_LVDS_MERGE On +set_global_assignment -name EQC_RAM_UNMERGING On +set_global_assignment -name EQC_DFF_SS_EMULATION On +set_global_assignment -name EQC_RAM_REGISTER_UNPACK On +set_global_assignment -name EQC_MAC_REGISTER_UNPACK On +set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On +set_global_assignment -name EQC_STRUCTURE_MATCHING On +set_global_assignment -name EQC_AUTO_BREAK_CONE On +set_global_assignment -name EQC_POWER_UP_COMPARE Off +set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On +set_global_assignment -name EQC_AUTO_INVERSION On +set_global_assignment -name EQC_AUTO_TERMINATE On +set_global_assignment -name EQC_SUB_CONE_REPORT Off +set_global_assignment -name EQC_RENAMING_RULES On +set_global_assignment -name EQC_PARAMETER_CHECK On +set_global_assignment -name EQC_AUTO_PORTSWAP On +set_global_assignment -name EQC_DETECT_DONT_CARES On +set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off +set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ? +set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ? +set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ? +set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ? +set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ? +set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ? +set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ? +set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ? +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ? +set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ? +set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "<None>" -section_id ? +set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ? +set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ? +set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ? +set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ? +set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ? +set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ? +set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ? +set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ? +set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ? +set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ? +set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ? +set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ? +set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ? +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST On -section_id ? +set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ? +set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ? +set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ? +set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ? +set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ? +set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ? +set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ? +set_global_assignment -name EDA_IBIS_EXTENDED_MODEL_SELECTOR Off -section_id ? +set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ? +set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ? +set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ? +set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ? +set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ? +set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p2 -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ? +set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ? +set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ? +set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ? +set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ? +set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ? +set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ? +set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ? +set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ? +set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ? +set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ? +set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ? +set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ? +set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ? diff --git a/manufacturer/altera/cyclone10_lp/betsy_gpio_description.txt b/manufacturer/altera/cyclone10_lp/betsy_gpio_description.txt new file mode 100644 index 0000000..8a1c9e6 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/betsy_gpio_description.txt @@ -0,0 +1,2 @@ +Created on:Friday, July 03, 2026 +Based on:betsy |
