ml_module_agilex3 - ML Module using Agilex 3 for Betsy

summary refs log tree commit diff homepage

path: root/sym-lib-table

Age	Commit message (Expand)	Author
7 days	initial commit of design template + starting local libraries	Private Island Networks Inc.

Highly Recommended Verilog Books

Digital VLSI Design with Verilog: A Textbook from Silicon Valley Polytechnic Institute

The Verilog Hardware Description Language

Verilog HDL A Guide to Digital Design and Synthesis