Overview
Note that this is an under development, draft article.
This article summarizes the concept for an FPGA-based machine learning / inferencing module utilizing an Altera Agilex 3 device. The system would initially be realized as a daughter board for the Betsy™ maker board.
Figure 1 below depicts the machine learning architecture with Betsy, a GigE daughter board, and an external PC performing real-time inferencing for network and other applications. Although the Betsy Cyclone 10 LP is well suited for general network processing, data collection, and vector / tensor generation, it most likely lacks a suitable DSP architecture for real-time inferencing except for simple cases.
Note that the "Machine Learning Engine" block shown below is responsible for pre-processing of network data and generation of vectors / tensors to transfer to an inferencing engine.
Figure 2 depicts a self-contained machine learning architecture utilizing a real-time inferencing daughter board with Betsy. In this system scenario, the Cyclone 10 LP is directly transferring vectors / tensors to the Inferencing Daughter Board via its local high speed bus across the daughter board connectors.
Presentation Slides
The following slides were presented to the UNF IEEE group on 4/15/26.
The slide above mentions some of the design issues, such as required bandwidth and bus implementation. Other issues include:
- Which Agilex 3 devices can be procured during the summer of 2026?
- Power conversion requirements for the Agilex 3 device to meet all voltage rail and sequencing requirements
- LPDDR4 design (if required)
Regarding the ball locatons for the VPBGA, Altera provides a spreadsheet that defines the X,Y location of each package ball. The expectation is that the package does not require HDI PCB technology, such as VIP (VIA-in-PAD) and blind & buried VIAs. This requires validation.
The slide above, which provides the Altera AI Design Flow, conveys the following information:
- The design flow supports all major AI frameworks for model creation, such as PyTorch and Keras.
- The OpenVINO framework converts the AI model to an Intermediate Represenation (IR Data).
- Using the FPGA AI Suite, the OpenVINO model can be targeted at a particular Altera FPGA. The model is integrated and compiled with the rest of the design using Quartus Prime Pro and ultimately instantiated on the FPGA device.
