ml_module_agilex3 - ML Module using Agilex 3 for Betsy

summary refs log tree commit diff homepage

path: root/fpga_banks_6c_6d.kicad_sch

Age	Commit message (Expand)	Author
11 days	update Agliex footprint and symbol, all schematic pages, move bank 3A to lpdd...	Private Island Networks Inc.

Highly Recommended Verilog Books

Digital VLSI Design with Verilog: A Textbook from Silicon Valley Polytechnic Institute

The Verilog Hardware Description Language

Verilog HDL A Guide to Digital Design and Synthesis