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| -rw-r--r-- | .gitignore | 30 | ||||
| -rw-r--r-- | LICENSE | 201 | ||||
| -rw-r--r-- | README.txt | 45 | ||||
| -rw-r--r-- | ip/.gitignore | 3 | ||||
| -rw-r--r-- | ip/ddr_i.ip | 448 | ||||
| -rw-r--r-- | ip/ddr_o.ip | 446 | ||||
| -rw-r--r-- | ip/pll_io.ip | 1816 | ||||
| -rw-r--r-- | ml_module_agilex.qpf | 31 | ||||
| -rw-r--r-- | ml_module_agilex.qsf | 69 | ||||
| -rw-r--r-- | ml_module_agilex.sdc | 28 | ||||
| -rw-r--r-- | sim/.gitignore | 13 | ||||
| -rw-r--r-- | sim/data/ml.dat | 145 | ||||
| -rw-r--r-- | sim/lin/modelsim.ini | 2237 | ||||
| -rw-r--r-- | sim/lin/sim.do | 66 | ||||
| -rw-r--r-- | sim/src/tb.sv | 188 | ||||
| -rw-r--r-- | sim/wav/basic_wav.do | 53 | ||||
| -rw-r--r-- | sim/win/.gitignore | 1 | ||||
| -rw-r--r-- | sim/win/common/modelsim_files.tcl | 90 | ||||
| -rw-r--r-- | sim/win/elab.do | 66 | ||||
| -rw-r--r-- | sim/win/mentor/msim_setup.tcl | 441 | ||||
| -rw-r--r-- | sim/win/mentor/run_msim_setup.tcl | 36 | ||||
| -rw-r--r-- | sim/win/ml_module.mpf | 2300 | ||||
| -rw-r--r-- | sim/win/modelsim.ini | 2237 | ||||
| -rw-r--r-- | sim/win/sim.do | 2 | ||||
| -rw-r--r-- | src/ml_module_agilex.v | 96 |
25 files changed, 11088 insertions, 0 deletions
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We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + + Copyright [yyyy] [name of copyright owner] + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. diff --git a/README.txt b/README.txt new file mode 100644 index 0000000..8fca6a6 --- /dev/null +++ b/README.txt @@ -0,0 +1,45 @@ +ReadMe file for ML Module FW Project + +UNF Summer Project sponsored by Private Island Networks Inc. + +See open source license file in same top level folder + +Project utilizes Altera Quartus Prime Pro and targets an Agilex 3 FPGA. + +Refer to project landing page for more information: https://privateisland.tech/dev/ml-module-agilex + +Folders: + +src: Verilog source code +sim: Simulation (see more below) +ip: IP files and related folders for both synth and simulation + +Build Folders (do not archive): +dni +output_files: this will eventually have the bit file for programming +qdb + +Simulation Folders: +data: data files read by the test bench +lin: simulation project for Ubuntu Linux 24.04 (not currently supported in Questa) +src: System Verilog test bench source +wav: Simulation Wave files that can be invoked on sim command line using "do <file>" +win: simulation project for Windows + +Windows Simulation Folder: + +elab.do: run this the first time to compile Altera libraries (Fully compile in Quartus first) +sim.do: run this each time you wish to start simulation +ml_module.mpf: Questa project file. Use this folder pane inside Questa to re-compile source files (and add them). + +To Simulate: + +# cd to project folder: +> cd C:/Projects/fw_ml_module/sim/win +> do elab.do +> do ../wav/basic_wav.do +> run 50 us + + + + diff --git a/ip/.gitignore b/ip/.gitignore new file mode 100644 index 0000000..d8b56d2 --- /dev/null +++ b/ip/.gitignore @@ -0,0 +1,3 @@ +ddr_i +ddr_o +pll_io diff --git a/ip/ddr_i.ip b/ip/ddr_i.ip new file mode 100644 index 0000000..571350c --- /dev/null +++ b/ip/ddr_i.ip @@ -0,0 +1,448 @@ +<?xml version="1.0" ?> +<!--Your use of Altera Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, the Altera Quartus Prime License Agreement, +the Altera FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Altera and sold by Altera or its authorized distributors.--> +<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"> + <ipxact:vendor>Altera</ipxact:vendor> + <ipxact:library>ddr_i</ipxact:library> + <ipxact:name>gpio_0</ipxact:name> + <ipxact:version>23.0.0</ipxact:version> + <ipxact:busInterfaces> + <ipxact:busInterface> + <ipxact:name>ck</ipxact:name> + <ipxact:busType vendor="intel" library="intel" name="conduit" version="26.1"></ipxact:busType> + <ipxact:abstractionTypes> + <ipxact:abstractionType> + <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="26.1"></ipxact:abstractionRef> + <ipxact:portMaps> + <ipxact:portMap> + <ipxact:logicalPort> + <ipxact:name>export</ipxact:name> + </ipxact:logicalPort> + <ipxact:physicalPort> + <ipxact:name>ck</ipxact:name> + </ipxact:physicalPort> + </ipxact:portMap> + </ipxact:portMaps> + </ipxact:abstractionType> + </ipxact:abstractionTypes> + <ipxact:slave></ipxact:slave> + <ipxact:parameters> + <ipxact:parameter parameterId="associatedClock" type="string"> + <ipxact:name>associatedClock</ipxact:name> + <ipxact:displayName>associatedClock</ipxact:displayName> + <ipxact:value></ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="associatedReset" type="string"> + <ipxact:name>associatedReset</ipxact:name> + <ipxact:displayName>associatedReset</ipxact:displayName> + <ipxact:value></ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="prSafe" type="bit"> + <ipxact:name>prSafe</ipxact:name> + <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + </ipxact:parameters> + </ipxact:busInterface> + <ipxact:busInterface> + <ipxact:name>dout</ipxact:name> + <ipxact:busType vendor="intel" library="intel" name="conduit" version="26.1"></ipxact:busType> + <ipxact:abstractionTypes> + <ipxact:abstractionType> + <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="26.1"></ipxact:abstractionRef> + <ipxact:portMaps> + <ipxact:portMap> + <ipxact:logicalPort> + <ipxact:name>export</ipxact:name> + </ipxact:logicalPort> + <ipxact:physicalPort> + <ipxact:name>dout</ipxact:name> + </ipxact:physicalPort> + </ipxact:portMap> + </ipxact:portMaps> + </ipxact:abstractionType> + </ipxact:abstractionTypes> + <ipxact:slave></ipxact:slave> + <ipxact:parameters> + <ipxact:parameter parameterId="associatedClock" type="string"> + <ipxact:name>associatedClock</ipxact:name> + <ipxact:displayName>associatedClock</ipxact:displayName> + <ipxact:value></ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="associatedReset" type="string"> + <ipxact:name>associatedReset</ipxact:name> + <ipxact:displayName>associatedReset</ipxact:displayName> + <ipxact:value></ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="prSafe" type="bit"> + <ipxact:name>prSafe</ipxact:name> + <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + </ipxact:parameters> + <ipxact:vendorExtensions> + <altera:altera_assignments> + <ipxact:parameters> + <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string"> + <ipxact:name>ui.blockdiagram.direction</ipxact:name> + <ipxact:value>output</ipxact:value> + </ipxact:parameter> + </ipxact:parameters> + </altera:altera_assignments> + </ipxact:vendorExtensions> + </ipxact:busInterface> + <ipxact:busInterface> + <ipxact:name>pad_in</ipxact:name> + <ipxact:busType vendor="intel" library="intel" name="conduit" version="26.1"></ipxact:busType> + <ipxact:abstractionTypes> + <ipxact:abstractionType> + <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="26.1"></ipxact:abstractionRef> + <ipxact:portMaps> + <ipxact:portMap> + <ipxact:logicalPort> + <ipxact:name>export</ipxact:name> + </ipxact:logicalPort> + <ipxact:physicalPort> + <ipxact:name>pad_in</ipxact:name> + </ipxact:physicalPort> + </ipxact:portMap> + </ipxact:portMaps> + </ipxact:abstractionType> + </ipxact:abstractionTypes> + <ipxact:slave></ipxact:slave> + <ipxact:parameters> + <ipxact:parameter parameterId="associatedClock" type="string"> + <ipxact:name>associatedClock</ipxact:name> + <ipxact:displayName>associatedClock</ipxact:displayName> + <ipxact:value></ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="associatedReset" type="string"> + <ipxact:name>associatedReset</ipxact:name> + <ipxact:displayName>associatedReset</ipxact:displayName> + <ipxact:value></ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="prSafe" type="bit"> + <ipxact:name>prSafe</ipxact:name> + <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + </ipxact:parameters> + <ipxact:vendorExtensions> + <altera:altera_assignments> + <ipxact:parameters> + <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string"> + <ipxact:name>ui.blockdiagram.direction</ipxact:name> + <ipxact:value>input</ipxact:value> + </ipxact:parameter> + </ipxact:parameters> + </altera:altera_assignments> + </ipxact:vendorExtensions> + </ipxact:busInterface> + </ipxact:busInterfaces> + <ipxact:model> + <ipxact:views> + <ipxact:view> + <ipxact:name>QUARTUS_SYNTH</ipxact:name> + <ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier> + <ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef> + </ipxact:view> + </ipxact:views> + <ipxact:instantiations> + <ipxact:componentInstantiation> + <ipxact:name>QUARTUS_SYNTH</ipxact:name> + <ipxact:moduleName>altera_gpio</ipxact:moduleName> + <ipxact:fileSetRef> + <ipxact:localName>QUARTUS_SYNTH</ipxact:localName> + </ipxact:fileSetRef> + </ipxact:componentInstantiation> + </ipxact:instantiations> + <ipxact:ports> + <ipxact:port> + <ipxact:name>ck</ipxact:name> + <ipxact:wire> + <ipxact:direction>in</ipxact:direction> + <ipxact:wireTypeDefs> + <ipxact:wireTypeDef> + <ipxact:typeName>STD_LOGIC</ipxact:typeName> + <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef> + </ipxact:wireTypeDef> + </ipxact:wireTypeDefs> + </ipxact:wire> + </ipxact:port> + <ipxact:port> + <ipxact:name>dout</ipxact:name> + <ipxact:wire> + <ipxact:direction>out</ipxact:direction> + <ipxact:vectors> + <ipxact:vector> + <ipxact:left>0</ipxact:left> + <ipxact:right>9</ipxact:right> + </ipxact:vector> + </ipxact:vectors> + <ipxact:wireTypeDefs> + <ipxact:wireTypeDef> + <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName> + <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef> + </ipxact:wireTypeDef> + </ipxact:wireTypeDefs> + </ipxact:wire> + </ipxact:port> + <ipxact:port> + <ipxact:name>pad_in</ipxact:name> + <ipxact:wire> + <ipxact:direction>in</ipxact:direction> + <ipxact:vectors> + <ipxact:vector> + <ipxact:left>0</ipxact:left> + <ipxact:right>4</ipxact:right> + </ipxact:vector> + </ipxact:vectors> + <ipxact:wireTypeDefs> + <ipxact:wireTypeDef> + <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName> + <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef> + </ipxact:wireTypeDef> + </ipxact:wireTypeDefs> + </ipxact:wire> + </ipxact:port> + </ipxact:ports> + </ipxact:model> + <ipxact:vendorExtensions> + <altera:entity_info> + <ipxact:vendor>Altera</ipxact:vendor> + <ipxact:library>ddr_i</ipxact:library> + <ipxact:name>altera_gpio</ipxact:name> + <ipxact:version>23.0.0</ipxact:version> + </altera:entity_info> + <altera:altera_module_parameters> + <ipxact:parameters> + <ipxact:parameter parameterId="device_family" type="string"> + <ipxact:name>device_family</ipxact:name> + <ipxact:displayName>device_family</ipxact:displayName> + <ipxact:value>Agilex 3</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="PIN_TYPE_GUI" type="string"> + <ipxact:name>PIN_TYPE_GUI</ipxact:name> + <ipxact:displayName>Data Direction</ipxact:displayName> + <ipxact:value>Input</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="SIZE" type="int"> + <ipxact:name>SIZE</ipxact:name> + <ipxact:displayName>Data width</ipxact:displayName> + <ipxact:value>5</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_enable_migratable_port_names" type="bit"> + <ipxact:name>gui_enable_migratable_port_names</ipxact:name> + <ipxact:displayName>Use legacy top-level port names</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_diff_buff" type="bit"> + <ipxact:name>gui_diff_buff</ipxact:name> + <ipxact:displayName>Use differential buffer</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_pseudo_diff" type="bit"> + <ipxact:name>gui_pseudo_diff</ipxact:name> + <ipxact:displayName>Use pseudo-differential buffer</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_bus_hold" type="bit"> + <ipxact:name>gui_bus_hold</ipxact:name> + <ipxact:displayName>Use bus-hold circuitry</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_open_drain" type="bit"> + <ipxact:name>gui_open_drain</ipxact:name> + <ipxact:displayName>Use open-drain output</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_use_oe" type="bit"> + <ipxact:name>gui_use_oe</ipxact:name> + <ipxact:displayName>Enable output enable port</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_enable_termination_ports" type="bit"> + <ipxact:name>gui_enable_termination_ports</ipxact:name> + <ipxact:displayName>Enable seriestermination/paralleltermination ports</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_use_puen" type="bit"> + <ipxact:name>gui_use_puen</ipxact:name> + <ipxact:displayName>Enable dynamic pull-up port</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_io_reg_mode" type="string"> + <ipxact:name>gui_io_reg_mode</ipxact:name> + <ipxact:displayName>Register mode</ipxact:displayName> + <ipxact:value>DDIO</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_sreset_mode" type="string"> + <ipxact:name>gui_sreset_mode</ipxact:name> + <ipxact:displayName>Enable synchronous clear / preset port</ipxact:displayName> + <ipxact:value>None</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_areset_mode" type="string"> + <ipxact:name>gui_areset_mode</ipxact:name> + <ipxact:displayName>Enable asynchronous clear / preset port</ipxact:displayName> + <ipxact:value>None</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_enable_cke" type="bit"> + <ipxact:name>gui_enable_cke</ipxact:name> + <ipxact:displayName>Enable clock enable port</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_hr_logic" type="bit"> + <ipxact:name>gui_hr_logic</ipxact:name> + <ipxact:displayName>Half Rate Logic</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_ddio_with_delay" type="bit"> + <ipxact:name>gui_ddio_with_delay</ipxact:name> + <ipxact:displayName>Input DDIO With Delay</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_separate_io_clks" type="bit"> + <ipxact:name>gui_separate_io_clks</ipxact:name> + <ipxact:displayName>Separate input/output Clocks</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="SYS_INFO_DEVICE" type="string"> + <ipxact:name>SYS_INFO_DEVICE</ipxact:name> + <ipxact:displayName>SYS_INFO_DEVICE</ipxact:displayName> + <ipxact:value>A3CY050BB18AI6S</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="SYS_INFO_FAMILY" type="string"> + <ipxact:name>SYS_INFO_FAMILY</ipxact:name> + <ipxact:displayName>SYS_INFO_FAMILY</ipxact:displayName> + <ipxact:value>Agilex 3</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="SYS_INFO_TRAIT_IOBANK_REVISION" type="string"> + <ipxact:name>SYS_INFO_TRAIT_IOBANK_REVISION</ipxact:name> + <ipxact:displayName>SYS_INFO_TRAIT_IOBANK_REVISION</ipxact:displayName> + <ipxact:value>IO96B_REVB1</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="EXT_DRIVER_PARAM" type="bit"> + <ipxact:name>EXT_DRIVER_PARAM</ipxact:name> + <ipxact:displayName>EXT_DRIVER_PARAM</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="GENERATE_SDC_FILE" type="bit"> + <ipxact:name>GENERATE_SDC_FILE</ipxact:name> + <ipxact:displayName>GENERATE_SDC_FILE</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="IP_MIGRATE_PORT_MAP_FILE" type="string"> + <ipxact:name>IP_MIGRATE_PORT_MAP_FILE</ipxact:name> + <ipxact:displayName>IP_MIGRATE_PORT_MAP_FILE</ipxact:displayName> + <ipxact:value>altddio_bidir_port_map.csv</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="AUTO_DEVICE_SPEEDGRADE" type="string"> + <ipxact:name>AUTO_DEVICE_SPEEDGRADE</ipxact:name> + <ipxact:displayName>Auto DEVICE_SPEEDGRADE</ipxact:displayName> + <ipxact:value>6</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="AUTO_BOARD" type="string"> + <ipxact:name>AUTO_BOARD</ipxact:name> + <ipxact:displayName>Auto BOARD</ipxact:displayName> + <ipxact:value>default</ipxact:value> + </ipxact:parameter> + </ipxact:parameters> + </altera:altera_module_parameters> + <altera:altera_system_parameters> + <ipxact:parameters> + <ipxact:parameter parameterId="board" type="string"> + <ipxact:name>board</ipxact:name> + <ipxact:displayName>Board</ipxact:displayName> + <ipxact:value>default</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="device" type="string"> + <ipxact:name>device</ipxact:name> + <ipxact:displayName>Device</ipxact:displayName> + <ipxact:value>A3CY050BB18AI6S</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="deviceFamily" type="string"> + <ipxact:name>deviceFamily</ipxact:name> + <ipxact:displayName>Device family</ipxact:displayName> + <ipxact:value>Agilex 3</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="deviceSpeedGrade" type="string"> + <ipxact:name>deviceSpeedGrade</ipxact:name> + <ipxact:displayName>Device Speed Grade</ipxact:displayName> + <ipxact:value>6</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="generationId" type="int"> + <ipxact:name>generationId</ipxact:name> + <ipxact:displayName>Generation Id</ipxact:displayName> + <ipxact:value>0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="bonusData" type="string"> + <ipxact:name>bonusData</ipxact:name> + <ipxact:displayName>bonusData</ipxact:displayName> + <ipxact:value>bonusData +{ + element gpio_0 + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} +</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="hideFromIPCatalog" type="bit"> + <ipxact:name>hideFromIPCatalog</ipxact:name> + <ipxact:displayName>Hide from IP Catalog</ipxact:displayName> + <ipxact:value>true</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="lockedInterfaceDefinition" type="string"> + <ipxact:name>lockedInterfaceDefinition</ipxact:name> + <ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName> + <ipxact:value></ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="systemInfos" type="string"> + <ipxact:name>systemInfos</ipxact:name> + <ipxact:displayName>systemInfos</ipxact:displayName> + <ipxact:value><systemInfosDefinition> + <connPtSystemInfos/> +</systemInfosDefinition></ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="dflBitArray" type="string"> + <ipxact:name>dflBitArray</ipxact:name> + <ipxact:displayName>dflBitArray</ipxact:displayName> + <ipxact:value></ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="cpuInfo" type="string"> + <ipxact:name>cpuInfo</ipxact:name> + <ipxact:displayName>cpuInfo</ipxact:displayName> + <ipxact:value></ipxact:value> + </ipxact:parameter> + </ipxact:parameters> + </altera:altera_system_parameters> + <altera:altera_interface_boundary> + <altera:interface_mapping altera:name="ck" altera:internal="gpio_0.ck" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="ck" altera:internal="ck"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="din" altera:internal="gpio_0.din"></altera:interface_mapping> + <altera:interface_mapping altera:name="dout" altera:internal="gpio_0.dout" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="dout" altera:internal="dout"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="pad_in" altera:internal="gpio_0.pad_in" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="pad_in" altera:internal="pad_in"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="pad_out" altera:internal="gpio_0.pad_out"></altera:interface_mapping> + </altera:altera_interface_boundary> + <altera:altera_has_warnings>false</altera:altera_has_warnings> + <altera:altera_has_errors>false</altera:altera_has_errors> + </ipxact:vendorExtensions> +</ipxact:component>
\ No newline at end of file diff --git a/ip/ddr_o.ip b/ip/ddr_o.ip new file mode 100644 index 0000000..285625a --- /dev/null +++ b/ip/ddr_o.ip @@ -0,0 +1,446 @@ +<?xml version="1.0" ?> +<!--Your use of Altera Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, the Altera Quartus Prime License Agreement, +the Altera FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Altera and sold by Altera or its authorized distributors.--> +<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"> + <ipxact:vendor>Altera</ipxact:vendor> + <ipxact:library>ddr_o</ipxact:library> + <ipxact:name>gpio_0</ipxact:name> + <ipxact:version>23.0.0</ipxact:version> + <ipxact:busInterfaces> + <ipxact:busInterface> + <ipxact:name>ck</ipxact:name> + <ipxact:busType vendor="intel" library="intel" name="conduit" version="26.1"></ipxact:busType> + <ipxact:abstractionTypes> + <ipxact:abstractionType> + <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="26.1"></ipxact:abstractionRef> + <ipxact:portMaps> + <ipxact:portMap> + <ipxact:logicalPort> + <ipxact:name>export</ipxact:name> + </ipxact:logicalPort> + <ipxact:physicalPort> + <ipxact:name>ck</ipxact:name> + </ipxact:physicalPort> + </ipxact:portMap> + </ipxact:portMaps> + </ipxact:abstractionType> + </ipxact:abstractionTypes> + <ipxact:slave></ipxact:slave> + <ipxact:parameters> + <ipxact:parameter parameterId="associatedClock" type="string"> + <ipxact:name>associatedClock</ipxact:name> + <ipxact:displayName>associatedClock</ipxact:displayName> + <ipxact:value></ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="associatedReset" type="string"> + <ipxact:name>associatedReset</ipxact:name> + <ipxact:displayName>associatedReset</ipxact:displayName> + <ipxact:value></ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="prSafe" type="bit"> + <ipxact:name>prSafe</ipxact:name> + <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + </ipxact:parameters> + </ipxact:busInterface> + <ipxact:busInterface> + <ipxact:name>din</ipxact:name> + <ipxact:busType vendor="intel" library="intel" name="conduit" version="26.1"></ipxact:busType> + <ipxact:abstractionTypes> + <ipxact:abstractionType> + <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="26.1"></ipxact:abstractionRef> + <ipxact:portMaps> + <ipxact:portMap> + <ipxact:logicalPort> + <ipxact:name>export</ipxact:name> + </ipxact:logicalPort> + <ipxact:physicalPort> + <ipxact:name>din</ipxact:name> + </ipxact:physicalPort> + </ipxact:portMap> + </ipxact:portMaps> + </ipxact:abstractionType> + </ipxact:abstractionTypes> + <ipxact:slave></ipxact:slave> + <ipxact:parameters> + <ipxact:parameter parameterId="associatedClock" type="string"> + <ipxact:name>associatedClock</ipxact:name> + <ipxact:displayName>associatedClock</ipxact:displayName> + <ipxact:value></ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="associatedReset" type="string"> + <ipxact:name>associatedReset</ipxact:name> + <ipxact:displayName>associatedReset</ipxact:displayName> + <ipxact:value></ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="prSafe" type="bit"> + <ipxact:name>prSafe</ipxact:name> + <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + </ipxact:parameters> + <ipxact:vendorExtensions> + <altera:altera_assignments> + <ipxact:parameters> + <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string"> + <ipxact:name>ui.blockdiagram.direction</ipxact:name> + <ipxact:value>input</ipxact:value> + </ipxact:parameter> + </ipxact:parameters> + </altera:altera_assignments> + </ipxact:vendorExtensions> + </ipxact:busInterface> + <ipxact:busInterface> + <ipxact:name>pad_out</ipxact:name> + <ipxact:busType vendor="intel" library="intel" name="conduit" version="26.1"></ipxact:busType> + <ipxact:abstractionTypes> + <ipxact:abstractionType> + <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="26.1"></ipxact:abstractionRef> + <ipxact:portMaps> + <ipxact:portMap> + <ipxact:logicalPort> + <ipxact:name>export</ipxact:name> + </ipxact:logicalPort> + <ipxact:physicalPort> + <ipxact:name>pad_out</ipxact:name> + </ipxact:physicalPort> + </ipxact:portMap> + </ipxact:portMaps> + </ipxact:abstractionType> + </ipxact:abstractionTypes> + <ipxact:slave></ipxact:slave> + <ipxact:parameters> + <ipxact:parameter parameterId="associatedClock" type="string"> + <ipxact:name>associatedClock</ipxact:name> + <ipxact:displayName>associatedClock</ipxact:displayName> + <ipxact:value></ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="associatedReset" type="string"> + <ipxact:name>associatedReset</ipxact:name> + <ipxact:displayName>associatedReset</ipxact:displayName> + <ipxact:value></ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="prSafe" type="bit"> + <ipxact:name>prSafe</ipxact:name> + <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + </ipxact:parameters> + <ipxact:vendorExtensions> + <altera:altera_assignments> + <ipxact:parameters> + <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string"> + <ipxact:name>ui.blockdiagram.direction</ipxact:name> + <ipxact:value>output</ipxact:value> + </ipxact:parameter> + </ipxact:parameters> + </altera:altera_assignments> + </ipxact:vendorExtensions> + </ipxact:busInterface> + </ipxact:busInterfaces> + <ipxact:model> + <ipxact:views> + <ipxact:view> + <ipxact:name>QUARTUS_SYNTH</ipxact:name> + <ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier> + <ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef> + </ipxact:view> + </ipxact:views> + <ipxact:instantiations> + <ipxact:componentInstantiation> + <ipxact:name>QUARTUS_SYNTH</ipxact:name> + <ipxact:moduleName>altera_gpio</ipxact:moduleName> + <ipxact:fileSetRef> + <ipxact:localName>QUARTUS_SYNTH</ipxact:localName> + </ipxact:fileSetRef> + </ipxact:componentInstantiation> + </ipxact:instantiations> + <ipxact:ports> + <ipxact:port> + <ipxact:name>ck</ipxact:name> + <ipxact:wire> + <ipxact:direction>in</ipxact:direction> + <ipxact:wireTypeDefs> + <ipxact:wireTypeDef> + <ipxact:typeName>STD_LOGIC</ipxact:typeName> + <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef> + </ipxact:wireTypeDef> + </ipxact:wireTypeDefs> + </ipxact:wire> + </ipxact:port> + <ipxact:port> + <ipxact:name>din</ipxact:name> + <ipxact:wire> + <ipxact:direction>in</ipxact:direction> + <ipxact:vectors> + <ipxact:vector> + <ipxact:left>0</ipxact:left> + <ipxact:right>11</ipxact:right> + </ipxact:vector> + </ipxact:vectors> + <ipxact:wireTypeDefs> + <ipxact:wireTypeDef> + <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName> + <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef> + </ipxact:wireTypeDef> + </ipxact:wireTypeDefs> + </ipxact:wire> + </ipxact:port> + <ipxact:port> + <ipxact:name>pad_out</ipxact:name> + <ipxact:wire> + <ipxact:direction>out</ipxact:direction> + <ipxact:vectors> + <ipxact:vector> + <ipxact:left>0</ipxact:left> + <ipxact:right>5</ipxact:right> + </ipxact:vector> + </ipxact:vectors> + <ipxact:wireTypeDefs> + <ipxact:wireTypeDef> + <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName> + <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef> + </ipxact:wireTypeDef> + </ipxact:wireTypeDefs> + </ipxact:wire> + </ipxact:port> + </ipxact:ports> + </ipxact:model> + <ipxact:vendorExtensions> + <altera:entity_info> + <ipxact:vendor>Altera</ipxact:vendor> + <ipxact:library>ddr_o</ipxact:library> + <ipxact:name>altera_gpio</ipxact:name> + <ipxact:version>23.0.0</ipxact:version> + </altera:entity_info> + <altera:altera_module_parameters> + <ipxact:parameters> + <ipxact:parameter parameterId="device_family" type="string"> + <ipxact:name>device_family</ipxact:name> + <ipxact:displayName>device_family</ipxact:displayName> + <ipxact:value>Agilex 3</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="PIN_TYPE_GUI" type="string"> + <ipxact:name>PIN_TYPE_GUI</ipxact:name> + <ipxact:displayName>Data Direction</ipxact:displayName> + <ipxact:value>Output</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="SIZE" type="int"> + <ipxact:name>SIZE</ipxact:name> + <ipxact:displayName>Data width</ipxact:displayName> + <ipxact:value>6</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_enable_migratable_port_names" type="bit"> + <ipxact:name>gui_enable_migratable_port_names</ipxact:name> + <ipxact:displayName>Use legacy top-level port names</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_diff_buff" type="bit"> + <ipxact:name>gui_diff_buff</ipxact:name> + <ipxact:displayName>Use differential buffer</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_pseudo_diff" type="bit"> + <ipxact:name>gui_pseudo_diff</ipxact:name> + <ipxact:displayName>Use pseudo-differential buffer</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_bus_hold" type="bit"> + <ipxact:name>gui_bus_hold</ipxact:name> + <ipxact:displayName>Use bus-hold circuitry</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_open_drain" type="bit"> + <ipxact:name>gui_open_drain</ipxact:name> + <ipxact:displayName>Use open-drain output</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_use_oe" type="bit"> + <ipxact:name>gui_use_oe</ipxact:name> + <ipxact:displayName>Enable output enable port</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_enable_termination_ports" type="bit"> + <ipxact:name>gui_enable_termination_ports</ipxact:name> + <ipxact:displayName>Enable seriestermination/paralleltermination ports</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_use_puen" type="bit"> + <ipxact:name>gui_use_puen</ipxact:name> + <ipxact:displayName>Enable dynamic pull-up port</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_io_reg_mode" type="string"> + <ipxact:name>gui_io_reg_mode</ipxact:name> + <ipxact:displayName>Register mode</ipxact:displayName> + <ipxact:value>DDIO</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_sreset_mode" type="string"> + <ipxact:name>gui_sreset_mode</ipxact:name> + <ipxact:displayName>Enable synchronous clear / preset port</ipxact:displayName> + <ipxact:value>None</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_areset_mode" type="string"> + <ipxact:name>gui_areset_mode</ipxact:name> + <ipxact:displayName>Enable asynchronous clear / preset port</ipxact:displayName> + <ipxact:value>None</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_enable_cke" type="bit"> + <ipxact:name>gui_enable_cke</ipxact:name> + <ipxact:displayName>Enable clock enable port</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_hr_logic" type="bit"> + <ipxact:name>gui_hr_logic</ipxact:name> + <ipxact:displayName>Half Rate Logic</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_ddio_with_delay" type="bit"> + <ipxact:name>gui_ddio_with_delay</ipxact:name> + <ipxact:displayName>Input DDIO With Delay</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_separate_io_clks" type="bit"> + <ipxact:name>gui_separate_io_clks</ipxact:name> + <ipxact:displayName>Separate input/output Clocks</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="SYS_INFO_DEVICE" type="string"> + <ipxact:name>SYS_INFO_DEVICE</ipxact:name> + <ipxact:displayName>SYS_INFO_DEVICE</ipxact:displayName> + <ipxact:value>A3CY050BB18AI6S</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="SYS_INFO_FAMILY" type="string"> + <ipxact:name>SYS_INFO_FAMILY</ipxact:name> + <ipxact:displayName>SYS_INFO_FAMILY</ipxact:displayName> + <ipxact:value>Agilex 3</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="SYS_INFO_TRAIT_IOBANK_REVISION" type="string"> + <ipxact:name>SYS_INFO_TRAIT_IOBANK_REVISION</ipxact:name> + <ipxact:displayName>SYS_INFO_TRAIT_IOBANK_REVISION</ipxact:displayName> + <ipxact:value>IO96B_REVB1</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="EXT_DRIVER_PARAM" type="bit"> + <ipxact:name>EXT_DRIVER_PARAM</ipxact:name> + <ipxact:displayName>EXT_DRIVER_PARAM</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="GENERATE_SDC_FILE" type="bit"> + <ipxact:name>GENERATE_SDC_FILE</ipxact:name> + <ipxact:displayName>GENERATE_SDC_FILE</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="IP_MIGRATE_PORT_MAP_FILE" type="string"> + <ipxact:name>IP_MIGRATE_PORT_MAP_FILE</ipxact:name> + <ipxact:displayName>IP_MIGRATE_PORT_MAP_FILE</ipxact:displayName> + <ipxact:value>altddio_bidir_port_map.csv</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="AUTO_DEVICE_SPEEDGRADE" type="string"> + <ipxact:name>AUTO_DEVICE_SPEEDGRADE</ipxact:name> + <ipxact:displayName>Auto DEVICE_SPEEDGRADE</ipxact:displayName> + <ipxact:value>6</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="AUTO_BOARD" type="string"> + <ipxact:name>AUTO_BOARD</ipxact:name> + <ipxact:displayName>Auto BOARD</ipxact:displayName> + <ipxact:value>default</ipxact:value> + </ipxact:parameter> + </ipxact:parameters> + </altera:altera_module_parameters> + <altera:altera_system_parameters> + <ipxact:parameters> + <ipxact:parameter parameterId="board" type="string"> + <ipxact:name>board</ipxact:name> + <ipxact:displayName>Board</ipxact:displayName> + <ipxact:value>default</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="device" type="string"> + <ipxact:name>device</ipxact:name> + <ipxact:displayName>Device</ipxact:displayName> + <ipxact:value>A3CY050BB18AI6S</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="deviceFamily" type="string"> + <ipxact:name>deviceFamily</ipxact:name> + <ipxact:displayName>Device family</ipxact:displayName> + <ipxact:value>Agilex 3</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="deviceSpeedGrade" type="string"> + <ipxact:name>deviceSpeedGrade</ipxact:name> + <ipxact:displayName>Device Speed Grade</ipxact:displayName> + <ipxact:value>6</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="generationId" type="int"> + <ipxact:name>generationId</ipxact:name> + <ipxact:displayName>Generation Id</ipxact:displayName> + <ipxact:value>0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="bonusData" type="string"> + <ipxact:name>bonusData</ipxact:name> + <ipxact:displayName>bonusData</ipxact:displayName> + <ipxact:value>bonusData +{ + element gpio_0 + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} +</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="hideFromIPCatalog" type="bit"> + <ipxact:name>hideFromIPCatalog</ipxact:name> + <ipxact:displayName>Hide from IP Catalog</ipxact:displayName> + <ipxact:value>true</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="lockedInterfaceDefinition" type="string"> + <ipxact:name>lockedInterfaceDefinition</ipxact:name> + <ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName> + <ipxact:value></ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="systemInfos" type="string"> + <ipxact:name>systemInfos</ipxact:name> + <ipxact:displayName>systemInfos</ipxact:displayName> + <ipxact:value><systemInfosDefinition> + <connPtSystemInfos/> +</systemInfosDefinition></ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="dflBitArray" type="string"> + <ipxact:name>dflBitArray</ipxact:name> + <ipxact:displayName>dflBitArray</ipxact:displayName> + <ipxact:value></ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="cpuInfo" type="string"> + <ipxact:name>cpuInfo</ipxact:name> + <ipxact:displayName>cpuInfo</ipxact:displayName> + <ipxact:value></ipxact:value> + </ipxact:parameter> + </ipxact:parameters> + </altera:altera_system_parameters> + <altera:altera_interface_boundary> + <altera:interface_mapping altera:name="ck" altera:internal="gpio_0.ck" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="ck" altera:internal="ck"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="din" altera:internal="gpio_0.din" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="din" altera:internal="din"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="pad_out" altera:internal="gpio_0.pad_out" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="pad_out" altera:internal="pad_out"></altera:port_mapping> + </altera:interface_mapping> + </altera:altera_interface_boundary> + <altera:altera_has_warnings>false</altera:altera_has_warnings> + <altera:altera_has_errors>false</altera:altera_has_errors> + </ipxact:vendorExtensions> +</ipxact:component>
\ No newline at end of file diff --git a/ip/pll_io.ip b/ip/pll_io.ip new file mode 100644 index 0000000..84caf8f --- /dev/null +++ b/ip/pll_io.ip @@ -0,0 +1,1816 @@ +<?xml version="1.0" ?> +<!--Your use of Altera Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, the Altera Quartus Prime License Agreement, +the Altera FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Altera and sold by Altera or its authorized distributors.--> +<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"> + <ipxact:vendor>Altera</ipxact:vendor> + <ipxact:library>pll_io</ipxact:library> + <ipxact:name>iopll_0</ipxact:name> + <ipxact:version>21.1.0</ipxact:version> + <ipxact:busInterfaces> + <ipxact:busInterface> + <ipxact:name>refclk</ipxact:name> + <ipxact:busType vendor="intel" library="intel" name="clock" version="26.1"></ipxact:busType> + <ipxact:abstractionTypes> + <ipxact:abstractionType> + <ipxact:abstractionRef vendor="intel" library="intel" name="clock" version="26.1"></ipxact:abstractionRef> + <ipxact:portMaps> + <ipxact:portMap> + <ipxact:logicalPort> + <ipxact:name>clk</ipxact:name> + </ipxact:logicalPort> + <ipxact:physicalPort> + <ipxact:name>refclk</ipxact:name> + </ipxact:physicalPort> + </ipxact:portMap> + </ipxact:portMaps> + </ipxact:abstractionType> + </ipxact:abstractionTypes> + <ipxact:slave></ipxact:slave> + <ipxact:parameters> + <ipxact:parameter parameterId="clockRate" type="longint"> + <ipxact:name>clockRate</ipxact:name> + <ipxact:displayName>Clock rate</ipxact:displayName> + <ipxact:value>25000000</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="externallyDriven" type="bit"> + <ipxact:name>externallyDriven</ipxact:name> + <ipxact:displayName>Externally driven</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="ptfSchematicName" type="string"> + <ipxact:name>ptfSchematicName</ipxact:name> + <ipxact:displayName>PTF schematic name</ipxact:displayName> + <ipxact:value></ipxact:value> + </ipxact:parameter> + </ipxact:parameters> + <ipxact:vendorExtensions> + <altera:altera_assignments> + <ipxact:parameters> + <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string"> + <ipxact:name>ui.blockdiagram.direction</ipxact:name> + <ipxact:value>input</ipxact:value> + </ipxact:parameter> + </ipxact:parameters> + </altera:altera_assignments> + </ipxact:vendorExtensions> + </ipxact:busInterface> + <ipxact:busInterface> + <ipxact:name>locked</ipxact:name> + <ipxact:busType vendor="intel" library="intel" name="conduit" version="26.1"></ipxact:busType> + <ipxact:abstractionTypes> + <ipxact:abstractionType> + <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="26.1"></ipxact:abstractionRef> + <ipxact:portMaps> + <ipxact:portMap> + <ipxact:logicalPort> + <ipxact:name>export</ipxact:name> + </ipxact:logicalPort> + <ipxact:physicalPort> + <ipxact:name>locked</ipxact:name> + </ipxact:physicalPort> + </ipxact:portMap> + </ipxact:portMaps> + </ipxact:abstractionType> + </ipxact:abstractionTypes> + <ipxact:slave></ipxact:slave> + <ipxact:parameters> + <ipxact:parameter parameterId="associatedClock" type="string"> + <ipxact:name>associatedClock</ipxact:name> + <ipxact:displayName>associatedClock</ipxact:displayName> + <ipxact:value></ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="associatedReset" type="string"> + <ipxact:name>associatedReset</ipxact:name> + <ipxact:displayName>associatedReset</ipxact:displayName> + <ipxact:value></ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="prSafe" type="bit"> + <ipxact:name>prSafe</ipxact:name> + <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + </ipxact:parameters> + <ipxact:vendorExtensions> + <altera:altera_assignments> + <ipxact:parameters> + <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string"> + <ipxact:name>ui.blockdiagram.direction</ipxact:name> + <ipxact:value>output</ipxact:value> + </ipxact:parameter> + </ipxact:parameters> + </altera:altera_assignments> + </ipxact:vendorExtensions> + </ipxact:busInterface> + <ipxact:busInterface> + <ipxact:name>reset</ipxact:name> + <ipxact:busType vendor="intel" library="intel" name="reset" version="26.1"></ipxact:busType> + <ipxact:abstractionTypes> + <ipxact:abstractionType> + <ipxact:abstractionRef vendor="intel" library="intel" name="reset" version="26.1"></ipxact:abstractionRef> + <ipxact:portMaps> + <ipxact:portMap> + <ipxact:logicalPort> + <ipxact:name>reset</ipxact:name> + </ipxact:logicalPort> + <ipxact:physicalPort> + <ipxact:name>rst</ipxact:name> + </ipxact:physicalPort> + </ipxact:portMap> + </ipxact:portMaps> + </ipxact:abstractionType> + </ipxact:abstractionTypes> + <ipxact:slave></ipxact:slave> + <ipxact:parameters> + <ipxact:parameter parameterId="associatedClock" type="string"> + <ipxact:name>associatedClock</ipxact:name> + <ipxact:displayName>Associated clock</ipxact:displayName> + <ipxact:value></ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="synchronousEdges" type="string"> + <ipxact:name>synchronousEdges</ipxact:name> + <ipxact:displayName>Synchronous edges</ipxact:displayName> + <ipxact:value>NONE</ipxact:value> + </ipxact:parameter> + </ipxact:parameters> + <ipxact:vendorExtensions> + <altera:altera_assignments> + <ipxact:parameters> + <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string"> + <ipxact:name>ui.blockdiagram.direction</ipxact:name> + <ipxact:value>input</ipxact:value> + </ipxact:parameter> + </ipxact:parameters> + </altera:altera_assignments> + </ipxact:vendorExtensions> + </ipxact:busInterface> + <ipxact:busInterface> + <ipxact:name>outclk0</ipxact:name> + <ipxact:busType vendor="intel" library="intel" name="clock" version="26.1"></ipxact:busType> + <ipxact:abstractionTypes> + <ipxact:abstractionType> + <ipxact:abstractionRef vendor="intel" library="intel" name="clock" version="26.1"></ipxact:abstractionRef> + <ipxact:portMaps> + <ipxact:portMap> + <ipxact:logicalPort> + <ipxact:name>clk</ipxact:name> + </ipxact:logicalPort> + <ipxact:physicalPort> + <ipxact:name>outclk_0</ipxact:name> + </ipxact:physicalPort> + </ipxact:portMap> + </ipxact:portMaps> + </ipxact:abstractionType> + </ipxact:abstractionTypes> + <ipxact:master></ipxact:master> + <ipxact:parameters> + <ipxact:parameter parameterId="associatedDirectClock" type="string"> + <ipxact:name>associatedDirectClock</ipxact:name> + <ipxact:displayName>Associated direct clock</ipxact:displayName> + <ipxact:value></ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="clockRate" type="longint"> + <ipxact:name>clockRate</ipxact:name> + <ipxact:displayName>Clock rate</ipxact:displayName> + <ipxact:value>25000000</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="clockRateKnown" type="bit"> + <ipxact:name>clockRateKnown</ipxact:name> + <ipxact:displayName>Clock rate known</ipxact:displayName> + <ipxact:value>true</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="externallyDriven" type="bit"> + <ipxact:name>externallyDriven</ipxact:name> + <ipxact:displayName>Externally driven</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="ptfSchematicName" type="string"> + <ipxact:name>ptfSchematicName</ipxact:name> + <ipxact:displayName>PTF schematic name</ipxact:displayName> + <ipxact:value></ipxact:value> + </ipxact:parameter> + </ipxact:parameters> + <ipxact:vendorExtensions> + <altera:altera_assignments> + <ipxact:parameters> + <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string"> + <ipxact:name>ui.blockdiagram.direction</ipxact:name> + <ipxact:value>output</ipxact:value> + </ipxact:parameter> + </ipxact:parameters> + </altera:altera_assignments> + </ipxact:vendorExtensions> + </ipxact:busInterface> + <ipxact:busInterface> + <ipxact:name>outclk1</ipxact:name> + <ipxact:busType vendor="intel" library="intel" name="clock" version="26.1"></ipxact:busType> + <ipxact:abstractionTypes> + <ipxact:abstractionType> + <ipxact:abstractionRef vendor="intel" library="intel" name="clock" version="26.1"></ipxact:abstractionRef> + <ipxact:portMaps> + <ipxact:portMap> + <ipxact:logicalPort> + <ipxact:name>clk</ipxact:name> + </ipxact:logicalPort> + <ipxact:physicalPort> + <ipxact:name>outclk_1</ipxact:name> + </ipxact:physicalPort> + </ipxact:portMap> + </ipxact:portMaps> + </ipxact:abstractionType> + </ipxact:abstractionTypes> + <ipxact:master></ipxact:master> + <ipxact:parameters> + <ipxact:parameter parameterId="associatedDirectClock" type="string"> + <ipxact:name>associatedDirectClock</ipxact:name> + <ipxact:displayName>Associated direct clock</ipxact:displayName> + <ipxact:value></ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="clockRate" type="longint"> + <ipxact:name>clockRate</ipxact:name> + <ipxact:displayName>Clock rate</ipxact:displayName> + <ipxact:value>125000000</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="clockRateKnown" type="bit"> + <ipxact:name>clockRateKnown</ipxact:name> + <ipxact:displayName>Clock rate known</ipxact:displayName> + <ipxact:value>true</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="externallyDriven" type="bit"> + <ipxact:name>externallyDriven</ipxact:name> + <ipxact:displayName>Externally driven</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="ptfSchematicName" type="string"> + <ipxact:name>ptfSchematicName</ipxact:name> + <ipxact:displayName>PTF schematic name</ipxact:displayName> + <ipxact:value></ipxact:value> + </ipxact:parameter> + </ipxact:parameters> + <ipxact:vendorExtensions> + <altera:altera_assignments> + <ipxact:parameters> + <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string"> + <ipxact:name>ui.blockdiagram.direction</ipxact:name> + <ipxact:value>output</ipxact:value> + </ipxact:parameter> + </ipxact:parameters> + </altera:altera_assignments> + </ipxact:vendorExtensions> + </ipxact:busInterface> + </ipxact:busInterfaces> + <ipxact:model> + <ipxact:views> + <ipxact:view> + <ipxact:name>QUARTUS_SYNTH</ipxact:name> + <ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier> + <ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef> + </ipxact:view> + </ipxact:views> + <ipxact:instantiations> + <ipxact:componentInstantiation> + <ipxact:name>QUARTUS_SYNTH</ipxact:name> + <ipxact:moduleName>altera_iopll</ipxact:moduleName> + <ipxact:fileSetRef> + <ipxact:localName>QUARTUS_SYNTH</ipxact:localName> + </ipxact:fileSetRef> + </ipxact:componentInstantiation> + </ipxact:instantiations> + <ipxact:ports> + <ipxact:port> + <ipxact:name>refclk</ipxact:name> + <ipxact:wire> + <ipxact:direction>in</ipxact:direction> + <ipxact:wireTypeDefs> + <ipxact:wireTypeDef> + <ipxact:typeName>STD_LOGIC</ipxact:typeName> + <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef> + </ipxact:wireTypeDef> + </ipxact:wireTypeDefs> + </ipxact:wire> + </ipxact:port> + <ipxact:port> + <ipxact:name>locked</ipxact:name> + <ipxact:wire> + <ipxact:direction>out</ipxact:direction> + <ipxact:wireTypeDefs> + <ipxact:wireTypeDef> + <ipxact:typeName>STD_LOGIC</ipxact:typeName> + <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef> + </ipxact:wireTypeDef> + </ipxact:wireTypeDefs> + </ipxact:wire> + </ipxact:port> + <ipxact:port> + <ipxact:name>rst</ipxact:name> + <ipxact:wire> + <ipxact:direction>in</ipxact:direction> + <ipxact:wireTypeDefs> + <ipxact:wireTypeDef> + <ipxact:typeName>STD_LOGIC</ipxact:typeName> + <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef> + </ipxact:wireTypeDef> + </ipxact:wireTypeDefs> + </ipxact:wire> + </ipxact:port> + <ipxact:port> + <ipxact:name>outclk_0</ipxact:name> + <ipxact:wire> + <ipxact:direction>out</ipxact:direction> + <ipxact:wireTypeDefs> + <ipxact:wireTypeDef> + <ipxact:typeName>STD_LOGIC</ipxact:typeName> + <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef> + </ipxact:wireTypeDef> + </ipxact:wireTypeDefs> + </ipxact:wire> + </ipxact:port> + <ipxact:port> + <ipxact:name>outclk_1</ipxact:name> + <ipxact:wire> + <ipxact:direction>out</ipxact:direction> + <ipxact:wireTypeDefs> + <ipxact:wireTypeDef> + <ipxact:typeName>STD_LOGIC</ipxact:typeName> + <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef> + </ipxact:wireTypeDef> + </ipxact:wireTypeDefs> + </ipxact:wire> + </ipxact:port> + </ipxact:ports> + </ipxact:model> + <ipxact:vendorExtensions> + <altera:entity_info> + <ipxact:vendor>Altera</ipxact:vendor> + <ipxact:library>pll_io</ipxact:library> + <ipxact:name>altera_iopll</ipxact:name> + <ipxact:version>21.1.0</ipxact:version> + </altera:entity_info> + <altera:altera_module_parameters> + <ipxact:parameters> + <ipxact:parameter parameterId="gui_debug_mode" type="bit"> + <ipxact:name>gui_debug_mode</ipxact:name> + <ipxact:displayName></ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_skip_sdc_generation" type="bit"> + <ipxact:name>gui_skip_sdc_generation</ipxact:name> + <ipxact:displayName></ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_include_iossm" type="bit"> + <ipxact:name>gui_include_iossm</ipxact:name> + <ipxact:displayName></ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_cal_code_hex_file" type="string"> + <ipxact:name>gui_cal_code_hex_file</ipxact:name> + <ipxact:displayName></ipxact:displayName> + <ipxact:value>iossm.hex</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_parameter_table_hex_file" type="string"> + <ipxact:name>gui_parameter_table_hex_file</ipxact:name> + <ipxact:displayName></ipxact:displayName> + <ipxact:value>seq_params_sim.hex</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_pll_tclk_mux_en" type="bit"> + <ipxact:name>gui_pll_tclk_mux_en</ipxact:name> + <ipxact:displayName></ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_pll_tclk_sel" type="string"> + <ipxact:name>gui_pll_tclk_sel</ipxact:name> + <ipxact:displayName></ipxact:displayName> + <ipxact:value>pll_tclk_m_src</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_pll_vco_freq_band_0" type="string"> + <ipxact:name>gui_pll_vco_freq_band_0</ipxact:name> + <ipxact:displayName></ipxact:displayName> + <ipxact:value>pll_freq_clk0_band18</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_pll_vco_freq_band_1" type="string"> + <ipxact:name>gui_pll_vco_freq_band_1</ipxact:name> + <ipxact:displayName></ipxact:displayName> + <ipxact:value>pll_freq_clk1_band18</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_pll_freqcal_en" type="bit"> + <ipxact:name>gui_pll_freqcal_en</ipxact:name> + <ipxact:displayName></ipxact:displayName> + <ipxact:value>true</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_pll_freqcal_req_flag" type="bit"> + <ipxact:name>gui_pll_freqcal_req_flag</ipxact:name> + <ipxact:displayName></ipxact:displayName> + <ipxact:value>true</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_cal_converge" type="bit"> + <ipxact:name>gui_cal_converge</ipxact:name> + <ipxact:displayName></ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_cal_error" type="string"> + <ipxact:name>gui_cal_error</ipxact:name> + <ipxact:displayName></ipxact:displayName> + <ipxact:value>cal_clean</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_pll_cal_done" type="bit"> + <ipxact:name>gui_pll_cal_done</ipxact:name> + <ipxact:displayName></ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_pll_type" type="string"> + <ipxact:name>gui_pll_type</ipxact:name> + <ipxact:displayName></ipxact:displayName> + <ipxact:value>S10_Physical</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_pll_m_cnt_in_src" type="string"> + <ipxact:name>gui_pll_m_cnt_in_src</ipxact:name> + <ipxact:displayName></ipxact:displayName> + <ipxact:value>c_m_cnt_in_src_ph_mux_clk</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_c_cnt_in_src0" type="string"> + <ipxact:name>gui_c_cnt_in_src0</ipxact:name> + <ipxact:displayName></ipxact:displayName> + <ipxact:value>c_m_cnt_in_src_ph_mux_clk</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_c_cnt_in_src1" type="string"> + <ipxact:name>gui_c_cnt_in_src1</ipxact:name> + <ipxact:displayName></ipxact:displayName> + <ipxact:value>c_m_cnt_in_src_ph_mux_clk</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_c_cnt_in_src2" type="string"> + <ipxact:name>gui_c_cnt_in_src2</ipxact:name> + <ipxact:displayName></ipxact:displayName> + <ipxact:value>c_m_cnt_in_src_ph_mux_clk</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_c_cnt_in_src3" type="string"> + <ipxact:name>gui_c_cnt_in_src3</ipxact:name> + <ipxact:displayName></ipxact:displayName> + <ipxact:value>c_m_cnt_in_src_ph_mux_clk</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_c_cnt_in_src4" type="string"> + <ipxact:name>gui_c_cnt_in_src4</ipxact:name> + <ipxact:displayName></ipxact:displayName> + <ipxact:value>c_m_cnt_in_src_ph_mux_clk</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_c_cnt_in_src5" type="string"> + <ipxact:name>gui_c_cnt_in_src5</ipxact:name> + <ipxact:displayName></ipxact:displayName> + <ipxact:value>c_m_cnt_in_src_ph_mux_clk</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_c_cnt_in_src6" type="string"> + <ipxact:name>gui_c_cnt_in_src6</ipxact:name> + <ipxact:displayName></ipxact:displayName> + <ipxact:value>c_m_cnt_in_src_ph_mux_clk</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_c_cnt_in_src7" type="string"> + <ipxact:name>gui_c_cnt_in_src7</ipxact:name> + <ipxact:displayName></ipxact:displayName> + <ipxact:value>c_m_cnt_in_src_ph_mux_clk</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_c_cnt_in_src8" type="string"> + <ipxact:name>gui_c_cnt_in_src8</ipxact:name> + <ipxact:displayName></ipxact:displayName> + <ipxact:value>c_m_cnt_in_src_ph_mux_clk</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="system_info_device_family" type="string"> + <ipxact:name>system_info_device_family</ipxact:name> + <ipxact:displayName>Device Family</ipxact:displayName> + <ipxact:value>Agilex 3</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="system_info_device_component" type="string"> + <ipxact:name>system_info_device_component</ipxact:name> + <ipxact:displayName>Component</ipxact:displayName> + <ipxact:value>A3CY050BB18AI6S</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="system_info_device_iobank_rev" type="string"> + <ipxact:name>system_info_device_iobank_rev</ipxact:name> + <ipxact:displayName>IO Bank Revision</ipxact:displayName> + <ipxact:value></ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="system_part_trait_speed_grade" type="string"> + <ipxact:name>system_part_trait_speed_grade</ipxact:name> + <ipxact:displayName>Speed Grade Trait</ipxact:displayName> + <ipxact:value>6</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="system_part_trait_iobank_rev" type="string"> + <ipxact:name>system_part_trait_iobank_rev</ipxact:name> + <ipxact:displayName>IO Bank Revision Trait</ipxact:displayName> + <ipxact:value>IO96B_REVB1</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="system_info_device_speed_grade" type="string"> + <ipxact:name>system_info_device_speed_grade</ipxact:name> + <ipxact:displayName>Speed Grade</ipxact:displayName> + <ipxact:value>5</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_usr_device_speed_grade" type="string"> + <ipxact:name>gui_usr_device_speed_grade</ipxact:name> + <ipxact:displayName>Speed Grade</ipxact:displayName> + <ipxact:value>1</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_en_reconf" type="bit"> + <ipxact:name>gui_en_reconf</ipxact:name> + <ipxact:displayName>Enable dynamic reconfiguration of PLL</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_en_hvio_reconf" type="bit"> + <ipxact:name>gui_en_hvio_reconf</ipxact:name> + <ipxact:displayName>Enable dynamic reconfiguration of PLL</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_en_iossm_reconf" type="bit"> + <ipxact:name>gui_en_iossm_reconf</ipxact:name> + <ipxact:displayName>Enable dynamic reconfiguration of PLL using Calibration IP</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_user_base_address" type="int"> + <ipxact:name>gui_user_base_address</ipxact:name> + <ipxact:displayName>User base address of PLL for dynamic reconfiguration (0..255)</ipxact:displayName> + <ipxact:value>0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_en_dps_ports" type="bit"> + <ipxact:name>gui_en_dps_ports</ipxact:name> + <ipxact:displayName>Enable access to dynamic phase shift ports</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_pll_mode" type="string"> + <ipxact:name>gui_pll_mode</ipxact:name> + <ipxact:displayName>PLL Mode</ipxact:displayName> + <ipxact:value>Integer-N PLL</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_location_type" type="string"> + <ipxact:name>gui_location_type</ipxact:name> + <ipxact:displayName>IOPLL Type</ipxact:displayName> + <ipxact:value>I/O Bank</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_use_logical" type="bit"> + <ipxact:name>gui_use_logical</ipxact:name> + <ipxact:displayName>Use logical PLL</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_reference_clock_frequency" type="real"> + <ipxact:name>gui_reference_clock_frequency</ipxact:name> + <ipxact:displayName>Reference Clock Frequency</ipxact:displayName> + <ipxact:value>25.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_reference_clock_frequency_ps" type="real"> + <ipxact:name>gui_reference_clock_frequency_ps</ipxact:name> + <ipxact:displayName>Reference Clock Frequency</ipxact:displayName> + <ipxact:value>40000.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_use_coreclk" type="bit"> + <ipxact:name>gui_use_coreclk</ipxact:name> + <ipxact:displayName>Refclk source is global clock</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_refclk_might_change" type="bit"> + <ipxact:name>gui_refclk_might_change</ipxact:name> + <ipxact:displayName>My reference clock frequency might change</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_fractional_cout" type="int"> + <ipxact:name>gui_fractional_cout</ipxact:name> + <ipxact:displayName>Fractional carry out</ipxact:displayName> + <ipxact:value>24</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_prot_mode" type="string"> + <ipxact:name>gui_prot_mode</ipxact:name> + <ipxact:displayName>prot_mode</ipxact:displayName> + <ipxact:value>UNUSED</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_dsm_out_sel" type="string"> + <ipxact:name>gui_dsm_out_sel</ipxact:name> + <ipxact:displayName>DSM Order</ipxact:displayName> + <ipxact:value>1st_order</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_use_locked" type="bit"> + <ipxact:name>gui_use_locked</ipxact:name> + <ipxact:displayName>Enable 'locked' output port</ipxact:displayName> + <ipxact:value>true</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_set_locked_as_reset" type="bit"> + <ipxact:name>gui_set_locked_as_reset</ipxact:name> + <ipxact:displayName>Set 'locked' as reset interface</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_en_adv_params" type="bit"> + <ipxact:name>gui_en_adv_params</ipxact:name> + <ipxact:displayName>Enable physical output clock parameters</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_use_fractional_division" type="bit"> + <ipxact:name>gui_use_fractional_division</ipxact:name> + <ipxact:displayName>Enable fractional division</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_pll_bandwidth_preset" type="string"> + <ipxact:name>gui_pll_bandwidth_preset</ipxact:name> + <ipxact:displayName>PLL Bandwidth Preset</ipxact:displayName> + <ipxact:value>Low</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_lock_setting" type="string"> + <ipxact:name>gui_lock_setting</ipxact:name> + <ipxact:displayName>Lock Threshold Setting</ipxact:displayName> + <ipxact:value>Low Lock Time</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_pll_auto_reset" type="bit"> + <ipxact:name>gui_pll_auto_reset</ipxact:name> + <ipxact:displayName>PLL Auto Reset</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_en_lvds_ports" type="string"> + <ipxact:name>gui_en_lvds_ports</ipxact:name> + <ipxact:displayName>Access to PLL LVDS_CLK/LOADEN output port</ipxact:displayName> + <ipxact:value>Disabled</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_en_periphery_ports" type="bit"> + <ipxact:name>gui_en_periphery_ports</ipxact:name> + <ipxact:displayName>Enable access to I/O Bank clock ports</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_operation_mode" type="string"> + <ipxact:name>gui_operation_mode</ipxact:name> + <ipxact:displayName>Compensation Mode</ipxact:displayName> + <ipxact:value>direct</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_feedback_clock" type="string"> + <ipxact:name>gui_feedback_clock</ipxact:name> + <ipxact:displayName>Feedback Clock</ipxact:displayName> + <ipxact:value>Global Clock</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_clock_to_compensate" type="int"> + <ipxact:name>gui_clock_to_compensate</ipxact:name> + <ipxact:displayName>Compensated Outclk</ipxact:displayName> + <ipxact:value>0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_use_NDFB_modes" type="bit"> + <ipxact:name>gui_use_NDFB_modes</ipxact:name> + <ipxact:displayName>Use Nondedicated Feedback Path</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_refclk_switch" type="bit"> + <ipxact:name>gui_refclk_switch</ipxact:name> + <ipxact:displayName>Create a second input clock signal 'refclk1'</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_refclk1_frequency" type="real"> + <ipxact:name>gui_refclk1_frequency</ipxact:name> + <ipxact:displayName>Second Reference Clock Frequency</ipxact:displayName> + <ipxact:value>100.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_en_phout_ports" type="bit"> + <ipxact:name>gui_en_phout_ports</ipxact:name> + <ipxact:displayName>Enable access to PLL DPA output port</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_phout_division" type="int"> + <ipxact:name>gui_phout_division</ipxact:name> + <ipxact:displayName>PLL DPA output division</ipxact:displayName> + <ipxact:value>1</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_en_extclkout_ports" type="bit"> + <ipxact:name>gui_en_extclkout_ports</ipxact:name> + <ipxact:displayName>Enable access to PLL external clock output port</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_number_of_clocks" type="int"> + <ipxact:name>gui_number_of_clocks</ipxact:name> + <ipxact:displayName>Number Of Clocks</ipxact:displayName> + <ipxact:value>2</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_multiply_factor" type="int"> + <ipxact:name>gui_multiply_factor</ipxact:name> + <ipxact:displayName>Multiply Factor (M-Counter)</ipxact:displayName> + <ipxact:value>6</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_multiply_fraction" type="int"> + <ipxact:name>gui_multiply_fraction</ipxact:name> + <ipxact:displayName>Multiply Factor (Fraction)</ipxact:displayName> + <ipxact:value>0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_use_slvs_refclk" type="bit"> + <ipxact:name>gui_use_slvs_refclk</ipxact:name> + <ipxact:displayName>Use SLVS400 for the PLL reference clock</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_use_slvs_refclk1" type="bit"> + <ipxact:name>gui_use_slvs_refclk1</ipxact:name> + <ipxact:displayName>Use SLVS400 for the second PLL reference clock</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_divide_factor_n" type="int"> + <ipxact:name>gui_divide_factor_n</ipxact:name> + <ipxact:displayName>Divide Factor (N-Counter)</ipxact:displayName> + <ipxact:value>1</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_frac_multiply_factor" type="longint"> + <ipxact:name>gui_frac_multiply_factor</ipxact:name> + <ipxact:displayName>Fractional Multiply Factor (K)</ipxact:displayName> + <ipxact:value>0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_fix_vco_frequency" type="bit"> + <ipxact:name>gui_fix_vco_frequency</ipxact:name> + <ipxact:displayName>Specify VCO frequency</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_fixed_vco_frequency" type="real"> + <ipxact:name>gui_fixed_vco_frequency</ipxact:name> + <ipxact:displayName>Desired VCO Frequency</ipxact:displayName> + <ipxact:value>600.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_fixed_vco_frequency_ps" type="real"> + <ipxact:name>gui_fixed_vco_frequency_ps</ipxact:name> + <ipxact:displayName>Desired VCO Frequency</ipxact:displayName> + <ipxact:value>1667.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_vco_frequency" type="string"> + <ipxact:name>gui_vco_frequency</ipxact:name> + <ipxact:displayName>Actual VCO Frequency</ipxact:displayName> + <ipxact:value>600.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_enable_output_counter_cascading" type="bit"> + <ipxact:name>gui_enable_output_counter_cascading</ipxact:name> + <ipxact:displayName>Enable output counter cascading</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_mif_gen_options" type="string"> + <ipxact:name>gui_mif_gen_options</ipxact:name> + <ipxact:displayName>MIF Generation Options</ipxact:displayName> + <ipxact:value>Generate New MIF File</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_new_mif_file_path" type="string"> + <ipxact:name>gui_new_mif_file_path</ipxact:name> + <ipxact:displayName>Path to New MIF file</ipxact:displayName> + <ipxact:value>~/pll.mif</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_existing_mif_file_path" type="string"> + <ipxact:name>gui_existing_mif_file_path</ipxact:name> + <ipxact:displayName>Path to Existing MIF file</ipxact:displayName> + <ipxact:value>~/pll.mif</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_mif_config_name" type="string"> + <ipxact:name>gui_mif_config_name</ipxact:name> + <ipxact:displayName>Name of Current Configuration</ipxact:displayName> + <ipxact:value>unnamed</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_active_clk" type="bit"> + <ipxact:name>gui_active_clk</ipxact:name> + <ipxact:displayName>Create an 'active_clk' signal to indicate the input clock in use</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_clk_bad" type="bit"> + <ipxact:name>gui_clk_bad</ipxact:name> + <ipxact:displayName>Create a 'clkbad' signal for each of the input clocks</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_switchover_mode" type="string"> + <ipxact:name>gui_switchover_mode</ipxact:name> + <ipxact:displayName>Switchover Mode</ipxact:displayName> + <ipxact:value>Automatic Switchover</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_switchover_delay" type="int"> + <ipxact:name>gui_switchover_delay</ipxact:name> + <ipxact:displayName>Switchover Delay</ipxact:displayName> + <ipxact:value>0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_enable_cascade_out" type="bit"> + <ipxact:name>gui_enable_cascade_out</ipxact:name> + <ipxact:displayName>Create a 'cascade_out' signal to connect to a downstream PLL</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_cascade_outclk_index" type="string"> + <ipxact:name>gui_cascade_outclk_index</ipxact:name> + <ipxact:displayName>cascade_out source</ipxact:displayName> + <ipxact:value>5</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_enable_cascade_in" type="bit"> + <ipxact:name>gui_enable_cascade_in</ipxact:name> + <ipxact:displayName>Create an 'adjpllin' (cascade in) signal to connect to an upstream PLL through IO Column Cascading</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_enable_permit_cal" type="bit"> + <ipxact:name>gui_enable_permit_cal</ipxact:name> + <ipxact:displayName>Connect to an upstream PLL through Core Clock Network Cascading (create a permit_cal input signal)</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_enable_upstream_out_clk" type="bit"> + <ipxact:name>gui_enable_upstream_out_clk</ipxact:name> + <ipxact:displayName>Connect outclk to a downstream PLL through Core Clock Network Cascading</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_pll_cascading_mode" type="string"> + <ipxact:name>gui_pll_cascading_mode</ipxact:name> + <ipxact:displayName>Connection Signal Type to Upstream PLL</ipxact:displayName> + <ipxact:value>adjpllin</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_enable_mif_dps" type="bit"> + <ipxact:name>gui_enable_mif_dps</ipxact:name> + <ipxact:displayName>Enable Dynamic Phase Shift for MIF streaming</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_dps_cntr" type="string"> + <ipxact:name>gui_dps_cntr</ipxact:name> + <ipxact:displayName>DPS Counter Selection</ipxact:displayName> + <ipxact:value>C0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_dps_num" type="int"> + <ipxact:name>gui_dps_num</ipxact:name> + <ipxact:displayName>Number of Dynamic Phase Shifts</ipxact:displayName> + <ipxact:value>1</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_dps_dir" type="string"> + <ipxact:name>gui_dps_dir</ipxact:name> + <ipxact:displayName>Dynamic Phase Shift Direction</ipxact:displayName> + <ipxact:value>Positive</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_extclkout_0_source" type="string"> + <ipxact:name>gui_extclkout_0_source</ipxact:name> + <ipxact:displayName>extclk_out[0] source</ipxact:displayName> + <ipxact:value>C0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_extclkout_1_source" type="string"> + <ipxact:name>gui_extclkout_1_source</ipxact:name> + <ipxact:displayName>extclk_out[1] source</ipxact:displayName> + <ipxact:value>C0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_extclkout_source" type="string"> + <ipxact:name>gui_extclkout_source</ipxact:name> + <ipxact:displayName>extclk_out source</ipxact:displayName> + <ipxact:value>C0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_clock_name_global" type="bit"> + <ipxact:name>gui_clock_name_global</ipxact:name> + <ipxact:displayName>Give clocks global names</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_clock_name_instantiation" type="bit"> + <ipxact:name>gui_clock_name_instantiation</ipxact:name> + <ipxact:displayName>Use clock names as ports in instantiation</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_clock_name_string0" type="string"> + <ipxact:name>gui_clock_name_string0</ipxact:name> + <ipxact:displayName>Clock Name</ipxact:displayName> + <ipxact:value>outclk0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_clock_name_string1" type="string"> + <ipxact:name>gui_clock_name_string1</ipxact:name> + <ipxact:displayName>Clock Name</ipxact:displayName> + <ipxact:value>outclk1</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_clock_name_string2" type="string"> + <ipxact:name>gui_clock_name_string2</ipxact:name> + <ipxact:displayName>Clock Name</ipxact:displayName> + <ipxact:value>outclk2</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_clock_name_string3" type="string"> + <ipxact:name>gui_clock_name_string3</ipxact:name> + <ipxact:displayName>Clock Name</ipxact:displayName> + <ipxact:value>outclk3</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_clock_name_string4" type="string"> + <ipxact:name>gui_clock_name_string4</ipxact:name> + <ipxact:displayName>Clock Name</ipxact:displayName> + <ipxact:value>outclk4</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_clock_name_string5" type="string"> + <ipxact:name>gui_clock_name_string5</ipxact:name> + <ipxact:displayName>Clock Name</ipxact:displayName> + <ipxact:value>outclk5</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_clock_name_string6" type="string"> + <ipxact:name>gui_clock_name_string6</ipxact:name> + <ipxact:displayName>Clock Name</ipxact:displayName> + <ipxact:value>outclk6</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_clock_name_string7" type="string"> + <ipxact:name>gui_clock_name_string7</ipxact:name> + <ipxact:displayName>Clock Name</ipxact:displayName> + <ipxact:value>outclk7</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_clock_name_string8" type="string"> + <ipxact:name>gui_clock_name_string8</ipxact:name> + <ipxact:displayName>Clock Name</ipxact:displayName> + <ipxact:value>outclk8</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_clock_name_string9" type="string"> + <ipxact:name>gui_clock_name_string9</ipxact:name> + <ipxact:displayName>Clock Name</ipxact:displayName> + <ipxact:value>outclk9</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_clock_name_string10" type="string"> + <ipxact:name>gui_clock_name_string10</ipxact:name> + <ipxact:displayName>Clock Name</ipxact:displayName> + <ipxact:value>outclk10</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_clock_name_string11" type="string"> + <ipxact:name>gui_clock_name_string11</ipxact:name> + <ipxact:displayName>Clock Name</ipxact:displayName> + <ipxact:value>outclk11</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_clock_name_string12" type="string"> + <ipxact:name>gui_clock_name_string12</ipxact:name> + <ipxact:displayName>Clock Name</ipxact:displayName> + <ipxact:value>outclk12</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_clock_name_string13" type="string"> + <ipxact:name>gui_clock_name_string13</ipxact:name> + <ipxact:displayName>Clock Name</ipxact:displayName> + <ipxact:value>outclk13</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_clock_name_string14" type="string"> + <ipxact:name>gui_clock_name_string14</ipxact:name> + <ipxact:displayName>Clock Name</ipxact:displayName> + <ipxact:value>outclk14</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_clock_name_string15" type="string"> + <ipxact:name>gui_clock_name_string15</ipxact:name> + <ipxact:displayName>Clock Name</ipxact:displayName> + <ipxact:value>outclk15</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_clock_name_string16" type="string"> + <ipxact:name>gui_clock_name_string16</ipxact:name> + <ipxact:displayName>Clock Name</ipxact:displayName> + <ipxact:value>outclk16</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_clock_name_string17" type="string"> + <ipxact:name>gui_clock_name_string17</ipxact:name> + <ipxact:displayName>Clock Name</ipxact:displayName> + <ipxact:value>outclk17</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_divide_factor_c0" type="int"> + <ipxact:name>gui_divide_factor_c0</ipxact:name> + <ipxact:displayName>Divide Factor (C-Counter)</ipxact:displayName> + <ipxact:value>6</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_divide_factor_c1" type="int"> + <ipxact:name>gui_divide_factor_c1</ipxact:name> + <ipxact:displayName>Divide Factor (C-Counter)</ipxact:displayName> + <ipxact:value>6</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_divide_factor_c2" type="int"> + <ipxact:name>gui_divide_factor_c2</ipxact:name> + <ipxact:displayName>Divide Factor (C-Counter)</ipxact:displayName> + <ipxact:value>6</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_divide_factor_c3" type="int"> + <ipxact:name>gui_divide_factor_c3</ipxact:name> + <ipxact:displayName>Divide Factor (C-Counter)</ipxact:displayName> + <ipxact:value>6</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_divide_factor_c4" type="int"> + <ipxact:name>gui_divide_factor_c4</ipxact:name> + <ipxact:displayName>Divide Factor (C-Counter)</ipxact:displayName> + <ipxact:value>6</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_divide_factor_c5" type="int"> + <ipxact:name>gui_divide_factor_c5</ipxact:name> + <ipxact:displayName>Divide Factor (C-Counter)</ipxact:displayName> + <ipxact:value>6</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_divide_factor_c6" type="int"> + <ipxact:name>gui_divide_factor_c6</ipxact:name> + <ipxact:displayName>Divide Factor (C-Counter)</ipxact:displayName> + <ipxact:value>6</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_divide_factor_c7" type="int"> + <ipxact:name>gui_divide_factor_c7</ipxact:name> + <ipxact:displayName>Divide Factor (C-Counter)</ipxact:displayName> + <ipxact:value>6</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_divide_factor_c8" type="int"> + <ipxact:name>gui_divide_factor_c8</ipxact:name> + <ipxact:displayName>Divide Factor (C-Counter)</ipxact:displayName> + <ipxact:value>6</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_divide_factor_c9" type="int"> + <ipxact:name>gui_divide_factor_c9</ipxact:name> + <ipxact:displayName>Divide Factor (C-Counter)</ipxact:displayName> + <ipxact:value>6</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_divide_factor_c10" type="int"> + <ipxact:name>gui_divide_factor_c10</ipxact:name> + <ipxact:displayName>Divide Factor (C-Counter)</ipxact:displayName> + <ipxact:value>6</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_divide_factor_c11" type="int"> + <ipxact:name>gui_divide_factor_c11</ipxact:name> + <ipxact:displayName>Divide Factor (C-Counter)</ipxact:displayName> + <ipxact:value>6</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_divide_factor_c12" type="int"> + <ipxact:name>gui_divide_factor_c12</ipxact:name> + <ipxact:displayName>Divide Factor (C-Counter)</ipxact:displayName> + <ipxact:value>6</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_divide_factor_c13" type="int"> + <ipxact:name>gui_divide_factor_c13</ipxact:name> + <ipxact:displayName>Divide Factor (C-Counter)</ipxact:displayName> + <ipxact:value>6</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_divide_factor_c14" type="int"> + <ipxact:name>gui_divide_factor_c14</ipxact:name> + <ipxact:displayName>Divide Factor (C-Counter)</ipxact:displayName> + <ipxact:value>6</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_divide_factor_c15" type="int"> + <ipxact:name>gui_divide_factor_c15</ipxact:name> + <ipxact:displayName>Divide Factor (C-Counter)</ipxact:displayName> + <ipxact:value>6</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_divide_factor_c16" type="int"> + <ipxact:name>gui_divide_factor_c16</ipxact:name> + <ipxact:displayName>Divide Factor (C-Counter)</ipxact:displayName> + <ipxact:value>6</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_divide_factor_c17" type="int"> + <ipxact:name>gui_divide_factor_c17</ipxact:name> + <ipxact:displayName>Divide Factor (C-Counter)</ipxact:displayName> + <ipxact:value>6</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_cascade_counter0" type="bit"> + <ipxact:name>gui_cascade_counter0</ipxact:name> + <ipxact:displayName>Make this a cascade counter</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_cascade_counter1" type="bit"> + <ipxact:name>gui_cascade_counter1</ipxact:name> + <ipxact:displayName>Make this a cascade counter</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_cascade_counter2" type="bit"> + <ipxact:name>gui_cascade_counter2</ipxact:name> + <ipxact:displayName>Make this a cascade counter</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_cascade_counter3" type="bit"> + <ipxact:name>gui_cascade_counter3</ipxact:name> + <ipxact:displayName>Make this a cascade counter</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_cascade_counter4" type="bit"> + <ipxact:name>gui_cascade_counter4</ipxact:name> + <ipxact:displayName>Make this a cascade counter</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_cascade_counter5" type="bit"> + <ipxact:name>gui_cascade_counter5</ipxact:name> + <ipxact:displayName>Make this a cascade counter</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_cascade_counter6" type="bit"> + <ipxact:name>gui_cascade_counter6</ipxact:name> + <ipxact:displayName>Make this a cascade counter</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_cascade_counter7" type="bit"> + <ipxact:name>gui_cascade_counter7</ipxact:name> + <ipxact:displayName>Make this a cascade counter</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_cascade_counter8" type="bit"> + <ipxact:name>gui_cascade_counter8</ipxact:name> + <ipxact:displayName>Make this a cascade counter</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_cascade_counter9" type="bit"> + <ipxact:name>gui_cascade_counter9</ipxact:name> + <ipxact:displayName>Make this a cascade counter</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_cascade_counter10" type="bit"> + <ipxact:name>gui_cascade_counter10</ipxact:name> + <ipxact:displayName>Make this a cascade counter</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_cascade_counter11" type="bit"> + <ipxact:name>gui_cascade_counter11</ipxact:name> + <ipxact:displayName>Make this a cascade counter</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_cascade_counter12" type="bit"> + <ipxact:name>gui_cascade_counter12</ipxact:name> + <ipxact:displayName>Make this a cascade counter</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_cascade_counter13" type="bit"> + <ipxact:name>gui_cascade_counter13</ipxact:name> + <ipxact:displayName>Make this a cascade counter</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_cascade_counter14" type="bit"> + <ipxact:name>gui_cascade_counter14</ipxact:name> + <ipxact:displayName>Make this a cascade counter</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_cascade_counter15" type="bit"> + <ipxact:name>gui_cascade_counter15</ipxact:name> + <ipxact:displayName>Make this a cascade counter</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_cascade_counter16" type="bit"> + <ipxact:name>gui_cascade_counter16</ipxact:name> + <ipxact:displayName>Make this a cascade counter</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_cascade_counter17" type="bit"> + <ipxact:name>gui_cascade_counter17</ipxact:name> + <ipxact:displayName>Make this a cascade counter</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_output_clock_frequency0" type="real"> + <ipxact:name>gui_output_clock_frequency0</ipxact:name> + <ipxact:displayName>Desired Frequency</ipxact:displayName> + <ipxact:value>25.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_output_clock_frequency1" type="real"> + <ipxact:name>gui_output_clock_frequency1</ipxact:name> + <ipxact:displayName>Desired Frequency</ipxact:displayName> + <ipxact:value>125.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_output_clock_frequency2" type="real"> + <ipxact:name>gui_output_clock_frequency2</ipxact:name> + <ipxact:displayName>Desired Frequency</ipxact:displayName> + <ipxact:value>100.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_output_clock_frequency3" type="real"> + <ipxact:name>gui_output_clock_frequency3</ipxact:name> + <ipxact:displayName>Desired Frequency</ipxact:displayName> + <ipxact:value>100.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_output_clock_frequency4" type="real"> + <ipxact:name>gui_output_clock_frequency4</ipxact:name> + <ipxact:displayName>Desired Frequency</ipxact:displayName> + <ipxact:value>100.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_output_clock_frequency5" type="real"> + <ipxact:name>gui_output_clock_frequency5</ipxact:name> + <ipxact:displayName>Desired Frequency</ipxact:displayName> + <ipxact:value>100.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_output_clock_frequency6" type="real"> + <ipxact:name>gui_output_clock_frequency6</ipxact:name> + <ipxact:displayName>Desired Frequency</ipxact:displayName> + <ipxact:value>100.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_output_clock_frequency7" type="real"> + <ipxact:name>gui_output_clock_frequency7</ipxact:name> + <ipxact:displayName>Desired Frequency</ipxact:displayName> + <ipxact:value>100.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_output_clock_frequency8" type="real"> + <ipxact:name>gui_output_clock_frequency8</ipxact:name> + <ipxact:displayName>Desired Frequency</ipxact:displayName> + <ipxact:value>100.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_output_clock_frequency9" type="real"> + <ipxact:name>gui_output_clock_frequency9</ipxact:name> + <ipxact:displayName>Desired Frequency</ipxact:displayName> + <ipxact:value>100.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_output_clock_frequency10" type="real"> + <ipxact:name>gui_output_clock_frequency10</ipxact:name> + <ipxact:displayName>Desired Frequency</ipxact:displayName> + <ipxact:value>100.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_output_clock_frequency11" type="real"> + <ipxact:name>gui_output_clock_frequency11</ipxact:name> + <ipxact:displayName>Desired Frequency</ipxact:displayName> + <ipxact:value>100.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_output_clock_frequency12" type="real"> + <ipxact:name>gui_output_clock_frequency12</ipxact:name> + <ipxact:displayName>Desired Frequency</ipxact:displayName> + <ipxact:value>100.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_output_clock_frequency13" type="real"> + <ipxact:name>gui_output_clock_frequency13</ipxact:name> + <ipxact:displayName>Desired Frequency</ipxact:displayName> + <ipxact:value>100.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_output_clock_frequency14" type="real"> + <ipxact:name>gui_output_clock_frequency14</ipxact:name> + <ipxact:displayName>Desired Frequency</ipxact:displayName> + <ipxact:value>100.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_output_clock_frequency15" type="real"> + <ipxact:name>gui_output_clock_frequency15</ipxact:name> + <ipxact:displayName>Desired Frequency</ipxact:displayName> + <ipxact:value>100.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_output_clock_frequency16" type="real"> + <ipxact:name>gui_output_clock_frequency16</ipxact:name> + <ipxact:displayName>Desired Frequency</ipxact:displayName> + <ipxact:value>100.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_output_clock_frequency17" type="real"> + <ipxact:name>gui_output_clock_frequency17</ipxact:name> + <ipxact:displayName>Desired Frequency</ipxact:displayName> + <ipxact:value>100.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_output_clock_frequency_ps0" type="real"> + <ipxact:name>gui_output_clock_frequency_ps0</ipxact:name> + <ipxact:displayName>Desired Frequency</ipxact:displayName> + <ipxact:value>40000.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_output_clock_frequency_ps1" type="real"> + <ipxact:name>gui_output_clock_frequency_ps1</ipxact:name> + <ipxact:displayName>Desired Frequency</ipxact:displayName> + <ipxact:value>8000.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_output_clock_frequency_ps2" type="real"> + <ipxact:name>gui_output_clock_frequency_ps2</ipxact:name> + <ipxact:displayName>Desired Frequency</ipxact:displayName> + <ipxact:value>10000.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_output_clock_frequency_ps3" type="real"> + <ipxact:name>gui_output_clock_frequency_ps3</ipxact:name> + <ipxact:displayName>Desired Frequency</ipxact:displayName> + <ipxact:value>10000.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_output_clock_frequency_ps4" type="real"> + <ipxact:name>gui_output_clock_frequency_ps4</ipxact:name> + <ipxact:displayName>Desired Frequency</ipxact:displayName> + <ipxact:value>10000.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_output_clock_frequency_ps5" type="real"> + <ipxact:name>gui_output_clock_frequency_ps5</ipxact:name> + <ipxact:displayName>Desired Frequency</ipxact:displayName> + <ipxact:value>10000.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_output_clock_frequency_ps6" type="real"> + <ipxact:name>gui_output_clock_frequency_ps6</ipxact:name> + <ipxact:displayName>Desired Frequency</ipxact:displayName> + <ipxact:value>10000.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_output_clock_frequency_ps7" type="real"> + <ipxact:name>gui_output_clock_frequency_ps7</ipxact:name> + <ipxact:displayName>Desired Frequency</ipxact:displayName> + <ipxact:value>10000.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_output_clock_frequency_ps8" type="real"> + <ipxact:name>gui_output_clock_frequency_ps8</ipxact:name> + <ipxact:displayName>Desired Frequency</ipxact:displayName> + <ipxact:value>10000.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_output_clock_frequency_ps9" type="real"> + <ipxact:name>gui_output_clock_frequency_ps9</ipxact:name> + <ipxact:displayName>Desired Frequency</ipxact:displayName> + <ipxact:value>10000.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_output_clock_frequency_ps10" type="real"> + <ipxact:name>gui_output_clock_frequency_ps10</ipxact:name> + <ipxact:displayName>Desired Frequency</ipxact:displayName> + <ipxact:value>10000.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_output_clock_frequency_ps11" type="real"> + <ipxact:name>gui_output_clock_frequency_ps11</ipxact:name> + <ipxact:displayName>Desired Frequency</ipxact:displayName> + <ipxact:value>10000.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_output_clock_frequency_ps12" type="real"> + <ipxact:name>gui_output_clock_frequency_ps12</ipxact:name> + <ipxact:displayName>Desired Frequency</ipxact:displayName> + <ipxact:value>10000.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_output_clock_frequency_ps13" type="real"> + <ipxact:name>gui_output_clock_frequency_ps13</ipxact:name> + <ipxact:displayName>Desired Frequency</ipxact:displayName> + <ipxact:value>10000.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_output_clock_frequency_ps14" type="real"> + <ipxact:name>gui_output_clock_frequency_ps14</ipxact:name> + <ipxact:displayName>Desired Frequency</ipxact:displayName> + <ipxact:value>10000.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_output_clock_frequency_ps15" type="real"> + <ipxact:name>gui_output_clock_frequency_ps15</ipxact:name> + <ipxact:displayName>Desired Frequency</ipxact:displayName> + <ipxact:value>10000.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_output_clock_frequency_ps16" type="real"> + <ipxact:name>gui_output_clock_frequency_ps16</ipxact:name> + <ipxact:displayName>Desired Frequency</ipxact:displayName> + <ipxact:value>10000.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_output_clock_frequency_ps17" type="real"> + <ipxact:name>gui_output_clock_frequency_ps17</ipxact:name> + <ipxact:displayName>Desired Frequency</ipxact:displayName> + <ipxact:value>10000.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_ps_units0" type="string"> + <ipxact:name>gui_ps_units0</ipxact:name> + <ipxact:displayName>Phase Shift Units</ipxact:displayName> + <ipxact:value>ps</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_ps_units1" type="string"> + <ipxact:name>gui_ps_units1</ipxact:name> + <ipxact:displayName>Phase Shift Units</ipxact:displayName> + <ipxact:value>ps</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_ps_units2" type="string"> + <ipxact:name>gui_ps_units2</ipxact:name> + <ipxact:displayName>Phase Shift Units</ipxact:displayName> + <ipxact:value>ps</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_ps_units3" type="string"> + <ipxact:name>gui_ps_units3</ipxact:name> + <ipxact:displayName>Phase Shift Units</ipxact:displayName> + <ipxact:value>ps</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_ps_units4" type="string"> + <ipxact:name>gui_ps_units4</ipxact:name> + <ipxact:displayName>Phase Shift Units</ipxact:displayName> + <ipxact:value>ps</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_ps_units5" type="string"> + <ipxact:name>gui_ps_units5</ipxact:name> + <ipxact:displayName>Phase Shift Units</ipxact:displayName> + <ipxact:value>ps</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_ps_units6" type="string"> + <ipxact:name>gui_ps_units6</ipxact:name> + <ipxact:displayName>Phase Shift Units</ipxact:displayName> + <ipxact:value>ps</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_ps_units7" type="string"> + <ipxact:name>gui_ps_units7</ipxact:name> + <ipxact:displayName>Phase Shift Units</ipxact:displayName> + <ipxact:value>ps</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_ps_units8" type="string"> + <ipxact:name>gui_ps_units8</ipxact:name> + <ipxact:displayName>Phase Shift Units</ipxact:displayName> + <ipxact:value>ps</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_ps_units9" type="string"> + <ipxact:name>gui_ps_units9</ipxact:name> + <ipxact:displayName>Phase Shift Units</ipxact:displayName> + <ipxact:value>ps</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_ps_units10" type="string"> + <ipxact:name>gui_ps_units10</ipxact:name> + <ipxact:displayName>Phase Shift Units</ipxact:displayName> + <ipxact:value>ps</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_ps_units11" type="string"> + <ipxact:name>gui_ps_units11</ipxact:name> + <ipxact:displayName>Phase Shift Units</ipxact:displayName> + <ipxact:value>ps</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_ps_units12" type="string"> + <ipxact:name>gui_ps_units12</ipxact:name> + <ipxact:displayName>Phase Shift Units</ipxact:displayName> + <ipxact:value>ps</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_ps_units13" type="string"> + <ipxact:name>gui_ps_units13</ipxact:name> + <ipxact:displayName>Phase Shift Units</ipxact:displayName> + <ipxact:value>ps</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_ps_units14" type="string"> + <ipxact:name>gui_ps_units14</ipxact:name> + <ipxact:displayName>Phase Shift Units</ipxact:displayName> + <ipxact:value>ps</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_ps_units15" type="string"> + <ipxact:name>gui_ps_units15</ipxact:name> + <ipxact:displayName>Phase Shift Units</ipxact:displayName> + <ipxact:value>ps</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_ps_units16" type="string"> + <ipxact:name>gui_ps_units16</ipxact:name> + <ipxact:displayName>Phase Shift Units</ipxact:displayName> + <ipxact:value>ps</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_ps_units17" type="string"> + <ipxact:name>gui_ps_units17</ipxact:name> + <ipxact:displayName>Phase Shift Units</ipxact:displayName> + <ipxact:value>ps</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_phase_shift0" type="real"> + <ipxact:name>gui_phase_shift0</ipxact:name> + <ipxact:displayName>Desired Phase Shift</ipxact:displayName> + <ipxact:value>0.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_phase_shift1" type="real"> + <ipxact:name>gui_phase_shift1</ipxact:name> + <ipxact:displayName>Desired Phase Shift</ipxact:displayName> + <ipxact:value>0.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_phase_shift2" type="real"> + <ipxact:name>gui_phase_shift2</ipxact:name> + <ipxact:displayName>Desired Phase Shift</ipxact:displayName> + <ipxact:value>0.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_phase_shift3" type="real"> + <ipxact:name>gui_phase_shift3</ipxact:name> + <ipxact:displayName>Desired Phase Shift</ipxact:displayName> + <ipxact:value>0.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_phase_shift4" type="real"> + <ipxact:name>gui_phase_shift4</ipxact:name> + <ipxact:displayName>Desired Phase Shift</ipxact:displayName> + <ipxact:value>0.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_phase_shift5" type="real"> + <ipxact:name>gui_phase_shift5</ipxact:name> + <ipxact:displayName>Desired Phase Shift</ipxact:displayName> + <ipxact:value>0.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_phase_shift6" type="real"> + <ipxact:name>gui_phase_shift6</ipxact:name> + <ipxact:displayName>Desired Phase Shift</ipxact:displayName> + <ipxact:value>0.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_phase_shift7" type="real"> + <ipxact:name>gui_phase_shift7</ipxact:name> + <ipxact:displayName>Desired Phase Shift</ipxact:displayName> + <ipxact:value>0.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_phase_shift8" type="real"> + <ipxact:name>gui_phase_shift8</ipxact:name> + <ipxact:displayName>Desired Phase Shift</ipxact:displayName> + <ipxact:value>0.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_phase_shift9" type="real"> + <ipxact:name>gui_phase_shift9</ipxact:name> + <ipxact:displayName>Desired Phase Shift</ipxact:displayName> + <ipxact:value>0.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_phase_shift10" type="real"> + <ipxact:name>gui_phase_shift10</ipxact:name> + <ipxact:displayName>Desired Phase Shift</ipxact:displayName> + <ipxact:value>0.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_phase_shift11" type="real"> + <ipxact:name>gui_phase_shift11</ipxact:name> + <ipxact:displayName>Desired Phase Shift</ipxact:displayName> + <ipxact:value>0.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_phase_shift12" type="real"> + <ipxact:name>gui_phase_shift12</ipxact:name> + <ipxact:displayName>Desired Phase Shift</ipxact:displayName> + <ipxact:value>0.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_phase_shift13" type="real"> + <ipxact:name>gui_phase_shift13</ipxact:name> + <ipxact:displayName>Desired Phase Shift</ipxact:displayName> + <ipxact:value>0.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_phase_shift14" type="real"> + <ipxact:name>gui_phase_shift14</ipxact:name> + <ipxact:displayName>Desired Phase Shift</ipxact:displayName> + <ipxact:value>0.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_phase_shift15" type="real"> + <ipxact:name>gui_phase_shift15</ipxact:name> + <ipxact:displayName>Desired Phase Shift</ipxact:displayName> + <ipxact:value>0.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_phase_shift16" type="real"> + <ipxact:name>gui_phase_shift16</ipxact:name> + <ipxact:displayName>Desired Phase Shift</ipxact:displayName> + <ipxact:value>0.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_phase_shift17" type="real"> + <ipxact:name>gui_phase_shift17</ipxact:name> + <ipxact:displayName>Desired Phase Shift</ipxact:displayName> + <ipxact:value>0.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_phase_shift_deg0" type="real"> + <ipxact:name>gui_phase_shift_deg0</ipxact:name> + <ipxact:displayName>Desired Phase Shift</ipxact:displayName> + <ipxact:value>0.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_phase_shift_deg1" type="real"> + <ipxact:name>gui_phase_shift_deg1</ipxact:name> + <ipxact:displayName>Desired Phase Shift</ipxact:displayName> + <ipxact:value>0.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_phase_shift_deg2" type="real"> + <ipxact:name>gui_phase_shift_deg2</ipxact:name> + <ipxact:displayName>Desired Phase Shift</ipxact:displayName> + <ipxact:value>0.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_phase_shift_deg3" type="real"> + <ipxact:name>gui_phase_shift_deg3</ipxact:name> + <ipxact:displayName>Desired Phase Shift</ipxact:displayName> + <ipxact:value>0.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_phase_shift_deg4" type="real"> + <ipxact:name>gui_phase_shift_deg4</ipxact:name> + <ipxact:displayName>Desired Phase Shift</ipxact:displayName> + <ipxact:value>0.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_phase_shift_deg5" type="real"> + <ipxact:name>gui_phase_shift_deg5</ipxact:name> + <ipxact:displayName>Desired Phase Shift</ipxact:displayName> + <ipxact:value>0.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_phase_shift_deg6" type="real"> + <ipxact:name>gui_phase_shift_deg6</ipxact:name> + <ipxact:displayName>Desired Phase Shift</ipxact:displayName> + <ipxact:value>0.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_phase_shift_deg7" type="real"> + <ipxact:name>gui_phase_shift_deg7</ipxact:name> + <ipxact:displayName>Desired Phase Shift</ipxact:displayName> + <ipxact:value>0.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_phase_shift_deg8" type="real"> + <ipxact:name>gui_phase_shift_deg8</ipxact:name> + <ipxact:displayName>Desired Phase Shift</ipxact:displayName> + <ipxact:value>0.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_phase_shift_deg9" type="real"> + <ipxact:name>gui_phase_shift_deg9</ipxact:name> + <ipxact:displayName>Desired Phase Shift</ipxact:displayName> + <ipxact:value>0.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_phase_shift_deg10" type="real"> + <ipxact:name>gui_phase_shift_deg10</ipxact:name> + <ipxact:displayName>Desired Phase Shift</ipxact:displayName> + <ipxact:value>0.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_phase_shift_deg11" type="real"> + <ipxact:name>gui_phase_shift_deg11</ipxact:name> + <ipxact:displayName>Desired Phase Shift</ipxact:displayName> + <ipxact:value>0.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_phase_shift_deg12" type="real"> + <ipxact:name>gui_phase_shift_deg12</ipxact:name> + <ipxact:displayName>Desired Phase Shift</ipxact:displayName> + <ipxact:value>0.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_phase_shift_deg13" type="real"> + <ipxact:name>gui_phase_shift_deg13</ipxact:name> + <ipxact:displayName>Desired Phase Shift</ipxact:displayName> + <ipxact:value>0.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_phase_shift_deg14" type="real"> + <ipxact:name>gui_phase_shift_deg14</ipxact:name> + <ipxact:displayName>Desired Phase Shift</ipxact:displayName> + <ipxact:value>0.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_phase_shift_deg15" type="real"> + <ipxact:name>gui_phase_shift_deg15</ipxact:name> + <ipxact:displayName>Desired Phase Shift</ipxact:displayName> + <ipxact:value>0.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_phase_shift_deg16" type="real"> + <ipxact:name>gui_phase_shift_deg16</ipxact:name> + <ipxact:displayName>Desired Phase Shift</ipxact:displayName> + <ipxact:value>0.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_phase_shift_deg17" type="real"> + <ipxact:name>gui_phase_shift_deg17</ipxact:name> + <ipxact:displayName>Desired Phase Shift</ipxact:displayName> + <ipxact:value>0.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_duty_cycle0" type="real"> + <ipxact:name>gui_duty_cycle0</ipxact:name> + <ipxact:displayName>Desired Duty Cycle</ipxact:displayName> + <ipxact:value>50.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_duty_cycle1" type="real"> + <ipxact:name>gui_duty_cycle1</ipxact:name> + <ipxact:displayName>Desired Duty Cycle</ipxact:displayName> + <ipxact:value>50.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_duty_cycle2" type="real"> + <ipxact:name>gui_duty_cycle2</ipxact:name> + <ipxact:displayName>Desired Duty Cycle</ipxact:displayName> + <ipxact:value>50.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_duty_cycle3" type="real"> + <ipxact:name>gui_duty_cycle3</ipxact:name> + <ipxact:displayName>Desired Duty Cycle</ipxact:displayName> + <ipxact:value>50.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_duty_cycle4" type="real"> + <ipxact:name>gui_duty_cycle4</ipxact:name> + <ipxact:displayName>Desired Duty Cycle</ipxact:displayName> + <ipxact:value>50.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_duty_cycle5" type="real"> + <ipxact:name>gui_duty_cycle5</ipxact:name> + <ipxact:displayName>Desired Duty Cycle</ipxact:displayName> + <ipxact:value>50.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_duty_cycle6" type="real"> + <ipxact:name>gui_duty_cycle6</ipxact:name> + <ipxact:displayName>Desired Duty Cycle</ipxact:displayName> + <ipxact:value>50.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_duty_cycle7" type="real"> + <ipxact:name>gui_duty_cycle7</ipxact:name> + <ipxact:displayName>Desired Duty Cycle</ipxact:displayName> + <ipxact:value>50.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_duty_cycle8" type="real"> + <ipxact:name>gui_duty_cycle8</ipxact:name> + <ipxact:displayName>Desired Duty Cycle</ipxact:displayName> + <ipxact:value>50.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_duty_cycle9" type="real"> + <ipxact:name>gui_duty_cycle9</ipxact:name> + <ipxact:displayName>Desired Duty Cycle</ipxact:displayName> + <ipxact:value>50.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_duty_cycle10" type="real"> + <ipxact:name>gui_duty_cycle10</ipxact:name> + <ipxact:displayName>Desired Duty Cycle</ipxact:displayName> + <ipxact:value>50.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_duty_cycle11" type="real"> + <ipxact:name>gui_duty_cycle11</ipxact:name> + <ipxact:displayName>Desired Duty Cycle</ipxact:displayName> + <ipxact:value>50.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_duty_cycle12" type="real"> + <ipxact:name>gui_duty_cycle12</ipxact:name> + <ipxact:displayName>Desired Duty Cycle</ipxact:displayName> + <ipxact:value>50.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_duty_cycle13" type="real"> + <ipxact:name>gui_duty_cycle13</ipxact:name> + <ipxact:displayName>Desired Duty Cycle</ipxact:displayName> + <ipxact:value>50.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_duty_cycle14" type="real"> + <ipxact:name>gui_duty_cycle14</ipxact:name> + <ipxact:displayName>Desired Duty Cycle</ipxact:displayName> + <ipxact:value>50.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_duty_cycle15" type="real"> + <ipxact:name>gui_duty_cycle15</ipxact:name> + <ipxact:displayName>Desired Duty Cycle</ipxact:displayName> + <ipxact:value>50.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_duty_cycle16" type="real"> + <ipxact:name>gui_duty_cycle16</ipxact:name> + <ipxact:displayName>Desired Duty Cycle</ipxact:displayName> + <ipxact:value>50.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_duty_cycle17" type="real"> + <ipxact:name>gui_duty_cycle17</ipxact:name> + <ipxact:displayName>Desired Duty Cycle</ipxact:displayName> + <ipxact:value>50.0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="gui_simulation_type" type="bit"> + <ipxact:name>gui_simulation_type</ipxact:name> + <ipxact:displayName>Force full PLL simulation model</ipxact:displayName> + <ipxact:value>true</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="hp_qsys_scripting_mode" type="bit"> + <ipxact:name>hp_qsys_scripting_mode</ipxact:name> + <ipxact:displayName>hp_qsys_scripting_mode</ipxact:displayName> + <ipxact:value>false</ipxact:value> + </ipxact:parameter> + </ipxact:parameters> + </altera:altera_module_parameters> + <altera:altera_assignments> + <ipxact:parameters> + <ipxact:parameter parameterId="embeddedsw.dts.compatible" type="string"> + <ipxact:name>embeddedsw.dts.compatible</ipxact:name> + <ipxact:value>altr,pll</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="embeddedsw.dts.group" type="string"> + <ipxact:name>embeddedsw.dts.group</ipxact:name> + <ipxact:value>clock</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="embeddedsw.dts.vendor" type="string"> + <ipxact:name>embeddedsw.dts.vendor</ipxact:name> + <ipxact:value>altr</ipxact:value> + </ipxact:parameter> + </ipxact:parameters> + </altera:altera_assignments> + <altera:altera_system_parameters> + <ipxact:parameters> + <ipxact:parameter parameterId="board" type="string"> + <ipxact:name>board</ipxact:name> + <ipxact:displayName>Board</ipxact:displayName> + <ipxact:value>default</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="device" type="string"> + <ipxact:name>device</ipxact:name> + <ipxact:displayName>Device</ipxact:displayName> + <ipxact:value>A3CY050BB18AI6S</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="deviceFamily" type="string"> + <ipxact:name>deviceFamily</ipxact:name> + <ipxact:displayName>Device family</ipxact:displayName> + <ipxact:value>Agilex 3</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="deviceSpeedGrade" type="string"> + <ipxact:name>deviceSpeedGrade</ipxact:name> + <ipxact:displayName>Device Speed Grade</ipxact:displayName> + <ipxact:value>6</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="generationId" type="int"> + <ipxact:name>generationId</ipxact:name> + <ipxact:displayName>Generation Id</ipxact:displayName> + <ipxact:value>0</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="bonusData" type="string"> + <ipxact:name>bonusData</ipxact:name> + <ipxact:displayName>bonusData</ipxact:displayName> + <ipxact:value>bonusData +{ + element iopll_0 + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} +</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="hideFromIPCatalog" type="bit"> + <ipxact:name>hideFromIPCatalog</ipxact:name> + <ipxact:displayName>Hide from IP Catalog</ipxact:displayName> + <ipxact:value>true</ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="lockedInterfaceDefinition" type="string"> + <ipxact:name>lockedInterfaceDefinition</ipxact:name> + <ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName> + <ipxact:value></ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="systemInfos" type="string"> + <ipxact:name>systemInfos</ipxact:name> + <ipxact:displayName>systemInfos</ipxact:displayName> + <ipxact:value><systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>outclk0</key> + <value> + <connectionPointName>outclk0</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>25000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>outclk1</key> + <value> + <connectionPointName>outclk1</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>125000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition></ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="dflBitArray" type="string"> + <ipxact:name>dflBitArray</ipxact:name> + <ipxact:displayName>dflBitArray</ipxact:displayName> + <ipxact:value></ipxact:value> + </ipxact:parameter> + <ipxact:parameter parameterId="cpuInfo" type="string"> + <ipxact:name>cpuInfo</ipxact:name> + <ipxact:displayName>cpuInfo</ipxact:displayName> + <ipxact:value></ipxact:value> + </ipxact:parameter> + </ipxact:parameters> + </altera:altera_system_parameters> + <altera:altera_interface_boundary> + <altera:interface_mapping altera:name="locked" altera:internal="iopll_0.locked" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="locked" altera:internal="locked"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="outclk0" altera:internal="iopll_0.outclk0" altera:type="clock" altera:dir="start"> + <altera:port_mapping altera:name="outclk_0" altera:internal="outclk_0"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="outclk1" altera:internal="iopll_0.outclk1" altera:type="clock" altera:dir="start"> + <altera:port_mapping altera:name="outclk_1" altera:internal="outclk_1"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="refclk" altera:internal="iopll_0.refclk" altera:type="clock" altera:dir="end"> + <altera:port_mapping altera:name="refclk" altera:internal="refclk"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="reset" altera:internal="iopll_0.reset" altera:type="reset" altera:dir="end"> + <altera:port_mapping altera:name="rst" altera:internal="rst"></altera:port_mapping> + </altera:interface_mapping> + </altera:altera_interface_boundary> + <altera:altera_has_warnings>false</altera:altera_has_warnings> + <altera:altera_has_errors>false</altera:altera_has_errors> + </ipxact:vendorExtensions> +</ipxact:component>
\ No newline at end of file diff --git a/ml_module_agilex.qpf b/ml_module_agilex.qpf new file mode 100644 index 0000000..adbda70 --- /dev/null +++ b/ml_module_agilex.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2026 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, the Altera Quartus Prime License Agreement, +# the Altera IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Altera and sold by Altera or its authorized distributors. Please +# refer to the Altera Software License Subscription Agreements +# on the Quartus Prime software download page. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 26.1.0 Build 110 03/26/2026 SC Pro Edition +# Date created = 00:02:55 May 06, 2026 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "26.1" +DATE = "00:02:55 May 06, 2026" + +# Revisions + +PROJECT_REVISION = "ml_module_agilex" diff --git a/ml_module_agilex.qsf b/ml_module_agilex.qsf new file mode 100644 index 0000000..c326afb --- /dev/null +++ b/ml_module_agilex.qsf @@ -0,0 +1,69 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2026 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, the Altera Quartus Prime License Agreement, +# the Altera IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Altera and sold by Altera or its authorized distributors. Please +# refer to the Altera Software License Subscription Agreements +# on the Quartus Prime software download page. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 26.1.0 Build 110 03/26/2026 SC Pro Edition +# Date created = 00:02:55 May 06, 2026 +# +# -------------------------------------------------------------------------- # +set_global_assignment -name TOP_LEVEL_ENTITY ml_module_agilex +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 26.1.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:02:55 MAY 06, 2026" +set_global_assignment -name LAST_QUARTUS_VERSION "26.1.0 Pro Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40" +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 +set_global_assignment -name DEVICE A3CY050BB18AI6S +set_global_assignment -name FAMILY "Agilex 3" +set_global_assignment -name DEVICE_FILTER_PACKAGE VPBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 474 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 +set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation +set_global_assignment -name BOARD default +set_instance_assignment -name IO_STANDARD "1.8-V LVCMOS" -to rgmii_rx_d[0] -entity ml_module_agilex +set_instance_assignment -name IO_STANDARD "1.8-V LVCMOS" -to rgmii_tx_d[3] -entity ml_module_agilex +set_instance_assignment -name IO_STANDARD "1.8-V LVCMOS" -to rgmii_tx_d[2] -entity ml_module_agilex +set_instance_assignment -name IO_STANDARD "1.8-V LVCMOS" -to rgmii_tx_d[1] -entity ml_module_agilex +set_instance_assignment -name IO_STANDARD "1.8-V LVCMOS" -to rgmii_tx_d[0] -entity ml_module_agilex +set_instance_assignment -name IO_STANDARD "1.8-V LVCMOS" -to rgmii_tx_d -entity ml_module_agilex +set_instance_assignment -name IO_STANDARD "1.8-V LVCMOS" -to rgmii_gpio[0] -entity ml_module_agilex +set_instance_assignment -name IO_STANDARD "1.8-V LVCMOS" -to rgmii_gpio[1] -entity ml_module_agilex +set_instance_assignment -name IO_STANDARD "1.8-V LVCMOS" -to rgmii_gpio -entity ml_module_agilex +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to fpga_led[0] -entity ml_module_agilex +set_instance_assignment -name IO_STANDARD "1.8-V LVCMOS" -to rgmii_mdc -entity ml_module_agilex +set_instance_assignment -name IO_STANDARD "1.8-V LVCMOS" -to rstn -entity ml_module_agilex +set_instance_assignment -name IO_STANDARD "1.8-V LVCMOS" -to rgmii_mdio -entity ml_module_agilex +set_instance_assignment -name IO_STANDARD "1.8-V LVCMOS" -to rgmii_intn -entity ml_module_agilex +set_instance_assignment -name IO_STANDARD "1.8-V LVCMOS" -to rgmii_rx_d[3] -entity ml_module_agilex +set_instance_assignment -name IO_STANDARD "1.8-V LVCMOS" -to rgmii_rx_d[2] -entity ml_module_agilex +set_instance_assignment -name IO_STANDARD "1.8-V LVCMOS" -to rgmii_tx_ctl -entity ml_module_agilex +set_instance_assignment -name IO_STANDARD "1.8-V LVCMOS" -to rgmii_tx_clk -entity ml_module_agilex +set_instance_assignment -name IO_STANDARD "1.8-V LVCMOS" -to rgmii_rx_d[1] -entity ml_module_agilex +set_instance_assignment -name IO_STANDARD "1.8-V LVCMOS" -to rgmii_rx_d -entity ml_module_agilex +set_instance_assignment -name IO_STANDARD "1.8-V LVCMOS" -to clk_i -entity ml_module_agilex +set_instance_assignment -name IO_STANDARD "1.8-V LVCMOS" -to rgmii_rx_ctl -entity ml_module_agilex +set_instance_assignment -name IO_STANDARD "1.8-V LVCMOS" -to rgmii_rx_clk -entity ml_module_agilex +set_global_assignment -name VERILOG_FILE src/ml_module_agilex.v +set_global_assignment -name SDC_FILE ml_module_agilex.sdc +set_global_assignment -name IP_FILE ip/pll_io.ip +set_global_assignment -name IP_FILE ip/ddr_o.ip +set_global_assignment -name IP_FILE ip/ddr_i.ip +set_global_assignment -name PROJECT_IP_REGENERATION_POLICY ALWAYS_REGENERATE_IP diff --git a/ml_module_agilex.sdc b/ml_module_agilex.sdc new file mode 100644 index 0000000..e5c100a --- /dev/null +++ b/ml_module_agilex.sdc @@ -0,0 +1,28 @@ +create_clock -name clk -period 40.0 [get_ports clk_i]; + +create_clock -name rgmii_rx_clk_v -period 8.0; # virtual clock for input constraint timing +create_clock -name rgmii_rx_clk -period 8.0 -waveform { 2 6 } [get_ports rgmii_rx_clk]; + +create_clock -name rgmii_tx_clk -period 8.0 [get_ports rgmii_tx_clk]; +create_clock -name rgmii_tx_clk_v -period 8.0; # virtual clock for input constraint timing + +derive_pll_clocks -create_base_clocks -use_net_name + +# RGMII Input Clock +set_input_delay -min -0.8 -clock { rgmii_rx_clk_v } [get_ports {rgmii_rx_d[0] rgmii_rx_d[1] rgmii_rx_d[2] rgmii_rx_d[3] rgmii_rx_ctl}] -add_delay +set_input_delay -min -0.8 -clock { rgmii_rx_clk_v } -clock_fall [get_ports {rgmii_rx_d[0] rgmii_rx_d[1] rgmii_rx_d[2] rgmii_rx_d[3] rgmii_rx_ctl}] -add_delay + +set_input_delay -max 0.8 -clock { rgmii_rx_clk_v } [get_ports {rgmii_rx_d[0] rgmii_rx_d[1] rgmii_rx_d[2] rgmii_rx_d[3] rgmii_rx_ctl}] -add_delay +set_input_delay -max 0.8 -clock { rgmii_rx_clk_v } -clock_fall [get_ports {rgmii_rx_d[0] rgmii_rx_d[1] rgmii_rx_d[2] rgmii_rx_d[3] rgmii_rx_ctl}] -add_delay + +# Set false paths to remove irrelevant setup and hold analysis +set_false_path -fall_from [get_clocks rgmii_rx_clk_v] -rise_to [get_clocks {rgmii_rx_clk}] -setup +set_false_path -rise_from [get_clocks rgmii_rx_clk_v] -fall_to [get_clocks {rgmii_rx_clk}] -setup +set_false_path -fall_from [get_clocks rgmii_rx_clk_v] -fall_to [get_clocks {rgmii_rx_clk}] -hold +set_false_path -rise_from [get_clocks rgmii_rx_clk_v] -rise_to [get_clocks {rgmii_rx_clk}] -hold + +set_output_delay -max 0.5 -clock { rgmii_tx_clk } [get_ports {rgmii_tx_d[0] rgmii_tx_d[1] rgmii_tx_d[2] rgmii_tx_d[3] rgmii_tx_ctl}] -add_delay +set_output_delay -max 0.5 -clock { rgmii_tx_clk } -clock_fall [get_ports {rgmii_tx_d[0] rgmii_tx_d[1] rgmii_tx_d[2] rgmii_tx_d[3] rgmii_tx_ctl}] -add_delay + +set_output_delay -min -0.5 -clock { rgmii_tx_clk } [get_ports {rgmii_tx_d[0] rgmii_tx_d[1] rgmii_tx_d[2] rgmii_tx_d[3] rgmii_tx_ctl}] -add_delay +set_output_delay -min -0.5 -clock { rgmii_tx_clk } -clock_fall [get_ports {rgmii_tx_d[0] rgmii_tx_d[1] rgmii_tx_d[2] rgmii_tx_d[3] rgmii_tx_ctl}] -add_delay diff --git a/sim/.gitignore b/sim/.gitignore new file mode 100644 index 0000000..2c89c7f --- /dev/null +++ b/sim/.gitignore @@ -0,0 +1,13 @@ +aldec/ +synopsys/ +xcelium/ +libraries/ +work/ +rtl_work/ +vsim.wlf +wlf* +transcript +*.mti +*.orig +*.bak +msim_transcript diff --git a/sim/data/ml.dat b/sim/data/ml.dat new file mode 100644 index 0000000..2ec3fa7 --- /dev/null +++ b/sim/data/ml.dat @@ -0,0 +1,145 @@ +55 // Preamble +55 +55 +55 +55 +55 +D5 +02 // Dest MAC Address +1A +2B +3C +4D +5E +C8 // Source MAC Address +F7 +50 +F3 +AB +DE +08 // Type IPv4 +00 +45 // IP Packet (Version, IHL)s +00 +00 // Total Length +23 +42 // Identification +41 +00 +00 +80 // TTL +11 // Identification (UDP) +70 // IP Checksum +C1 +C0 // IP Source Address +A8 +05 +14 +C0 // IP Dest Address, 192 +A8 // 168 +05 +64 // 100 +30 // UDP Source Port +00 +90 // UDP Dest Port +20 +00 // UDP Length +0f +AC // UDP Checksum +E6 +01 // Msg Type +ed // Token +07 // Address MSByte +00 // Address LSByte +00 // Data MSbyte +00 +00 +01 // Data LSbyte +00 // PAD +00 +00 +00 +00 +00 +00 +00 +00 +00 +71 // FCS +E3 // +95 +184 // Last Byte Flag Set +40 // Idle Clocks * 16 +55 // Preamble +55 +55 +55 +55 +55 +D5 +02 // Dest MAC Address +00 +0A +0B +0C +0D +C8 // Source MAC Address +F7 +50 +F3 +AB +DE +08 // Type IPv4 +00 +45 // IP Packet (Version, IHL)s +00 +00 // Total Length +23 +42 // Identification +41 +00 +00 +80 // TTL +11 // Identification (UDP) +70 // IP Checksum +C1 +C0 // IP Source Address +A8 +05 +14 +C0 // IP Dest Address, 192 +A8 // 168 +05 +64 // 100 +30 // UDP Source Port +00 +90 // UDP Dest Port +20 +00 // UDP Length +0f +AC // UDP Checksum +E6 +02 // Msg Type +c3 // Token +00 // Address MSByte +10 // Address LSByte +01 // Data MSbyte +02 +03 +04 // Data LSbyte +00 // Pad +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +71 // FCS +E3 // +95 +184 // Last Byte Flag Set +ff // Idle Clocks * 16
\ No newline at end of file diff --git a/sim/lin/modelsim.ini b/sim/lin/modelsim.ini new file mode 100644 index 0000000..f5063c6 --- /dev/null +++ b/sim/lin/modelsim.ini @@ -0,0 +1,2237 @@ +; vsim modelsim.ini file +[Version] +INIVersion = "2024.3" + +; Unpublished work. Copyright 2024 Siemens +; +; This material contains trade secrets or otherwise confidential information +; owned by Siemens Industry Software Inc. or its affiliates (collectively, +; "SISW"), or its licensors. Access to and use of this information is strictly +; limited as set forth in the Customer's applicable agreements with SISW. +; +; This material may not be copied, distributed, or otherwise disclosed outside +; of the Customer's facilities without the express written permission of SISW, +; and may not be used in any way not expressly authorized by SISW. +; + +[Library] +others = $QUESTASIM_DIR/../modelsim.ini +; +; VITAL concerns: +; +; The library ieee contains (among other packages) the packages of the +; VITAL 2000 standard. When a design uses VITAL 2000 exclusively, it should use +; the physical library ieee (recommended), or use the physical library +; vital2000, but not both. The design can use logical library ieee and/or +; vital2000 as long as each of these maps to the same physical library, either +; ieee or vital2000. +; +; A design using the 1995 version of the VITAL packages, whether or not +; it also uses the 2000 version of the VITAL packages, must have logical library +; name ieee mapped to physical library vital1995. (A design cannot use library +; vital1995 directly because some packages in this library use logical name ieee +; when referring to the other packages in the library.) The design source +; should use logical name ieee when referring to any packages there except the +; VITAL 2000 packages. Any VITAL 2000 present in the design must use logical +; name vital2000 (mapped to physical library vital2000) to refer to those +; packages. +; ieee = $MODEL_TECH/../vital1995 +; +; For compatiblity with previous releases, logical library name vital2000 maps +; to library vital2000 (a different library than library ieee, containing the +; same packages). +; A design should not reference VITAL from both the ieee library and the +; vital2000 library because the vital packages are effectively different. +; A design that references both the ieee and vital2000 libraries must have +; both logical names ieee and vital2000 mapped to the same library, either of +; these: +; $MODEL_TECH/../ieee +; $MODEL_TECH/../vital2000 +; + +; added mapping for ADMS + +;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers // Source files only for this release +;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release +;mvc_lib = $MODEL_TECH/../mvc_lib + +; Altera Primitive libraries +; +; VHDL Section +; +; +; Verilog Section +; + + +; Automatically perform logical->physical mapping for physical libraries that +; appear in -L/-Lf options with filesystem path delimiters (e.g. '.' or '/'). +; The tail of the filesystem path name is chosen as the logical library name. +; For example, in the command "vopt -L ./path/to/lib1 -o opttop top", +; vopt automatically performs the mapping "lib1 -> ./path/to/lib1". +; See the User Manual for more details. +; +; AutoLibMapping = 0 + +work = ./libraries/work/ +work_lib = ./libraries/work/ +altera_iopll_2110 = ./libraries/altera_iopll_2110/ +pll_io = ./libraries/pll_io/ +altera_gpio_core10_ph2_2210 = ./libraries/altera_gpio_core10_ph2_2210/ +altera_gpio_2300 = ./libraries/altera_gpio_2300/ +ddr_o = ./libraries/ddr_o/ +ddr_i = ./libraries/ddr_i/ +[BC_COMPAT] +; Start of Backward Compatibility Section +; The Variables in this section are dedicated for the Backward Compatibility feature +; Set desired release version for backward compatibility, note that currently this only supports 2023.1 +;BC_ReleaseCompat = 2023.1 +;BC_XClass = <activate/deactivate> +; End of Backward Compatibility Section + +[DefineOptionset] +; Define optionset entries for the various compilers, vmake, and vsim. +; These option sets can be used with the "-optionset <optionsetname>" syntax. +; i.e. +; vlog -optionset COMPILEDEBUG top.sv +; vsim -optionset UVMDEBUG my_top +; +; Following are some useful examples. + +; define a vsim optionset for uvm debugging +UVMDEBUG = -uvmcontrol=all -msgmode both -displaymsgmode both -classdebug -onfinish stop + +; define a vopt optionset for debugging +VOPTDEBUG = +acc -debugdb + +[encryption] +; For vencrypt and vhencrypt. + +; Controls whether to encrypt whole files by ignoring all protect directives +; (except "viewport" and "interface_viewport") that are present in the input. +; The default is 0, use embedded protect directives to control the encryption. +; Set this to 1 to encrypt whole files by ignoring embedded protect directives. +; wholefile = 0 + +; Sets the data_method to use for the symmetric session key. +; The session key is a symmetric key that is randomly generated for each +; protected region (envelope) and is the heart of all encryption. This is used +; to set the length of the session key to generate and use when encrypting the +; HDL text. Supported values are aes128, aes192, and aes256. +; data_method = aes128 + +; The following 2 are for specifying an IEEE Std. 1735 Version 2 (V2) encryption +; "recipe" comprising an optional common block, at least one tool block (which +; contains the key public key), and the text to be encrypted. The common block +; and any of the tool blocks may contain rights in the form of the "control" +; directive. The text to be encrypted is specified either by setting +; "wholefile" to 1 or by embedding protect "begin" and "end" directives in +; the input HDL files. + +; Common recipe specification file. This file is optional. Its presence will +; require at least one "toolblock" to be specified. +; Directives such as "author" "author_info" and "data_method", +; as well as the common block license specification, go in this file. +; common = <file name> + +; Tool block specification recipe(s). Public key file with optional tool block +; file name. May be multiply-defined; at least one tool block is required if +; a recipe is being specified. +; Key file is a file name with no extension (.deprecated or .active will be +; supplied by the encryption tool). +; Rights file name is optional. +; toolblock = <key file name>[,<rights file name>]{:<key file name>[,<rights file name>]} + +; Location of directory containing recipe files. +; The default location is in the product installation directory. +; keyring = $MODEL_TECH/../keyring + +; Enable encryption statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list] +; Add '-' to disable specific statistics. Default is [cmd,msg]. +Stats = cmd,msg + +[vcom] +; VHDL93 variable selects language version as the default. +; Default is VHDL-2002. +; Value of 0 or 1987 for VHDL-1987. +; Value of 1 or 1993 for VHDL-1993. +; Default or value of 2 or 2002 for VHDL-2002. +; Value of 3 or 2008 for VHDL-2008 +; Value of 4 or ams99 for VHDL-AMS-1999 +; Value of 5 or ams07 for VHDL-AMS-2007 +; Value of 7 or 2019 for VHDL-2019 +VHDL93 = 2002 + +; Ignore VHDL-2008 declaration of REAL_VECTOR in package STANDARD. Default is off. +; ignoreStandardRealVector = 1 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn off unbound-component warnings. Default is on. +; Show_Warning1 = 0 + +; Turn off process-without-a-wait-statement warnings. Default is on. +; Show_Warning2 = 0 + +; Turn off null-range warnings. Default is on. +; Show_Warning3 = 0 + +; Turn off no-space-in-time-literal warnings. Default is on. +; Show_Warning4 = 0 + +; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. +; Show_Warning5 = 0 + +; Turn off optimization for IEEE std_logic_1164 package. Default is on. +; Optimize_1164 = 0 + +; Enable compiler statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list] +; Add '-' to disable specific statistics. Default is [time,cmd,msg]. +; Stats = time,cmd,msg + +; Turn on resolving of ambiguous function overloading in favor of the +; "explicit" function declaration (not the one automatically created by +; the compiler for each type declaration). Default is off. +; The .ini file has Explicit enabled so that std_logic_signed/unsigned +; will match the behavior of synthesis tools. +Explicit = 1 + +; Turn off acceleration of the VITAL packages. Default is to accelerate. +; NoVital = 1 + +; Turn off VITAL compliance checking. Default is checking on. +; NoVitalCheck = 1 + +; Ignore VITAL compliance checking errors. Default is to not ignore. +; IgnoreVitalErrors = 1 + +; Turn off VITAL compliance checking warnings. Default is to show warnings. +; Show_VitalChecksWarnings = 0 + +; Turn off PSL assertion warning messages. Default is to show warnings. +; Show_PslChecksWarnings = 0 + +; Enable parsing of embedded PSL assertions. Default is enabled. +; EmbeddedPsl = 0 + +; Keep silent about case statement static warnings. +; Default is to give a warning. +; NoCaseStaticError = 1 + +; Keep silent about warnings caused by aggregates that are not locally static. +; Default is to give a warning. +; NoOthersStaticError = 1 + +; Treat as errors: +; case statement static warnings +; warnings caused by aggregates that are not locally static +; Overrides NoCaseStaticError, NoOthersStaticError settings. +; PedanticErrors = 1 + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on some limited synthesis rule compliance checking. Checks only: +; -- signals used (read) by a process must be in the sensitivity list +; CheckSynthesis = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +; Require the user to specify a configuration for all bindings, +; and do not generate a compile time default binding for the +; component. This will result in an elaboration error of +; 'component not bound' if the user fails to do so. Avoids the rare +; issue of a false dependency upon the unused default binding. +; RequireConfigForAllDefaultBinding = 1 + +; Perform default binding at compile time. +; Default is to do default binding at load time. +; BindAtCompile = 1; + +; Inhibit range checking on subscripts of arrays. Range checking on +; scalars defined with subtypes is inhibited by default. +; NoIndexCheck = 1 + +; Inhibit range checks on all (implicit and explicit) assignments to +; scalar objects defined with subtypes. +; NoRangeCheck = 1 + +; Set the prefix to be honored for synthesis/coverage pragma recognition. +; Default is "". +; AddPragmaPrefix = "" + +; Ignore synthesis and coverage pragmas with this prefix. +; Default is "". +; IgnorePragmaPrefix = "" + +; Turn on code coverage in VHDL design units. Default is off. +; Coverage = sbceft + +; Turn off code coverage in VHDL subprograms. Default is on. +; CoverSub = 0 + +; Automatically exclude VHDL case statement OTHERS choice branches. +; This includes OTHERS choices in selected signal assigment statements. +; Default is to not exclude. +; CoverExcludeDefault = 1 + +; Control compiler and VOPT optimizations that are allowed when +; code coverage is on. Refer to the comment for this in the [vlog] area. +; CoverOpt = 3 + +; Turn on or off clkOpt optimization for code coverage. Default is on. +; CoverClkOpt = 1 + +; Turn on or off clkOpt optimization builtins for code coverage. Default is on. +; CoverClkOptBuiltins = 0 + +; Inform code coverage optimizations to respect VHDL 'H' and 'L' +; values on signals in conditions and expressions, and to not automatically +; convert them to '1' and '0'. Default is to not convert. +; CoverRespectHandL = 0 + +; Increase or decrease the maximum number of rows allowed in a UDP table +; implementing a VHDL condition coverage or expression coverage expression. +; More rows leads to a longer compile time, but more expressions covered. +; CoverMaxUDPRows = 192 + +; Increase or decrease the maximum number of input patterns that are present +; in FEC table. This leads to a longer compile time with more expressions +; covered with FEC metric. +; CoverMaxFECRows = 192 + +; Increase or decrease the limit on the size of expressions and conditions +; considered for expression and condition coverages. Higher FecUdpEffort leads +; to higher compile, optimize and simulation time, but more expressions and +; conditions are considered for coverage in the design. FecUdpEffort can +; be set to a number ranging from 1 (low) to 3 (high), defined as: +; 1 - (low) Only small expressions and conditions considered for coverage. +; 2 - (medium) Bigger expressions and conditions considered for coverage. +; 3 - (high) Very large expressions and conditions considered for coverage. +; The default setting is 1 (low). +; FecUdpEffort = 1 + +; Enable or disable Focused Expression Coverage analysis for conditions and +; expressions. Focused Expression Coverage data is provided by default when +; expression and/or condition coverage is active. +; CoverFEC = 0 + +; Enable or disable UDP Coverage analysis for conditions and expressions. +; UDP Coverage data is disabled by default when expression and/or condition +; coverage is active. +; CoverUDP = 1 + +; Enable or disable Rapid Expression Coverage mode for conditions and expressions. +; Disabling this would convert non-masking conditions in FEC tables to matching +; input patterns. +; CoverREC = 1 + +; Enable or disable bit-blasting multi-bit operands of reduction prefix expressions +; for expression/condition coverage. +; NOTE: Enabling this may have a negative impact on simulation performance. +; CoverExpandReductionPrefix = 0 + +; Enable or disable short circuit evaluation of conditions and expressions when +; condition or expression coverage is active. Short circuit evaluation is enabled +; by default. +; CoverShortCircuit = 0 + +; Enable code coverage reporting of code that has been optimized away. +; The default is not to report. +; CoverReportCancelled = 1 + +; Enable deglitching of code coverage in combinatorial, non-clocked, processes. +; Default is no deglitching. +; CoverDeglitchOn = 1 + +; Control the code coverage deglitching period. A period of 0, eliminates delta +; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a +; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". +; CoverDeglitchPeriod = 0 + +; Use this directory for compiler temporary files instead of "work/_temp" +; CompilerTempDir = /tmp + +; Set this to cause the compilers to force data to be committed to disk +; when the files are closed. +; SyncCompilerFiles = 1 + +; Add VHDL-AMS declarations to package STANDARD +; Default is not to add +; AmsStandard = 1 + +; Range and length checking will be performed on array indices and discrete +; ranges, and when violations are found within subprograms, errors will be +; reported. Default is to issue warnings for violations, because subprograms +; may not be invoked. +; NoDeferSubpgmCheck = 0 + +; Turn ON detection of FSMs having single bit current state variable. +; FsmSingle = 1 + +; Turn off reset state transitions in FSM. +; FsmResetTrans = 0 + +; Turn ON detection of FSM Implicit Transitions. +; FsmImplicitTrans = 1 + +; Controls whether or not to show immediate assertions with constant expressions +; in GUI/report/UCDB etc. By default, immediate assertions with constant +; expressions are shown in GUI/report/UCDB etc. This does not affect +; evaluation of immediate assertions. +; ShowConstantImmediateAsserts = 0 + +; Controls how VHDL basic identifiers are stored with the design unit. +; Does not make the language case-sensitive, affects only how declarations +; declared with basic identifiers have their names stored and printed +; (in the GUI, examine, etc.). +; Default is to preserve the case as originally depicted in the VHDL source. +; Value of 0 indicates to change all basic identifiers to lower case. +; PreserveCase = 0 + +; For Configuration Declarations, controls the effect that USE clauses have +; on visibility inside the configuration items being configured. If 1 +; (the default), then use pre-10.0 behavior. If 0, then for stricter LRM-compliance, +; extend the visibility of objects made visible through USE clauses into nested +; component configurations. +; OldVHDLConfigurationVisibility = 0 + +; Allows VHDL configuration declarations to be in a different library from +; the corresponding configured entity. Default is to not allow this for +; stricter LRM-compliance. +; SeparateConfigLibrary = 1; + +; Determine how mode OUT subprogram parameters of type array and record are treated. +; If 0 (the default), then only VHDL 2008 will do this initialization. +; If 1, always initialize the mode OUT parameter to its default value. +; If 2, do not initialize the mode OUT out parameter. +; Note that prior to release 10.1, all language versions did not initialize mode +; OUT array and record type parameters, unless overridden here via this mechanism. +; In release 10.1 and later, only files compiled with VHDL 2008 will cause this +; initialization, unless overridden here. +; InitOutCompositeParam = 0 + +; Generate symbols debugging database in only some special cases to save on +; the number of files in the library. For other design-units, this database is +; generated on-demand in vsim. +; Default is to to generate debugging database for all design-units. +; SmartDbgSym = 1 + +; Enable or disable automatic creation of missing libraries. +; Default is 1 (enabled) +; CreateLib = 1 + +; Describe compilation options according to matching file patterns. +; File pattern * matches all printing characters other than '/'. +; File pattern **/x matches all paths containing file/directory x. +; File pattern x/** matches all paths beginning at directory x. +; FileOptMap = (**/*.vhd => -2008); + +; Describe library targets of compilation according to matching file patterns. +; LibMap = (**/*.vhd => work); + +; Enable or Disable Auto-order compilation. +; Default is 0 (disabled) +; Autoorder = 0 + +[vlog] +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on Verilog hazard checking (order-dependent accessing of global vars). +; Default is off. +; Hazard = 1 + +; Turn on converting regular Verilog identifiers to uppercase. Allows case +; insensitivity for module names. Default is no conversion. +; UpCase = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn on bad option warning. Default is off. +; Show_BadOptionWarning = 1 + +; Revert back to IEEE 1364-1995 syntax, default is 0 (off). +; vlog95compat = 1 + +; Turn off PSL warning messages. Default is to show warnings. +; Show_PslChecksWarnings = 0 + +; Enable parsing of embedded PSL assertions. Default is enabled. +; EmbeddedPsl = 0 + +; Enable compiler statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list,kb] +; Add '-' to disable specific statistics. Default is [time,cmd,msg]. +; Stats = time,cmd,msg + +; Check vlog plusargs. Default is 0 (off). +; The command line equivalent is -check_plusargs <number>. +; 0 = Don't check plusargs (this is the default) +; 1 = Warning on unrecognized plusarg +; 2 = Error and exit on unrecognized plusarg +; CheckPlusargs = 1 + +; Set the threshold for automatically identifying sparse Verilog memories. +; A memory with total size in bytes equal to or more than the sparse memory +; threshold gets marked as sparse automatically, unless specified otherwise +; in source code or by the +nosparse commandline option of vlog or vopt. +; The default is 1M. (i.e. memories with total size equal +; to or greater than 1Mb are marked as sparse) +; SparseMemThreshold = 1048576 + +; Set the prefix to be honored for synthesis and coverage pragma recognition. +; Default is "". +; AddPragmaPrefix = "" + +; Ignore synthesis and coverage pragmas with this prefix. +; Default is "". +; IgnorePragmaPrefix = "" + +; Set the option to treat all files specified in a vlog invocation as a +; single compilation unit. The default value is set to 0 which will treat +; each file as a separate compilation unit as specified in the P1800 draft standard. +; MultiFileCompilationUnit = 1 + +; Turn on code coverage in Verilog design units. Default is off. +; Coverage = sbceft + +; Automatically exclude Verilog case statement default branches. +; Default is to not automatically exclude defaults. +; CoverExcludeDefault = 1 + +; Increase or decrease the maximum number of rows allowed in a UDP table +; implementing a VHDL condition coverage or expression coverage expression. +; More rows leads to a longer compile time, but more expressions covered. +; CoverMaxUDPRows = 192 + +; Increase or decrease the maximum number of input patterns that are present +; in FEC table. This leads to a longer compile time with more expressions +; covered with FEC metric. +; CoverMaxFECRows = 192 + +; Enable Multi Bit Expression Coverage in a Design, If design has expression with +; multi bit operands, this option enables its Expression Coverage. +; The default value is 0. +; CoverFecMultiBit = 1 + +; Increase or decrease the limit on the size of expressions and conditions +; considered for expression and condition coverages. Higher FecUdpEffort leads +; to higher compile, optimize and simulation time, but more expressions and +; conditions are considered for coverage in the design. FecUdpEffort can +; be set to a number ranging from 1 (low) to 3 (high), defined as: +; 1 - (low) Only small expressions and conditions considered for coverage. +; 2 - (medium) Bigger expressions and conditions considered for coverage. +; 3 - (high) Very large expressions and conditions considered for coverage. +; The default setting is 1 (low). +; FecUdpEffort = 1 + +; Enable or disable Focused Expression Coverage analysis for conditions and +; expressions. Focused Expression Coverage data is provided by default when +; expression and/or condition coverage is active. +; CoverFEC = 0 + +; Enable or disable UDP Coverage analysis for conditions and expressions. +; UDP Coverage data is disabled by default when expression and/or condition +; coverage is active. +; CoverUDP = 1 + +; Enable or disable Rapid Expression Coverage mode for conditions and expressions. +; Disabling this would convert non-masking conditions in FEC tables to matching +; input patterns. +; CoverREC = 1 + +; Enable or disable bit-blasting multi-bit operands of reduction prefix expressions +; for expression/condition coverage. +; NOTE: Enabling this may have a negative impact on simulation performance. +; CoverExpandReductionPrefix = 0 + +; Enable or disable short circuit evaluation of conditions and expressions when +; condition or expression coverage is active. Short circuit evaluation is enabled +; by default. +; CoverShortCircuit = 0 + +; Enable deglitching of code coverage in combinatorial, non-clocked, processes. +; Default is no deglitching. +; CoverDeglitchOn = 1 + +; Control the code coverage deglitching period. A period of 0, eliminates delta +; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a +; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". +; CoverDeglitchPeriod = 0 + +; Turn on code coverage in VLOG `celldefine modules, modules containing +; specify blocks, and modules included using vlog -v and -y. Default is off. +; CoverCells = 1 + +; Enable code coverage reporting of code that has been optimized away. +; The default is not to report. +; CoverReportCancelled = 1 + +; Control compiler and VOPT optimizations that are allowed when +; code coverage is on. This is a number from 0 to 5, with the following +; meanings (the default is 3): +; 5 -- All allowable optimizations are on. +; 4 -- Turn off removing unreferenced code. +; 3 -- Turn off process, always block and if statement merging. +; 2 -- Turn off expression optimization, converting primitives +; to continuous assignments, VHDL subprogram inlining. +; and VHDL clkOpt (converting FF's to builtins). +; 1 -- Turn off continuous assignment optimizations and clock suppression. +; 0 -- Turn off Verilog module inlining and VHDL arch inlining. +; HOWEVER, if fsm coverage is turned on, optimizations will be forced to +; level 3, with also turning off converting primitives to continuous assigns. +; CoverOpt = 3 + +; Specify the override for the default value of "cross_num_print_missing" +; option for the Cross in Covergroups. If not specified then LRM default +; value of 0 (zero) is used. This is a compile time option. +; SVCrossNumPrintMissingDefault = 0 + +; Setting following to 1 would cause creation of variables which +; would represent the value of Coverpoint expressions. This is used +; in conjunction with "SVCoverpointExprVariablePrefix" option +; in the modelsim.ini +; EnableSVCoverpointExprVariable = 0 + +; Specify the override for the prefix used in forming the variable names +; which represent the Coverpoint expressions. This is used in conjunction with +; "EnableSVCoverpointExprVariable" option of the modelsim.ini +; The default prefix is "expr". +; The variable name is +; variable name => <prefix>_<coverpoint name> +; SVCoverpointExprVariablePrefix = expr + +; Override for the default value of the SystemVerilog covergroup, +; coverpoint, and cross option.goal (defined to be 100 in the LRM). +; NOTE: It does not override specific assignments in SystemVerilog +; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal" +; in the [vsim] section can override this value. +; SVCovergroupGoalDefault = 100 + +; Override for the default value of the SystemVerilog covergroup, +; coverpoint, and cross type_option.goal (defined to be 100 in the LRM) +; NOTE: It does not override specific assignments in SystemVerilog +; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal" +; in the [vsim] section can override this value. +; SVCovergroupTypeGoalDefault = 100 + +; Specify the override for the default value of "strobe" option for the +; Covergroup Type. This is a compile time option which forces "strobe" to +; a user specified default value and supersedes SystemVerilog specified +; default value of '0'(zero). NOTE: This can be overriden by a runtime +; modelsim.ini variable "SVCovergroupStrobe" in the [vsim] section. +; SVCovergroupStrobeDefault = 0 + +; Specify the override for the default value of "per_instance" option for the +; Covergroup variables. This is a compile time option which forces "per_instance" +; to a user specified default value and supersedes SystemVerilog specified +; default value of '0'(zero). +; SVCovergroupPerInstanceDefault = 0 + +; Specify the override for the default value of "get_inst_coverage" option for the +; Covergroup variables. This is a compile time option which forces +; "get_inst_coverage" to a user specified default value and supersedes +; SystemVerilog specified default value of '0'(zero). +; SVCovergroupGetInstCoverageDefault = 0 + +; +; A space separated list of resource libraries that contain precompiled +; packages. The behavior is identical to using the "-L" switch. +; +; LibrarySearchPath = <path/lib> [<path/lib> ...] +LibrarySearchPath = mtiAvm mtiRnm mtiOvm mtiUvm mtiUPF infact + +; The behavior is identical to the "-mixedansiports" switch. Default is off. +; MixedAnsiPorts = 1 + +; Enable SystemVerilog 3.1a $typeof() function. Default is off. +; EnableTypeOf = 1 + +; Only allow lower case pragmas. Default is disabled. +; AcceptLowerCasePragmaOnly = 1 + +; Set the maximum depth permitted for a recursive include file nesting. +; IncludeRecursionDepthMax = 5 + +; Turn ON detection of FSMs having single bit current state variable. +; FsmSingle = 1 + +; Turn off reset state transitions in FSM. +; FsmResetTrans = 0 + +; Turn off detections of FSMs having x-assignment. +; FsmXAssign = 0 + +; Turn ON detection of FSM Implicit Transitions. +; FsmImplicitTrans = 1 + +; List of file suffixes which will be read as SystemVerilog. White space +; in extensions can be specified with a back-slash: "\ ". Back-slashes +; can be specified with two consecutive back-slashes: "\\"; +; SvFileSuffixes = sv svp svh + +; This setting is the same as the vlog -sv command line switch. +; Enables SystemVerilog features and keywords when true (1). +; When false (0), the rules of IEEE Std 1364-2005 are followed and +; SystemVerilog keywords are ignored. +; Svlog = 0 + +; Prints attribute placed upon SV packages during package import +; when true (1). The attribute will be ignored when this +; entry is false (0). The attribute name is "mti_design_element_load_message". +; The value of this attribute is a string literal. +; Default is true (1). +; PrintSVPackageLoadingAttribute = 1 + +; Do not show immediate assertions with constant expressions in +; GUI/reports/UCDB etc. By default immediate assertions with constant +; expressions are shown in GUI/reports/UCDB etc. This does not affect +; evaluation of immediate assertions. +; ShowConstantImmediateAsserts = 0 + +; Controls if untyped parameters that are initialized with values greater +; than 2147483647 are mapped to generics of type INTEGER or ignored. +; If mapped to VHDL Integers, values greater than 2147483647 +; are mapped to negative values. +; Default is to map these parameter to generic of type INTEGER +; ForceUnsignedToVHDLInteger = 1 + +; Enable AMS wreal (wired real) extensions. Default is 0. +; WrealType = 1 + +; Controls SystemVerilog Language Extensions. These options enable +; some non-LRM compliant behavior. +; SvExtensions = [+|-]<extension>[,[+|-]<extension>]* + +; Generate symbols debugging database in only some special cases to save on +; the number of files in the library. For other design-units, this database is +; generated on-demand in vsim. +; Default is to to generate debugging database for all design-units. +; SmartDbgSym = 1 + +; Controls how $unit library entries are named. Valid options are: +; "file" (generate name based on the first file on the command line) +; "du" (generate name based on first design unit following an item +; found in $unit scope) +; CUAutoName = file + +; Enable or disable automatic creation of missing libraries. +; Default is 1 (enabled) +; CreateLib = 1 + +; Enable generating a warning when a module is overwritten in different vlog sessions in case +; the RTL source files are different. +; Default is 0 (disabled) +; WarnDuOverwrite = 1 + +[sccom] +; Enable use of SCV include files and library. Default is off. +; UseScv = 1 + +; Add C++ compiler options to the sccom command line by using this variable. +; CppOptions = -g + +; Use custom C++ compiler located at this path rather than the default path. +; The path should point directly at a compiler executable. +; CppPath = /usr/bin/g++ + +; Specify the compiler version from the list of support GNU compilers. +; examples 4.7.4, 5.3.0, 7.4.0 +; CppInstall = 7.4.0 + +; Enable verbose messages from sccom. Default is off. +; SccomVerbose = 1 + +; sccom logfile. Default is no logfile. +; SccomLogfile = sccom.log + +; Enable use of SC_MS include files and library. Default is off. +; UseScMs = 1 + +; Enable compiler statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list,kb] +; Add '-' to disable specific statistics. Default is [time,cmd,msg]. +; Stats = time,cmd,msg + +; Enable or disable automatic creation of missing libraries. +; Default is 1 (enabled) +; CreateLib = 1 + +; Enable use of UVMC library. Default is off. +; UseUvmc = 1 + +[vopt] +; Check vopt plusargs. Default is 0 (off). +; The command line equivalent is -check_plusargs <number>. +; 0 = Don't check plusargs (this is the default) +; 1 = Warning on unrecognized plusarg +; 2 = Error and exit on unrecognized plusarg +; CheckPlusargs = 1 + +; Turn on code coverage in vopt. Default is off. +; Coverage = sbceft + +; enable or disable param saving in UCDB. +; CoverageSaveParam = 0 + +; Control compiler optimizations that are allowed when +; code coverage is on. Refer to the comment for this in the [vlog] area. +; CoverOpt = 3 + +; Controls set of CoverConstructs that are being considered for Coverage +; Collection. +; Some of Valid options are: default,set1,set2 +; Covermode = default + +; Override all PA VOPT and VSIM commands to run simulation in Non-PA mode. +; NonPAmode = 1 + +; Controls set of HDL cover constructs that would be considered(or not considered) +; for Coverage Collection. (Default corresponds to covermode default). +; Some of Valid options are: "ca", "citf", "cifl", "tcint", "fsmqs". +; Coverconstruct = noca,nocitf,nofsmtf,nofsmds,noctes,nocicl,nocprc,nocfl,nofsmup,nocifl,nocpm,notcint,nocpkg,nocsva + +; Increase or decrease the maximum number of rows allowed in a UDP table +; implementing a VHDL condition coverage or expression coverage expression. +; More rows leads to a longer compile time, but more expressions covered. +; CoverMaxUDPRows = 192 + +; Increase or decrease the maximum number of input patterns that are present +; in FEC table. This leads to a longer compile time with more expressions +; covered with FEC metric. +; CoverMaxFECRows = 192 + +; Enable Multi Bit Expression Coverage in a Design, If design has expression with +; multi bit operands, this option enables its Expression Coverage. +; The default value is 0. +; CoverFecMultiBit = 1 + +; Increase or decrease the limit on the size of expressions and conditions +; considered for expression and condition coverages. Higher FecUdpEffort leads +; to higher compile, optimize and simulation time, but more expressions and +; conditions are considered for coverage in the design. FecUdpEffort can +; be set to a number ranging from 1 (low) to 3 (high), defined as: +; 1 - (low) Only small expressions and conditions considered for coverage. +; 2 - (medium) Bigger expressions and conditions considered for coverage. +; 3 - (high) Very large expressions and conditions considered for coverage. +; The default setting is 1 (low). +; FecUdpEffort = 1 + +; Enable code coverage reporting of code that has been optimized away. +; The default is not to report. +; CoverReportCancelled = 1 + +; Enable deglitching of code coverage in combinatorial, non-clocked, processes. +; Default is no deglitching. +; CoverDeglitchOn = 1 + +; Enable compiler statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list,kb] +; Add '-' to disable specific statistics. Default is [time,cmd,msg]. +; Stats = time,cmd,msg + +; Control the code coverage deglitching period. A period of 0, eliminates delta +; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a +; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". +; CoverDeglitchPeriod = 0 + +; Do not show immediate assertions with constant expressions in +; GUI/reports/UCDB etc. By default immediate assertions with constant +; expressions are shown in GUI/reports/UCDB etc. This does not affect +; evaluation of immediate assertions. +; ShowConstantImmediateAsserts = 0 + +; Set the maximum number of iterations permitted for a generate loop. +; Restricting this permits the implementation to recognize infinite +; generate loops. +; GenerateLoopIterationMax = 100000 + +; Set the maximum depth permitted for a recursive generate instantiation. +; Restricting this permits the implementation to recognize infinite +; recursions. +; GenerateRecursionDepthMax = 200 + +; Set the number of processes created during the code generation phase. +; By default a heuristic is used to set this value. This may be set to 0 +; to disable this feature completely. +; ParallelJobs = 0 + +; Controls SystemVerilog Language Extensions. These options enable +; some non-LRM compliant behavior. +; SvExtensions = [+|-]<extension>[,[+|-]<extension>]* + +; Load the specified shared objects with the RTLD_GLOBAL flag. +; This gives global visibility to all symbols in the shared objects, +; meaning that subsequently loaded shared objects can bind to symbols +; in the global shared objects. The list of shared objects should +; be whitespace delimited. This option is not supported on the +; Windows or AIX platforms. +; GlobalSharedObjectList = example1.so example2.so example3.so + +; Disable SystemVerilog elaboration system task messages +; IgnoreSVAInfo = 1 +; IgnoreSVAWarning = 1 +; IgnoreSVAError = 1 +; IgnoreSVAFatal = 1 + +; Enable or disable automatic creation of missing libraries. +; Default is 1 (enabled) +; CreateLib = 1 + +[vsim] +; vopt flow +; Set to turn on automatic optimization of a design. +; Default is on +VoptFlow = 1 + +; Simulator resolution +; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. +Resolution = ns + +; Disable certain code coverage exclusions automatically. +; Assertions and FSM are exluded from the code coverage by default +; Set AutoExclusionsDisable = fsm to enable code coverage for fsm +; Set AutoExclusionsDisable = assertions to enable code coverage for assertions +; Set AutoExclusionsDisable = all to enable code coverage for all the automatic exclusions +; Or specify comma or space separated list +;AutoExclusionsDisable = fsm,assertions + +; User time unit for run commands +; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the +; unit specified for Resolution. For example, if Resolution is 100ps, +; then UserTimeUnit defaults to ps. +; Should generally be set to default. +UserTimeUnit = default + +; Default run length +RunLength = 100 + +; Maximum iterations that can be run without advancing simulation time +IterationLimit = 10000000 + +; Specify libraries to be searched for precompiled modules +; LibrarySearchPath = <path/lib> [<path/lib> ...] + +; Set XPROP assertion fail limit. Default is 5. +; Any positive integer, -1 for infinity. +; XpropAssertionLimit = 5 + +; Control PSL and Verilog Assume directives during simulation +; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts +; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts +; SimulateAssumeDirectives = 1 + +; Control the simulation of PSL and SVA +; These switches can be overridden by the vsim command line switches: +; -psl, -nopsl, -sva, -nosva. +; Set SimulatePSL = 0 to disable PSL simulation +; Set SimulatePSL = 1 to enable PSL simulation (default) +; SimulatePSL = 1 +; Set SimulateSVA = 0 to disable SVA simulation +; Set SimulateSVA = 1 to enable concurrent SVA simulation (default) +; SimulateSVA = 1 + +; Control SVA and VHDL immediate assertion directives during simulation +; Set SimulateImmedAsserts = 0 to disable simulation of immediate asserts +; Set SimulateImmedAsserts = 1 to enable simulation of immediate asserts +; SimulateImmedAsserts = 1 + +; License feature mappings for Verilog and VHDL +; qhsimvh Single language VHDL license +; qhsimvl Single language Verilog license +; msimhdlsim Language neutral license for either Verilog or VHDL +; msimhdlmix Second language only, language neutral license for either +; Verilog or VHDL +; +; Directives to license manager can be set either as single value or as +; space separated multi-values: +; vhdl Immediately checkout and hold a VHDL license (i.e., one of +; qhsimvh, msimhdlsim, or msimhdlmix) +; vlog Immediately checkout and hold a Verilog license (i.e., one of +; qhsimvl, msimhdlsim, or msimhdlmix) +; plus Immediately checkout and hold a VHDL license and a Verilog license +; noqueue Do not wait in the license queue when a license is not available +; viewsim Try for viewer license but accept simulator license(s) instead +; of queuing for viewer license (PE ONLY) +; noviewer Disable checkout of msimviewer license feature (PE ONLY) +; noslvhdl Disable checkout of qhsimvh license feature +; noslvlog Disable checkout of qhsimvl license feature +; nomix Disable checkout of msimhdlmix license feature +; nolnl Disable checkout of msimhdlsim license feature +; mixedonly Disable checkout of qhsimvh and qhsimvl license features +; lnlonly Disable checkout of qhsimvh,qhsimvl, and msimhdlmix license features +; +; Examples (remove ";" comment character to activate licensing directives): +; Single directive: +; License = plus +; Multi-directive (Note: space delimited directives): +; License = noqueue plus + +; Severity level of a VHDL assertion message or of a SystemVerilog severity system task +; which will cause a running simulation to stop. +; VHDL assertions and SystemVerilog severity system task that occur with the +; given severity or higher will cause a running simulation to stop. +; This value is ignored during elaboration. +; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal +BreakOnAssertion = 3 + +; Severity level of a tool message which will cause a running simulation to +; stop. This value is ignored during elaboration. Default is to not break. +; 0 = Note 1 = Warning 2 = Error 3 = Fatal +;BreakOnMessage = 2 + +; The class debug feature enables more visibility and tracking of class instances +; during simulation. By default this feature is disabled (0). To enable this +; feature set ClassDebug to 1. +; ClassDebug = 1 + +; Message Format conversion specifications: +; %S - Severity Level of message/assertion +; %R - Text of message +; %T - Time of message +; %D - Delta value (iteration number) of Time +; %K - Kind of path: Instance/Region/Signal/Process/Foreign Process/Unknown/Protected +; %i - Instance/Region/Signal pathname with Process name (if available) +; %I - shorthand for one of these: +; " %K: %i" +; " %K: %i File: %F" (when path is not Process or Signal) +; except that the %i in this case does not report the Process name +; %O - Process name +; %P - Instance/Region path without leaf process +; %F - File name +; %L - Line number; if assertion message, then line number of assertion or, if +; assertion is in a subprogram, line from which the call is made +; %u - Design unit name in form library.primary +; %U - Design unit name in form library.primary(secondary) +; %% - The '%' character itself +; +; If specific format for Severity Level is defined, use that format. +; Else, for a message that occurs during elaboration: +; -- Failure/Fatal message in VHDL region that is not a Process, and in +; certain non-VHDL regions, uses MessageFormatBreakLine; +; -- Failure/Fatal message otherwise uses MessageFormatBreak; +; -- Note/Warning/Error message uses MessageFormat. +; Else, for a message that occurs during runtime and triggers a breakpoint because +; of the BreakOnAssertion setting: +; -- if in a VHDL region that is not a Process, uses MessageFormatBreakLine; +; -- otherwise uses MessageFormatBreak. +; Else (a runtime message that does not trigger a breakpoint) uses MessageFormat. +; +; MessageFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n" +; MessageFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n" +; MessageFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormatBreakLine = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F Line: %L\n" +; MessageFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" + +; Error File - alternate file for storing error messages +; ErrorFile = error.log + +; Simulation Breakpoint messages +; This flag controls the display of function names when reporting the location +; where the simulator stops because of a breakpoint or fatal error. +; Example with function name: # Break in Process ctr at counter.vhd line 44 +; Example without function name: # Break at counter.vhd line 44 +; Default value is 1. +ShowFunctions = 1 + +; Default radix for all windows and commands. +; Radix may be one of: symbolic, ascii, binary, octal, decimal, hex, unsigned +; Flags may be one of: enumnumeric, showbase, wreal +DefaultRadix = hexadecimal +DefaultRadixFlags = showbase +; Set to 1 for make the signal_force VHDL and Verilog functions use the +; default radix when processing the force value. Prior to 10.2 signal_force +; used the default radix, now it always uses symbolic unless value explicitly indicates base +;SignalForceFunctionUseDefaultRadix = 0 + +; VSIM Startup command +; Startup = do startup.do + +; VSIM Shutdown file +; Filename to save u/i formats and configurations. +; ShutdownFile = restart.do +; To explicitly disable auto save: +; ShutdownFile = --disable-auto-save + +; Run simulator in batch mode as if -batch were specified on the command line if none of -c, -gui, or -i specified. +; Simulator runs in interactive mode as if -i were specified if this option is 0. Default is 0. +; BatchMode = 1 + +; File for saving command transcript when -batch option used +; This option is ignored when -c, -gui, or -i options are used or if BatchMode above is zero +; default is unset so command transcript only goes to stdout for better performance +; BatchTranscriptFile = transcript + +; File for saving command transcript, this option is ignored when -batch option is used +TranscriptFile = transcript + +; Transcript file long line wrapping mode(s) +; mode == 0 :: no wrapping, line recorded as is +; mode == 1 :: wrap at first whitespace after WSColumn +; or at Column. +; mode == 2 :: wrap as above, but add continuation +; character ('\') at end of each wrapped line +; +; WrapMode = 0 +; WrapColumn = 30000 +; WrapWSColumn = 27000 + +; File for saving command history +; CommandHistory = cmdhist.log + +; Specify whether paths in simulator commands should be described +; in VHDL or Verilog format. +; For VHDL, PathSeparator = / +; For Verilog, PathSeparator = . +; Must not be the same character as DatasetSeparator. +PathSeparator = / + +; Specify the dataset separator for fully rooted contexts. +; The default is ':'. For example: sim:/top +; Must not be the same character as PathSeparator. +DatasetSeparator = : + +; Specify a unique path separator for the Signal Spy set of functions. +; The default will be to use the PathSeparator variable. +; Must not be the same character as DatasetSeparator. +; SignalSpyPathSeparator = / + +; Used to control parsing of HDL identifiers input to the tool. +; This includes CLI commands, vsim/vopt/vlog/vcom options, +; string arguments to FLI/VPI/DPI calls, etc. +; If set to 1, accept either Verilog escaped Id syntax or +; VHDL extended id syntax, regardless of source language. +; If set to 0, the syntax of the source language must be used. +; Each identifier in a hierarchical name may need different syntax, +; e.g. "/top/\vhdl*ext*id\/middle/\vlog*ext*id /bottom" or +; "top.\vhdl*ext*id\.middle.\vlog*ext*id .bottom" +; GenerousIdentifierParsing = 1 + +; Disable VHDL assertion messages +; IgnoreNote = 1 +; IgnoreWarning = 1 +; IgnoreError = 1 +; IgnoreFailure = 1 + +; Disable SystemVerilog assertion messages +; IgnoreSVAInfo = 1 +; IgnoreSVAWarning = 1 +; IgnoreSVAError = 1 +; IgnoreSVAFatal = 1 + +; Do not print any additional information from Severity System tasks. +; Only the message provided by the user is printed along with severity +; information. +; SVAPrintOnlyUserMessage = 1; + +; Default force kind. May be freeze, drive, deposit, or default +; or in other terms, fixed, wired, or charged. +; A value of "default" will use the signal kind to determine the +; force kind, drive for resolved signals, freeze for unresolved signals +; DefaultForceKind = freeze + +; Control the iteration of events when a VHDL signal is forced to a value +; This flag can be set to honour the signal update event in next iteration, +; the default is to update and propagate in the same iteration. +; ForceSigNextIter = 1 + +; Enable simulation statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list,kb,eor] +; Add '-' to disable specific statistics. Default is [time,cmd,msg]. +; Stats = time,cmd,msg + +; If zero, open files when elaborated; otherwise, open files on +; first read or write. Default is 0. +; DelayFileOpen = 1 + +; Control VHDL files opened for write. +; 0 = Buffered, 1 = Unbuffered +UnbufferedOutput = 0 + +; Control the number of VHDL files open concurrently. +; This number should always be less than the current ulimit +; setting for max file descriptors. +; 0 = unlimited +ConcurrentFileLimit = 40 + +; If nonzero, close files as soon as there is either an explicit call to +; file_close, or when the file variable's scope is closed. When zero, a +; file opened in append mode is not closed in case it is immediately +; reopened in append mode; otherwise, the file will be closed at the +; point it is reopened. +; AppendClose = 1 + +; Control the number of hierarchical regions displayed as +; part of a signal name shown in the Wave window. +; A value of zero tells VSIM to display the full name. +; The default is 0. +; WaveSignalNameWidth = 0 + +; Turn off warnings when changing VHDL constants and generics +; Default is 1 to generate warning messages +; WarnConstantChange = 0 + +; Turn off warnings from accelerated versions of the std_logic_arith, +; std_logic_unsigned, and std_logic_signed packages. +; StdArithNoWarnings = 1 + +; Turn off warnings from accelerated versions of the IEEE numeric_std +; and numeric_bit packages. +; NumericStdNoWarnings = 1 + +; Use old-style (pre-6.6) VHDL FOR GENERATE statement iteration names +; in the design hierarchy. +; This style is controlled by the value of the GenerateFormat +; value described next. Default is to use new-style names, which +; comprise the generate statement label, '(', the value of the generate +; parameter, and a closing ')'. +; Set this to 1 to use old-style names. +; OldVhdlForGenNames = 1 + +; Control the format of the old-style VHDL FOR generate statement region +; name for each iteration. Do not quote the value. +; The format string here must contain the conversion codes %s and %d, +; in that order, and no other conversion codes. The %s represents +; the generate statement label; the %d represents the generate parameter value +; at a particular iteration (this is the position number if the generate parameter +; is of an enumeration type). Embedded whitespace is allowed (but discouraged); +; leading and trailing whitespace is ignored. +; Application of the format must result in a unique region name over all +; loop iterations for a particular immediately enclosing scope so that name +; lookup can function properly. The default is %s__%d. +; GenerateFormat = %s__%d + +; Enable more efficient logging of VHDL Variables. +; Logging VHDL variables without this enabled, while possible, is very +; inefficient. Enabling this will provide a more efficient logging methodology +; at the expense of more memory usage. By default this feature is disabled (0). +; To enabled this feature, set this variable to 1. +; VhdlVariableLogging = 1 + +; Enable logging of VHDL access type variables and their designated objects. +; This setting will allow both variables of an access type ("access variables") +; and their designated objects ("access objects") to be logged. Logging a +; variable of an access type will automatically also cause the designated +; object(s) of that variable to be logged as the simulation progresses. +; Further, enabling this allows access objects to be logged by name. By default +; this feature is disabled (0). To enable this feature, set this variable to 1. +; Enabling this will automatically enable the VhdlVariableLogging feature also. +; AccessObjDebug = 1 + +; Make each VHDL package in a PDU has its own separate copy of the package instead +; of sharing the package between PDUs. The default is to share packages. +; To ensure that each PDU has its own set of packages, set this variable to 1. +; VhdlSeparatePduPackage = 1 + +; Specify whether checkpoint files should be compressed. +; The default is 1 (compressed). +; CheckpointCompressMode = 0 + +; Specify gcc compiler used in the compilation of automatically generated DPI exportwrapper. +; Use custom gcc compiler located at this path rather than the default path. +; The path should point directly at a compiler executable. +; DpiCppPath = <your-gcc-installation>/bin/gcc +; +; Specify the compiler version from the list of support GNU compilers. +; examples 4.7.4, 5.3.0, 7.4.0 +; DpiCppInstall = 7.4.0 + +; Specify whether to enable SystemVerilog DPI "out-of-the-blue" calls. +; The term "out-of-the-blue" refers to SystemVerilog export function calls +; made from C functions that don't have the proper context setup +; (as is the case when running under "DPI-C" import functions). +; When this is enabled, one can call a DPI export function +; (but not task) from any C code. +; the setting of this variable can be one of the following values: +; 0 : dpioutoftheblue call is disabled (default) +; 1 : dpioutoftheblue call is enabled, but export call debug support is not available. +; 2 : dpioutoftheblue call is enabled, and limited export call debug support is available. +; DpiOutOfTheBlue = 1 + +; Specify whether continuous assignments are run before other normal priority +; processes scheduled in the same iteration. This event ordering minimizes race +; differences between optimized and non-optimized designs, and is the default +; behavior beginning with the 6.5 release. For pre-6.5 event ordering, set +; ImmediateContinuousAssign to 0. +; The default is 1 (enabled). +; ImmediateContinuousAssign = 0 + +; List of dynamically loaded objects for Verilog PLI applications +; Veriuser = veriuser.sl + +; Which default VPI object model should the tool conform to? +; The 1364 modes are Verilog-only, for backwards compatibility with older +; libraries, and SystemVerilog objects are not available in these modes. +; +; In the absence of a user-specified default, the tool default is the +; latest available LRM behavior. +; Options for PliCompatDefault are: +; VPI_COMPATIBILITY_VERSION_1364v1995 +; VPI_COMPATIBILITY_VERSION_1364v2001 +; VPI_COMPATIBILITY_VERSION_1364v2005 +; VPI_COMPATIBILITY_VERSION_1800v2005 +; VPI_COMPATIBILITY_VERSION_1800v2008 +; +; Synonyms for each string are also recognized: +; VPI_COMPATIBILITY_VERSION_1364v1995 (1995, 95, 1364v1995, 1364V1995, VL1995) +; VPI_COMPATIBILITY_VERSION_1364v2001 (2001, 01, 1364v2001, 1364V2001, VL2001) +; VPI_COMPATIBILITY_VERSION_1364v2005 (1364v2005, 1364V2005, VL2005) +; VPI_COMPATIBILITY_VERSION_1800v2005 (2005, 05, 1800v2005, 1800V2005, SV2005) +; VPI_COMPATIBILITY_VERSION_1800v2008 (2008, 08, 1800v2008, 1800V2008, SV2008) + + +; PliCompatDefault = VPI_COMPATIBILITY_VERSION_1800v2005 + +; Specify whether the Verilog system task $fopen or vpi_mcd_open() +; will create directories that do not exist when opening the file +; in "a" or "w" mode. +; The default is 0 (do not create non-existent directories) +; CreateDirForFileAccess = 1 + +; Specify default options for the restart command. Options can be one +; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions +; DefaultRestartOptions = -force + + +; Specify default UVM-aware debug options if the vsim -uvmcontrol switch is not used. +; Valid options include: all, none, verbose, disable, struct, reseed, msglog, trlog, certe. +; Options can be enabled by just adding the name, or disabled by prefixing the option with a "-". +; The list of options must be delimited by commas, without spaces or tabs. +; +; Some examples +; To turn on all available UVM-aware debug features: +; UVMControl = all +; To turn on the struct window, mesage logging, and transaction logging: +; UVMControl = struct,msglog,trlog +; To turn on all options except certe: +; UVMControl = all,-certe +; To completely disable all UVM-aware debug functionality: +; UVMControl = disable + +; Specify the WildcardFilter setting. +; A space separated list of object types to be excluded when performing +; wildcard matches with log, wave, etc commands. The default value for this variable is: +; "Variable Constant Generic Parameter SpecParam Memory Assertion Cover Endpoint ScVariable CellInternal ImmediateAssert VHDLFile" +; See "Using the WildcardFilter Preference Variable" in the documentation for +; details on how to use this variable and for descriptions of the filter types. +WildcardFilter = Variable Constant Generic Parameter SpecParam Memory Assertion Cover Endpoint ScVariable CellInternal ImmediateAssert VHDLFile + +; Specify the WildcardSizeThreshold setting. +; This integer setting specifies the size at which objects will be excluded when +; performing wildcard matches with log, wave, etc commands. Objects of size equal +; to or greater than the WildcardSizeThreshold will be filtered out from the wildcard +; matches. The size is a simple calculation of number of bits or items in the object. +; The default value is 8k (8192). Setting this value to 0 will disable the checking +; of object size against this threshold and allow all objects of any size to be logged. +WildcardSizeThreshold = 8192 + +; Specify whether warning messages are output when objects are filtered out due to the +; WildcardSizeThreshold. The default is 0 (no messages generated). +WildcardSizeThresholdVerbose = 0 + +; Turn on (1) or off (0) WLF file compression. +; The default is 1 (compress WLF file). +; WLFCompress = 0 + +; Specify whether to save all design hierarchy (1) in the WLF file +; or only regions containing logged signals (0). +; The default is 0 (save only regions with logged signals). +; WLFSaveAllRegions = 1 + +; WLF file time limit. Limit WLF file by time, as closely as possible, +; to the specified amount of simulation time. When the limit is exceeded +; the earliest times get truncated from the file. +; If both time and size limits are specified the most restrictive is used. +; UserTimeUnits are used if time units are not specified. +; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} +; WLFTimeLimit = 0 + +; WLF file size limit. Limit WLF file size, as closely as possible, +; to the specified number of megabytes. If both time and size limits +; are specified then the most restrictive is used. +; The default is 0 (no limit). +; WLFSizeLimit = 1000 + +; Specify whether or not a WLF file should be deleted when the +; simulation ends. A value of 1 will cause the WLF file to be deleted. +; The default is 0 (do not delete WLF file when simulation ends). +; WLFDeleteOnQuit = 1 + +; Specify whether or not a WLF file should be optimized during +; simulation. If set to 0, the WLF file will not be optimized. +; The default is 1, optimize the WLF file. +; WLFOptimize = 0 + +; Specify the name of the WLF file. +; The default is vsim.wlf +; WLFFilename = vsim.wlf + +; Specify whether to lock the WLF file. +; Locking the file prevents other invocations of ModelSim/Questa tools from +; inadvertently overwriting the WLF file. +; The default is 1, lock the WLF file. +; WLFFileLock = 0 + +; Specify the update interval for the WLF file in live simulation. +; The interval is given in seconds. +; The value is the smallest interval between WLF file updates. The WLF file +; will be flushed (updated) after (at least) the interval has elapsed, ensuring +; that the data is correct when viewed from a separate viewer. +; A value of 0 means that no updating will occur. +; The default value is 10 seconds. +; WLFUpdateInterval = 10 + +; Specify the WLF cache size limit for WLF files. +; The value is given in megabytes. A value of 0 turns off the cache. +; On non-Windows platforms the default WLFCacheSize setting is 2000 (megabytes). +; On Windows, the default value is 1000 (megabytes) to help to avoid filling +; process memory. +; WLFSimCacheSize allows a different cache size to be set for a live simulation +; WLF file, independent of post-simulation WLF file viewing. If WLFSimCacheSize +; is not set, it defaults to the WLFCacheSize value. +; WLFCacheSize = 2000 +; WLFSimCacheSize = 500 + +; Specify the WLF file event collapse mode. +; 0 = Preserve all events and event order. (same as -wlfnocollapse) +; 1 = Only record values of logged objects at the end of a simulator iteration. +; (same as -wlfcollapsedelta) +; 2 = Only record values of logged objects at the end of a simulator time step. +; (same as -wlfcollapsetime) +; The default is 1. +; WLFCollapseMode = 0 + +; Specify whether WLF file logging can use threads on multi-processor machines. +; If 0, no threads will be used; if 1, threads will be used if the system has +; more than one processor. +; WLFUseThreads = 1 + +; Specify the size of objects that will trigger "large object" messages +; at log/wave/list time. The size calculation of the object is the same as that +; used by the WildcardSizeThreshold. The default LargeObjectSize size is 500,000. +; Setting LargeObjectSize to 0 will disable these messages. +; LargeObjectSize = 500000 + +; Specify the depth of stack frames returned by $stacktrace([level]). +; This depth will be picked up when the optional 'level' argument +; is not specified or its value is not a positive integer. +; StackTraceDepth = 100 + +; Turn on/off undebuggable SystemC type warnings. Default is on. +; ShowUndebuggableScTypeWarning = 0 + +; Turn on/off unassociated SystemC name warnings. Default is off. +; ShowUnassociatedScNameWarning = 1 + +; Turn on/off SystemC IEEE 1666 deprecation warnings. Default is off. +; ScShowIeeeDeprecationWarnings = 1 + +; Turn on/off the check for multiple drivers on a SystemC sc_signal. Default is off. +; For SystemC-2.3.2 the valid values are 0,1 and 2 +; 0 = SC_SIGNAL_WRITE_CHECK_DISABLE_ +; 1 = SC_SIGNAL_WRITE_CHECK_DEFAULT_ +; 2 = SC_SIGNAL_WRITE_CHECK_CONFLICT_ +; For SystemC-2.2 the valid values are 0 and 1 +; 0 = DISABLE +; 1 = ENABLE +; ScEnableScSignalWriteCheck = 1 + +; Set SystemC default time unit. +; Set to fs, ps, ns, us, ms, or sec with optional +; prefix of 1, 10, or 100. The default is 1 ns. +; The ScTimeUnit value is honored if it is coarser than Resolution. +; If ScTimeUnit is finer than Resolution, it is set to the value +; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns, +; then the default time unit will be 1 ns. However if Resolution +; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns. +ScTimeUnit = ns + +; Set SystemC sc_main stack size. The stack size is set as an integer +; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or +; Gb(Giga-byte). Default is 10 Mb. The stack size for sc_main depends +; on the amount of data on the sc_main() stack and the memory required +; to succesfully execute the longest function call chain of sc_main(). +ScMainStackSize = 10 Mb + +; Set SystemC thread stack size. The stack size is set as an integer +; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or +; Gb(Giga-byte). The stack size for sc_thread depends +; on the amount of data on the sc_thread stack and the memory required +; to succesfully execute the thread. +; ScStackSize = 1 Mb + +; Turn on/off execution of remainder of sc_main upon quitting the current +; simulation session. If the cumulative length of sc_main() in terms of +; simulation time units is less than the length of the current simulation +; run upon quit or restart, sc_main() will be in the middle of execution. +; This switch gives the option to execute the remainder of sc_main upon +; quitting simulation. The drawback of not running sc_main till the end +; is memory leaks for objects created by sc_main. If on, the remainder of +; sc_main will be executed ignoring all delays. This may cause the simulator +; to crash if the code in sc_main is dependent on some simulation state. +; Default is on. +ScMainFinishOnQuit = 1 + +; Enable calling of the DPI export taks/functions from the +; SystemC start_of_simulation() callback. +; The default is off. +; EnableDpiSosCb = 1 + + +; Set the SCV relationship name that will be used to identify phase +; relations. If the name given to a transactor relation matches this +; name, the transactions involved will be treated as phase transactions +ScvPhaseRelationName = mti_phase + +; Customize the vsim kernel shutdown behavior at the end of the simulation. +; Some common causes of the end of simulation are $finish (implicit or explicit), +; sc_stop(), tf_dofinish(), and assertion failures. +; This should be set to "ask", "exit", or "stop". The default is "ask". +; "ask" -- In batch mode, the vsim kernel will abruptly exit. +; In GUI mode, a dialog box will pop up and ask for user confirmation +; whether or not to quit the simulation. +; "stop" -- Cause the simulation to stay loaded in memory. This can make some +; post-simulation tasks easier. +; "exit" -- The simulation will abruptly exit without asking for any confirmation. +; "final" -- Run SystemVerilog final blocks then behave as "stop". +; Note: This variable can be overridden with the vsim "-onfinish" command line switch. +OnFinish = ask + +; Print pending deferred assertion messages. +; Deferred assertion messages may be scheduled after the $finish in the same +; time step. Deferred assertions scheduled to print after the $finish are +; printed before exiting with severity level NOTE since it's not known whether +; the assertion is still valid due to being printed in the active region +; instead of the reactive region where they are normally printed. +; OnFinishPendingAssert = 1; + +; Print "simstats" result. Default is 0. +; 0 == do not print simstats +; 1 == print at end of simulation +; 2 == print at end of each run command and end of simulation +; PrintSimStats = 1 + +; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages +; AssertFile = assert.log + +; Enable assertion counts. Default is off. +; AssertionCounts = 1 + +; Run simulator in assertion debug mode. Default is off. +; AssertionDebug = 1 + +; Turn on/off PSL/SVA/VHDL assertion enable. Default is on. +; AssertionEnable = 0 + +; Set PSL/SVA/VHDL concurrent assertion fail limit. Default is -1. +; Any positive integer, -1 for infinity. +; AssertionLimit = 1 + +; Turn on/off concurrent assertion pass log. Default is off. +; Assertion pass logging is only enabled when assertion is browseable +; and assertion debug is enabled. +; AssertionPassLog = 1 + +; Turn on/off PSL concurrent assertion fail log. Default is on. +; The flag does not affect SVA +; AssertionFailLog = 0 + +; Turn on/off SVA concurrent assertion local var printing in -assertdebug mode. Default is on. +; AssertionFailLocalVarLog = 0 + +; Set action type for PSL/SVA concurrent assertion fail action. Default is continue. +; 0 = Continue 1 = Break 2 = Exit +; AssertionFailAction = 1 + +; Enable the active thread monitor in the waveform display when assertion debug is enabled. +; AssertionActiveThreadMonitor = 1 + +; Control how many waveform rows will be used for displaying the active threads. Default is 5. +; AssertionActiveThreadMonitorLimit = 5 + +; Assertion thread limit after which assertion would be killed/switched off. +; The default is -1 (unlimited). If the number of threads for an assertion go +; beyond this limit, the assertion would be either switched off or killed. This +; limit applies to only assert directives. +;AssertionThreadLimit = -1 + +; Action to be taken once the assertion thread limit is reached. Default +; is kill. It can have a value of off,kill or killon. In case of kill, all the existing +; threads are terminated and no new attempts are started. In case of off, the +; existing attempts keep on evaluating but no new attempts are started. In case of killon, +; all the existing threads are terminated but new attempts are started. This +; variable applies to only assert directives. +;AssertionThreadLimitAction = kill + +; Cover thread limit after which cover would be killed/switched off. +; The default is -1 (unlimited). If the number of threads for a cover go +; beyond this limit, the cover would be either switched off or killed. This +; limit applies to only cover directives. +;CoverThreadLimit = -1 + +; Action to be taken once the cover thread limit is reached. Default +; is kill. It can have a value of off, kill or killon. In case of kill, all the existing +; threads are terminated and no new attempts are started. In case of off, the +; existing attempts keep on evaluating but no new attempts are started. In case of killon, +; all the existing threads are terminated but new attempts are started. This +; variable applies to only cover directives. +;CoverThreadLimitAction = kill + + +; By default immediate assertions do not participate in Assertion Coverage calculations +; unless they are executed. This switch causes all immediate assertions in the design +; to participate in Assertion Coverage calculations, whether attempted or not. +; UnattemptedImmediateAssertions = 0 + +; By default immediate covers participate in Coverage calculations +; whether they are attempted or not. This switch causes all unattempted +; immediate covers in the design to stop participating in Coverage +; calculations. +; UnattemptedImmediateCovers = 0 + +; By default pass action block is not executed for assertions on vacuous +; success. The following variable is provided to enable execution of +; pass action block on vacuous success. The following variable is only effective +; if the user does not disable pass action block execution by using either +; system tasks or CLI. Also there is a performance penalty for enabling +; the following variable. +;AssertionEnableVacuousPassActionBlock = 1 + +; As per strict 1850-2005 PSL LRM, an always property can either pass +; or fail. However, by default, Questa reports multiple passes and +; multiple fails on top always/never property (always/never operator +; is the top operator under Verification Directive). The reason +; being that Questa reports passes and fails on per attempt of the +; top always/never property. Use the following flag to instruct +; Questa to strictly follow LRM. With this flag, all assert/never +; directives will start an attempt once at start of simulation. +; The attempt can either fail, match or match vacuously. +; For e.g. if always is the top operator under assert, the always will +; keep on checking the property at every clock. If the property under +; always fails, the directive will be considered failed and no more +; checking will be done for that directive. A top always property, +; if it does not fail, will show a pass at end of simulation. +; The default value is '0' (i.e. zero is off). For example: +; PslOneAttempt = 1 + +; Specify the number of clock ticks to represent infinite clock ticks. +; This affects eventually!, until! and until_!. If at End of Simulation +; (EOS) an active strong-property has not clocked this number of +; clock ticks then neither pass or fail (vacuous match) is returned +; else respective fail/pass is returned. The default value is '0' (zero) +; which effectively does not check for clock tick condition. For example: +; PslInfinityThreshold = 5000 + +; Control how many thread start times will be preserved for ATV viewing for a given assertion +; instance. Default is -1 (ALL). +; ATVStartTimeKeepCount = -1 + +; Turn on/off code coverage +; CodeCoverage = 0 + +; This option applies to condition and expression coverage UDP tables. It +; has no effect unless UDP is enabled for coverage with vcom/vlog/vopt -coverudp. +; If this option is used and a match occurs in more than one row in the UDP table, +; none of the counts for all matching rows is incremented. By default, counts are +; incremented for all matching rows. +; CoverCountAll = 1 + +; Turn off automatic inclusion of VHDL integers in toggle coverage. Default +; is to include them. +; ToggleNoIntegers = 1 + +; Set the maximum number of values that are collected for toggle coverage of +; VHDL integers. Default is 100; +; ToggleMaxIntValues = 100 + +; Set the maximum number of values that are collected for toggle coverage of +; Verilog real. Default is 100; +; ToggleMaxRealValues = 100 + +; Turn on automatic inclusion of Verilog integers in toggle coverage, except +; for enumeration types. Default is to include them. +; ToggleVlogIntegers = 0 + +; Turn on automatic inclusion of Verilog real type in toggle coverage, except +; for shortreal types. Default is to not include them. +; ToggleVlogReal = 1 + +; Turn on automatic inclusion of Verilog fixed-size unpacked arrays, VHDL multi-d arrays +; and VHDL arrays-of-arrays in toggle coverage. +; Default is to not include them. +; ToggleFixedSizeArray = 1 + +; Increase or decrease the maximum size of Verilog unpacked fixed-size arrays, +; VHDL multi-d arrays and VHDL arrays-of-arrays that are included for toggle coverage. +; This leads to a longer simulation time with bigger arrays covered with toggle coverage. +; Default is 1024. +; ToggleMaxFixedSizeArray = 1024 + +; Treat Verilog multi-dimensional packed vectors and packed structures as equivalently sized +; one-dimensional packed vectors for toggle coverage. Default is 0. +; TogglePackedAsVec = 0 + +; Treat Verilog enumerated types as equivalently sized one-dimensional packed vectors for +; toggle coverage. Default is 0. +; ToggleVlogEnumBits = 0 + +; Turn off automatic inclusion of VHDL records in toggle coverage. +; Default is to include them. +; ToggleVHDLRecords = 0 + +; Limit the widths of registers automatically tracked for toggle coverage. Default is 128. +; For unlimited width, set to 0. +; ToggleWidthLimit = 128 + +; Limit the counts that are tracked for toggle coverage. When all edges for a bit have +; reached this count, further activity on the bit is ignored. Default is 1. +; For unlimited counts, set to 0. +; ToggleCountLimit = 1 + +; Change the mode of extended toggle coverage. Default is 3. Valid modes are 1, 2 and 3. +; Following is the toggle coverage calculation criteria based on extended toggle mode: +; Mode 1: 0L->1H & 1H->0L & any one 'Z' transition (to/from 'Z'). +; Mode 2: 0L->1H & 1H->0L & one transition to 'Z' & one transition from 'Z'. +; Mode 3: 0L->1H & 1H->0L & all 'Z' transitions. +; ExtendedToggleMode = 3 + +; Enable toggle statistics collection only for ports. Default is 0. +; TogglePortsOnly = 1 + +; Limit the counts that are tracked for Focussed Expression Coverage. When a bin has +; reached this count, further tracking of the input patterns linked to it is ignored. +; Default is 1. For unlimited counts, set to 0. +; NOTE: Changing this value from its default value may affect simulation performance. +; FecCountLimit = 1 + +; Limit the counts that are tracked for UDP Coverage. When a bin has +; reached this count, further tracking of the input patterns linked to it is ignored. +; Default is 1. For unlimited counts, set to 0. +; NOTE: Changing this value from its default value may affect simulation performance. +; UdpCountLimit = 1 + +; Control toggle coverage deglitching period. A period of 0, eliminates delta +; cycle glitches. This is the default. The value of ToggleDeglitchPeriod needs to be either +; 0 or a time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". +; ToggleDeglitchPeriod = 10.0ps + +; Turn on/off all PSL/SVA cover directive enables. Default is on. +; CoverEnable = 0 + +; Turn on/off PSL/SVA cover log. Default is off "0". +; CoverLog = 1 + +; Set "at_least" value for all PSL/SVA cover directives. Default is 1. +; CoverAtLeast = 2 + +; Set "limit" value for all PSL/SVA cover directives. Default is -1. +; Any positive integer, -1 for infinity. +; CoverLimit = 1 + +; Specify the coverage database filename. +; Default is "" (i.e. database is NOT automatically saved on close). +; UCDBFilename = vsim.ucdb + +; Specify the maximum limit for the number of Cross (bin) products reported +; in XML and UCDB report against a Cross. A warning is issued if the limit +; is crossed. Default is zero. vsim switch -cvgmaxrptrhscross can override this +; setting. +; MaxReportRhsSVCrossProducts = 1000 + +; Specify the override for the "auto_bin_max" option for the Covergroups. +; If not specified then value from Covergroup "option" is used. +; SVCoverpointAutoBinMax = 64 + +; Specify the override for the value of "cross_num_print_missing" +; option for the Cross in Covergroups. If not specified then value +; specified in the "option.cross_num_print_missing" is used. This +; is a runtime option. NOTE: This overrides any "cross_num_print_missing" +; value specified by user in source file and any SVCrossNumPrintMissingDefault +; specified in modelsim.ini. +; SVCrossNumPrintMissing = 0 + +; Specify whether to use the value of "cross_num_print_missing" +; option in report and GUI for the Cross in Covergroups. If not specified then +; cross_num_print_missing is ignored for creating reports and displaying +; covergroups in GUI. Default is 0, which means ignore "cross_num_print_missing". +; UseSVCrossNumPrintMissing = 0 + +; Specify the threshold of Coverpoint wildcard bin value range size, above which +; a warning will be triggered. The default is 4K -- 12 wildcard bits. +; SVCoverpointWildCardBinValueSizeWarn = 4096 + +; Specify the override for the value of "strobe" option for the +; Covergroup Type. If not specified then value in "type_option.strobe" +; will be used. This is runtime option which forces "strobe" to +; user specified value and supersedes user specified values in the +; SystemVerilog Code. NOTE: This also overrides the compile time +; default value override specified using "SVCovergroupStrobeDefault" +; SVCovergroupStrobe = 0 + +; Override for explicit assignments in source code to "option.goal" of +; SystemVerilog covergroup, coverpoint, and cross. It also overrides the +; default value of "option.goal" (defined to be 100 in the SystemVerilog +; LRM) and the value of modelsim.ini variable "SVCovergroupGoalDefault". +; SVCovergroupGoal = 100 + +; Override for explicit assignments in source code to "type_option.goal" of +; SystemVerilog covergroup, coverpoint, and cross. It also overrides the +; default value of "type_option.goal" (defined to be 100 in the SystemVerilog +; LRM) and the value of modelsim.ini variable "SVCovergroupTypeGoalDefault". +; SVCovergroupTypeGoal = 100 + +; Enforce the 6.3 behavior of covergroup get_coverage() and get_inst_coverage() +; builtin functions, and report. This setting changes the default values of +; option.get_inst_coverage and type_option.merge_instances to ensure the 6.3 +; behavior if explicit assignments are not made on option.get_inst_coverage and +; type_option.merge_instances by the user. There are two vsim command line +; options, -cvg63 and -nocvg63 to override this setting from vsim command line. +; The default value of this variable from release 6.6 onwards is 0. This default +; drives compliance with the clarified behavior in the IEEE 1800-2009 standard. +; SVCovergroup63Compatibility = 0 + +; Enforce the default behavior of covergroup get_coverage() builtin function, GUI +; and report. This variable sets the default value of type_option.merge_instances. +; There are two vsim command line options, -cvgmergeinstances and +; -nocvgmergeinstances to override this setting from vsim command line. +; The default value of this variable, -1 (don't care), allows the tool to determine +; the effective value, based on factors related to capacity and optimization. +; The type_option.merge_instances appears in the GUI and coverage reports as either +; auto(1) or auto(0), depending on whether the effective value was determined to +; be a 1 or a 0. +; SVCovergroupMergeInstancesDefault = -1 + +; Enable or disable generation of more detailed information about the sampling +; of covergroup, cross, and coverpoints. It provides the details of the number +; of times the covergroup instance and type were sampled, as well as details +; about why covergroup, cross and coverpoint were not covered. A non-zero value +; is to enable this feature. 0 is to disable this feature. Default is 0 +; SVCovergroupSampleInfo = 0 + +; Specify the maximum number of Coverpoint bins in whole design for +; all Covergroups. +; MaxSVCoverpointBinsDesign = 2147483648 + +; Specify maximum number of Coverpoint bins in any instance of a Covergroup, default is 2^10 bins +; MaxSVCoverpointBinsInst = 1048576 + +; Specify the maximum number of Cross bins in whole design for +; all Covergroups. +; MaxSVCrossBinsDesign = 2147483648 + +; Specify maximum number of Cross bins in any instance of a Covergroup, default is 2^16 bins +; MaxSVCrossBinsInst = 67108864 + +; Specify whether vsim will collect the coverage data of zero-weight coverage items or not. +; By default, this variable is set 0, in which case option.no_collect setting will take effect. +; If this variable is set to 1, all zero-weight coverage items will not be saved. +; Note that the usage of vsim switch -cvgzwnocollect, if present, will override the setting +; of this variable. +; CvgZWNoCollect = 1 + +; Specify a space delimited list of double quoted TCL style +; regular expressions which will be matched against the text of all messages. +; If any regular expression is found to be contained within any message, the +; status for that message will not be propagated to the UCDB TESTSTATUS. +; If no match is detected, then the status will be propagated to the +; UCDB TESTSTATUS. More than one such regular expression text is allowed, +; and each message text is compared for each regular expression in the list. +; UCDBTestStatusMessageFilter = "Done with Test Bench" "Ignore .* message" + +; Set weight for all PSL/SVA cover directives. Default is 1. +; CoverWeight = 2 + +; Check vsim plusargs. Default is 0 (off). +; The command line equivalent is -check_plusargs <number>. +; 0 = Don't check plusargs (this is the default) +; 1 = Warning on unrecognized plusarg +; 2 = Error and exit on unrecognized plusarg +; CheckPlusargs = 1 + +; Load the specified shared objects with the RTLD_GLOBAL flag. +; This gives global visibility to all symbols in the shared objects, +; meaning that subsequently loaded shared objects can bind to symbols +; in the global shared objects. The list of shared objects should +; be whitespace delimited. This option is not supported on the +; Windows or AIX platforms. +; GlobalSharedObjectList = example1.so example2.so example3.so + +; Generate the stub definitions for the undefined symbols in the shared libraries being +; loaded in the simulation. When this flow is turned on, the undefined symbols will not +; prevent vsim from loading. Calling undefined symbols at runtime will cause fatal error. +; The valid arguments are: on, off, verbose. +; on : turn on the automatic generation of stub definitions. +; off: turn off the flow. The undefined symbols will trigger an immediate load failure. +; verbose: Turn on the flow and report the undefined symbols for each shared library. +; NOTE: This variable can be overriden with vsim switch "-undefsyms". +; The default is on. +; +; UndefSyms = off + +; Enable the support for automatically checkpointing foreign C/C++ libraries. +; The valid arguments are: 0, 1, 2 +; 0: off (default) +; 1: on (manually save/restore user shared library data) +; 2: auto (automatically save/restore user shared library data) +; This option is not supported on the Windows platforms. +; +; AllowCheckpointCpp = 2 + +; Initial seed for the random number generator of the root thread (SystemVerilog). +; NOTE: This variable can be overridden with the vsim "-sv_seed" command line switch. +; The default value is 0. +; Sv_Seed = 0 + +; Specify the solver "engine" that vsim will select for constrained random +; generation. +; Valid values are: +; "auto" - automatically select the best engine for the current +; constraint scenario +; "bdd" - evaluate all constraint scenarios using the BDD solver engine +; "act" - evaluate all constraint scenarios using the ACT solver engine +; While the BDD solver engine is generally efficient with constraint scenarios +; involving bitwise logical relationships, the ACT solver engine can exhibit +; superior performance with constraint scenarios involving large numbers of +; random variables related via arithmetic operators (+, *, etc). +; NOTE: This variable can be overridden with the vsim "-solveengine" command +; line switch. +; The default value is "auto". +; SolveEngine = auto + +; Specify the maximum size that a random dynamic array or queue may be resized +; to by the solver. If the solver attempts to resize a dynamic array or queue +; to a size greater than the specified limit, an error will be issued and +; randomize() will fail. The default value is 65535. A value of 0 disables the +; resize check (i.e. no error will be issued regardless of size). +; SolveArrayResizeMax = 65535 + +; Specify the maximum size that a random dynamic array or queue may be resized +; to by the solver without a warning. If the solver attempts to resize a dynamic +; array or queue to a size greater than the specified limit, a warning will be +; issued. The default value is 65535. A value of 0 disables the resize check +; (i.e. no warning will be issued regardless of size). +; SolveArrayResizeWarn = 65535 + +; Specify error message severity when randomize() and randomize(null) failures +; are detected. +; +; Integer value up to two digits are allowed with each digit having the following legal values: +; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal +; +; 1) When a value with two digits is used, the digit at tenth place (leftmost digit) represents +; the severtity setting for normal randomize() calls. The digit at ones place (rightmost digit) +; represents the setting for randomize(null) calls. +; +; 2) When a single digit value is used, the setting is applied to both normal randomize() call +; and randomize(null) call. +; +; Example: Fatal error for randomize() failures and NO error for randomize(null) failures +; -solvefailseverity=40 +; +; NOTE: SolveFailSeverity can affect the behavior of SolveFailDebug. When SolveFailDebug is +; enabled, a constraint contradiction report will be displayed for randomize() calls that +; have a message severity >= warning (i.e. constraint contradiction reports will not be +; generated for randomize() calls having a "no error" severity level) +; +; NOTE: This variable can be overridden with the vsim "-solvefailseverity" command +; line switch. +; +; The default is 1 (warning). +; SolveFailSeverity = 1 + +; Error message severity for suppressible errors that are detected in a +; solve/before constraint. +; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal +; NOTE: This variable can be overridden with the vsim "-solvebeforeerrorseverity" +; command line switch. +; The default is 2 (error). +; SolveBeforeErrorSeverity = 2 + +; Error message severity for suppressible errors that are related to +; solve engine capacity limits +; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal +; NOTE: This variable can be overridden with the vsim "-solveengineerrorseverity" +; command line switch. +; The default is 2 (error). +; SolveEngineErrorSeverity = 2 + +; Enable/disable constraint conflicts on randomize() failure +; Valid values: +; 0 - disable solvefaildebug +; 1 - basic debug (no performance penalty) +; 2 - enhanced debug (runtime performance penalty) +; +; NOTE: SolveFailSeverity can affect the behavior of SolveFailDebug. When SolveFailDebug is +; enabled, a constraint contradiction report will be displayed for randomize() calls that +; have a message severity >= warning (i.e. constraint contradiction reports will not be +; generated for randomize() calls having a "no error" severity level) +; +; NOTE: This variable can be overridden with the vsim "-solvefaildebug" command +; line switch. +; +; The default is 1 (basic debug). +; SolveFailDebug = 1 + +; Upon encountering a randomize() failure, generate a simplified testcase that +; will reproduce the failure. Optionally output the testcase to a file. +; Testcases for 'no-solution' failures will only be produced if SolveFailDebug +; is enabled (see above). +; NOTE: This variable can be overridden with the vsim "-solvefailtestcase" +; command line switch. +; The default is OFF (do not generate a testcase). To enable testcase +; generation, uncomment this variable. To redirect testcase generation to a +; file, specify the name of the output file. +; SolveFailTestcase = + +; Specify solver timeout threshold (in seconds). randomize() will fail if the +; CPU time required to evaluate the call exceeds the specified timeout. +; The default value is 1000. A value of 0 will disable timeout failures. +; SolveTimeout = 1000 + +; Specify the alternative behavior during solver replay. Must be used when combined with -solvereplay switch. +; Valid <opt> settings: +; validate : toggle the checking of value changes of non-random variables involved in randomize(). (default is off)" +; SolveReplayOpt=[+|-]<option>[,[+|-]<option>]* + +; Switch to specify options that control the behavior of the solver profiler. +; Valid options are: +; cputime - use CPU time instead of elapsed time (wall time) to measure performance data (default is off) +; randsets - enable detailed profiling of randsets (default is off) +; testgen - generate randset testcases (only when 'randsets' option is enabled, default is off) +; SolverFProf = [+|-]<option>[,[+|-]<option>]* + +; Specify the maximum size of the solution graph generated by the BDD solver. +; This value can be used to force the BDD solver to abort the evaluation of a +; complex constraint scenario that cannot be evaluated with finite memory. +; This value is specified in 1000s of nodes. +; The default value is 10000. A value of 0 indicates no limit. +; SolveGraphMaxSize = 10000 + +; Specify the maximum number of evaluations that may be performed on the +; solution graph by the BDD solver. This value can be used to force the BDD +; solver to abort the evaluation of a complex constraint scenario that cannot +; be evaluated in finite time. This value is specified in 10000s of evaluations. +; The default value is 10000. A value of 0 indicates no limit. +; SolveGraphMaxEval = 10000 + +; Specify random sequence compatiblity with a prior release. This +; option is used to get the same random sequences during simulation as +; as a prior release. Only prior releases with the same major version +; as the current release are allowed. +; NOTE: This variable can be overridden with the vsim "-solverev" command +; line switch. +; Default value set to "" (no compatibility). +; SolveRev = + +; Environment variable expansion of command line arguments has been deprecated +; in favor shell level expansion. Universal environment variable expansion +; inside -f files is support and continued support for MGC Location Maps provide +; alternative methods for handling flexible pathnames. +; The following line may be uncommented and the value set to 1 to re-enable this +; deprecated behavior. The default value is 0. +; DeprecatedEnvironmentVariableExpansion = 0 + +; Specify the memory threshold for the System Verilog garbage collector. +; The value is the number of megabytes of class objects that must accumulate +; before the garbage collector is run. +; The GCThreshold setting is used when class debug mode is disabled to allow +; less frequent garbage collection and better simulation performance. +; The GCThresholdClassDebug setting is used when class debug mode is enabled +; to allow for more frequent garbage collection. +; GCThreshold = 100 +; GCThresholdClassDebug = 5 + +; Turn on/off collapsing of bus ports in VCD dumpports output +DumpportsCollapse = 1 + +; Location of Multi-Level Verification Component (MVC) installation. +; The default location is the product installation directory. +MvcHome = $QUESTA_MVC_HOME + +; Location of InFact installation. The default is $MODEL_TECH/../../infact +; +; InFactHome = $MODEL_TECH/../../infact + +; Initialize SystemVerilog enums using the base type's default value +; instead of the leftmost value. +; EnumBaseInit = 1 + +; Suppress file type registration. +; SuppressFileTypeReg = 1 + +; Controls SystemVerilog Language Extensions. These options enable +; some non-LRM compliant behavior. +; SvExtensions = [+|-]<extension>[,[+|-]<extension>]* + +; Enable/disable non-LRM compliant SystemVerilog constrained-random language extensions. +; Valid extensions are: +; arraymode - consider rand_mode of unpacked array field independently from its elements +; deepcheck - allow randomize(null) to recursively consider constraints from member rand class handles (Default) +; dynext - enhanced evaluation for constraints involving random dynamic arrays that are resized during randomize() +; funcback - enable function backtracking (ACT only) +; nodist - interpret 'dist' constraint as 'inside' (ACT only) +; noorder - ignore solve/before ordering constraints (ACT only) +; oobidx - allow out-of-bounds value for an indexed-expression with random indices if indexed-expression yields a 2-state packed type +; prerandfirst - execute all pre_randomize() functions before evaluating any constraints (Default) +; promotedist - promote priority of 'dist' constraint if LHS has no solve/before +; purecheck - suppress pre_randomize() and post_randomize() calls for randomize(null) +; randcext - allow 'randc' and other 'rand' variables to be solved in the same randset (Default) +; randindex - allow random index in constraint (Default) +; randstruct - consider all fields of unpacked structs as 'rand' +; skew - skew randomize results (ACT only) +; srandom - interpret $srandom(seed) system task calls as equivalent process::self().srandom(seed) calls (Default) +; strictstab - strict random stability +; SvRandExtensions = [+|-]<extension>[,[+|-]<extension>]* + +; Controls the formatting of '%p' and '%P' conversion specification, used in $display +; and similar system tasks. +; 1. SVPrettyPrintFlags=I<n><S|T> use <n> spaces(S) or tabs(T) per indentation level. +; The 'I' flag when present causes relevant data types to be expanded and indented into +; a more readable format. +; (e.g. SVPrettyPrintFlags=I4S will cause 4 spaces to be used per indentation level). +; 2. SVPrettyPrintFlags=L<numLines> limits the output to <numLines> lines. +; (e.g. SVPrettyPrintFlags=L20 will limit the output to 20 lines). +; 3. SVPrettyPrintFlags=C<numChars> limits the output to <numChars> characters. +; (e.g. SVPrettyPrintFlags=C256 will limit the output to 256 characters). +; 4. SVPrettyPrintFlags=F<numFields> limits the output to <numFields> of relevant datatypes +; (e.g. SVPrettyPrintFlags=F4 will limit the output to 4 fields of a structure). +; 5. SVPrettyPrintFlags=E<numElements> limits the output to <numElements> of relevant datatypes +; (e.g. SVPrettyPrintFlags=E50 will limit the output to 50 elements of an array). +; 6. SVPrettyPrintFlags=D<depth> suppresses the output of sub-elements below <depth>. +; (e.g. SVPrettyPrintFlags=D5 will suppresses the output of sub elements below a depth of 5). +; 7. SVPrettyPrintFlags=R<specifier> shows the output of specifier %p as per the specifed radix. +; It changes the output in $display and similar systasks. It does not affect formatted output functions ($displayh etc)). +; (e.g. SVPrettyPrintFlags=Rb will show the output of %p specifier in binary format. +; 8. Items 1-7 above can be combined as a comma separated list. +; (e.g. SVPrettyPrintFlags=I4S,L20,C256,F4,E50,D5,Rb) +; SVPrettyPrintFlags=I4S + +[lmc] +; The simulator's interface to Logic Modeling's SmartModel SWIFT software +libsm = $MODEL_TECH/libsm.sl +; The simulator's interface to Logic Modeling's SmartModel SWIFT software (Windows NT) +; libsm = $MODEL_TECH/libsm.dll +; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700) +; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl +; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000) +; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o +; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris) +; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so +; Logic Modeling's SmartModel SWIFT software (Windows NT) +; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll +; Logic Modeling's SmartModel SWIFT software (non-Enterprise versions of Linux) +; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so +; Logic Modeling's SmartModel SWIFT software (Enterprise versions of Linux) +; libswift = $LMC_HOME/lib/linux.lib/libswift.so + +; The simulator's interface to Logic Modeling's hardware modeler SFI software +libhm = $MODEL_TECH/libhm.sl +; The simulator's interface to Logic Modeling's hardware modeler SFI software (Windows NT) +; libhm = $MODEL_TECH/libhm.dll +; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700) +; libsfi = <sfi_dir>/lib/hp700/libsfi.sl +; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000) +; libsfi = <sfi_dir>/lib/rs6000/libsfi.a +; Logic Modeling's hardware modeler SFI software (Sun4 Solaris) +; libsfi = <sfi_dir>/lib/sun4.solaris/libsfi.so +; Logic Modeling's hardware modeler SFI software (Windows NT) +; libsfi = <sfi_dir>/lib/pcnt/lm_sfi.dll +; Logic Modeling's hardware modeler SFI software (Linux) +; libsfi = <sfi_dir>/lib/linux/libsfi.so + +[msg_system] +; Change a message severity or suppress a message. +; The format is: <msg directive> = <msg number>[,<msg number>...] +; suppress can be used to achieve +nowarn<CODE> functionality +; The format is: suppress = <CODE>,<msg number>,[<CODE>,<msg number>,...] +; Examples: +suppress = 8780 ;an explanation can be had by running: verror 8780 +; note = 3009 +; warning = 3033 +; error = 3010,3016 +; fatal = 3016,3033 +; suppress = 3009,3016,3601 +; suppress = 3009,CNNODP,3601,TFMPC +; suppress = 8683,8684 +; The command verror <msg number> can be used to get the complete +; description of a message. + +; Control transcripting of Verilog display system task messages and +; PLI/FLI print function call messages. The system tasks include +; $display[bho], $strobe[bho], $monitor[bho], and $write[bho]. They +; also include the analogous file I/O tasks that write to STDOUT +; (i.e. $fwrite or $fdisplay). The PLI/FLI calls include io_printf, +; vpi_printf, mti_PrintMessage, and mti_PrintFormatted. The default +; is to have messages appear only in the transcript. The other +; settings are to send messages to the wlf file only (messages that +; are recorded in the wlf file can be viewed in the MsgViewer) or +; to both the transcript and the wlf file. The valid values are +; tran {transcript only (default)} +; wlf {wlf file only} +; both {transcript and wlf file} +; displaymsgmode = tran + +; Control transcripting of elaboration/runtime messages not +; addressed by the displaymsgmode setting. The default is to +; have messages appear only in the transcript. The other settings +; are to send messages to the wlf file only (messages that are +; recorded in the wlf file can be viewed in the MsgViewer) or to both +; the transcript and the wlf file. The valid values are +; tran {transcript only (default)} +; wlf {wlf file only} +; both {transcript and wlf file} +; msgmode = tran + +; Controls number of displays of a particluar message +; default value is 5 +; MsgLimitCount = 5 + +[utils] +; Default Library Type (while creating a library with "vlib") +; 0 - legacy library using subdirectories for design units +; 2 - flat library +; DefaultLibType = 2 + +; Flat Library Page Size (while creating a library with "vlib") +; Set the size in bytes for flat library file pages. Libraries containing +; very large files may benefit from a larger value. +; FlatLibPageSize = 8192 + +; Flat Library Page Cleanup Percentage (while creating a library with "vlib") +; Set the percentage of total pages deleted before library cleanup can occur. +; This setting is applied together with FlatLibPageDeleteThreshold. +; FlatLibPageDeletePercentage = 50 + +; Flat Library Page Cleanup Threshold (while creating a library with "vlib") +; Set the number of pages deleted before library cleanup can occur. +; This setting is applied together with FlatLibPageDeletePercentage. +; FlatLibPageDeleteThreshold = 1000 + diff --git a/sim/lin/sim.do b/sim/lin/sim.do new file mode 100644 index 0000000..0d232dc --- /dev/null +++ b/sim/lin/sim.do @@ -0,0 +1,66 @@ +# +# file: sim.do +# +# # +# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to +# # construct paths to the files required to simulate the IP in your Quartus +# # project. By default, the IP script assumes that you are launching the +# # simulator from the IP script location. If launching from another +# # location, set QSYS_SIMDIR to the output directory you specified when you +# # generated the IP script, relative to the directory from which you launch +# # the simulator. +# # +set QSYS_SIMDIR . + +# # +# # Source the generated IP simulation script. + +source $QSYS_SIMDIR/mentor/msim_setup.tcl + +# # +# # Set any compilation options you require (this is unusual). +# set USER_DEFINED_COMPILE_OPTIONS <compilation options> +# set USER_DEFINED_VHDL_COMPILE_OPTIONS <compilation options for VHDL> +# set USER_DEFINED_VERILOG_COMPILE_OPTIONS <compilation options for Verilog> +# # +# # Call command to compile the Quartus EDA simulation library. + +dev_com + +# # +# # Call command to compile the Quartus-generated IP simulation files. + +com + +# # +# # Add commands to compile all design files and testbench files, including +# # the top level. (These are all the files required for simulation other +# # than the files compiled by the Quartus-generated IP simulation script) +# # + +vlog -work work -vopt +define+SIMULATION ../../src/ml_module_agilex.v +vlog -work work ../src/tb.sv + +# # +# # Set the top-level simulation or testbench module/entity name, which is +# # used by the elab command to elaborate the top level. +# # + +set TOP_LEVEL_NAME tb + +# # +# # Set any elaboration options you require. +# set USER_DEFINED_ELAB_OPTIONS <elaboration options> +# # +# # Call command to elaborate your design and testbench. + +elab + +# # +# # Run the simulation. +# run -a +# # +# # Report success to the shell. +# exit -code 0 +# # + diff --git a/sim/src/tb.sv b/sim/src/tb.sv new file mode 100644 index 0000000..107df8e --- /dev/null +++ b/sim/src/tb.sv @@ -0,0 +1,188 @@ +/* + * tb.sv + * + * Copyright (C) 2026 Private Island Networks Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * function: test bench for ML Module Agilex + * + * Notes: + * + * RX data is from the TB to the DUT (ML Module) + * TX data is from the DUT to the TB + * + */ + +`timescale 1ns / 1ps + +module tb; + + // System clocks + parameter PERIOD_CLK_25 = 40; // 25 MHz + parameter PERIOD_CLK_125 = 8; // 125 MHz + parameter PERIOD_CLK_250 = 4; // 250 MHz to support RGMII DDR + + localparam IDLE_SHIFT = 4; // Used to multiply the specified # of idle clocks + + localparam RX_CLK_CNT_START = 'd20; // clocks to wait after PLL Lock + + // FPGA I/O + reg rstn; + reg clk_125, clk_25, clk_250; + wire rgmii_rx_clk; + reg rgmii_rx_ctl; + reg [3:0] rgmii_rx_d; + wire rgmii_tx_clk; + wire rgmii_tx_ctl; + wire [3:0] rgmii_tx_d; + wire rgmii_mdc, rgmii_mdio, rgmii_resetn, rgmii_intn; + wire [2:0] led; + + // sim only I/O + wire pclk; + wire pll_lock; + wire [2:0] phy_up; + + ml_module_agilex dut( + .rstn(rstn), + .clk_i(clk_25), + + // Sim Only + .pll_locked_o(pll_lock), + .pclk(pclk), + + .rgmii_rx_clk(rgmii_rx_clk), + .rgmii_rx_ctl(rgmii_rx_ctl), + .rgmii_rx_d(rgmii_rx_d), + .rgmii_tx_clk(rgmii_tx_clk), + .rgmii_tx_ctl(rgmii_tx_ctl), + .rgmii_tx_d(rgmii_tx_d), + .rgmii_mdc(rgmii_mdc), + .rgmii_mdio(rgmii_mdio), + .rgmii_intn(rgmii_intn), + .rgmii_gpio(), + + .flash_clk(), + .flash_dqs(), + .flash_seln(), + .flash_d(), + + .fpga_led(led) + + ); + + assign #2 rgmii_rx_clk = !clk_125; // Provide 2ns clock skew similar to what an Ethernet PHY supports + + + reg [23:0] rx_clk_cnt; + reg [23:0] rx_clk_cnt_start; + reg [13:0] rx_idle_cnt; + reg [13:0] rx_data_cnt; + reg rx_last_byte; + reg [8:0] rx_d[0:16383]; // 2**14 + reg [8:0] rx_d_byte; + + +initial begin + $readmemh("../data/ml.dat",rx_d); + $display("[%0t ns] ==INFO== Load memory from file for rx: %0s.", $time, "ml.dat"); +end + + initial begin + rstn = 1'b0; + clk_25 = 1'b0; + clk_125 = 1'b0; + clk_250 = 0; + #25 rstn = 1'b1; + end + + // Clocks + always + #(PERIOD_CLK_125/2) clk_125 = ~clk_125; + + always + #(PERIOD_CLK_25/2) clk_25 = ~clk_25; + + always + #(PERIOD_CLK_250/2) clk_250 = ~clk_250; + + + // DDR clk count. Use bit 0 to indicate rising edge + always @(posedge clk_250, negedge rstn) + if (!rstn) + rx_clk_cnt <= 24'd0; + else if (pll_lock) + rx_clk_cnt <= rx_clk_cnt + 1'b1; + + // Capture the number of idle clocks before next packet (for debugging) + always @(posedge clk_125, negedge rstn) + if (!rstn) + rx_idle_cnt <= 14'd0; + else if (rx_d[rx_data_cnt][8]) + rx_idle_cnt <= rx_d[rx_data_cnt+1][7:0] << IDLE_SHIFT; + + // Counter to determine next packet to transmit into the DUT (receive path) + always @(posedge clk_125, negedge rstn) + if (!rstn) + rx_clk_cnt_start <= RX_CLK_CNT_START; + else if (rx_d[rx_data_cnt][8]) + rx_clk_cnt_start <= rx_clk_cnt + (rx_d[rx_data_cnt+1][7:0] << IDLE_SHIFT) + 1'b1; + + // The MSB bit (9th bit) of the data file denotes the last byte to transmit into the DUT + always @(negedge clk_250, negedge rstn) + if (!rstn) + rx_last_byte <= 1'b0; + else if (rx_d[rx_data_cnt][8] && rx_clk_cnt[0]) + rx_last_byte <= 1'b1; + else + rx_last_byte <= 1'b0; + + // rx_d_byte helps with debugging + always @(negedge clk_250, negedge rstn) + if (!rstn) + rx_d_byte <= 9'd0; + else + rx_d_byte <= rx_d[rx_data_cnt]; + + // RX data logic. Refer to RGMII spec for info on use of CTL bits. + always @(negedge clk_250, negedge rstn) + if (!rstn) begin + rgmii_rx_ctl <= 1'b0; + rgmii_rx_d <= 4'hD; + rx_data_cnt <= 24'd0; + end + else if (rx_clk_cnt >= rx_clk_cnt_start && !rx_last_byte) begin + if (!rx_clk_cnt[0]) begin + rgmii_rx_ctl <= 1'b1; + rgmii_rx_d <= rx_d[rx_data_cnt][3:0]; + end + else begin + rgmii_rx_ctl <= 1'b1; + rgmii_rx_d <= rx_d[rx_data_cnt][7:4]; + rx_data_cnt <= rx_data_cnt + 1'b1; + end + end + else if (rx_last_byte) begin + rgmii_rx_ctl <= 1'b0; + rgmii_rx_d <= 4'hD; + rx_data_cnt <= rx_data_cnt + 1'b1; + end + else begin + rgmii_rx_ctl <= 1'b0; + rgmii_rx_d <= 4'hD; + end + +endmodule + + diff --git a/sim/wav/basic_wav.do b/sim/wav/basic_wav.do new file mode 100644 index 0000000..5c461cd --- /dev/null +++ b/sim/wav/basic_wav.do @@ -0,0 +1,53 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -divider -height 20 TB +add wave -noupdate /tb/rstn +add wave -noupdate /tb/clk_25 +add wave -noupdate /tb/clk_125 +add wave -noupdate /tb/clk_250 +add wave -noupdate /tb/pll_lock +add wave -noupdate /tb/pclk +add wave -noupdate /tb/rx_d +add wave -noupdate -radix unsigned /tb/rx_clk_cnt +add wave -noupdate /tb/rx_clk_cnt_start +add wave -noupdate /tb/rx_idle_cnt +add wave -noupdate /tb/rx_last_byte +add wave -noupdate /tb/clk_125 +add wave -noupdate /tb/clk_250 +add wave -noupdate /tb/rx_data_cnt +add wave -noupdate /tb/rx_d_byte +add wave -noupdate /tb/rgmii_rx_clk +add wave -noupdate /tb/rgmii_rx_ctl +add wave -noupdate /tb/rgmii_rx_d +add wave -noupdate /tb/rgmii_tx_clk +add wave -noupdate /tb/rgmii_tx_ctl +add wave -noupdate /tb/rgmii_tx_d +add wave -noupdate -divider -height 20 DUT +add wave -noupdate /tb/dut/rgmii_rx_clk +add wave -noupdate /tb/dut/rgmii_rx_ctl +add wave -noupdate /tb/dut/rgmii_rx_d +add wave -noupdate /tb/dut/rx_ctl +add wave -noupdate /tb/dut/rx_d +add wave -noupdate /tb/dut/tx_ctl +add wave -noupdate /tb/dut/tx_d +add wave -noupdate /tb/dut/rgmii_tx_clk +add wave -noupdate /tb/dut/rgmii_tx_ctl +add wave -noupdate /tb/dut/rgmii_tx_d +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {26378096549 fs} 0} +quietly wave cursor active 1 +configure wave -namecolwidth 150 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {26360219488 fs} {26396029484 fs} diff --git a/sim/win/.gitignore b/sim/win/.gitignore new file mode 100644 index 0000000..2211df6 --- /dev/null +++ b/sim/win/.gitignore @@ -0,0 +1 @@ +*.txt diff --git a/sim/win/common/modelsim_files.tcl b/sim/win/common/modelsim_files.tcl new file mode 100644 index 0000000..0dd16b2 --- /dev/null +++ b/sim/win/common/modelsim_files.tcl @@ -0,0 +1,90 @@ + +proc get_design_libraries {} { + set libraries [dict create] + dict set libraries altera_iopll_2110 1 + dict set libraries pll_io 1 + dict set libraries altera_gpio_core10_ph2_2210 1 + dict set libraries altera_gpio_2300 1 + dict set libraries ddr_o 1 + dict set libraries ddr_i 1 + return $libraries +} + +proc get_memory_files {QSYS_SIMDIR QUARTUS_INSTALL_DIR} { + set memory_files [list] + return $memory_files +} + +proc get_common_design_files {USER_DEFINED_COMPILE_OPTIONS USER_DEFINED_VERILOG_COMPILE_OPTIONS USER_DEFINED_VHDL_COMPILE_OPTIONS QSYS_SIMDIR} { + set design_files [dict create] + return $design_files +} + +proc get_design_files {USER_DEFINED_COMPILE_OPTIONS USER_DEFINED_VERILOG_COMPILE_OPTIONS USER_DEFINED_VHDL_COMPILE_OPTIONS QSYS_SIMDIR QUARTUS_INSTALL_DIR} { + set design_files [list] + lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../../ip/pll_io/altera_iopll_2110/sim/pll_io_altera_iopll_2110_txusefy.vo"]\" -work altera_iopll_2110" + lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../../ip/pll_io/sim/pll_io.v"]\" -work pll_io" + lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../../ip/ddr_o/altera_gpio_core10_ph2_2210/sim/altera_gpio.sv"]\" -work altera_gpio_core10_ph2_2210" + lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../../ip/ddr_o/altera_gpio_2300/sim/ddr_o_altera_gpio_2300_hykp5oy.v"]\" -work altera_gpio_2300" + lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../../ip/ddr_o/sim/ddr_o.v"]\" -work ddr_o" + lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../../ip/ddr_i/altera_gpio_core10_ph2_2210/sim/altera_gpio.sv"]\" -work altera_gpio_core10_ph2_2210" + lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../../ip/ddr_i/altera_gpio_2300/sim/ddr_i_altera_gpio_2300_iejxysy.v"]\" -work altera_gpio_2300" + lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../../ip/ddr_i/sim/ddr_i.v"]\" -work ddr_i" + return $design_files +} + +proc get_non_duplicate_elab_option {ELAB_OPTIONS NEW_ELAB_OPTION} { + set IS_DUPLICATE [string first $NEW_ELAB_OPTION $ELAB_OPTIONS] + if {$IS_DUPLICATE == -1} { + return $NEW_ELAB_OPTION + } else { + return "" + } +} + + +proc get_elab_options {SIMULATOR_TOOL_BITNESS} { + set ELAB_OPTIONS "" + if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] { + } else { + } + return $ELAB_OPTIONS +} + + +proc get_sim_options {SIMULATOR_TOOL_BITNESS} { + set SIM_OPTIONS "" + if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] { + } else { + } + return $SIM_OPTIONS +} + + +proc get_env_variables {SIMULATOR_TOOL_BITNESS} { + set ENV_VARIABLES [dict create] + set LD_LIBRARY_PATH [dict create] + dict set ENV_VARIABLES "LD_LIBRARY_PATH" $LD_LIBRARY_PATH + if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] { + } else { + } + return $ENV_VARIABLES +} + + +proc normalize_path {FILEPATH} { + if {[catch { package require fileutil } err]} { + return $FILEPATH + } + set path [fileutil::lexnormalize [file join [pwd] $FILEPATH]] + if {[file pathtype $FILEPATH] eq "relative"} { + set path [fileutil::relative [pwd] $path] + } + return $path +} +proc get_dpi_libraries {QSYS_SIMDIR} { + set libraries [dict create] + + return $libraries +} + diff --git a/sim/win/elab.do b/sim/win/elab.do new file mode 100644 index 0000000..1175739 --- /dev/null +++ b/sim/win/elab.do @@ -0,0 +1,66 @@ +# +# file: sim.do +# +# # +# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to +# # construct paths to the files required to simulate the IP in your Quartus +# # project. By default, the IP script assumes that you are launching the +# # simulator from the IP script location. If launching from another +# # location, set QSYS_SIMDIR to the output directory you specified when you +# # generated the IP script, relative to the directory from which you launch +# # the simulator. +# # +set QSYS_SIMDIR . + +# # +# # Source the generated IP simulation script. + +source $QSYS_SIMDIR/mentor/msim_setup.tcl + +# # +# # Set any compilation options you require (this is unusual). +# set USER_DEFINED_COMPILE_OPTIONS <compilation options> +# set USER_DEFINED_VHDL_COMPILE_OPTIONS <compilation options for VHDL> +# set USER_DEFINED_VERILOG_COMPILE_OPTIONS <compilation options for Verilog> +# # +# # Call command to compile the Quartus EDA simulation library. + +dev_com + +# # +# # Call command to compile the Quartus-generated IP simulation files. + +com + +# # +# # Add commands to compile all design files and testbench files, including +# # the top level. (These are all the files required for simulation other +# # than the files compiled by the Quartus-generated IP simulation script) +# # + +vlog -work work -vopt +define+SIMULATION ../../src/ml_module_agilex.v +vlog -work work ../src/tb.sv + +# # +# # Set the top-level simulation or testbench module/entity name, which is +# # used by the elab command to elaborate the top level. +# # + +set TOP_LEVEL_NAME tb + +# # +# # Set any elaboration options you require. +set USER_DEFINED_ELAB_OPTIONS -voptargs=+acc +# # +# # Call command to elaborate your design and testbench. + +elab + +# # +# # Run the simulation. +# run -a +# # +# # Report success to the shell. +# exit -code 0 +# # + diff --git a/sim/win/mentor/msim_setup.tcl b/sim/win/mentor/msim_setup.tcl new file mode 100644 index 0000000..240bb0b --- /dev/null +++ b/sim/win/mentor/msim_setup.tcl @@ -0,0 +1,441 @@ + +# (C) 2001-2026 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions and +# other software and tools, and its AMPP partner logic functions, and +# any output files any of the foregoing (including device programming +# or simulation files), and any associated documentation or information +# are expressly subject to the terms and conditions of the Intel +# Program License Subscription Agreement, Intel MegaCore Function +# License Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Intel and sold by Intel +# or its authorized distributors. Please refer to the applicable +# agreement for further details. + +# ---------------------------------------- +# Auto-generated simulation script msim_setup.tcl +# ---------------------------------------- +# This script provides commands to simulate the following IP detected in +# your Quartus project: +# pll_io.pll_io +# ddr_o.ddr_o +# ddr_i.ddr_i +# +# Intel recommends that you source this Quartus-generated IP simulation +# script from your own customized top-level script, and avoid editing this +# generated script. +# +# To write a top-level script that compiles Intel simulation libraries and +# the Quartus-generated IP in your project, along with your design and +# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below +# into a new file, e.g. named "mentor.do", and modify the text as directed. +# +# ---------------------------------------- +# # TOP-LEVEL TEMPLATE - BEGIN +# # +# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to +# # construct paths to the files required to simulate the IP in your Quartus +# # project. By default, the IP script assumes that you are launching the +# # simulator from the IP script location. If launching from another +# # location, set QSYS_SIMDIR to the output directory you specified when you +# # generated the IP script, relative to the directory from which you launch +# # the simulator. +# # +# set QSYS_SIMDIR <script generation output directory> +# # +# # Source the generated IP simulation script. +# source $QSYS_SIMDIR/mentor/msim_setup.tcl +# # +# # Set any compilation options you require (this is unusual). +# set USER_DEFINED_COMPILE_OPTIONS <compilation options> +# set USER_DEFINED_VHDL_COMPILE_OPTIONS <compilation options for VHDL> +# set USER_DEFINED_VERILOG_COMPILE_OPTIONS <compilation options for Verilog> +# # +# # Call command to compile the Quartus EDA simulation library. +# dev_com +# # +# # Call command to compile the Quartus-generated IP simulation files. +# com +# # +# # Add commands to compile all design files and testbench files, including +# # the top level. (These are all the files required for simulation other +# # than the files compiled by the Quartus-generated IP simulation script) +# # +# vlog <compilation options> <design and testbench files> +# # +# # Set the top-level simulation or testbench module/entity name, which is +# # used by the elab command to elaborate the top level. +# # +# set TOP_LEVEL_NAME <simulation top> +# # +# # Set any elaboration options you require. +# set USER_DEFINED_ELAB_OPTIONS <elaboration options> +# # +# # Call command to elaborate your design and testbench. +# elab +# # +# # Run the simulation. +# run -a +# # +# # Report success to the shell. +# exit -code 0 +# # +# # TOP-LEVEL TEMPLATE - END +# ---------------------------------------- +# +# IP SIMULATION SCRIPT +# ---------------------------------------- +# ACDS 26.1 110 win32 2026.05.10.00:14:46 + +# ---------------------------------------- +# Initialize variables +if ![info exists SYSTEM_INSTANCE_NAME] { + set SYSTEM_INSTANCE_NAME "" +} elseif { ![ string match "" $SYSTEM_INSTANCE_NAME ] } { + set SYSTEM_INSTANCE_NAME "/$SYSTEM_INSTANCE_NAME" +} + +if ![info exists TOP_LEVEL_NAME] { + set TOP_LEVEL_NAME "ddr_i.ddr_i" +} + +if ![info exists QSYS_SIMDIR] { + set QSYS_SIMDIR "./../" +} + +if ![info exists QUARTUS_INSTALL_DIR] { + set QUARTUS_INSTALL_DIR "C:/altera_pro/26.1/quartus/" +} + +if ![info exists QUARTUS_SIM_LIB_DIR] { + set QUARTUS_SIM_LIB_DIR "$QUARTUS_INSTALL_DIR/eda/sim_lib/" +} + +if ![info exists DEVICES_SIM_LIB_DIR] { + set DEVICES_SIM_LIB_DIR "$QUARTUS_INSTALL_DIR/../devices/sim_lib/" +} + +if ![info exists USER_DEFINED_COMPILE_OPTIONS] { + set USER_DEFINED_COMPILE_OPTIONS "" +} + +if ![info exists USER_DEFINED_VHDL_COMPILE_OPTIONS] { + set USER_DEFINED_VHDL_COMPILE_OPTIONS "" +} + +if ![info exists USER_DEFINED_VERILOG_COMPILE_OPTIONS] { + set USER_DEFINED_VERILOG_COMPILE_OPTIONS "" +} + +if ![info exists USER_DEFINED_ELAB_OPTIONS] { + set USER_DEFINED_ELAB_OPTIONS "" +} + +if ![info exists SILENCE] { + set SILENCE "false" +} + +if ![info exists PRECOMP_DEVICE_LIB_FILE] { + set PRECOMP_DEVICE_LIB_FILE "" +} + +if ![info exists FORCE_MODELSIM_AE_SELECTION] { + set FORCE_MODELSIM_AE_SELECTION "false" +} +if ![info exists ENABLE_QE_LIBRARY_COMPILATION] { + set ENABLE_QE_LIBRARY_COMPILATION "false" +} + +#------------------------------------------- +# read .tcl file to override initialized variables +if { [info exists ::env(QSYS_SIM_SCRIPT_QUESTASIM_OPTIONS_FILE)] && [file exist $::env(QSYS_SIM_SCRIPT_QUESTASIM_OPTIONS_FILE)] } { + echo "Sourcing $::env(QSYS_SIM_SCRIPT_QUESTASIM_OPTIONS_FILE)" + source $::env(QSYS_SIM_SCRIPT_QUESTASIM_OPTIONS_FILE) +} + + +# ---------------------------------------- +# Source Common Tcl File +source $QSYS_SIMDIR/common/modelsim_files.tcl + + +# ---------------------------------------- +# Initialize simulation properties - DO NOT MODIFY! +set ELAB_OPTIONS "" +set SIM_OPTIONS "" +set LD_LIBRARY_PATH [dict create] +if { ![ string match "*-64 vsim*" [ vsimVersionString ] ] } { + set SIMULATOR_TOOL_BITNESS "bit_32" +} else { + set SIMULATOR_TOOL_BITNESS "bit_64" +} +set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]] +if {[dict size $LD_LIBRARY_PATH] !=0 } { + set LD_LIBRARY_PATH [subst [join [dict keys $LD_LIBRARY_PATH] ":"]] + setenv LD_LIBRARY_PATH "$LD_LIBRARY_PATH" +} +append ELAB_OPTIONS [subst [get_elab_options $SIMULATOR_TOOL_BITNESS]] +append SIM_OPTIONS [subst [get_sim_options $SIMULATOR_TOOL_BITNESS]] + +proc check_precomp_device {precomp_device_lib_path force_select_modelsim_ae enable_qe_library_compilation} { + set len [string length $precomp_device_lib_path] + if {($len == 0) && ([string is false -strict [modelsim_ae_select $force_select_modelsim_ae]] || [string is true -strict $enable_qe_library_compilation])} { + return 1 + } + return 0 + +} + +proc modelsim_ae_select {force_select_modelsim_ae} { + if [string is true -strict $force_select_modelsim_ae] { + return 1 + } + return [string match -nocase "*Altera*FPGA*" [ vsimVersionString ]] + +} + + +# ---------------------------------------- +# Copy ROM/RAM files to simulation directory +alias file_copy { + if [string is false -strict $SILENCE] { + echo "\[exec\] file_copy" + } + set memory_files [list] + set memory_files [concat $memory_files [get_memory_files "$QSYS_SIMDIR" "$QUARTUS_INSTALL_DIR"]] + foreach file $memory_files { + set itercount 0 + while {$itercount < 10 && [file type $file] eq "link"} { + set nf [file readlink $file] + if {[string index $nf 0] ne "/"} { + set nf [file dirname $file]/$nf + } + set file $nf + } + set dest_file [file join ./ [file tail $file]] + set normalized_src [normalize_path "$file"] + set normalized_dest [normalize_path "$dest_file"] + if { $normalized_src ne $normalized_dest } { + file copy -force $file ./ + } + } + +} +# ---------------------------------------- +# Modify modelsim.ini if precompiled device libraries are in use +if { $PRECOMP_DEVICE_LIB_FILE ne "" } { + echo "Modifying modelsim.ini according to $PRECOMP_DEVICE_LIB_FILE" + set PRECOMP_DEVICE_LIB_FILE [string trim $PRECOMP_DEVICE_LIB_FILE] + if { [file exists $PRECOMP_DEVICE_LIB_FILE] && [string match [file tail $PRECOMP_DEVICE_LIB_FILE] "modelsim.ini" ] } { + if { [file exists "modelsim.ini"] } { + echo "modelsim.ini already exists, making backup modelsim.ini.bak" + file copy -force "modelsim.ini" "modelsim.ini.bak" + } + echo "Copying modelsim.ini from $PRECOMP_DEVICE_LIB_FILE" + file copy -force $PRECOMP_DEVICE_LIB_FILE ./ + } elseif { [file exists $PRECOMP_DEVICE_LIB_FILE] && [string match "*tcl" [file tail $PRECOMP_DEVICE_LIB_FILE] ] } { + echo "Running $PRECOMP_DEVICE_LIB_FILE to generate device library mapping" + source $PRECOMP_DEVICE_LIB_FILE + } else { + echo "Unable to use $PRECOMP_DEVICE_LIB_FILE for device library mapping. Switching back to local library compilation" + set PRECOMP_DEVICE_LIB_FILE "" + } +} + +# ---------------------------------------- +# Create compilation libraries + +set logical_libraries [list "work" "work_lib" "lpm_ver" "sgate_ver" "altera_ver" "altera_mf_ver" "altera_lnsim_ver" "tennm_ver" "tennm_sm_hps_ver" "tennm_sm4_hssi_ver" "tennm_revb_hvio_ver" "tennm_revb_io96_ver"] + +proc ensure_lib { lib } { if ![file isdirectory $lib] { vlib $lib } } +ensure_lib ./libraries/ +ensure_lib ./libraries/work/ +vmap work ./libraries/work/ +vmap work_lib ./libraries/work/ + +# ---------------------------------------- +# get DPI libraries +set libraries [dict create] +set libraries [dict merge $libraries [get_dpi_libraries "$QSYS_SIMDIR"]] +set dpi_libraries [dict values $libraries] + +# ---------------------------------------- +# setup shared libraries +set DPI_LIBRARIES_ELAB "" +if { [llength $dpi_libraries] != 0 } { + echo "Using DPI Library settings" + foreach library $dpi_libraries { + append DPI_LIBRARIES_ELAB "-sv_lib $library " + } +} + +if [ check_precomp_device $PRECOMP_DEVICE_LIB_FILE $FORCE_MODELSIM_AE_SELECTION $ENABLE_QE_LIBRARY_COMPILATION ] { + ensure_lib ./libraries/lpm_ver/ + vmap lpm_ver ./libraries/lpm_ver/ + ensure_lib ./libraries/sgate_ver/ + vmap sgate_ver ./libraries/sgate_ver/ + ensure_lib ./libraries/altera_ver/ + vmap altera_ver ./libraries/altera_ver/ + ensure_lib ./libraries/altera_mf_ver/ + vmap altera_mf_ver ./libraries/altera_mf_ver/ + ensure_lib ./libraries/altera_lnsim_ver/ + vmap altera_lnsim_ver ./libraries/altera_lnsim_ver/ + ensure_lib ./libraries/tennm_ver/ + vmap tennm_ver ./libraries/tennm_ver/ + ensure_lib ./libraries/tennm_sm_hps_ver/ + vmap tennm_sm_hps_ver ./libraries/tennm_sm_hps_ver/ + ensure_lib ./libraries/tennm_sm4_hssi_ver/ + vmap tennm_sm4_hssi_ver ./libraries/tennm_sm4_hssi_ver/ + ensure_lib ./libraries/tennm_revb_hvio_ver/ + vmap tennm_revb_hvio_ver ./libraries/tennm_revb_hvio_ver/ + ensure_lib ./libraries/tennm_revb_io96_ver/ + vmap tennm_revb_io96_ver ./libraries/tennm_revb_io96_ver/ +} +set design_libraries [dict create] +set design_libraries [dict merge $design_libraries [get_design_libraries]] +set libraries [dict keys $design_libraries] +foreach library $libraries { + ensure_lib ./libraries/$library/ + vmap $library ./libraries/$library/ + lappend logical_libraries $library +} + +# ---------------------------------------- +# Compile device library files +alias dev_com { + if [string is false -strict $SILENCE] { + echo "\[exec\] dev_com" + } + if [ check_precomp_device $PRECOMP_DEVICE_LIB_FILE $FORCE_MODELSIM_AE_SELECTION $ENABLE_QE_LIBRARY_COMPILATION ] { + eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/220model.v" -work lpm_ver + eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/sgate.v" -work sgate_ver + eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_primitives.v" -work altera_ver + eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_mf.v" -work altera_mf_ver + eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_lnsim.sv" -work altera_lnsim_ver + eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/tennm_atoms.sv" -work tennm_ver + eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/mentor/tennm_atoms_ncrypt.sv" -work tennm_ver + eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/fmica_atoms_ncrypt.sv" -work tennm_ver + eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm_hps.sv" -work tennm_sm_hps_ver + eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm_hps_ncrypt.sv" -work tennm_sm_hps_ver + eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm4_hssi.sv" -work tennm_sm4_hssi_ver + eval vlog -sv -suppress 7061,2583,13314,2244,2283,2600,3691 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm4_hssi_ncrypt.sv" -work tennm_sm4_hssi_ver + eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_hvio.sv" -work tennm_revb_hvio_ver + eval vlog -sv -suppress 2583 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_hvio_ncrypt.sv" -work tennm_revb_hvio_ver + eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_io96.sv" -work tennm_revb_io96_ver + eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_io96_ncrypt.sv" -work tennm_revb_io96_ver + } + eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/simsf_dpi.cpp" +} + +# ---------------------------------------- +# Compile the design files in correct order +alias com { + if [string is false -strict $SILENCE] { + echo "\[exec\] com" + } + set design_files [dict create] + set design_files [dict merge [get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR"]] + set common_design_files [dict values $design_files] + foreach file $common_design_files { + eval $file + } + set design_files [list] + set design_files [concat $design_files [get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR" "$QUARTUS_INSTALL_DIR"]] + foreach file $design_files { + eval $file + } +} + +# ---------------------------------------- +# Elaborate top level design +alias elab { + if [string is false -strict $SILENCE] { + echo "\[exec\] elab" + } + set elabcommand " $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS" + foreach library $logical_libraries { append elabcommand " -L $library" } + append elabcommand " $TOP_LEVEL_NAME $DPI_LIBRARIES_ELAB " + eval vsim $elabcommand +} + +# ---------------------------------------- +# Elaborate the top level design with -voptargs=+acc option +alias elab_debug { + if [string is false -strict $SILENCE] { + echo "\[exec\] elab_debug" + } + set elabcommand " $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS" + foreach library $logical_libraries { append elabcommand " -L $library" } + append elabcommand " $TOP_LEVEL_NAME $DPI_LIBRARIES_ELAB " + eval vsim -voptargs=+acc $elabcommand +} + +# ---------------------------------------- +# Compile all the design files and elaborate the top level design +alias ld " + dev_com + com + elab +" + +# ---------------------------------------- +# Compile all the design files and elaborate the top level design with -voptargs=+acc +alias ld_debug " + dev_com + com + elab_debug +" + +# ---------------------------------------- +# Print out user commmand line aliases +alias h { + echo "List Of Command Line Aliases" + echo + echo "file_copy -- Copy ROM/RAM files to simulation directory" + echo + echo "dev_com -- Compile device library files" + echo + echo "com -- Compile the design files in correct order" + echo + echo "elab -- Elaborate top level design" + echo + echo "elab_debug -- Elaborate the top level design with -voptargs=+acc option" + echo + echo "ld -- Compile all the design files and elaborate the top level design" + echo + echo "ld_debug -- Compile all the design files and elaborate the top level design with -voptargs=+acc" + echo + echo + echo + echo "List Of Variables" + echo + echo "TOP_LEVEL_NAME -- Top level module name." + echo " For most designs, this should be overridden" + echo " to enable the elab/elab_debug aliases." + echo + echo "SYSTEM_INSTANCE_NAME -- Instantiated system module name inside top level module." + echo + echo "QSYS_SIMDIR -- Qsys base simulation directory." + echo + echo "QUARTUS_INSTALL_DIR -- Quartus installation directory." + echo + echo "USER_DEFINED_COMPILE_OPTIONS -- User-defined compile options, added to com/dev_com aliases." + echo + echo "USER_DEFINED_VHDL_COMPILE_OPTIONS -- User-defined vhdl compile options, added to com/dev_com aliases." + echo + echo "USER_DEFINED_VERILOG_COMPILE_OPTIONS -- User-defined verilog compile options, added to com/dev_com aliases." + echo + echo "USER_DEFINED_ELAB_OPTIONS -- User-defined elaboration options, added to elab/elab_debug aliases." + echo + echo "SILENCE -- Set to true to suppress all informational and/or warning messages in the generated simulation script. " + echo + echo "PRECOMP_DEVICE_LIB_FILE -- Precompiled device library file." + echo " Use this variable to provide modelsim.ini or tcl containing device library mapping and dev_com will be skipped" + echo " If value is empty, device libraries will be compiled local" + echo + echo "FORCE_MODELSIM_AE_SELECTION -- Set to true to force to select Modelsim AE always." + echo + echo "ENABLE_QE_LIBRARY_COMPILATION -- Set to true to enable device library compilation for Questa FE." +} +file_copy +h diff --git a/sim/win/mentor/run_msim_setup.tcl b/sim/win/mentor/run_msim_setup.tcl new file mode 100644 index 0000000..7a21c47 --- /dev/null +++ b/sim/win/mentor/run_msim_setup.tcl @@ -0,0 +1,36 @@ +# (C) 2001-2026 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions and +# other software and tools, and its AMPP partner logic functions, and +# any output files any of the foregoing (including device programming +# or simulation files), and any associated documentation or information +# are expressly subject to the terms and conditions of the Intel +# Program License Subscription Agreement, Intel MegaCore Function +# License Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Intel and sold by Intel +# or its authorized distributors. Please refer to the applicable +# agreement for further details. + +# ACDS 26.1 110 win32 2026.05.10.00:14:46 +# ---------------------------------------- +# Auto-generated simulation script run_msim_setup.tcl +# ---------------------------------------- +# This script provides commands to run the msim_setup.tcl script for the following IP detected in +# your Quartus project: +# pll_io.pll_io +# ddr_o.ddr_o +# ddr_i.ddr_i +# +# +# Intel recommends that you source this Quartus-generated IP simulation +# script to compile, elab and run the design without any customization. +# For customization, please follow the steps mentioned in msim_setup.tcl. + +if ![info exists QSYS_SIMDIR] { + set QSYS_SIMDIR "./../" +} + +source $QSYS_SIMDIR/mentor/msim_setup.tcl +ld +run -all +quit diff --git a/sim/win/ml_module.mpf b/sim/win/ml_module.mpf new file mode 100644 index 0000000..a23c648 --- /dev/null +++ b/sim/win/ml_module.mpf @@ -0,0 +1,2300 @@ +; vsim modelsim.ini file +[Version] +INIVersion = "2024.3" + +; Unpublished work. Copyright 2024 Siemens +; +; This material contains trade secrets or otherwise confidential information +; owned by Siemens Industry Software Inc. or its affiliates (collectively, +; "SISW"), or its licensors. Access to and use of this information is strictly +; limited as set forth in the Customer's applicable agreements with SISW. +; +; This material may not be copied, distributed, or otherwise disclosed outside +; of the Customer's facilities without the express written permission of SISW, +; and may not be used in any way not expressly authorized by SISW. +; + +[Library] +others = $QUESTASIM_DIR/../modelsim.ini +; +; VITAL concerns: +; +; The library ieee contains (among other packages) the packages of the +; VITAL 2000 standard. When a design uses VITAL 2000 exclusively, it should use +; the physical library ieee (recommended), or use the physical library +; vital2000, but not both. The design can use logical library ieee and/or +; vital2000 as long as each of these maps to the same physical library, either +; ieee or vital2000. +; +; A design using the 1995 version of the VITAL packages, whether or not +; it also uses the 2000 version of the VITAL packages, must have logical library +; name ieee mapped to physical library vital1995. (A design cannot use library +; vital1995 directly because some packages in this library use logical name ieee +; when referring to the other packages in the library.) The design source +; should use logical name ieee when referring to any packages there except the +; VITAL 2000 packages. Any VITAL 2000 present in the design must use logical +; name vital2000 (mapped to physical library vital2000) to refer to those +; packages. +; ieee = $MODEL_TECH/../vital1995 +; +; For compatiblity with previous releases, logical library name vital2000 maps +; to library vital2000 (a different library than library ieee, containing the +; same packages). +; A design should not reference VITAL from both the ieee library and the +; vital2000 library because the vital packages are effectively different. +; A design that references both the ieee and vital2000 libraries must have +; both logical names ieee and vital2000 mapped to the same library, either of +; these: +; $MODEL_TECH/../ieee +; $MODEL_TECH/../vital2000 +; + +; added mapping for ADMS + +;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers // Source files only for this release +;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release +;mvc_lib = $MODEL_TECH/../mvc_lib + +; Altera Primitive libraries +; +; VHDL Section +; +; +; Verilog Section +; + + +; Automatically perform logical->physical mapping for physical libraries that +; appear in -L/-Lf options with filesystem path delimiters (e.g. '.' or '/'). +; The tail of the filesystem path name is chosen as the logical library name. +; For example, in the command "vopt -L ./path/to/lib1 -o opttop top", +; vopt automatically performs the mapping "lib1 -> ./path/to/lib1". +; See the User Manual for more details. +; +; AutoLibMapping = 0 + +work = work +work_lib = ./libraries/work/ +altera_iopll_2110 = ./libraries/altera_iopll_2110/ +pll_io = ./libraries/pll_io/ +altera_gpio_core10_ph2_2210 = ./libraries/altera_gpio_core10_ph2_2210/ +altera_gpio_2300 = ./libraries/altera_gpio_2300/ +ddr_o = ./libraries/ddr_o/ +ddr_i = ./libraries/ddr_i/ +[BC_COMPAT] +; Start of Backward Compatibility Section +; The Variables in this section are dedicated for the Backward Compatibility feature +; Set desired release version for backward compatibility, note that currently this only supports 2023.1 +;BC_ReleaseCompat = 2023.1 +;BC_XClass = <activate/deactivate> +; End of Backward Compatibility Section + +[DefineOptionset] +; Define optionset entries for the various compilers, vmake, and vsim. +; These option sets can be used with the "-optionset <optionsetname>" syntax. +; i.e. +; vlog -optionset COMPILEDEBUG top.sv +; vsim -optionset UVMDEBUG my_top +; +; Following are some useful examples. + +; define a vsim optionset for uvm debugging +UVMDEBUG = -uvmcontrol=all -msgmode both -displaymsgmode both -classdebug -onfinish stop + +; define a vopt optionset for debugging +VOPTDEBUG = +acc -debugdb + +[encryption] +; For vencrypt and vhencrypt. + +; Controls whether to encrypt whole files by ignoring all protect directives +; (except "viewport" and "interface_viewport") that are present in the input. +; The default is 0, use embedded protect directives to control the encryption. +; Set this to 1 to encrypt whole files by ignoring embedded protect directives. +; wholefile = 0 + +; Sets the data_method to use for the symmetric session key. +; The session key is a symmetric key that is randomly generated for each +; protected region (envelope) and is the heart of all encryption. This is used +; to set the length of the session key to generate and use when encrypting the +; HDL text. Supported values are aes128, aes192, and aes256. +; data_method = aes128 + +; The following 2 are for specifying an IEEE Std. 1735 Version 2 (V2) encryption +; "recipe" comprising an optional common block, at least one tool block (which +; contains the key public key), and the text to be encrypted. The common block +; and any of the tool blocks may contain rights in the form of the "control" +; directive. The text to be encrypted is specified either by setting +; "wholefile" to 1 or by embedding protect "begin" and "end" directives in +; the input HDL files. + +; Common recipe specification file. This file is optional. Its presence will +; require at least one "toolblock" to be specified. +; Directives such as "author" "author_info" and "data_method", +; as well as the common block license specification, go in this file. +; common = <file name> + +; Tool block specification recipe(s). Public key file with optional tool block +; file name. May be multiply-defined; at least one tool block is required if +; a recipe is being specified. +; Key file is a file name with no extension (.deprecated or .active will be +; supplied by the encryption tool). +; Rights file name is optional. +; toolblock = <key file name>[,<rights file name>]{:<key file name>[,<rights file name>]} + +; Location of directory containing recipe files. +; The default location is in the product installation directory. +; keyring = $MODEL_TECH/../keyring + +; Enable encryption statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list] +; Add '-' to disable specific statistics. Default is [cmd,msg]. +Stats = cmd,msg + +[vcom] +; VHDL93 variable selects language version as the default. +; Default is VHDL-2002. +; Value of 0 or 1987 for VHDL-1987. +; Value of 1 or 1993 for VHDL-1993. +; Default or value of 2 or 2002 for VHDL-2002. +; Value of 3 or 2008 for VHDL-2008 +; Value of 4 or ams99 for VHDL-AMS-1999 +; Value of 5 or ams07 for VHDL-AMS-2007 +; Value of 7 or 2019 for VHDL-2019 +VHDL93 = 2002 + +; Ignore VHDL-2008 declaration of REAL_VECTOR in package STANDARD. Default is off. +; ignoreStandardRealVector = 1 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn off unbound-component warnings. Default is on. +; Show_Warning1 = 0 + +; Turn off process-without-a-wait-statement warnings. Default is on. +; Show_Warning2 = 0 + +; Turn off null-range warnings. Default is on. +; Show_Warning3 = 0 + +; Turn off no-space-in-time-literal warnings. Default is on. +; Show_Warning4 = 0 + +; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. +; Show_Warning5 = 0 + +; Turn off optimization for IEEE std_logic_1164 package. Default is on. +; Optimize_1164 = 0 + +; Enable compiler statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list] +; Add '-' to disable specific statistics. Default is [time,cmd,msg]. +; Stats = time,cmd,msg + +; Turn on resolving of ambiguous function overloading in favor of the +; "explicit" function declaration (not the one automatically created by +; the compiler for each type declaration). Default is off. +; The .ini file has Explicit enabled so that std_logic_signed/unsigned +; will match the behavior of synthesis tools. +Explicit = 1 + +; Turn off acceleration of the VITAL packages. Default is to accelerate. +; NoVital = 1 + +; Turn off VITAL compliance checking. Default is checking on. +; NoVitalCheck = 1 + +; Ignore VITAL compliance checking errors. Default is to not ignore. +; IgnoreVitalErrors = 1 + +; Turn off VITAL compliance checking warnings. Default is to show warnings. +; Show_VitalChecksWarnings = 0 + +; Turn off PSL assertion warning messages. Default is to show warnings. +; Show_PslChecksWarnings = 0 + +; Enable parsing of embedded PSL assertions. Default is enabled. +; EmbeddedPsl = 0 + +; Keep silent about case statement static warnings. +; Default is to give a warning. +; NoCaseStaticError = 1 + +; Keep silent about warnings caused by aggregates that are not locally static. +; Default is to give a warning. +; NoOthersStaticError = 1 + +; Treat as errors: +; case statement static warnings +; warnings caused by aggregates that are not locally static +; Overrides NoCaseStaticError, NoOthersStaticError settings. +; PedanticErrors = 1 + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on some limited synthesis rule compliance checking. Checks only: +; -- signals used (read) by a process must be in the sensitivity list +; CheckSynthesis = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +; Require the user to specify a configuration for all bindings, +; and do not generate a compile time default binding for the +; component. This will result in an elaboration error of +; 'component not bound' if the user fails to do so. Avoids the rare +; issue of a false dependency upon the unused default binding. +; RequireConfigForAllDefaultBinding = 1 + +; Perform default binding at compile time. +; Default is to do default binding at load time. +; BindAtCompile = 1; + +; Inhibit range checking on subscripts of arrays. Range checking on +; scalars defined with subtypes is inhibited by default. +; NoIndexCheck = 1 + +; Inhibit range checks on all (implicit and explicit) assignments to +; scalar objects defined with subtypes. +; NoRangeCheck = 1 + +; Set the prefix to be honored for synthesis/coverage pragma recognition. +; Default is "". +; AddPragmaPrefix = "" + +; Ignore synthesis and coverage pragmas with this prefix. +; Default is "". +; IgnorePragmaPrefix = "" + +; Turn on code coverage in VHDL design units. Default is off. +; Coverage = sbceft + +; Turn off code coverage in VHDL subprograms. Default is on. +; CoverSub = 0 + +; Automatically exclude VHDL case statement OTHERS choice branches. +; This includes OTHERS choices in selected signal assigment statements. +; Default is to not exclude. +; CoverExcludeDefault = 1 + +; Control compiler and VOPT optimizations that are allowed when +; code coverage is on. Refer to the comment for this in the [vlog] area. +; CoverOpt = 3 + +; Turn on or off clkOpt optimization for code coverage. Default is on. +; CoverClkOpt = 1 + +; Turn on or off clkOpt optimization builtins for code coverage. Default is on. +; CoverClkOptBuiltins = 0 + +; Inform code coverage optimizations to respect VHDL 'H' and 'L' +; values on signals in conditions and expressions, and to not automatically +; convert them to '1' and '0'. Default is to not convert. +; CoverRespectHandL = 0 + +; Increase or decrease the maximum number of rows allowed in a UDP table +; implementing a VHDL condition coverage or expression coverage expression. +; More rows leads to a longer compile time, but more expressions covered. +; CoverMaxUDPRows = 192 + +; Increase or decrease the maximum number of input patterns that are present +; in FEC table. This leads to a longer compile time with more expressions +; covered with FEC metric. +; CoverMaxFECRows = 192 + +; Increase or decrease the limit on the size of expressions and conditions +; considered for expression and condition coverages. Higher FecUdpEffort leads +; to higher compile, optimize and simulation time, but more expressions and +; conditions are considered for coverage in the design. FecUdpEffort can +; be set to a number ranging from 1 (low) to 3 (high), defined as: +; 1 - (low) Only small expressions and conditions considered for coverage. +; 2 - (medium) Bigger expressions and conditions considered for coverage. +; 3 - (high) Very large expressions and conditions considered for coverage. +; The default setting is 1 (low). +; FecUdpEffort = 1 + +; Enable or disable Focused Expression Coverage analysis for conditions and +; expressions. Focused Expression Coverage data is provided by default when +; expression and/or condition coverage is active. +; CoverFEC = 0 + +; Enable or disable UDP Coverage analysis for conditions and expressions. +; UDP Coverage data is disabled by default when expression and/or condition +; coverage is active. +; CoverUDP = 1 + +; Enable or disable Rapid Expression Coverage mode for conditions and expressions. +; Disabling this would convert non-masking conditions in FEC tables to matching +; input patterns. +; CoverREC = 1 + +; Enable or disable bit-blasting multi-bit operands of reduction prefix expressions +; for expression/condition coverage. +; NOTE: Enabling this may have a negative impact on simulation performance. +; CoverExpandReductionPrefix = 0 + +; Enable or disable short circuit evaluation of conditions and expressions when +; condition or expression coverage is active. Short circuit evaluation is enabled +; by default. +; CoverShortCircuit = 0 + +; Enable code coverage reporting of code that has been optimized away. +; The default is not to report. +; CoverReportCancelled = 1 + +; Enable deglitching of code coverage in combinatorial, non-clocked, processes. +; Default is no deglitching. +; CoverDeglitchOn = 1 + +; Control the code coverage deglitching period. A period of 0, eliminates delta +; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a +; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". +; CoverDeglitchPeriod = 0 + +; Use this directory for compiler temporary files instead of "work/_temp" +; CompilerTempDir = /tmp + +; Set this to cause the compilers to force data to be committed to disk +; when the files are closed. +; SyncCompilerFiles = 1 + +; Add VHDL-AMS declarations to package STANDARD +; Default is not to add +; AmsStandard = 1 + +; Range and length checking will be performed on array indices and discrete +; ranges, and when violations are found within subprograms, errors will be +; reported. Default is to issue warnings for violations, because subprograms +; may not be invoked. +; NoDeferSubpgmCheck = 0 + +; Turn ON detection of FSMs having single bit current state variable. +; FsmSingle = 1 + +; Turn off reset state transitions in FSM. +; FsmResetTrans = 0 + +; Turn ON detection of FSM Implicit Transitions. +; FsmImplicitTrans = 1 + +; Controls whether or not to show immediate assertions with constant expressions +; in GUI/report/UCDB etc. By default, immediate assertions with constant +; expressions are shown in GUI/report/UCDB etc. This does not affect +; evaluation of immediate assertions. +; ShowConstantImmediateAsserts = 0 + +; Controls how VHDL basic identifiers are stored with the design unit. +; Does not make the language case-sensitive, affects only how declarations +; declared with basic identifiers have their names stored and printed +; (in the GUI, examine, etc.). +; Default is to preserve the case as originally depicted in the VHDL source. +; Value of 0 indicates to change all basic identifiers to lower case. +; PreserveCase = 0 + +; For Configuration Declarations, controls the effect that USE clauses have +; on visibility inside the configuration items being configured. If 1 +; (the default), then use pre-10.0 behavior. If 0, then for stricter LRM-compliance, +; extend the visibility of objects made visible through USE clauses into nested +; component configurations. +; OldVHDLConfigurationVisibility = 0 + +; Allows VHDL configuration declarations to be in a different library from +; the corresponding configured entity. Default is to not allow this for +; stricter LRM-compliance. +; SeparateConfigLibrary = 1; + +; Determine how mode OUT subprogram parameters of type array and record are treated. +; If 0 (the default), then only VHDL 2008 will do this initialization. +; If 1, always initialize the mode OUT parameter to its default value. +; If 2, do not initialize the mode OUT out parameter. +; Note that prior to release 10.1, all language versions did not initialize mode +; OUT array and record type parameters, unless overridden here via this mechanism. +; In release 10.1 and later, only files compiled with VHDL 2008 will cause this +; initialization, unless overridden here. +; InitOutCompositeParam = 0 + +; Generate symbols debugging database in only some special cases to save on +; the number of files in the library. For other design-units, this database is +; generated on-demand in vsim. +; Default is to to generate debugging database for all design-units. +; SmartDbgSym = 1 + +; Enable or disable automatic creation of missing libraries. +; Default is 1 (enabled) +; CreateLib = 1 + +; Describe compilation options according to matching file patterns. +; File pattern * matches all printing characters other than '/'. +; File pattern **/x matches all paths containing file/directory x. +; File pattern x/** matches all paths beginning at directory x. +; FileOptMap = (**/*.vhd => -2008); + +; Describe library targets of compilation according to matching file patterns. +; LibMap = (**/*.vhd => work); + +; Enable or Disable Auto-order compilation. +; Default is 0 (disabled) +; Autoorder = 0 + +[vlog] +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on Verilog hazard checking (order-dependent accessing of global vars). +; Default is off. +; Hazard = 1 + +; Turn on converting regular Verilog identifiers to uppercase. Allows case +; insensitivity for module names. Default is no conversion. +; UpCase = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn on bad option warning. Default is off. +; Show_BadOptionWarning = 1 + +; Revert back to IEEE 1364-1995 syntax, default is 0 (off). +; vlog95compat = 1 + +; Turn off PSL warning messages. Default is to show warnings. +; Show_PslChecksWarnings = 0 + +; Enable parsing of embedded PSL assertions. Default is enabled. +; EmbeddedPsl = 0 + +; Enable compiler statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list,kb] +; Add '-' to disable specific statistics. Default is [time,cmd,msg]. +; Stats = time,cmd,msg + +; Check vlog plusargs. Default is 0 (off). +; The command line equivalent is -check_plusargs <number>. +; 0 = Don't check plusargs (this is the default) +; 1 = Warning on unrecognized plusarg +; 2 = Error and exit on unrecognized plusarg +; CheckPlusargs = 1 + +; Set the threshold for automatically identifying sparse Verilog memories. +; A memory with total size in bytes equal to or more than the sparse memory +; threshold gets marked as sparse automatically, unless specified otherwise +; in source code or by the +nosparse commandline option of vlog or vopt. +; The default is 1M. (i.e. memories with total size equal +; to or greater than 1Mb are marked as sparse) +; SparseMemThreshold = 1048576 + +; Set the prefix to be honored for synthesis and coverage pragma recognition. +; Default is "". +; AddPragmaPrefix = "" + +; Ignore synthesis and coverage pragmas with this prefix. +; Default is "". +; IgnorePragmaPrefix = "" + +; Set the option to treat all files specified in a vlog invocation as a +; single compilation unit. The default value is set to 0 which will treat +; each file as a separate compilation unit as specified in the P1800 draft standard. +; MultiFileCompilationUnit = 1 + +; Turn on code coverage in Verilog design units. Default is off. +; Coverage = sbceft + +; Automatically exclude Verilog case statement default branches. +; Default is to not automatically exclude defaults. +; CoverExcludeDefault = 1 + +; Increase or decrease the maximum number of rows allowed in a UDP table +; implementing a VHDL condition coverage or expression coverage expression. +; More rows leads to a longer compile time, but more expressions covered. +; CoverMaxUDPRows = 192 + +; Increase or decrease the maximum number of input patterns that are present +; in FEC table. This leads to a longer compile time with more expressions +; covered with FEC metric. +; CoverMaxFECRows = 192 + +; Enable Multi Bit Expression Coverage in a Design, If design has expression with +; multi bit operands, this option enables its Expression Coverage. +; The default value is 0. +; CoverFecMultiBit = 1 + +; Increase or decrease the limit on the size of expressions and conditions +; considered for expression and condition coverages. Higher FecUdpEffort leads +; to higher compile, optimize and simulation time, but more expressions and +; conditions are considered for coverage in the design. FecUdpEffort can +; be set to a number ranging from 1 (low) to 3 (high), defined as: +; 1 - (low) Only small expressions and conditions considered for coverage. +; 2 - (medium) Bigger expressions and conditions considered for coverage. +; 3 - (high) Very large expressions and conditions considered for coverage. +; The default setting is 1 (low). +; FecUdpEffort = 1 + +; Enable or disable Focused Expression Coverage analysis for conditions and +; expressions. Focused Expression Coverage data is provided by default when +; expression and/or condition coverage is active. +; CoverFEC = 0 + +; Enable or disable UDP Coverage analysis for conditions and expressions. +; UDP Coverage data is disabled by default when expression and/or condition +; coverage is active. +; CoverUDP = 1 + +; Enable or disable Rapid Expression Coverage mode for conditions and expressions. +; Disabling this would convert non-masking conditions in FEC tables to matching +; input patterns. +; CoverREC = 1 + +; Enable or disable bit-blasting multi-bit operands of reduction prefix expressions +; for expression/condition coverage. +; NOTE: Enabling this may have a negative impact on simulation performance. +; CoverExpandReductionPrefix = 0 + +; Enable or disable short circuit evaluation of conditions and expressions when +; condition or expression coverage is active. Short circuit evaluation is enabled +; by default. +; CoverShortCircuit = 0 + +; Enable deglitching of code coverage in combinatorial, non-clocked, processes. +; Default is no deglitching. +; CoverDeglitchOn = 1 + +; Control the code coverage deglitching period. A period of 0, eliminates delta +; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a +; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". +; CoverDeglitchPeriod = 0 + +; Turn on code coverage in VLOG `celldefine modules, modules containing +; specify blocks, and modules included using vlog -v and -y. Default is off. +; CoverCells = 1 + +; Enable code coverage reporting of code that has been optimized away. +; The default is not to report. +; CoverReportCancelled = 1 + +; Control compiler and VOPT optimizations that are allowed when +; code coverage is on. This is a number from 0 to 5, with the following +; meanings (the default is 3): +; 5 -- All allowable optimizations are on. +; 4 -- Turn off removing unreferenced code. +; 3 -- Turn off process, always block and if statement merging. +; 2 -- Turn off expression optimization, converting primitives +; to continuous assignments, VHDL subprogram inlining. +; and VHDL clkOpt (converting FF's to builtins). +; 1 -- Turn off continuous assignment optimizations and clock suppression. +; 0 -- Turn off Verilog module inlining and VHDL arch inlining. +; HOWEVER, if fsm coverage is turned on, optimizations will be forced to +; level 3, with also turning off converting primitives to continuous assigns. +; CoverOpt = 3 + +; Specify the override for the default value of "cross_num_print_missing" +; option for the Cross in Covergroups. If not specified then LRM default +; value of 0 (zero) is used. This is a compile time option. +; SVCrossNumPrintMissingDefault = 0 + +; Setting following to 1 would cause creation of variables which +; would represent the value of Coverpoint expressions. This is used +; in conjunction with "SVCoverpointExprVariablePrefix" option +; in the modelsim.ini +; EnableSVCoverpointExprVariable = 0 + +; Specify the override for the prefix used in forming the variable names +; which represent the Coverpoint expressions. This is used in conjunction with +; "EnableSVCoverpointExprVariable" option of the modelsim.ini +; The default prefix is "expr". +; The variable name is +; variable name => <prefix>_<coverpoint name> +; SVCoverpointExprVariablePrefix = expr + +; Override for the default value of the SystemVerilog covergroup, +; coverpoint, and cross option.goal (defined to be 100 in the LRM). +; NOTE: It does not override specific assignments in SystemVerilog +; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal" +; in the [vsim] section can override this value. +; SVCovergroupGoalDefault = 100 + +; Override for the default value of the SystemVerilog covergroup, +; coverpoint, and cross type_option.goal (defined to be 100 in the LRM) +; NOTE: It does not override specific assignments in SystemVerilog +; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal" +; in the [vsim] section can override this value. +; SVCovergroupTypeGoalDefault = 100 + +; Specify the override for the default value of "strobe" option for the +; Covergroup Type. This is a compile time option which forces "strobe" to +; a user specified default value and supersedes SystemVerilog specified +; default value of '0'(zero). NOTE: This can be overriden by a runtime +; modelsim.ini variable "SVCovergroupStrobe" in the [vsim] section. +; SVCovergroupStrobeDefault = 0 + +; Specify the override for the default value of "per_instance" option for the +; Covergroup variables. This is a compile time option which forces "per_instance" +; to a user specified default value and supersedes SystemVerilog specified +; default value of '0'(zero). +; SVCovergroupPerInstanceDefault = 0 + +; Specify the override for the default value of "get_inst_coverage" option for the +; Covergroup variables. This is a compile time option which forces +; "get_inst_coverage" to a user specified default value and supersedes +; SystemVerilog specified default value of '0'(zero). +; SVCovergroupGetInstCoverageDefault = 0 + +; +; A space separated list of resource libraries that contain precompiled +; packages. The behavior is identical to using the "-L" switch. +; +; LibrarySearchPath = <path/lib> [<path/lib> ...] +LibrarySearchPath = mtiAvm mtiRnm mtiOvm mtiUvm mtiUPF infact + +; The behavior is identical to the "-mixedansiports" switch. Default is off. +; MixedAnsiPorts = 1 + +; Enable SystemVerilog 3.1a $typeof() function. Default is off. +; EnableTypeOf = 1 + +; Only allow lower case pragmas. Default is disabled. +; AcceptLowerCasePragmaOnly = 1 + +; Set the maximum depth permitted for a recursive include file nesting. +; IncludeRecursionDepthMax = 5 + +; Turn ON detection of FSMs having single bit current state variable. +; FsmSingle = 1 + +; Turn off reset state transitions in FSM. +; FsmResetTrans = 0 + +; Turn off detections of FSMs having x-assignment. +; FsmXAssign = 0 + +; Turn ON detection of FSM Implicit Transitions. +; FsmImplicitTrans = 1 + +; List of file suffixes which will be read as SystemVerilog. White space +; in extensions can be specified with a back-slash: "\ ". Back-slashes +; can be specified with two consecutive back-slashes: "\\"; +; SvFileSuffixes = sv svp svh + +; This setting is the same as the vlog -sv command line switch. +; Enables SystemVerilog features and keywords when true (1). +; When false (0), the rules of IEEE Std 1364-2005 are followed and +; SystemVerilog keywords are ignored. +; Svlog = 0 + +; Prints attribute placed upon SV packages during package import +; when true (1). The attribute will be ignored when this +; entry is false (0). The attribute name is "mti_design_element_load_message". +; The value of this attribute is a string literal. +; Default is true (1). +; PrintSVPackageLoadingAttribute = 1 + +; Do not show immediate assertions with constant expressions in +; GUI/reports/UCDB etc. By default immediate assertions with constant +; expressions are shown in GUI/reports/UCDB etc. This does not affect +; evaluation of immediate assertions. +; ShowConstantImmediateAsserts = 0 + +; Controls if untyped parameters that are initialized with values greater +; than 2147483647 are mapped to generics of type INTEGER or ignored. +; If mapped to VHDL Integers, values greater than 2147483647 +; are mapped to negative values. +; Default is to map these parameter to generic of type INTEGER +; ForceUnsignedToVHDLInteger = 1 + +; Enable AMS wreal (wired real) extensions. Default is 0. +; WrealType = 1 + +; Controls SystemVerilog Language Extensions. These options enable +; some non-LRM compliant behavior. +; SvExtensions = [+|-]<extension>[,[+|-]<extension>]* + +; Generate symbols debugging database in only some special cases to save on +; the number of files in the library. For other design-units, this database is +; generated on-demand in vsim. +; Default is to to generate debugging database for all design-units. +; SmartDbgSym = 1 + +; Controls how $unit library entries are named. Valid options are: +; "file" (generate name based on the first file on the command line) +; "du" (generate name based on first design unit following an item +; found in $unit scope) +; CUAutoName = file + +; Enable or disable automatic creation of missing libraries. +; Default is 1 (enabled) +; CreateLib = 1 + +; Enable generating a warning when a module is overwritten in different vlog sessions in case +; the RTL source files are different. +; Default is 0 (disabled) +; WarnDuOverwrite = 1 + +[sccom] +; Enable use of SCV include files and library. Default is off. +; UseScv = 1 + +; Add C++ compiler options to the sccom command line by using this variable. +; CppOptions = -g + +; Use custom C++ compiler located at this path rather than the default path. +; The path should point directly at a compiler executable. +; CppPath = /usr/bin/g++ + +; Specify the compiler version from the list of support GNU compilers. +; examples 4.7.4, 5.3.0, 7.4.0 +; CppInstall = 7.4.0 + +; Enable verbose messages from sccom. Default is off. +; SccomVerbose = 1 + +; sccom logfile. Default is no logfile. +; SccomLogfile = sccom.log + +; Enable use of SC_MS include files and library. Default is off. +; UseScMs = 1 + +; Enable compiler statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list,kb] +; Add '-' to disable specific statistics. Default is [time,cmd,msg]. +; Stats = time,cmd,msg + +; Enable or disable automatic creation of missing libraries. +; Default is 1 (enabled) +; CreateLib = 1 + +; Enable use of UVMC library. Default is off. +; UseUvmc = 1 + +[vopt] +; Check vopt plusargs. Default is 0 (off). +; The command line equivalent is -check_plusargs <number>. +; 0 = Don't check plusargs (this is the default) +; 1 = Warning on unrecognized plusarg +; 2 = Error and exit on unrecognized plusarg +; CheckPlusargs = 1 + +; Turn on code coverage in vopt. Default is off. +; Coverage = sbceft + +; enable or disable param saving in UCDB. +; CoverageSaveParam = 0 + +; Control compiler optimizations that are allowed when +; code coverage is on. Refer to the comment for this in the [vlog] area. +; CoverOpt = 3 + +; Controls set of CoverConstructs that are being considered for Coverage +; Collection. +; Some of Valid options are: default,set1,set2 +; Covermode = default + +; Override all PA VOPT and VSIM commands to run simulation in Non-PA mode. +; NonPAmode = 1 + +; Controls set of HDL cover constructs that would be considered(or not considered) +; for Coverage Collection. (Default corresponds to covermode default). +; Some of Valid options are: "ca", "citf", "cifl", "tcint", "fsmqs". +; Coverconstruct = noca,nocitf,nofsmtf,nofsmds,noctes,nocicl,nocprc,nocfl,nofsmup,nocifl,nocpm,notcint,nocpkg,nocsva + +; Increase or decrease the maximum number of rows allowed in a UDP table +; implementing a VHDL condition coverage or expression coverage expression. +; More rows leads to a longer compile time, but more expressions covered. +; CoverMaxUDPRows = 192 + +; Increase or decrease the maximum number of input patterns that are present +; in FEC table. This leads to a longer compile time with more expressions +; covered with FEC metric. +; CoverMaxFECRows = 192 + +; Enable Multi Bit Expression Coverage in a Design, If design has expression with +; multi bit operands, this option enables its Expression Coverage. +; The default value is 0. +; CoverFecMultiBit = 1 + +; Increase or decrease the limit on the size of expressions and conditions +; considered for expression and condition coverages. Higher FecUdpEffort leads +; to higher compile, optimize and simulation time, but more expressions and +; conditions are considered for coverage in the design. FecUdpEffort can +; be set to a number ranging from 1 (low) to 3 (high), defined as: +; 1 - (low) Only small expressions and conditions considered for coverage. +; 2 - (medium) Bigger expressions and conditions considered for coverage. +; 3 - (high) Very large expressions and conditions considered for coverage. +; The default setting is 1 (low). +; FecUdpEffort = 1 + +; Enable code coverage reporting of code that has been optimized away. +; The default is not to report. +; CoverReportCancelled = 1 + +; Enable deglitching of code coverage in combinatorial, non-clocked, processes. +; Default is no deglitching. +; CoverDeglitchOn = 1 + +; Enable compiler statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list,kb] +; Add '-' to disable specific statistics. Default is [time,cmd,msg]. +; Stats = time,cmd,msg + +; Control the code coverage deglitching period. A period of 0, eliminates delta +; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a +; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". +; CoverDeglitchPeriod = 0 + +; Do not show immediate assertions with constant expressions in +; GUI/reports/UCDB etc. By default immediate assertions with constant +; expressions are shown in GUI/reports/UCDB etc. This does not affect +; evaluation of immediate assertions. +; ShowConstantImmediateAsserts = 0 + +; Set the maximum number of iterations permitted for a generate loop. +; Restricting this permits the implementation to recognize infinite +; generate loops. +; GenerateLoopIterationMax = 100000 + +; Set the maximum depth permitted for a recursive generate instantiation. +; Restricting this permits the implementation to recognize infinite +; recursions. +; GenerateRecursionDepthMax = 200 + +; Set the number of processes created during the code generation phase. +; By default a heuristic is used to set this value. This may be set to 0 +; to disable this feature completely. +; ParallelJobs = 0 + +; Controls SystemVerilog Language Extensions. These options enable +; some non-LRM compliant behavior. +; SvExtensions = [+|-]<extension>[,[+|-]<extension>]* + +; Load the specified shared objects with the RTLD_GLOBAL flag. +; This gives global visibility to all symbols in the shared objects, +; meaning that subsequently loaded shared objects can bind to symbols +; in the global shared objects. The list of shared objects should +; be whitespace delimited. This option is not supported on the +; Windows or AIX platforms. +; GlobalSharedObjectList = example1.so example2.so example3.so + +; Disable SystemVerilog elaboration system task messages +; IgnoreSVAInfo = 1 +; IgnoreSVAWarning = 1 +; IgnoreSVAError = 1 +; IgnoreSVAFatal = 1 + +; Enable or disable automatic creation of missing libraries. +; Default is 1 (enabled) +; CreateLib = 1 + +[vsim] +; vopt flow +; Set to turn on automatic optimization of a design. +; Default is on +VoptFlow = 1 + +; Simulator resolution +; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. +Resolution = ns + +; Disable certain code coverage exclusions automatically. +; Assertions and FSM are exluded from the code coverage by default +; Set AutoExclusionsDisable = fsm to enable code coverage for fsm +; Set AutoExclusionsDisable = assertions to enable code coverage for assertions +; Set AutoExclusionsDisable = all to enable code coverage for all the automatic exclusions +; Or specify comma or space separated list +;AutoExclusionsDisable = fsm,assertions + +; User time unit for run commands +; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the +; unit specified for Resolution. For example, if Resolution is 100ps, +; then UserTimeUnit defaults to ps. +; Should generally be set to default. +UserTimeUnit = default + +; Default run length +RunLength = 50 us + +; Maximum iterations that can be run without advancing simulation time +IterationLimit = 10000000 + +; Specify libraries to be searched for precompiled modules +; LibrarySearchPath = <path/lib> [<path/lib> ...] + +; Set XPROP assertion fail limit. Default is 5. +; Any positive integer, -1 for infinity. +; XpropAssertionLimit = 5 + +; Control PSL and Verilog Assume directives during simulation +; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts +; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts +; SimulateAssumeDirectives = 1 + +; Control the simulation of PSL and SVA +; These switches can be overridden by the vsim command line switches: +; -psl, -nopsl, -sva, -nosva. +; Set SimulatePSL = 0 to disable PSL simulation +; Set SimulatePSL = 1 to enable PSL simulation (default) +; SimulatePSL = 1 +; Set SimulateSVA = 0 to disable SVA simulation +; Set SimulateSVA = 1 to enable concurrent SVA simulation (default) +; SimulateSVA = 1 + +; Control SVA and VHDL immediate assertion directives during simulation +; Set SimulateImmedAsserts = 0 to disable simulation of immediate asserts +; Set SimulateImmedAsserts = 1 to enable simulation of immediate asserts +; SimulateImmedAsserts = 1 + +; License feature mappings for Verilog and VHDL +; qhsimvh Single language VHDL license +; qhsimvl Single language Verilog license +; msimhdlsim Language neutral license for either Verilog or VHDL +; msimhdlmix Second language only, language neutral license for either +; Verilog or VHDL +; +; Directives to license manager can be set either as single value or as +; space separated multi-values: +; vhdl Immediately checkout and hold a VHDL license (i.e., one of +; qhsimvh, msimhdlsim, or msimhdlmix) +; vlog Immediately checkout and hold a Verilog license (i.e., one of +; qhsimvl, msimhdlsim, or msimhdlmix) +; plus Immediately checkout and hold a VHDL license and a Verilog license +; noqueue Do not wait in the license queue when a license is not available +; viewsim Try for viewer license but accept simulator license(s) instead +; of queuing for viewer license (PE ONLY) +; noviewer Disable checkout of msimviewer license feature (PE ONLY) +; noslvhdl Disable checkout of qhsimvh license feature +; noslvlog Disable checkout of qhsimvl license feature +; nomix Disable checkout of msimhdlmix license feature +; nolnl Disable checkout of msimhdlsim license feature +; mixedonly Disable checkout of qhsimvh and qhsimvl license features +; lnlonly Disable checkout of qhsimvh,qhsimvl, and msimhdlmix license features +; +; Examples (remove ";" comment character to activate licensing directives): +; Single directive: +; License = plus +; Multi-directive (Note: space delimited directives): +; License = noqueue plus + +; Severity level of a VHDL assertion message or of a SystemVerilog severity system task +; which will cause a running simulation to stop. +; VHDL assertions and SystemVerilog severity system task that occur with the +; given severity or higher will cause a running simulation to stop. +; This value is ignored during elaboration. +; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal +BreakOnAssertion = 3 + +; Severity level of a tool message which will cause a running simulation to +; stop. This value is ignored during elaboration. Default is to not break. +; 0 = Note 1 = Warning 2 = Error 3 = Fatal +;BreakOnMessage = 2 + +; The class debug feature enables more visibility and tracking of class instances +; during simulation. By default this feature is disabled (0). To enable this +; feature set ClassDebug to 1. +; ClassDebug = 1 + +; Message Format conversion specifications: +; %S - Severity Level of message/assertion +; %R - Text of message +; %T - Time of message +; %D - Delta value (iteration number) of Time +; %K - Kind of path: Instance/Region/Signal/Process/Foreign Process/Unknown/Protected +; %i - Instance/Region/Signal pathname with Process name (if available) +; %I - shorthand for one of these: +; " %K: %i" +; " %K: %i File: %F" (when path is not Process or Signal) +; except that the %i in this case does not report the Process name +; %O - Process name +; %P - Instance/Region path without leaf process +; %F - File name +; %L - Line number; if assertion message, then line number of assertion or, if +; assertion is in a subprogram, line from which the call is made +; %u - Design unit name in form library.primary +; %U - Design unit name in form library.primary(secondary) +; %% - The '%' character itself +; +; If specific format for Severity Level is defined, use that format. +; Else, for a message that occurs during elaboration: +; -- Failure/Fatal message in VHDL region that is not a Process, and in +; certain non-VHDL regions, uses MessageFormatBreakLine; +; -- Failure/Fatal message otherwise uses MessageFormatBreak; +; -- Note/Warning/Error message uses MessageFormat. +; Else, for a message that occurs during runtime and triggers a breakpoint because +; of the BreakOnAssertion setting: +; -- if in a VHDL region that is not a Process, uses MessageFormatBreakLine; +; -- otherwise uses MessageFormatBreak. +; Else (a runtime message that does not trigger a breakpoint) uses MessageFormat. +; +; MessageFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n" +; MessageFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n" +; MessageFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormatBreakLine = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F Line: %L\n" +; MessageFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" + +; Error File - alternate file for storing error messages +; ErrorFile = error.log + +; Simulation Breakpoint messages +; This flag controls the display of function names when reporting the location +; where the simulator stops because of a breakpoint or fatal error. +; Example with function name: # Break in Process ctr at counter.vhd line 44 +; Example without function name: # Break at counter.vhd line 44 +; Default value is 1. +ShowFunctions = 1 + +; Default radix for all windows and commands. +; Radix may be one of: symbolic, ascii, binary, octal, decimal, hex, unsigned +; Flags may be one of: enumnumeric, showbase, wreal +DefaultRadix = hexadecimal +DefaultRadixFlags = showbase +; Set to 1 for make the signal_force VHDL and Verilog functions use the +; default radix when processing the force value. Prior to 10.2 signal_force +; used the default radix, now it always uses symbolic unless value explicitly indicates base +;SignalForceFunctionUseDefaultRadix = 0 + +; VSIM Startup command +; Startup = do startup.do + +; VSIM Shutdown file +; Filename to save u/i formats and configurations. +; ShutdownFile = restart.do +; To explicitly disable auto save: +; ShutdownFile = --disable-auto-save + +; Run simulator in batch mode as if -batch were specified on the command line if none of -c, -gui, or -i specified. +; Simulator runs in interactive mode as if -i were specified if this option is 0. Default is 0. +; BatchMode = 1 + +; File for saving command transcript when -batch option used +; This option is ignored when -c, -gui, or -i options are used or if BatchMode above is zero +; default is unset so command transcript only goes to stdout for better performance +; BatchTranscriptFile = transcript + +; File for saving command transcript, this option is ignored when -batch option is used +TranscriptFile = transcript + +; Transcript file long line wrapping mode(s) +; mode == 0 :: no wrapping, line recorded as is +; mode == 1 :: wrap at first whitespace after WSColumn +; or at Column. +; mode == 2 :: wrap as above, but add continuation +; character ('\') at end of each wrapped line +; +; WrapMode = 0 +; WrapColumn = 30000 +; WrapWSColumn = 27000 + +; File for saving command history +; CommandHistory = cmdhist.log + +; Specify whether paths in simulator commands should be described +; in VHDL or Verilog format. +; For VHDL, PathSeparator = / +; For Verilog, PathSeparator = . +; Must not be the same character as DatasetSeparator. +PathSeparator = / + +; Specify the dataset separator for fully rooted contexts. +; The default is ':'. For example: sim:/top +; Must not be the same character as PathSeparator. +DatasetSeparator = : + +; Specify a unique path separator for the Signal Spy set of functions. +; The default will be to use the PathSeparator variable. +; Must not be the same character as DatasetSeparator. +; SignalSpyPathSeparator = / + +; Used to control parsing of HDL identifiers input to the tool. +; This includes CLI commands, vsim/vopt/vlog/vcom options, +; string arguments to FLI/VPI/DPI calls, etc. +; If set to 1, accept either Verilog escaped Id syntax or +; VHDL extended id syntax, regardless of source language. +; If set to 0, the syntax of the source language must be used. +; Each identifier in a hierarchical name may need different syntax, +; e.g. "/top/\vhdl*ext*id\/middle/\vlog*ext*id /bottom" or +; "top.\vhdl*ext*id\.middle.\vlog*ext*id .bottom" +; GenerousIdentifierParsing = 1 + +; Disable VHDL assertion messages +; IgnoreNote = 1 +; IgnoreWarning = 1 +; IgnoreError = 1 +; IgnoreFailure = 1 + +; Disable SystemVerilog assertion messages +; IgnoreSVAInfo = 1 +; IgnoreSVAWarning = 1 +; IgnoreSVAError = 1 +; IgnoreSVAFatal = 1 + +; Do not print any additional information from Severity System tasks. +; Only the message provided by the user is printed along with severity +; information. +; SVAPrintOnlyUserMessage = 1; + +; Default force kind. May be freeze, drive, deposit, or default +; or in other terms, fixed, wired, or charged. +; A value of "default" will use the signal kind to determine the +; force kind, drive for resolved signals, freeze for unresolved signals +; DefaultForceKind = freeze + +; Control the iteration of events when a VHDL signal is forced to a value +; This flag can be set to honour the signal update event in next iteration, +; the default is to update and propagate in the same iteration. +; ForceSigNextIter = 1 + +; Enable simulation statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list,kb,eor] +; Add '-' to disable specific statistics. Default is [time,cmd,msg]. +; Stats = time,cmd,msg + +; If zero, open files when elaborated; otherwise, open files on +; first read or write. Default is 0. +; DelayFileOpen = 1 + +; Control VHDL files opened for write. +; 0 = Buffered, 1 = Unbuffered +UnbufferedOutput = 0 + +; Control the number of VHDL files open concurrently. +; This number should always be less than the current ulimit +; setting for max file descriptors. +; 0 = unlimited +ConcurrentFileLimit = 40 + +; If nonzero, close files as soon as there is either an explicit call to +; file_close, or when the file variable's scope is closed. When zero, a +; file opened in append mode is not closed in case it is immediately +; reopened in append mode; otherwise, the file will be closed at the +; point it is reopened. +; AppendClose = 1 + +; Control the number of hierarchical regions displayed as +; part of a signal name shown in the Wave window. +; A value of zero tells VSIM to display the full name. +; The default is 0. +; WaveSignalNameWidth = 0 + +; Turn off warnings when changing VHDL constants and generics +; Default is 1 to generate warning messages +; WarnConstantChange = 0 + +; Turn off warnings from accelerated versions of the std_logic_arith, +; std_logic_unsigned, and std_logic_signed packages. +; StdArithNoWarnings = 1 + +; Turn off warnings from accelerated versions of the IEEE numeric_std +; and numeric_bit packages. +; NumericStdNoWarnings = 1 + +; Use old-style (pre-6.6) VHDL FOR GENERATE statement iteration names +; in the design hierarchy. +; This style is controlled by the value of the GenerateFormat +; value described next. Default is to use new-style names, which +; comprise the generate statement label, '(', the value of the generate +; parameter, and a closing ')'. +; Set this to 1 to use old-style names. +; OldVhdlForGenNames = 1 + +; Control the format of the old-style VHDL FOR generate statement region +; name for each iteration. Do not quote the value. +; The format string here must contain the conversion codes %s and %d, +; in that order, and no other conversion codes. The %s represents +; the generate statement label; the %d represents the generate parameter value +; at a particular iteration (this is the position number if the generate parameter +; is of an enumeration type). Embedded whitespace is allowed (but discouraged); +; leading and trailing whitespace is ignored. +; Application of the format must result in a unique region name over all +; loop iterations for a particular immediately enclosing scope so that name +; lookup can function properly. The default is %s__%d. +; GenerateFormat = %s__%d + +; Enable more efficient logging of VHDL Variables. +; Logging VHDL variables without this enabled, while possible, is very +; inefficient. Enabling this will provide a more efficient logging methodology +; at the expense of more memory usage. By default this feature is disabled (0). +; To enabled this feature, set this variable to 1. +; VhdlVariableLogging = 1 + +; Enable logging of VHDL access type variables and their designated objects. +; This setting will allow both variables of an access type ("access variables") +; and their designated objects ("access objects") to be logged. Logging a +; variable of an access type will automatically also cause the designated +; object(s) of that variable to be logged as the simulation progresses. +; Further, enabling this allows access objects to be logged by name. By default +; this feature is disabled (0). To enable this feature, set this variable to 1. +; Enabling this will automatically enable the VhdlVariableLogging feature also. +; AccessObjDebug = 1 + +; Make each VHDL package in a PDU has its own separate copy of the package instead +; of sharing the package between PDUs. The default is to share packages. +; To ensure that each PDU has its own set of packages, set this variable to 1. +; VhdlSeparatePduPackage = 1 + +; Specify whether checkpoint files should be compressed. +; The default is 1 (compressed). +; CheckpointCompressMode = 0 + +; Specify gcc compiler used in the compilation of automatically generated DPI exportwrapper. +; Use custom gcc compiler located at this path rather than the default path. +; The path should point directly at a compiler executable. +; DpiCppPath = <your-gcc-installation>/bin/gcc +; +; Specify the compiler version from the list of support GNU compilers. +; examples 4.7.4, 5.3.0, 7.4.0 +; DpiCppInstall = 7.4.0 + +; Specify whether to enable SystemVerilog DPI "out-of-the-blue" calls. +; The term "out-of-the-blue" refers to SystemVerilog export function calls +; made from C functions that don't have the proper context setup +; (as is the case when running under "DPI-C" import functions). +; When this is enabled, one can call a DPI export function +; (but not task) from any C code. +; the setting of this variable can be one of the following values: +; 0 : dpioutoftheblue call is disabled (default) +; 1 : dpioutoftheblue call is enabled, but export call debug support is not available. +; 2 : dpioutoftheblue call is enabled, and limited export call debug support is available. +; DpiOutOfTheBlue = 1 + +; Specify whether continuous assignments are run before other normal priority +; processes scheduled in the same iteration. This event ordering minimizes race +; differences between optimized and non-optimized designs, and is the default +; behavior beginning with the 6.5 release. For pre-6.5 event ordering, set +; ImmediateContinuousAssign to 0. +; The default is 1 (enabled). +; ImmediateContinuousAssign = 0 + +; List of dynamically loaded objects for Verilog PLI applications +; Veriuser = veriuser.sl + +; Which default VPI object model should the tool conform to? +; The 1364 modes are Verilog-only, for backwards compatibility with older +; libraries, and SystemVerilog objects are not available in these modes. +; +; In the absence of a user-specified default, the tool default is the +; latest available LRM behavior. +; Options for PliCompatDefault are: +; VPI_COMPATIBILITY_VERSION_1364v1995 +; VPI_COMPATIBILITY_VERSION_1364v2001 +; VPI_COMPATIBILITY_VERSION_1364v2005 +; VPI_COMPATIBILITY_VERSION_1800v2005 +; VPI_COMPATIBILITY_VERSION_1800v2008 +; +; Synonyms for each string are also recognized: +; VPI_COMPATIBILITY_VERSION_1364v1995 (1995, 95, 1364v1995, 1364V1995, VL1995) +; VPI_COMPATIBILITY_VERSION_1364v2001 (2001, 01, 1364v2001, 1364V2001, VL2001) +; VPI_COMPATIBILITY_VERSION_1364v2005 (1364v2005, 1364V2005, VL2005) +; VPI_COMPATIBILITY_VERSION_1800v2005 (2005, 05, 1800v2005, 1800V2005, SV2005) +; VPI_COMPATIBILITY_VERSION_1800v2008 (2008, 08, 1800v2008, 1800V2008, SV2008) + + +; PliCompatDefault = VPI_COMPATIBILITY_VERSION_1800v2005 + +; Specify whether the Verilog system task $fopen or vpi_mcd_open() +; will create directories that do not exist when opening the file +; in "a" or "w" mode. +; The default is 0 (do not create non-existent directories) +; CreateDirForFileAccess = 1 + +; Specify default options for the restart command. Options can be one +; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions +; DefaultRestartOptions = -force + + +; Specify default UVM-aware debug options if the vsim -uvmcontrol switch is not used. +; Valid options include: all, none, verbose, disable, struct, reseed, msglog, trlog, certe. +; Options can be enabled by just adding the name, or disabled by prefixing the option with a "-". +; The list of options must be delimited by commas, without spaces or tabs. +; +; Some examples +; To turn on all available UVM-aware debug features: +; UVMControl = all +; To turn on the struct window, mesage logging, and transaction logging: +; UVMControl = struct,msglog,trlog +; To turn on all options except certe: +; UVMControl = all,-certe +; To completely disable all UVM-aware debug functionality: +; UVMControl = disable + +; Specify the WildcardFilter setting. +; A space separated list of object types to be excluded when performing +; wildcard matches with log, wave, etc commands. The default value for this variable is: +; "Variable Constant Generic Parameter SpecParam Memory Assertion Cover Endpoint ScVariable CellInternal ImmediateAssert VHDLFile" +; See "Using the WildcardFilter Preference Variable" in the documentation for +; details on how to use this variable and for descriptions of the filter types. +WildcardFilter = Variable Constant Generic Parameter SpecParam Memory Assertion Cover Endpoint ScVariable CellInternal ImmediateAssert VHDLFile + +; Specify the WildcardSizeThreshold setting. +; This integer setting specifies the size at which objects will be excluded when +; performing wildcard matches with log, wave, etc commands. Objects of size equal +; to or greater than the WildcardSizeThreshold will be filtered out from the wildcard +; matches. The size is a simple calculation of number of bits or items in the object. +; The default value is 8k (8192). Setting this value to 0 will disable the checking +; of object size against this threshold and allow all objects of any size to be logged. +WildcardSizeThreshold = 8192 + +; Specify whether warning messages are output when objects are filtered out due to the +; WildcardSizeThreshold. The default is 0 (no messages generated). +WildcardSizeThresholdVerbose = 0 + +; Turn on (1) or off (0) WLF file compression. +; The default is 1 (compress WLF file). +; WLFCompress = 0 + +; Specify whether to save all design hierarchy (1) in the WLF file +; or only regions containing logged signals (0). +; The default is 0 (save only regions with logged signals). +; WLFSaveAllRegions = 1 + +; WLF file time limit. Limit WLF file by time, as closely as possible, +; to the specified amount of simulation time. When the limit is exceeded +; the earliest times get truncated from the file. +; If both time and size limits are specified the most restrictive is used. +; UserTimeUnits are used if time units are not specified. +; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} +; WLFTimeLimit = 0 + +; WLF file size limit. Limit WLF file size, as closely as possible, +; to the specified number of megabytes. If both time and size limits +; are specified then the most restrictive is used. +; The default is 0 (no limit). +; WLFSizeLimit = 1000 + +; Specify whether or not a WLF file should be deleted when the +; simulation ends. A value of 1 will cause the WLF file to be deleted. +; The default is 0 (do not delete WLF file when simulation ends). +; WLFDeleteOnQuit = 1 + +; Specify whether or not a WLF file should be optimized during +; simulation. If set to 0, the WLF file will not be optimized. +; The default is 1, optimize the WLF file. +; WLFOptimize = 0 + +; Specify the name of the WLF file. +; The default is vsim.wlf +; WLFFilename = vsim.wlf + +; Specify whether to lock the WLF file. +; Locking the file prevents other invocations of ModelSim/Questa tools from +; inadvertently overwriting the WLF file. +; The default is 1, lock the WLF file. +; WLFFileLock = 0 + +; Specify the update interval for the WLF file in live simulation. +; The interval is given in seconds. +; The value is the smallest interval between WLF file updates. The WLF file +; will be flushed (updated) after (at least) the interval has elapsed, ensuring +; that the data is correct when viewed from a separate viewer. +; A value of 0 means that no updating will occur. +; The default value is 10 seconds. +; WLFUpdateInterval = 10 + +; Specify the WLF cache size limit for WLF files. +; The value is given in megabytes. A value of 0 turns off the cache. +; On non-Windows platforms the default WLFCacheSize setting is 2000 (megabytes). +; On Windows, the default value is 1000 (megabytes) to help to avoid filling +; process memory. +; WLFSimCacheSize allows a different cache size to be set for a live simulation +; WLF file, independent of post-simulation WLF file viewing. If WLFSimCacheSize +; is not set, it defaults to the WLFCacheSize value. +; WLFCacheSize = 2000 +; WLFSimCacheSize = 500 + +; Specify the WLF file event collapse mode. +; 0 = Preserve all events and event order. (same as -wlfnocollapse) +; 1 = Only record values of logged objects at the end of a simulator iteration. +; (same as -wlfcollapsedelta) +; 2 = Only record values of logged objects at the end of a simulator time step. +; (same as -wlfcollapsetime) +; The default is 1. +; WLFCollapseMode = 0 + +; Specify whether WLF file logging can use threads on multi-processor machines. +; If 0, no threads will be used; if 1, threads will be used if the system has +; more than one processor. +; WLFUseThreads = 1 + +; Specify the size of objects that will trigger "large object" messages +; at log/wave/list time. The size calculation of the object is the same as that +; used by the WildcardSizeThreshold. The default LargeObjectSize size is 500,000. +; Setting LargeObjectSize to 0 will disable these messages. +; LargeObjectSize = 500000 + +; Specify the depth of stack frames returned by $stacktrace([level]). +; This depth will be picked up when the optional 'level' argument +; is not specified or its value is not a positive integer. +; StackTraceDepth = 100 + +; Turn on/off undebuggable SystemC type warnings. Default is on. +; ShowUndebuggableScTypeWarning = 0 + +; Turn on/off unassociated SystemC name warnings. Default is off. +; ShowUnassociatedScNameWarning = 1 + +; Turn on/off SystemC IEEE 1666 deprecation warnings. Default is off. +; ScShowIeeeDeprecationWarnings = 1 + +; Turn on/off the check for multiple drivers on a SystemC sc_signal. Default is off. +; For SystemC-2.3.2 the valid values are 0,1 and 2 +; 0 = SC_SIGNAL_WRITE_CHECK_DISABLE_ +; 1 = SC_SIGNAL_WRITE_CHECK_DEFAULT_ +; 2 = SC_SIGNAL_WRITE_CHECK_CONFLICT_ +; For SystemC-2.2 the valid values are 0 and 1 +; 0 = DISABLE +; 1 = ENABLE +; ScEnableScSignalWriteCheck = 1 + +; Set SystemC default time unit. +; Set to fs, ps, ns, us, ms, or sec with optional +; prefix of 1, 10, or 100. The default is 1 ns. +; The ScTimeUnit value is honored if it is coarser than Resolution. +; If ScTimeUnit is finer than Resolution, it is set to the value +; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns, +; then the default time unit will be 1 ns. However if Resolution +; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns. +ScTimeUnit = ns + +; Set SystemC sc_main stack size. The stack size is set as an integer +; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or +; Gb(Giga-byte). Default is 10 Mb. The stack size for sc_main depends +; on the amount of data on the sc_main() stack and the memory required +; to succesfully execute the longest function call chain of sc_main(). +ScMainStackSize = 10 Mb + +; Set SystemC thread stack size. The stack size is set as an integer +; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or +; Gb(Giga-byte). The stack size for sc_thread depends +; on the amount of data on the sc_thread stack and the memory required +; to succesfully execute the thread. +; ScStackSize = 1 Mb + +; Turn on/off execution of remainder of sc_main upon quitting the current +; simulation session. If the cumulative length of sc_main() in terms of +; simulation time units is less than the length of the current simulation +; run upon quit or restart, sc_main() will be in the middle of execution. +; This switch gives the option to execute the remainder of sc_main upon +; quitting simulation. The drawback of not running sc_main till the end +; is memory leaks for objects created by sc_main. If on, the remainder of +; sc_main will be executed ignoring all delays. This may cause the simulator +; to crash if the code in sc_main is dependent on some simulation state. +; Default is on. +ScMainFinishOnQuit = 1 + +; Enable calling of the DPI export taks/functions from the +; SystemC start_of_simulation() callback. +; The default is off. +; EnableDpiSosCb = 1 + + +; Set the SCV relationship name that will be used to identify phase +; relations. If the name given to a transactor relation matches this +; name, the transactions involved will be treated as phase transactions +ScvPhaseRelationName = mti_phase + +; Customize the vsim kernel shutdown behavior at the end of the simulation. +; Some common causes of the end of simulation are $finish (implicit or explicit), +; sc_stop(), tf_dofinish(), and assertion failures. +; This should be set to "ask", "exit", or "stop". The default is "ask". +; "ask" -- In batch mode, the vsim kernel will abruptly exit. +; In GUI mode, a dialog box will pop up and ask for user confirmation +; whether or not to quit the simulation. +; "stop" -- Cause the simulation to stay loaded in memory. This can make some +; post-simulation tasks easier. +; "exit" -- The simulation will abruptly exit without asking for any confirmation. +; "final" -- Run SystemVerilog final blocks then behave as "stop". +; Note: This variable can be overridden with the vsim "-onfinish" command line switch. +OnFinish = ask + +; Print pending deferred assertion messages. +; Deferred assertion messages may be scheduled after the $finish in the same +; time step. Deferred assertions scheduled to print after the $finish are +; printed before exiting with severity level NOTE since it's not known whether +; the assertion is still valid due to being printed in the active region +; instead of the reactive region where they are normally printed. +; OnFinishPendingAssert = 1; + +; Print "simstats" result. Default is 0. +; 0 == do not print simstats +; 1 == print at end of simulation +; 2 == print at end of each run command and end of simulation +; PrintSimStats = 1 + +; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages +; AssertFile = assert.log + +; Enable assertion counts. Default is off. +; AssertionCounts = 1 + +; Run simulator in assertion debug mode. Default is off. +; AssertionDebug = 1 + +; Turn on/off PSL/SVA/VHDL assertion enable. Default is on. +; AssertionEnable = 0 + +; Set PSL/SVA/VHDL concurrent assertion fail limit. Default is -1. +; Any positive integer, -1 for infinity. +; AssertionLimit = 1 + +; Turn on/off concurrent assertion pass log. Default is off. +; Assertion pass logging is only enabled when assertion is browseable +; and assertion debug is enabled. +; AssertionPassLog = 1 + +; Turn on/off PSL concurrent assertion fail log. Default is on. +; The flag does not affect SVA +; AssertionFailLog = 0 + +; Turn on/off SVA concurrent assertion local var printing in -assertdebug mode. Default is on. +; AssertionFailLocalVarLog = 0 + +; Set action type for PSL/SVA concurrent assertion fail action. Default is continue. +; 0 = Continue 1 = Break 2 = Exit +; AssertionFailAction = 1 + +; Enable the active thread monitor in the waveform display when assertion debug is enabled. +; AssertionActiveThreadMonitor = 1 + +; Control how many waveform rows will be used for displaying the active threads. Default is 5. +; AssertionActiveThreadMonitorLimit = 5 + +; Assertion thread limit after which assertion would be killed/switched off. +; The default is -1 (unlimited). If the number of threads for an assertion go +; beyond this limit, the assertion would be either switched off or killed. This +; limit applies to only assert directives. +;AssertionThreadLimit = -1 + +; Action to be taken once the assertion thread limit is reached. Default +; is kill. It can have a value of off,kill or killon. In case of kill, all the existing +; threads are terminated and no new attempts are started. In case of off, the +; existing attempts keep on evaluating but no new attempts are started. In case of killon, +; all the existing threads are terminated but new attempts are started. This +; variable applies to only assert directives. +;AssertionThreadLimitAction = kill + +; Cover thread limit after which cover would be killed/switched off. +; The default is -1 (unlimited). If the number of threads for a cover go +; beyond this limit, the cover would be either switched off or killed. This +; limit applies to only cover directives. +;CoverThreadLimit = -1 + +; Action to be taken once the cover thread limit is reached. Default +; is kill. It can have a value of off, kill or killon. In case of kill, all the existing +; threads are terminated and no new attempts are started. In case of off, the +; existing attempts keep on evaluating but no new attempts are started. In case of killon, +; all the existing threads are terminated but new attempts are started. This +; variable applies to only cover directives. +;CoverThreadLimitAction = kill + + +; By default immediate assertions do not participate in Assertion Coverage calculations +; unless they are executed. This switch causes all immediate assertions in the design +; to participate in Assertion Coverage calculations, whether attempted or not. +; UnattemptedImmediateAssertions = 0 + +; By default immediate covers participate in Coverage calculations +; whether they are attempted or not. This switch causes all unattempted +; immediate covers in the design to stop participating in Coverage +; calculations. +; UnattemptedImmediateCovers = 0 + +; By default pass action block is not executed for assertions on vacuous +; success. The following variable is provided to enable execution of +; pass action block on vacuous success. The following variable is only effective +; if the user does not disable pass action block execution by using either +; system tasks or CLI. Also there is a performance penalty for enabling +; the following variable. +;AssertionEnableVacuousPassActionBlock = 1 + +; As per strict 1850-2005 PSL LRM, an always property can either pass +; or fail. However, by default, Questa reports multiple passes and +; multiple fails on top always/never property (always/never operator +; is the top operator under Verification Directive). The reason +; being that Questa reports passes and fails on per attempt of the +; top always/never property. Use the following flag to instruct +; Questa to strictly follow LRM. With this flag, all assert/never +; directives will start an attempt once at start of simulation. +; The attempt can either fail, match or match vacuously. +; For e.g. if always is the top operator under assert, the always will +; keep on checking the property at every clock. If the property under +; always fails, the directive will be considered failed and no more +; checking will be done for that directive. A top always property, +; if it does not fail, will show a pass at end of simulation. +; The default value is '0' (i.e. zero is off). For example: +; PslOneAttempt = 1 + +; Specify the number of clock ticks to represent infinite clock ticks. +; This affects eventually!, until! and until_!. If at End of Simulation +; (EOS) an active strong-property has not clocked this number of +; clock ticks then neither pass or fail (vacuous match) is returned +; else respective fail/pass is returned. The default value is '0' (zero) +; which effectively does not check for clock tick condition. For example: +; PslInfinityThreshold = 5000 + +; Control how many thread start times will be preserved for ATV viewing for a given assertion +; instance. Default is -1 (ALL). +; ATVStartTimeKeepCount = -1 + +; Turn on/off code coverage +; CodeCoverage = 0 + +; This option applies to condition and expression coverage UDP tables. It +; has no effect unless UDP is enabled for coverage with vcom/vlog/vopt -coverudp. +; If this option is used and a match occurs in more than one row in the UDP table, +; none of the counts for all matching rows is incremented. By default, counts are +; incremented for all matching rows. +; CoverCountAll = 1 + +; Turn off automatic inclusion of VHDL integers in toggle coverage. Default +; is to include them. +; ToggleNoIntegers = 1 + +; Set the maximum number of values that are collected for toggle coverage of +; VHDL integers. Default is 100; +; ToggleMaxIntValues = 100 + +; Set the maximum number of values that are collected for toggle coverage of +; Verilog real. Default is 100; +; ToggleMaxRealValues = 100 + +; Turn on automatic inclusion of Verilog integers in toggle coverage, except +; for enumeration types. Default is to include them. +; ToggleVlogIntegers = 0 + +; Turn on automatic inclusion of Verilog real type in toggle coverage, except +; for shortreal types. Default is to not include them. +; ToggleVlogReal = 1 + +; Turn on automatic inclusion of Verilog fixed-size unpacked arrays, VHDL multi-d arrays +; and VHDL arrays-of-arrays in toggle coverage. +; Default is to not include them. +; ToggleFixedSizeArray = 1 + +; Increase or decrease the maximum size of Verilog unpacked fixed-size arrays, +; VHDL multi-d arrays and VHDL arrays-of-arrays that are included for toggle coverage. +; This leads to a longer simulation time with bigger arrays covered with toggle coverage. +; Default is 1024. +; ToggleMaxFixedSizeArray = 1024 + +; Treat Verilog multi-dimensional packed vectors and packed structures as equivalently sized +; one-dimensional packed vectors for toggle coverage. Default is 0. +; TogglePackedAsVec = 0 + +; Treat Verilog enumerated types as equivalently sized one-dimensional packed vectors for +; toggle coverage. Default is 0. +; ToggleVlogEnumBits = 0 + +; Turn off automatic inclusion of VHDL records in toggle coverage. +; Default is to include them. +; ToggleVHDLRecords = 0 + +; Limit the widths of registers automatically tracked for toggle coverage. Default is 128. +; For unlimited width, set to 0. +; ToggleWidthLimit = 128 + +; Limit the counts that are tracked for toggle coverage. When all edges for a bit have +; reached this count, further activity on the bit is ignored. Default is 1. +; For unlimited counts, set to 0. +; ToggleCountLimit = 1 + +; Change the mode of extended toggle coverage. Default is 3. Valid modes are 1, 2 and 3. +; Following is the toggle coverage calculation criteria based on extended toggle mode: +; Mode 1: 0L->1H & 1H->0L & any one 'Z' transition (to/from 'Z'). +; Mode 2: 0L->1H & 1H->0L & one transition to 'Z' & one transition from 'Z'. +; Mode 3: 0L->1H & 1H->0L & all 'Z' transitions. +; ExtendedToggleMode = 3 + +; Enable toggle statistics collection only for ports. Default is 0. +; TogglePortsOnly = 1 + +; Limit the counts that are tracked for Focussed Expression Coverage. When a bin has +; reached this count, further tracking of the input patterns linked to it is ignored. +; Default is 1. For unlimited counts, set to 0. +; NOTE: Changing this value from its default value may affect simulation performance. +; FecCountLimit = 1 + +; Limit the counts that are tracked for UDP Coverage. When a bin has +; reached this count, further tracking of the input patterns linked to it is ignored. +; Default is 1. For unlimited counts, set to 0. +; NOTE: Changing this value from its default value may affect simulation performance. +; UdpCountLimit = 1 + +; Control toggle coverage deglitching period. A period of 0, eliminates delta +; cycle glitches. This is the default. The value of ToggleDeglitchPeriod needs to be either +; 0 or a time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". +; ToggleDeglitchPeriod = 10.0ps + +; Turn on/off all PSL/SVA cover directive enables. Default is on. +; CoverEnable = 0 + +; Turn on/off PSL/SVA cover log. Default is off "0". +; CoverLog = 1 + +; Set "at_least" value for all PSL/SVA cover directives. Default is 1. +; CoverAtLeast = 2 + +; Set "limit" value for all PSL/SVA cover directives. Default is -1. +; Any positive integer, -1 for infinity. +; CoverLimit = 1 + +; Specify the coverage database filename. +; Default is "" (i.e. database is NOT automatically saved on close). +; UCDBFilename = vsim.ucdb + +; Specify the maximum limit for the number of Cross (bin) products reported +; in XML and UCDB report against a Cross. A warning is issued if the limit +; is crossed. Default is zero. vsim switch -cvgmaxrptrhscross can override this +; setting. +; MaxReportRhsSVCrossProducts = 1000 + +; Specify the override for the "auto_bin_max" option for the Covergroups. +; If not specified then value from Covergroup "option" is used. +; SVCoverpointAutoBinMax = 64 + +; Specify the override for the value of "cross_num_print_missing" +; option for the Cross in Covergroups. If not specified then value +; specified in the "option.cross_num_print_missing" is used. This +; is a runtime option. NOTE: This overrides any "cross_num_print_missing" +; value specified by user in source file and any SVCrossNumPrintMissingDefault +; specified in modelsim.ini. +; SVCrossNumPrintMissing = 0 + +; Specify whether to use the value of "cross_num_print_missing" +; option in report and GUI for the Cross in Covergroups. If not specified then +; cross_num_print_missing is ignored for creating reports and displaying +; covergroups in GUI. Default is 0, which means ignore "cross_num_print_missing". +; UseSVCrossNumPrintMissing = 0 + +; Specify the threshold of Coverpoint wildcard bin value range size, above which +; a warning will be triggered. The default is 4K -- 12 wildcard bits. +; SVCoverpointWildCardBinValueSizeWarn = 4096 + +; Specify the override for the value of "strobe" option for the +; Covergroup Type. If not specified then value in "type_option.strobe" +; will be used. This is runtime option which forces "strobe" to +; user specified value and supersedes user specified values in the +; SystemVerilog Code. NOTE: This also overrides the compile time +; default value override specified using "SVCovergroupStrobeDefault" +; SVCovergroupStrobe = 0 + +; Override for explicit assignments in source code to "option.goal" of +; SystemVerilog covergroup, coverpoint, and cross. It also overrides the +; default value of "option.goal" (defined to be 100 in the SystemVerilog +; LRM) and the value of modelsim.ini variable "SVCovergroupGoalDefault". +; SVCovergroupGoal = 100 + +; Override for explicit assignments in source code to "type_option.goal" of +; SystemVerilog covergroup, coverpoint, and cross. It also overrides the +; default value of "type_option.goal" (defined to be 100 in the SystemVerilog +; LRM) and the value of modelsim.ini variable "SVCovergroupTypeGoalDefault". +; SVCovergroupTypeGoal = 100 + +; Enforce the 6.3 behavior of covergroup get_coverage() and get_inst_coverage() +; builtin functions, and report. This setting changes the default values of +; option.get_inst_coverage and type_option.merge_instances to ensure the 6.3 +; behavior if explicit assignments are not made on option.get_inst_coverage and +; type_option.merge_instances by the user. There are two vsim command line +; options, -cvg63 and -nocvg63 to override this setting from vsim command line. +; The default value of this variable from release 6.6 onwards is 0. This default +; drives compliance with the clarified behavior in the IEEE 1800-2009 standard. +; SVCovergroup63Compatibility = 0 + +; Enforce the default behavior of covergroup get_coverage() builtin function, GUI +; and report. This variable sets the default value of type_option.merge_instances. +; There are two vsim command line options, -cvgmergeinstances and +; -nocvgmergeinstances to override this setting from vsim command line. +; The default value of this variable, -1 (don't care), allows the tool to determine +; the effective value, based on factors related to capacity and optimization. +; The type_option.merge_instances appears in the GUI and coverage reports as either +; auto(1) or auto(0), depending on whether the effective value was determined to +; be a 1 or a 0. +; SVCovergroupMergeInstancesDefault = -1 + +; Enable or disable generation of more detailed information about the sampling +; of covergroup, cross, and coverpoints. It provides the details of the number +; of times the covergroup instance and type were sampled, as well as details +; about why covergroup, cross and coverpoint were not covered. A non-zero value +; is to enable this feature. 0 is to disable this feature. Default is 0 +; SVCovergroupSampleInfo = 0 + +; Specify the maximum number of Coverpoint bins in whole design for +; all Covergroups. +; MaxSVCoverpointBinsDesign = 2147483648 + +; Specify maximum number of Coverpoint bins in any instance of a Covergroup, default is 2^10 bins +; MaxSVCoverpointBinsInst = 1048576 + +; Specify the maximum number of Cross bins in whole design for +; all Covergroups. +; MaxSVCrossBinsDesign = 2147483648 + +; Specify maximum number of Cross bins in any instance of a Covergroup, default is 2^16 bins +; MaxSVCrossBinsInst = 67108864 + +; Specify whether vsim will collect the coverage data of zero-weight coverage items or not. +; By default, this variable is set 0, in which case option.no_collect setting will take effect. +; If this variable is set to 1, all zero-weight coverage items will not be saved. +; Note that the usage of vsim switch -cvgzwnocollect, if present, will override the setting +; of this variable. +; CvgZWNoCollect = 1 + +; Specify a space delimited list of double quoted TCL style +; regular expressions which will be matched against the text of all messages. +; If any regular expression is found to be contained within any message, the +; status for that message will not be propagated to the UCDB TESTSTATUS. +; If no match is detected, then the status will be propagated to the +; UCDB TESTSTATUS. More than one such regular expression text is allowed, +; and each message text is compared for each regular expression in the list. +; UCDBTestStatusMessageFilter = "Done with Test Bench" "Ignore .* message" + +; Set weight for all PSL/SVA cover directives. Default is 1. +; CoverWeight = 2 + +; Check vsim plusargs. Default is 0 (off). +; The command line equivalent is -check_plusargs <number>. +; 0 = Don't check plusargs (this is the default) +; 1 = Warning on unrecognized plusarg +; 2 = Error and exit on unrecognized plusarg +; CheckPlusargs = 1 + +; Load the specified shared objects with the RTLD_GLOBAL flag. +; This gives global visibility to all symbols in the shared objects, +; meaning that subsequently loaded shared objects can bind to symbols +; in the global shared objects. The list of shared objects should +; be whitespace delimited. This option is not supported on the +; Windows or AIX platforms. +; GlobalSharedObjectList = example1.so example2.so example3.so + +; Generate the stub definitions for the undefined symbols in the shared libraries being +; loaded in the simulation. When this flow is turned on, the undefined symbols will not +; prevent vsim from loading. Calling undefined symbols at runtime will cause fatal error. +; The valid arguments are: on, off, verbose. +; on : turn on the automatic generation of stub definitions. +; off: turn off the flow. The undefined symbols will trigger an immediate load failure. +; verbose: Turn on the flow and report the undefined symbols for each shared library. +; NOTE: This variable can be overriden with vsim switch "-undefsyms". +; The default is on. +; +; UndefSyms = off + +; Enable the support for automatically checkpointing foreign C/C++ libraries. +; The valid arguments are: 0, 1, 2 +; 0: off (default) +; 1: on (manually save/restore user shared library data) +; 2: auto (automatically save/restore user shared library data) +; This option is not supported on the Windows platforms. +; +; AllowCheckpointCpp = 2 + +; Initial seed for the random number generator of the root thread (SystemVerilog). +; NOTE: This variable can be overridden with the vsim "-sv_seed" command line switch. +; The default value is 0. +; Sv_Seed = 0 + +; Specify the solver "engine" that vsim will select for constrained random +; generation. +; Valid values are: +; "auto" - automatically select the best engine for the current +; constraint scenario +; "bdd" - evaluate all constraint scenarios using the BDD solver engine +; "act" - evaluate all constraint scenarios using the ACT solver engine +; While the BDD solver engine is generally efficient with constraint scenarios +; involving bitwise logical relationships, the ACT solver engine can exhibit +; superior performance with constraint scenarios involving large numbers of +; random variables related via arithmetic operators (+, *, etc). +; NOTE: This variable can be overridden with the vsim "-solveengine" command +; line switch. +; The default value is "auto". +; SolveEngine = auto + +; Specify the maximum size that a random dynamic array or queue may be resized +; to by the solver. If the solver attempts to resize a dynamic array or queue +; to a size greater than the specified limit, an error will be issued and +; randomize() will fail. The default value is 65535. A value of 0 disables the +; resize check (i.e. no error will be issued regardless of size). +; SolveArrayResizeMax = 65535 + +; Specify the maximum size that a random dynamic array or queue may be resized +; to by the solver without a warning. If the solver attempts to resize a dynamic +; array or queue to a size greater than the specified limit, a warning will be +; issued. The default value is 65535. A value of 0 disables the resize check +; (i.e. no warning will be issued regardless of size). +; SolveArrayResizeWarn = 65535 + +; Specify error message severity when randomize() and randomize(null) failures +; are detected. +; +; Integer value up to two digits are allowed with each digit having the following legal values: +; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal +; +; 1) When a value with two digits is used, the digit at tenth place (leftmost digit) represents +; the severtity setting for normal randomize() calls. The digit at ones place (rightmost digit) +; represents the setting for randomize(null) calls. +; +; 2) When a single digit value is used, the setting is applied to both normal randomize() call +; and randomize(null) call. +; +; Example: Fatal error for randomize() failures and NO error for randomize(null) failures +; -solvefailseverity=40 +; +; NOTE: SolveFailSeverity can affect the behavior of SolveFailDebug. When SolveFailDebug is +; enabled, a constraint contradiction report will be displayed for randomize() calls that +; have a message severity >= warning (i.e. constraint contradiction reports will not be +; generated for randomize() calls having a "no error" severity level) +; +; NOTE: This variable can be overridden with the vsim "-solvefailseverity" command +; line switch. +; +; The default is 1 (warning). +; SolveFailSeverity = 1 + +; Error message severity for suppressible errors that are detected in a +; solve/before constraint. +; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal +; NOTE: This variable can be overridden with the vsim "-solvebeforeerrorseverity" +; command line switch. +; The default is 2 (error). +; SolveBeforeErrorSeverity = 2 + +; Error message severity for suppressible errors that are related to +; solve engine capacity limits +; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal +; NOTE: This variable can be overridden with the vsim "-solveengineerrorseverity" +; command line switch. +; The default is 2 (error). +; SolveEngineErrorSeverity = 2 + +; Enable/disable constraint conflicts on randomize() failure +; Valid values: +; 0 - disable solvefaildebug +; 1 - basic debug (no performance penalty) +; 2 - enhanced debug (runtime performance penalty) +; +; NOTE: SolveFailSeverity can affect the behavior of SolveFailDebug. When SolveFailDebug is +; enabled, a constraint contradiction report will be displayed for randomize() calls that +; have a message severity >= warning (i.e. constraint contradiction reports will not be +; generated for randomize() calls having a "no error" severity level) +; +; NOTE: This variable can be overridden with the vsim "-solvefaildebug" command +; line switch. +; +; The default is 1 (basic debug). +; SolveFailDebug = 1 + +; Upon encountering a randomize() failure, generate a simplified testcase that +; will reproduce the failure. Optionally output the testcase to a file. +; Testcases for 'no-solution' failures will only be produced if SolveFailDebug +; is enabled (see above). +; NOTE: This variable can be overridden with the vsim "-solvefailtestcase" +; command line switch. +; The default is OFF (do not generate a testcase). To enable testcase +; generation, uncomment this variable. To redirect testcase generation to a +; file, specify the name of the output file. +; SolveFailTestcase = + +; Specify solver timeout threshold (in seconds). randomize() will fail if the +; CPU time required to evaluate the call exceeds the specified timeout. +; The default value is 1000. A value of 0 will disable timeout failures. +; SolveTimeout = 1000 + +; Specify the alternative behavior during solver replay. Must be used when combined with -solvereplay switch. +; Valid <opt> settings: +; validate : toggle the checking of value changes of non-random variables involved in randomize(). (default is off)" +; SolveReplayOpt=[+|-]<option>[,[+|-]<option>]* + +; Switch to specify options that control the behavior of the solver profiler. +; Valid options are: +; cputime - use CPU time instead of elapsed time (wall time) to measure performance data (default is off) +; randsets - enable detailed profiling of randsets (default is off) +; testgen - generate randset testcases (only when 'randsets' option is enabled, default is off) +; SolverFProf = [+|-]<option>[,[+|-]<option>]* + +; Specify the maximum size of the solution graph generated by the BDD solver. +; This value can be used to force the BDD solver to abort the evaluation of a +; complex constraint scenario that cannot be evaluated with finite memory. +; This value is specified in 1000s of nodes. +; The default value is 10000. A value of 0 indicates no limit. +; SolveGraphMaxSize = 10000 + +; Specify the maximum number of evaluations that may be performed on the +; solution graph by the BDD solver. This value can be used to force the BDD +; solver to abort the evaluation of a complex constraint scenario that cannot +; be evaluated in finite time. This value is specified in 10000s of evaluations. +; The default value is 10000. A value of 0 indicates no limit. +; SolveGraphMaxEval = 10000 + +; Specify random sequence compatiblity with a prior release. This +; option is used to get the same random sequences during simulation as +; as a prior release. Only prior releases with the same major version +; as the current release are allowed. +; NOTE: This variable can be overridden with the vsim "-solverev" command +; line switch. +; Default value set to "" (no compatibility). +; SolveRev = + +; Environment variable expansion of command line arguments has been deprecated +; in favor shell level expansion. Universal environment variable expansion +; inside -f files is support and continued support for MGC Location Maps provide +; alternative methods for handling flexible pathnames. +; The following line may be uncommented and the value set to 1 to re-enable this +; deprecated behavior. The default value is 0. +; DeprecatedEnvironmentVariableExpansion = 0 + +; Specify the memory threshold for the System Verilog garbage collector. +; The value is the number of megabytes of class objects that must accumulate +; before the garbage collector is run. +; The GCThreshold setting is used when class debug mode is disabled to allow +; less frequent garbage collection and better simulation performance. +; The GCThresholdClassDebug setting is used when class debug mode is enabled +; to allow for more frequent garbage collection. +; GCThreshold = 100 +; GCThresholdClassDebug = 5 + +; Turn on/off collapsing of bus ports in VCD dumpports output +DumpportsCollapse = 1 + +; Location of Multi-Level Verification Component (MVC) installation. +; The default location is the product installation directory. +MvcHome = $QUESTA_MVC_HOME + +; Location of InFact installation. The default is $MODEL_TECH/../../infact +; +; InFactHome = $MODEL_TECH/../../infact + +; Initialize SystemVerilog enums using the base type's default value +; instead of the leftmost value. +; EnumBaseInit = 1 + +; Suppress file type registration. +; SuppressFileTypeReg = 1 + +; Controls SystemVerilog Language Extensions. These options enable +; some non-LRM compliant behavior. +; SvExtensions = [+|-]<extension>[,[+|-]<extension>]* + +; Enable/disable non-LRM compliant SystemVerilog constrained-random language extensions. +; Valid extensions are: +; arraymode - consider rand_mode of unpacked array field independently from its elements +; deepcheck - allow randomize(null) to recursively consider constraints from member rand class handles (Default) +; dynext - enhanced evaluation for constraints involving random dynamic arrays that are resized during randomize() +; funcback - enable function backtracking (ACT only) +; nodist - interpret 'dist' constraint as 'inside' (ACT only) +; noorder - ignore solve/before ordering constraints (ACT only) +; oobidx - allow out-of-bounds value for an indexed-expression with random indices if indexed-expression yields a 2-state packed type +; prerandfirst - execute all pre_randomize() functions before evaluating any constraints (Default) +; promotedist - promote priority of 'dist' constraint if LHS has no solve/before +; purecheck - suppress pre_randomize() and post_randomize() calls for randomize(null) +; randcext - allow 'randc' and other 'rand' variables to be solved in the same randset (Default) +; randindex - allow random index in constraint (Default) +; randstruct - consider all fields of unpacked structs as 'rand' +; skew - skew randomize results (ACT only) +; srandom - interpret $srandom(seed) system task calls as equivalent process::self().srandom(seed) calls (Default) +; strictstab - strict random stability +; SvRandExtensions = [+|-]<extension>[,[+|-]<extension>]* + +; Controls the formatting of '%p' and '%P' conversion specification, used in $display +; and similar system tasks. +; 1. SVPrettyPrintFlags=I<n><S|T> use <n> spaces(S) or tabs(T) per indentation level. +; The 'I' flag when present causes relevant data types to be expanded and indented into +; a more readable format. +; (e.g. SVPrettyPrintFlags=I4S will cause 4 spaces to be used per indentation level). +; 2. SVPrettyPrintFlags=L<numLines> limits the output to <numLines> lines. +; (e.g. SVPrettyPrintFlags=L20 will limit the output to 20 lines). +; 3. SVPrettyPrintFlags=C<numChars> limits the output to <numChars> characters. +; (e.g. SVPrettyPrintFlags=C256 will limit the output to 256 characters). +; 4. SVPrettyPrintFlags=F<numFields> limits the output to <numFields> of relevant datatypes +; (e.g. SVPrettyPrintFlags=F4 will limit the output to 4 fields of a structure). +; 5. SVPrettyPrintFlags=E<numElements> limits the output to <numElements> of relevant datatypes +; (e.g. SVPrettyPrintFlags=E50 will limit the output to 50 elements of an array). +; 6. SVPrettyPrintFlags=D<depth> suppresses the output of sub-elements below <depth>. +; (e.g. SVPrettyPrintFlags=D5 will suppresses the output of sub elements below a depth of 5). +; 7. SVPrettyPrintFlags=R<specifier> shows the output of specifier %p as per the specifed radix. +; It changes the output in $display and similar systasks. It does not affect formatted output functions ($displayh etc)). +; (e.g. SVPrettyPrintFlags=Rb will show the output of %p specifier in binary format. +; 8. Items 1-7 above can be combined as a comma separated list. +; (e.g. SVPrettyPrintFlags=I4S,L20,C256,F4,E50,D5,Rb) +; SVPrettyPrintFlags=I4S + +[lmc] +; The simulator's interface to Logic Modeling's SmartModel SWIFT software +libsm = $MODEL_TECH/libsm.sl +; The simulator's interface to Logic Modeling's SmartModel SWIFT software (Windows NT) +; libsm = $MODEL_TECH/libsm.dll +; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700) +; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl +; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000) +; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o +; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris) +; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so +; Logic Modeling's SmartModel SWIFT software (Windows NT) +; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll +; Logic Modeling's SmartModel SWIFT software (non-Enterprise versions of Linux) +; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so +; Logic Modeling's SmartModel SWIFT software (Enterprise versions of Linux) +; libswift = $LMC_HOME/lib/linux.lib/libswift.so + +; The simulator's interface to Logic Modeling's hardware modeler SFI software +libhm = $MODEL_TECH/libhm.sl +; The simulator's interface to Logic Modeling's hardware modeler SFI software (Windows NT) +; libhm = $MODEL_TECH/libhm.dll +; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700) +; libsfi = <sfi_dir>/lib/hp700/libsfi.sl +; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000) +; libsfi = <sfi_dir>/lib/rs6000/libsfi.a +; Logic Modeling's hardware modeler SFI software (Sun4 Solaris) +; libsfi = <sfi_dir>/lib/sun4.solaris/libsfi.so +; Logic Modeling's hardware modeler SFI software (Windows NT) +; libsfi = <sfi_dir>/lib/pcnt/lm_sfi.dll +; Logic Modeling's hardware modeler SFI software (Linux) +; libsfi = <sfi_dir>/lib/linux/libsfi.so + +[msg_system] +; Change a message severity or suppress a message. +; The format is: <msg directive> = <msg number>[,<msg number>...] +; suppress can be used to achieve +nowarn<CODE> functionality +; The format is: suppress = <CODE>,<msg number>,[<CODE>,<msg number>,...] +; Examples: +suppress = 8780 ;an explanation can be had by running: verror 8780 +; note = 3009 +; warning = 3033 +; error = 3010,3016 +; fatal = 3016,3033 +; suppress = 3009,3016,3601 +; suppress = 3009,CNNODP,3601,TFMPC +; suppress = 8683,8684 +; The command verror <msg number> can be used to get the complete +; description of a message. + +; Control transcripting of Verilog display system task messages and +; PLI/FLI print function call messages. The system tasks include +; $display[bho], $strobe[bho], $monitor[bho], and $write[bho]. They +; also include the analogous file I/O tasks that write to STDOUT +; (i.e. $fwrite or $fdisplay). The PLI/FLI calls include io_printf, +; vpi_printf, mti_PrintMessage, and mti_PrintFormatted. The default +; is to have messages appear only in the transcript. The other +; settings are to send messages to the wlf file only (messages that +; are recorded in the wlf file can be viewed in the MsgViewer) or +; to both the transcript and the wlf file. The valid values are +; tran {transcript only (default)} +; wlf {wlf file only} +; both {transcript and wlf file} +; displaymsgmode = tran + +; Control transcripting of elaboration/runtime messages not +; addressed by the displaymsgmode setting. The default is to +; have messages appear only in the transcript. The other settings +; are to send messages to the wlf file only (messages that are +; recorded in the wlf file can be viewed in the MsgViewer) or to both +; the transcript and the wlf file. The valid values are +; tran {transcript only (default)} +; wlf {wlf file only} +; both {transcript and wlf file} +; msgmode = tran + +; Controls number of displays of a particluar message +; default value is 5 +; MsgLimitCount = 5 + +[utils] +; Default Library Type (while creating a library with "vlib") +; 0 - legacy library using subdirectories for design units +; 2 - flat library +; DefaultLibType = 2 + +; Flat Library Page Size (while creating a library with "vlib") +; Set the size in bytes for flat library file pages. Libraries containing +; very large files may benefit from a larger value. +; FlatLibPageSize = 8192 + +; Flat Library Page Cleanup Percentage (while creating a library with "vlib") +; Set the percentage of total pages deleted before library cleanup can occur. +; This setting is applied together with FlatLibPageDeleteThreshold. +; FlatLibPageDeletePercentage = 50 + +; Flat Library Page Cleanup Threshold (while creating a library with "vlib") +; Set the number of pages deleted before library cleanup can occur. +; This setting is applied together with FlatLibPageDeletePercentage. +; FlatLibPageDeleteThreshold = 1000 + +[Project] +** Warning: ; Warning -- Do not edit the project properties directly. +; Property names are dynamic in nature and property +; values have special syntax. Changing property data directly +; can result in a corrupt MPF file. All project properties +; can be modified through project window dialogs. +Project_Version = 6 +Project_DefaultLib = work +Project_SortMethod = unused +Project_Files_Count = 2 +Project_File_0 = C:/Projects/ml_module_agilex/src/ml_module_agilex.v +Project_File_P_0 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 last_compile 1778681604 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +define+SIMULATION=1 compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_1 = C:/Projects/ml_module_agilex/sim/src/tb.sv +Project_File_P_1 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1778683295 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 1 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_Sim_Count = 0 +Project_Folder_Count = 0 +Echo_Compile_Output = 0 +Save_Compile_Report = 1 +Project_Opt_Count = 0 +ForceSoftPaths = 0 +ProjectStatusDelay = 5000 +VERILOG_DoubleClick = Edit +VERILOG_CustomDoubleClick = +SYSTEMVERILOG_DoubleClick = Edit +SYSTEMVERILOG_CustomDoubleClick = +VHDL_DoubleClick = Edit +VHDL_CustomDoubleClick = +PSL_DoubleClick = Edit +PSL_CustomDoubleClick = +TEXT_DoubleClick = Edit +TEXT_CustomDoubleClick = +SYSTEMC_DoubleClick = Edit +SYSTEMC_CustomDoubleClick = +TCL_DoubleClick = Edit +TCL_CustomDoubleClick = +MACRO_DoubleClick = Edit +MACRO_CustomDoubleClick = +VCD_DoubleClick = Edit +VCD_CustomDoubleClick = +SDF_DoubleClick = Edit +SDF_CustomDoubleClick = +XML_DoubleClick = Edit +XML_CustomDoubleClick = +LOGFILE_DoubleClick = Edit +LOGFILE_CustomDoubleClick = +UCDB_DoubleClick = Edit +UCDB_CustomDoubleClick = +TDB_DoubleClick = Edit +TDB_CustomDoubleClick = +UPF_DoubleClick = Edit +UPF_CustomDoubleClick = +PCF_DoubleClick = Edit +PCF_CustomDoubleClick = +PROJECT_DoubleClick = Edit +PROJECT_CustomDoubleClick = +VRM_DoubleClick = Edit +VRM_CustomDoubleClick = +DEBUGDATABASE_DoubleClick = Edit +DEBUGDATABASE_CustomDoubleClick = +DEBUGARCHIVE_DoubleClick = Edit +DEBUGARCHIVE_CustomDoubleClick = +Project_Major_Version = 2025 +Project_Minor_Version = 3 diff --git a/sim/win/modelsim.ini b/sim/win/modelsim.ini new file mode 100644 index 0000000..f5063c6 --- /dev/null +++ b/sim/win/modelsim.ini @@ -0,0 +1,2237 @@ +; vsim modelsim.ini file +[Version] +INIVersion = "2024.3" + +; Unpublished work. Copyright 2024 Siemens +; +; This material contains trade secrets or otherwise confidential information +; owned by Siemens Industry Software Inc. or its affiliates (collectively, +; "SISW"), or its licensors. Access to and use of this information is strictly +; limited as set forth in the Customer's applicable agreements with SISW. +; +; This material may not be copied, distributed, or otherwise disclosed outside +; of the Customer's facilities without the express written permission of SISW, +; and may not be used in any way not expressly authorized by SISW. +; + +[Library] +others = $QUESTASIM_DIR/../modelsim.ini +; +; VITAL concerns: +; +; The library ieee contains (among other packages) the packages of the +; VITAL 2000 standard. When a design uses VITAL 2000 exclusively, it should use +; the physical library ieee (recommended), or use the physical library +; vital2000, but not both. The design can use logical library ieee and/or +; vital2000 as long as each of these maps to the same physical library, either +; ieee or vital2000. +; +; A design using the 1995 version of the VITAL packages, whether or not +; it also uses the 2000 version of the VITAL packages, must have logical library +; name ieee mapped to physical library vital1995. (A design cannot use library +; vital1995 directly because some packages in this library use logical name ieee +; when referring to the other packages in the library.) The design source +; should use logical name ieee when referring to any packages there except the +; VITAL 2000 packages. Any VITAL 2000 present in the design must use logical +; name vital2000 (mapped to physical library vital2000) to refer to those +; packages. +; ieee = $MODEL_TECH/../vital1995 +; +; For compatiblity with previous releases, logical library name vital2000 maps +; to library vital2000 (a different library than library ieee, containing the +; same packages). +; A design should not reference VITAL from both the ieee library and the +; vital2000 library because the vital packages are effectively different. +; A design that references both the ieee and vital2000 libraries must have +; both logical names ieee and vital2000 mapped to the same library, either of +; these: +; $MODEL_TECH/../ieee +; $MODEL_TECH/../vital2000 +; + +; added mapping for ADMS + +;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers // Source files only for this release +;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release +;mvc_lib = $MODEL_TECH/../mvc_lib + +; Altera Primitive libraries +; +; VHDL Section +; +; +; Verilog Section +; + + +; Automatically perform logical->physical mapping for physical libraries that +; appear in -L/-Lf options with filesystem path delimiters (e.g. '.' or '/'). +; The tail of the filesystem path name is chosen as the logical library name. +; For example, in the command "vopt -L ./path/to/lib1 -o opttop top", +; vopt automatically performs the mapping "lib1 -> ./path/to/lib1". +; See the User Manual for more details. +; +; AutoLibMapping = 0 + +work = ./libraries/work/ +work_lib = ./libraries/work/ +altera_iopll_2110 = ./libraries/altera_iopll_2110/ +pll_io = ./libraries/pll_io/ +altera_gpio_core10_ph2_2210 = ./libraries/altera_gpio_core10_ph2_2210/ +altera_gpio_2300 = ./libraries/altera_gpio_2300/ +ddr_o = ./libraries/ddr_o/ +ddr_i = ./libraries/ddr_i/ +[BC_COMPAT] +; Start of Backward Compatibility Section +; The Variables in this section are dedicated for the Backward Compatibility feature +; Set desired release version for backward compatibility, note that currently this only supports 2023.1 +;BC_ReleaseCompat = 2023.1 +;BC_XClass = <activate/deactivate> +; End of Backward Compatibility Section + +[DefineOptionset] +; Define optionset entries for the various compilers, vmake, and vsim. +; These option sets can be used with the "-optionset <optionsetname>" syntax. +; i.e. +; vlog -optionset COMPILEDEBUG top.sv +; vsim -optionset UVMDEBUG my_top +; +; Following are some useful examples. + +; define a vsim optionset for uvm debugging +UVMDEBUG = -uvmcontrol=all -msgmode both -displaymsgmode both -classdebug -onfinish stop + +; define a vopt optionset for debugging +VOPTDEBUG = +acc -debugdb + +[encryption] +; For vencrypt and vhencrypt. + +; Controls whether to encrypt whole files by ignoring all protect directives +; (except "viewport" and "interface_viewport") that are present in the input. +; The default is 0, use embedded protect directives to control the encryption. +; Set this to 1 to encrypt whole files by ignoring embedded protect directives. +; wholefile = 0 + +; Sets the data_method to use for the symmetric session key. +; The session key is a symmetric key that is randomly generated for each +; protected region (envelope) and is the heart of all encryption. This is used +; to set the length of the session key to generate and use when encrypting the +; HDL text. Supported values are aes128, aes192, and aes256. +; data_method = aes128 + +; The following 2 are for specifying an IEEE Std. 1735 Version 2 (V2) encryption +; "recipe" comprising an optional common block, at least one tool block (which +; contains the key public key), and the text to be encrypted. The common block +; and any of the tool blocks may contain rights in the form of the "control" +; directive. The text to be encrypted is specified either by setting +; "wholefile" to 1 or by embedding protect "begin" and "end" directives in +; the input HDL files. + +; Common recipe specification file. This file is optional. Its presence will +; require at least one "toolblock" to be specified. +; Directives such as "author" "author_info" and "data_method", +; as well as the common block license specification, go in this file. +; common = <file name> + +; Tool block specification recipe(s). Public key file with optional tool block +; file name. May be multiply-defined; at least one tool block is required if +; a recipe is being specified. +; Key file is a file name with no extension (.deprecated or .active will be +; supplied by the encryption tool). +; Rights file name is optional. +; toolblock = <key file name>[,<rights file name>]{:<key file name>[,<rights file name>]} + +; Location of directory containing recipe files. +; The default location is in the product installation directory. +; keyring = $MODEL_TECH/../keyring + +; Enable encryption statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list] +; Add '-' to disable specific statistics. Default is [cmd,msg]. +Stats = cmd,msg + +[vcom] +; VHDL93 variable selects language version as the default. +; Default is VHDL-2002. +; Value of 0 or 1987 for VHDL-1987. +; Value of 1 or 1993 for VHDL-1993. +; Default or value of 2 or 2002 for VHDL-2002. +; Value of 3 or 2008 for VHDL-2008 +; Value of 4 or ams99 for VHDL-AMS-1999 +; Value of 5 or ams07 for VHDL-AMS-2007 +; Value of 7 or 2019 for VHDL-2019 +VHDL93 = 2002 + +; Ignore VHDL-2008 declaration of REAL_VECTOR in package STANDARD. Default is off. +; ignoreStandardRealVector = 1 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn off unbound-component warnings. Default is on. +; Show_Warning1 = 0 + +; Turn off process-without-a-wait-statement warnings. Default is on. +; Show_Warning2 = 0 + +; Turn off null-range warnings. Default is on. +; Show_Warning3 = 0 + +; Turn off no-space-in-time-literal warnings. Default is on. +; Show_Warning4 = 0 + +; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. +; Show_Warning5 = 0 + +; Turn off optimization for IEEE std_logic_1164 package. Default is on. +; Optimize_1164 = 0 + +; Enable compiler statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list] +; Add '-' to disable specific statistics. Default is [time,cmd,msg]. +; Stats = time,cmd,msg + +; Turn on resolving of ambiguous function overloading in favor of the +; "explicit" function declaration (not the one automatically created by +; the compiler for each type declaration). Default is off. +; The .ini file has Explicit enabled so that std_logic_signed/unsigned +; will match the behavior of synthesis tools. +Explicit = 1 + +; Turn off acceleration of the VITAL packages. Default is to accelerate. +; NoVital = 1 + +; Turn off VITAL compliance checking. Default is checking on. +; NoVitalCheck = 1 + +; Ignore VITAL compliance checking errors. Default is to not ignore. +; IgnoreVitalErrors = 1 + +; Turn off VITAL compliance checking warnings. Default is to show warnings. +; Show_VitalChecksWarnings = 0 + +; Turn off PSL assertion warning messages. Default is to show warnings. +; Show_PslChecksWarnings = 0 + +; Enable parsing of embedded PSL assertions. Default is enabled. +; EmbeddedPsl = 0 + +; Keep silent about case statement static warnings. +; Default is to give a warning. +; NoCaseStaticError = 1 + +; Keep silent about warnings caused by aggregates that are not locally static. +; Default is to give a warning. +; NoOthersStaticError = 1 + +; Treat as errors: +; case statement static warnings +; warnings caused by aggregates that are not locally static +; Overrides NoCaseStaticError, NoOthersStaticError settings. +; PedanticErrors = 1 + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on some limited synthesis rule compliance checking. Checks only: +; -- signals used (read) by a process must be in the sensitivity list +; CheckSynthesis = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +; Require the user to specify a configuration for all bindings, +; and do not generate a compile time default binding for the +; component. This will result in an elaboration error of +; 'component not bound' if the user fails to do so. Avoids the rare +; issue of a false dependency upon the unused default binding. +; RequireConfigForAllDefaultBinding = 1 + +; Perform default binding at compile time. +; Default is to do default binding at load time. +; BindAtCompile = 1; + +; Inhibit range checking on subscripts of arrays. Range checking on +; scalars defined with subtypes is inhibited by default. +; NoIndexCheck = 1 + +; Inhibit range checks on all (implicit and explicit) assignments to +; scalar objects defined with subtypes. +; NoRangeCheck = 1 + +; Set the prefix to be honored for synthesis/coverage pragma recognition. +; Default is "". +; AddPragmaPrefix = "" + +; Ignore synthesis and coverage pragmas with this prefix. +; Default is "". +; IgnorePragmaPrefix = "" + +; Turn on code coverage in VHDL design units. Default is off. +; Coverage = sbceft + +; Turn off code coverage in VHDL subprograms. Default is on. +; CoverSub = 0 + +; Automatically exclude VHDL case statement OTHERS choice branches. +; This includes OTHERS choices in selected signal assigment statements. +; Default is to not exclude. +; CoverExcludeDefault = 1 + +; Control compiler and VOPT optimizations that are allowed when +; code coverage is on. Refer to the comment for this in the [vlog] area. +; CoverOpt = 3 + +; Turn on or off clkOpt optimization for code coverage. Default is on. +; CoverClkOpt = 1 + +; Turn on or off clkOpt optimization builtins for code coverage. Default is on. +; CoverClkOptBuiltins = 0 + +; Inform code coverage optimizations to respect VHDL 'H' and 'L' +; values on signals in conditions and expressions, and to not automatically +; convert them to '1' and '0'. Default is to not convert. +; CoverRespectHandL = 0 + +; Increase or decrease the maximum number of rows allowed in a UDP table +; implementing a VHDL condition coverage or expression coverage expression. +; More rows leads to a longer compile time, but more expressions covered. +; CoverMaxUDPRows = 192 + +; Increase or decrease the maximum number of input patterns that are present +; in FEC table. This leads to a longer compile time with more expressions +; covered with FEC metric. +; CoverMaxFECRows = 192 + +; Increase or decrease the limit on the size of expressions and conditions +; considered for expression and condition coverages. Higher FecUdpEffort leads +; to higher compile, optimize and simulation time, but more expressions and +; conditions are considered for coverage in the design. FecUdpEffort can +; be set to a number ranging from 1 (low) to 3 (high), defined as: +; 1 - (low) Only small expressions and conditions considered for coverage. +; 2 - (medium) Bigger expressions and conditions considered for coverage. +; 3 - (high) Very large expressions and conditions considered for coverage. +; The default setting is 1 (low). +; FecUdpEffort = 1 + +; Enable or disable Focused Expression Coverage analysis for conditions and +; expressions. Focused Expression Coverage data is provided by default when +; expression and/or condition coverage is active. +; CoverFEC = 0 + +; Enable or disable UDP Coverage analysis for conditions and expressions. +; UDP Coverage data is disabled by default when expression and/or condition +; coverage is active. +; CoverUDP = 1 + +; Enable or disable Rapid Expression Coverage mode for conditions and expressions. +; Disabling this would convert non-masking conditions in FEC tables to matching +; input patterns. +; CoverREC = 1 + +; Enable or disable bit-blasting multi-bit operands of reduction prefix expressions +; for expression/condition coverage. +; NOTE: Enabling this may have a negative impact on simulation performance. +; CoverExpandReductionPrefix = 0 + +; Enable or disable short circuit evaluation of conditions and expressions when +; condition or expression coverage is active. Short circuit evaluation is enabled +; by default. +; CoverShortCircuit = 0 + +; Enable code coverage reporting of code that has been optimized away. +; The default is not to report. +; CoverReportCancelled = 1 + +; Enable deglitching of code coverage in combinatorial, non-clocked, processes. +; Default is no deglitching. +; CoverDeglitchOn = 1 + +; Control the code coverage deglitching period. A period of 0, eliminates delta +; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a +; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". +; CoverDeglitchPeriod = 0 + +; Use this directory for compiler temporary files instead of "work/_temp" +; CompilerTempDir = /tmp + +; Set this to cause the compilers to force data to be committed to disk +; when the files are closed. +; SyncCompilerFiles = 1 + +; Add VHDL-AMS declarations to package STANDARD +; Default is not to add +; AmsStandard = 1 + +; Range and length checking will be performed on array indices and discrete +; ranges, and when violations are found within subprograms, errors will be +; reported. Default is to issue warnings for violations, because subprograms +; may not be invoked. +; NoDeferSubpgmCheck = 0 + +; Turn ON detection of FSMs having single bit current state variable. +; FsmSingle = 1 + +; Turn off reset state transitions in FSM. +; FsmResetTrans = 0 + +; Turn ON detection of FSM Implicit Transitions. +; FsmImplicitTrans = 1 + +; Controls whether or not to show immediate assertions with constant expressions +; in GUI/report/UCDB etc. By default, immediate assertions with constant +; expressions are shown in GUI/report/UCDB etc. This does not affect +; evaluation of immediate assertions. +; ShowConstantImmediateAsserts = 0 + +; Controls how VHDL basic identifiers are stored with the design unit. +; Does not make the language case-sensitive, affects only how declarations +; declared with basic identifiers have their names stored and printed +; (in the GUI, examine, etc.). +; Default is to preserve the case as originally depicted in the VHDL source. +; Value of 0 indicates to change all basic identifiers to lower case. +; PreserveCase = 0 + +; For Configuration Declarations, controls the effect that USE clauses have +; on visibility inside the configuration items being configured. If 1 +; (the default), then use pre-10.0 behavior. If 0, then for stricter LRM-compliance, +; extend the visibility of objects made visible through USE clauses into nested +; component configurations. +; OldVHDLConfigurationVisibility = 0 + +; Allows VHDL configuration declarations to be in a different library from +; the corresponding configured entity. Default is to not allow this for +; stricter LRM-compliance. +; SeparateConfigLibrary = 1; + +; Determine how mode OUT subprogram parameters of type array and record are treated. +; If 0 (the default), then only VHDL 2008 will do this initialization. +; If 1, always initialize the mode OUT parameter to its default value. +; If 2, do not initialize the mode OUT out parameter. +; Note that prior to release 10.1, all language versions did not initialize mode +; OUT array and record type parameters, unless overridden here via this mechanism. +; In release 10.1 and later, only files compiled with VHDL 2008 will cause this +; initialization, unless overridden here. +; InitOutCompositeParam = 0 + +; Generate symbols debugging database in only some special cases to save on +; the number of files in the library. For other design-units, this database is +; generated on-demand in vsim. +; Default is to to generate debugging database for all design-units. +; SmartDbgSym = 1 + +; Enable or disable automatic creation of missing libraries. +; Default is 1 (enabled) +; CreateLib = 1 + +; Describe compilation options according to matching file patterns. +; File pattern * matches all printing characters other than '/'. +; File pattern **/x matches all paths containing file/directory x. +; File pattern x/** matches all paths beginning at directory x. +; FileOptMap = (**/*.vhd => -2008); + +; Describe library targets of compilation according to matching file patterns. +; LibMap = (**/*.vhd => work); + +; Enable or Disable Auto-order compilation. +; Default is 0 (disabled) +; Autoorder = 0 + +[vlog] +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on Verilog hazard checking (order-dependent accessing of global vars). +; Default is off. +; Hazard = 1 + +; Turn on converting regular Verilog identifiers to uppercase. Allows case +; insensitivity for module names. Default is no conversion. +; UpCase = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn on bad option warning. Default is off. +; Show_BadOptionWarning = 1 + +; Revert back to IEEE 1364-1995 syntax, default is 0 (off). +; vlog95compat = 1 + +; Turn off PSL warning messages. Default is to show warnings. +; Show_PslChecksWarnings = 0 + +; Enable parsing of embedded PSL assertions. Default is enabled. +; EmbeddedPsl = 0 + +; Enable compiler statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list,kb] +; Add '-' to disable specific statistics. Default is [time,cmd,msg]. +; Stats = time,cmd,msg + +; Check vlog plusargs. Default is 0 (off). +; The command line equivalent is -check_plusargs <number>. +; 0 = Don't check plusargs (this is the default) +; 1 = Warning on unrecognized plusarg +; 2 = Error and exit on unrecognized plusarg +; CheckPlusargs = 1 + +; Set the threshold for automatically identifying sparse Verilog memories. +; A memory with total size in bytes equal to or more than the sparse memory +; threshold gets marked as sparse automatically, unless specified otherwise +; in source code or by the +nosparse commandline option of vlog or vopt. +; The default is 1M. (i.e. memories with total size equal +; to or greater than 1Mb are marked as sparse) +; SparseMemThreshold = 1048576 + +; Set the prefix to be honored for synthesis and coverage pragma recognition. +; Default is "". +; AddPragmaPrefix = "" + +; Ignore synthesis and coverage pragmas with this prefix. +; Default is "". +; IgnorePragmaPrefix = "" + +; Set the option to treat all files specified in a vlog invocation as a +; single compilation unit. The default value is set to 0 which will treat +; each file as a separate compilation unit as specified in the P1800 draft standard. +; MultiFileCompilationUnit = 1 + +; Turn on code coverage in Verilog design units. Default is off. +; Coverage = sbceft + +; Automatically exclude Verilog case statement default branches. +; Default is to not automatically exclude defaults. +; CoverExcludeDefault = 1 + +; Increase or decrease the maximum number of rows allowed in a UDP table +; implementing a VHDL condition coverage or expression coverage expression. +; More rows leads to a longer compile time, but more expressions covered. +; CoverMaxUDPRows = 192 + +; Increase or decrease the maximum number of input patterns that are present +; in FEC table. This leads to a longer compile time with more expressions +; covered with FEC metric. +; CoverMaxFECRows = 192 + +; Enable Multi Bit Expression Coverage in a Design, If design has expression with +; multi bit operands, this option enables its Expression Coverage. +; The default value is 0. +; CoverFecMultiBit = 1 + +; Increase or decrease the limit on the size of expressions and conditions +; considered for expression and condition coverages. Higher FecUdpEffort leads +; to higher compile, optimize and simulation time, but more expressions and +; conditions are considered for coverage in the design. FecUdpEffort can +; be set to a number ranging from 1 (low) to 3 (high), defined as: +; 1 - (low) Only small expressions and conditions considered for coverage. +; 2 - (medium) Bigger expressions and conditions considered for coverage. +; 3 - (high) Very large expressions and conditions considered for coverage. +; The default setting is 1 (low). +; FecUdpEffort = 1 + +; Enable or disable Focused Expression Coverage analysis for conditions and +; expressions. Focused Expression Coverage data is provided by default when +; expression and/or condition coverage is active. +; CoverFEC = 0 + +; Enable or disable UDP Coverage analysis for conditions and expressions. +; UDP Coverage data is disabled by default when expression and/or condition +; coverage is active. +; CoverUDP = 1 + +; Enable or disable Rapid Expression Coverage mode for conditions and expressions. +; Disabling this would convert non-masking conditions in FEC tables to matching +; input patterns. +; CoverREC = 1 + +; Enable or disable bit-blasting multi-bit operands of reduction prefix expressions +; for expression/condition coverage. +; NOTE: Enabling this may have a negative impact on simulation performance. +; CoverExpandReductionPrefix = 0 + +; Enable or disable short circuit evaluation of conditions and expressions when +; condition or expression coverage is active. Short circuit evaluation is enabled +; by default. +; CoverShortCircuit = 0 + +; Enable deglitching of code coverage in combinatorial, non-clocked, processes. +; Default is no deglitching. +; CoverDeglitchOn = 1 + +; Control the code coverage deglitching period. A period of 0, eliminates delta +; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a +; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". +; CoverDeglitchPeriod = 0 + +; Turn on code coverage in VLOG `celldefine modules, modules containing +; specify blocks, and modules included using vlog -v and -y. Default is off. +; CoverCells = 1 + +; Enable code coverage reporting of code that has been optimized away. +; The default is not to report. +; CoverReportCancelled = 1 + +; Control compiler and VOPT optimizations that are allowed when +; code coverage is on. This is a number from 0 to 5, with the following +; meanings (the default is 3): +; 5 -- All allowable optimizations are on. +; 4 -- Turn off removing unreferenced code. +; 3 -- Turn off process, always block and if statement merging. +; 2 -- Turn off expression optimization, converting primitives +; to continuous assignments, VHDL subprogram inlining. +; and VHDL clkOpt (converting FF's to builtins). +; 1 -- Turn off continuous assignment optimizations and clock suppression. +; 0 -- Turn off Verilog module inlining and VHDL arch inlining. +; HOWEVER, if fsm coverage is turned on, optimizations will be forced to +; level 3, with also turning off converting primitives to continuous assigns. +; CoverOpt = 3 + +; Specify the override for the default value of "cross_num_print_missing" +; option for the Cross in Covergroups. If not specified then LRM default +; value of 0 (zero) is used. This is a compile time option. +; SVCrossNumPrintMissingDefault = 0 + +; Setting following to 1 would cause creation of variables which +; would represent the value of Coverpoint expressions. This is used +; in conjunction with "SVCoverpointExprVariablePrefix" option +; in the modelsim.ini +; EnableSVCoverpointExprVariable = 0 + +; Specify the override for the prefix used in forming the variable names +; which represent the Coverpoint expressions. This is used in conjunction with +; "EnableSVCoverpointExprVariable" option of the modelsim.ini +; The default prefix is "expr". +; The variable name is +; variable name => <prefix>_<coverpoint name> +; SVCoverpointExprVariablePrefix = expr + +; Override for the default value of the SystemVerilog covergroup, +; coverpoint, and cross option.goal (defined to be 100 in the LRM). +; NOTE: It does not override specific assignments in SystemVerilog +; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal" +; in the [vsim] section can override this value. +; SVCovergroupGoalDefault = 100 + +; Override for the default value of the SystemVerilog covergroup, +; coverpoint, and cross type_option.goal (defined to be 100 in the LRM) +; NOTE: It does not override specific assignments in SystemVerilog +; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal" +; in the [vsim] section can override this value. +; SVCovergroupTypeGoalDefault = 100 + +; Specify the override for the default value of "strobe" option for the +; Covergroup Type. This is a compile time option which forces "strobe" to +; a user specified default value and supersedes SystemVerilog specified +; default value of '0'(zero). NOTE: This can be overriden by a runtime +; modelsim.ini variable "SVCovergroupStrobe" in the [vsim] section. +; SVCovergroupStrobeDefault = 0 + +; Specify the override for the default value of "per_instance" option for the +; Covergroup variables. This is a compile time option which forces "per_instance" +; to a user specified default value and supersedes SystemVerilog specified +; default value of '0'(zero). +; SVCovergroupPerInstanceDefault = 0 + +; Specify the override for the default value of "get_inst_coverage" option for the +; Covergroup variables. This is a compile time option which forces +; "get_inst_coverage" to a user specified default value and supersedes +; SystemVerilog specified default value of '0'(zero). +; SVCovergroupGetInstCoverageDefault = 0 + +; +; A space separated list of resource libraries that contain precompiled +; packages. The behavior is identical to using the "-L" switch. +; +; LibrarySearchPath = <path/lib> [<path/lib> ...] +LibrarySearchPath = mtiAvm mtiRnm mtiOvm mtiUvm mtiUPF infact + +; The behavior is identical to the "-mixedansiports" switch. Default is off. +; MixedAnsiPorts = 1 + +; Enable SystemVerilog 3.1a $typeof() function. Default is off. +; EnableTypeOf = 1 + +; Only allow lower case pragmas. Default is disabled. +; AcceptLowerCasePragmaOnly = 1 + +; Set the maximum depth permitted for a recursive include file nesting. +; IncludeRecursionDepthMax = 5 + +; Turn ON detection of FSMs having single bit current state variable. +; FsmSingle = 1 + +; Turn off reset state transitions in FSM. +; FsmResetTrans = 0 + +; Turn off detections of FSMs having x-assignment. +; FsmXAssign = 0 + +; Turn ON detection of FSM Implicit Transitions. +; FsmImplicitTrans = 1 + +; List of file suffixes which will be read as SystemVerilog. White space +; in extensions can be specified with a back-slash: "\ ". Back-slashes +; can be specified with two consecutive back-slashes: "\\"; +; SvFileSuffixes = sv svp svh + +; This setting is the same as the vlog -sv command line switch. +; Enables SystemVerilog features and keywords when true (1). +; When false (0), the rules of IEEE Std 1364-2005 are followed and +; SystemVerilog keywords are ignored. +; Svlog = 0 + +; Prints attribute placed upon SV packages during package import +; when true (1). The attribute will be ignored when this +; entry is false (0). The attribute name is "mti_design_element_load_message". +; The value of this attribute is a string literal. +; Default is true (1). +; PrintSVPackageLoadingAttribute = 1 + +; Do not show immediate assertions with constant expressions in +; GUI/reports/UCDB etc. By default immediate assertions with constant +; expressions are shown in GUI/reports/UCDB etc. This does not affect +; evaluation of immediate assertions. +; ShowConstantImmediateAsserts = 0 + +; Controls if untyped parameters that are initialized with values greater +; than 2147483647 are mapped to generics of type INTEGER or ignored. +; If mapped to VHDL Integers, values greater than 2147483647 +; are mapped to negative values. +; Default is to map these parameter to generic of type INTEGER +; ForceUnsignedToVHDLInteger = 1 + +; Enable AMS wreal (wired real) extensions. Default is 0. +; WrealType = 1 + +; Controls SystemVerilog Language Extensions. These options enable +; some non-LRM compliant behavior. +; SvExtensions = [+|-]<extension>[,[+|-]<extension>]* + +; Generate symbols debugging database in only some special cases to save on +; the number of files in the library. For other design-units, this database is +; generated on-demand in vsim. +; Default is to to generate debugging database for all design-units. +; SmartDbgSym = 1 + +; Controls how $unit library entries are named. Valid options are: +; "file" (generate name based on the first file on the command line) +; "du" (generate name based on first design unit following an item +; found in $unit scope) +; CUAutoName = file + +; Enable or disable automatic creation of missing libraries. +; Default is 1 (enabled) +; CreateLib = 1 + +; Enable generating a warning when a module is overwritten in different vlog sessions in case +; the RTL source files are different. +; Default is 0 (disabled) +; WarnDuOverwrite = 1 + +[sccom] +; Enable use of SCV include files and library. Default is off. +; UseScv = 1 + +; Add C++ compiler options to the sccom command line by using this variable. +; CppOptions = -g + +; Use custom C++ compiler located at this path rather than the default path. +; The path should point directly at a compiler executable. +; CppPath = /usr/bin/g++ + +; Specify the compiler version from the list of support GNU compilers. +; examples 4.7.4, 5.3.0, 7.4.0 +; CppInstall = 7.4.0 + +; Enable verbose messages from sccom. Default is off. +; SccomVerbose = 1 + +; sccom logfile. Default is no logfile. +; SccomLogfile = sccom.log + +; Enable use of SC_MS include files and library. Default is off. +; UseScMs = 1 + +; Enable compiler statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list,kb] +; Add '-' to disable specific statistics. Default is [time,cmd,msg]. +; Stats = time,cmd,msg + +; Enable or disable automatic creation of missing libraries. +; Default is 1 (enabled) +; CreateLib = 1 + +; Enable use of UVMC library. Default is off. +; UseUvmc = 1 + +[vopt] +; Check vopt plusargs. Default is 0 (off). +; The command line equivalent is -check_plusargs <number>. +; 0 = Don't check plusargs (this is the default) +; 1 = Warning on unrecognized plusarg +; 2 = Error and exit on unrecognized plusarg +; CheckPlusargs = 1 + +; Turn on code coverage in vopt. Default is off. +; Coverage = sbceft + +; enable or disable param saving in UCDB. +; CoverageSaveParam = 0 + +; Control compiler optimizations that are allowed when +; code coverage is on. Refer to the comment for this in the [vlog] area. +; CoverOpt = 3 + +; Controls set of CoverConstructs that are being considered for Coverage +; Collection. +; Some of Valid options are: default,set1,set2 +; Covermode = default + +; Override all PA VOPT and VSIM commands to run simulation in Non-PA mode. +; NonPAmode = 1 + +; Controls set of HDL cover constructs that would be considered(or not considered) +; for Coverage Collection. (Default corresponds to covermode default). +; Some of Valid options are: "ca", "citf", "cifl", "tcint", "fsmqs". +; Coverconstruct = noca,nocitf,nofsmtf,nofsmds,noctes,nocicl,nocprc,nocfl,nofsmup,nocifl,nocpm,notcint,nocpkg,nocsva + +; Increase or decrease the maximum number of rows allowed in a UDP table +; implementing a VHDL condition coverage or expression coverage expression. +; More rows leads to a longer compile time, but more expressions covered. +; CoverMaxUDPRows = 192 + +; Increase or decrease the maximum number of input patterns that are present +; in FEC table. This leads to a longer compile time with more expressions +; covered with FEC metric. +; CoverMaxFECRows = 192 + +; Enable Multi Bit Expression Coverage in a Design, If design has expression with +; multi bit operands, this option enables its Expression Coverage. +; The default value is 0. +; CoverFecMultiBit = 1 + +; Increase or decrease the limit on the size of expressions and conditions +; considered for expression and condition coverages. Higher FecUdpEffort leads +; to higher compile, optimize and simulation time, but more expressions and +; conditions are considered for coverage in the design. FecUdpEffort can +; be set to a number ranging from 1 (low) to 3 (high), defined as: +; 1 - (low) Only small expressions and conditions considered for coverage. +; 2 - (medium) Bigger expressions and conditions considered for coverage. +; 3 - (high) Very large expressions and conditions considered for coverage. +; The default setting is 1 (low). +; FecUdpEffort = 1 + +; Enable code coverage reporting of code that has been optimized away. +; The default is not to report. +; CoverReportCancelled = 1 + +; Enable deglitching of code coverage in combinatorial, non-clocked, processes. +; Default is no deglitching. +; CoverDeglitchOn = 1 + +; Enable compiler statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list,kb] +; Add '-' to disable specific statistics. Default is [time,cmd,msg]. +; Stats = time,cmd,msg + +; Control the code coverage deglitching period. A period of 0, eliminates delta +; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a +; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". +; CoverDeglitchPeriod = 0 + +; Do not show immediate assertions with constant expressions in +; GUI/reports/UCDB etc. By default immediate assertions with constant +; expressions are shown in GUI/reports/UCDB etc. This does not affect +; evaluation of immediate assertions. +; ShowConstantImmediateAsserts = 0 + +; Set the maximum number of iterations permitted for a generate loop. +; Restricting this permits the implementation to recognize infinite +; generate loops. +; GenerateLoopIterationMax = 100000 + +; Set the maximum depth permitted for a recursive generate instantiation. +; Restricting this permits the implementation to recognize infinite +; recursions. +; GenerateRecursionDepthMax = 200 + +; Set the number of processes created during the code generation phase. +; By default a heuristic is used to set this value. This may be set to 0 +; to disable this feature completely. +; ParallelJobs = 0 + +; Controls SystemVerilog Language Extensions. These options enable +; some non-LRM compliant behavior. +; SvExtensions = [+|-]<extension>[,[+|-]<extension>]* + +; Load the specified shared objects with the RTLD_GLOBAL flag. +; This gives global visibility to all symbols in the shared objects, +; meaning that subsequently loaded shared objects can bind to symbols +; in the global shared objects. The list of shared objects should +; be whitespace delimited. This option is not supported on the +; Windows or AIX platforms. +; GlobalSharedObjectList = example1.so example2.so example3.so + +; Disable SystemVerilog elaboration system task messages +; IgnoreSVAInfo = 1 +; IgnoreSVAWarning = 1 +; IgnoreSVAError = 1 +; IgnoreSVAFatal = 1 + +; Enable or disable automatic creation of missing libraries. +; Default is 1 (enabled) +; CreateLib = 1 + +[vsim] +; vopt flow +; Set to turn on automatic optimization of a design. +; Default is on +VoptFlow = 1 + +; Simulator resolution +; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. +Resolution = ns + +; Disable certain code coverage exclusions automatically. +; Assertions and FSM are exluded from the code coverage by default +; Set AutoExclusionsDisable = fsm to enable code coverage for fsm +; Set AutoExclusionsDisable = assertions to enable code coverage for assertions +; Set AutoExclusionsDisable = all to enable code coverage for all the automatic exclusions +; Or specify comma or space separated list +;AutoExclusionsDisable = fsm,assertions + +; User time unit for run commands +; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the +; unit specified for Resolution. For example, if Resolution is 100ps, +; then UserTimeUnit defaults to ps. +; Should generally be set to default. +UserTimeUnit = default + +; Default run length +RunLength = 100 + +; Maximum iterations that can be run without advancing simulation time +IterationLimit = 10000000 + +; Specify libraries to be searched for precompiled modules +; LibrarySearchPath = <path/lib> [<path/lib> ...] + +; Set XPROP assertion fail limit. Default is 5. +; Any positive integer, -1 for infinity. +; XpropAssertionLimit = 5 + +; Control PSL and Verilog Assume directives during simulation +; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts +; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts +; SimulateAssumeDirectives = 1 + +; Control the simulation of PSL and SVA +; These switches can be overridden by the vsim command line switches: +; -psl, -nopsl, -sva, -nosva. +; Set SimulatePSL = 0 to disable PSL simulation +; Set SimulatePSL = 1 to enable PSL simulation (default) +; SimulatePSL = 1 +; Set SimulateSVA = 0 to disable SVA simulation +; Set SimulateSVA = 1 to enable concurrent SVA simulation (default) +; SimulateSVA = 1 + +; Control SVA and VHDL immediate assertion directives during simulation +; Set SimulateImmedAsserts = 0 to disable simulation of immediate asserts +; Set SimulateImmedAsserts = 1 to enable simulation of immediate asserts +; SimulateImmedAsserts = 1 + +; License feature mappings for Verilog and VHDL +; qhsimvh Single language VHDL license +; qhsimvl Single language Verilog license +; msimhdlsim Language neutral license for either Verilog or VHDL +; msimhdlmix Second language only, language neutral license for either +; Verilog or VHDL +; +; Directives to license manager can be set either as single value or as +; space separated multi-values: +; vhdl Immediately checkout and hold a VHDL license (i.e., one of +; qhsimvh, msimhdlsim, or msimhdlmix) +; vlog Immediately checkout and hold a Verilog license (i.e., one of +; qhsimvl, msimhdlsim, or msimhdlmix) +; plus Immediately checkout and hold a VHDL license and a Verilog license +; noqueue Do not wait in the license queue when a license is not available +; viewsim Try for viewer license but accept simulator license(s) instead +; of queuing for viewer license (PE ONLY) +; noviewer Disable checkout of msimviewer license feature (PE ONLY) +; noslvhdl Disable checkout of qhsimvh license feature +; noslvlog Disable checkout of qhsimvl license feature +; nomix Disable checkout of msimhdlmix license feature +; nolnl Disable checkout of msimhdlsim license feature +; mixedonly Disable checkout of qhsimvh and qhsimvl license features +; lnlonly Disable checkout of qhsimvh,qhsimvl, and msimhdlmix license features +; +; Examples (remove ";" comment character to activate licensing directives): +; Single directive: +; License = plus +; Multi-directive (Note: space delimited directives): +; License = noqueue plus + +; Severity level of a VHDL assertion message or of a SystemVerilog severity system task +; which will cause a running simulation to stop. +; VHDL assertions and SystemVerilog severity system task that occur with the +; given severity or higher will cause a running simulation to stop. +; This value is ignored during elaboration. +; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal +BreakOnAssertion = 3 + +; Severity level of a tool message which will cause a running simulation to +; stop. This value is ignored during elaboration. Default is to not break. +; 0 = Note 1 = Warning 2 = Error 3 = Fatal +;BreakOnMessage = 2 + +; The class debug feature enables more visibility and tracking of class instances +; during simulation. By default this feature is disabled (0). To enable this +; feature set ClassDebug to 1. +; ClassDebug = 1 + +; Message Format conversion specifications: +; %S - Severity Level of message/assertion +; %R - Text of message +; %T - Time of message +; %D - Delta value (iteration number) of Time +; %K - Kind of path: Instance/Region/Signal/Process/Foreign Process/Unknown/Protected +; %i - Instance/Region/Signal pathname with Process name (if available) +; %I - shorthand for one of these: +; " %K: %i" +; " %K: %i File: %F" (when path is not Process or Signal) +; except that the %i in this case does not report the Process name +; %O - Process name +; %P - Instance/Region path without leaf process +; %F - File name +; %L - Line number; if assertion message, then line number of assertion or, if +; assertion is in a subprogram, line from which the call is made +; %u - Design unit name in form library.primary +; %U - Design unit name in form library.primary(secondary) +; %% - The '%' character itself +; +; If specific format for Severity Level is defined, use that format. +; Else, for a message that occurs during elaboration: +; -- Failure/Fatal message in VHDL region that is not a Process, and in +; certain non-VHDL regions, uses MessageFormatBreakLine; +; -- Failure/Fatal message otherwise uses MessageFormatBreak; +; -- Note/Warning/Error message uses MessageFormat. +; Else, for a message that occurs during runtime and triggers a breakpoint because +; of the BreakOnAssertion setting: +; -- if in a VHDL region that is not a Process, uses MessageFormatBreakLine; +; -- otherwise uses MessageFormatBreak. +; Else (a runtime message that does not trigger a breakpoint) uses MessageFormat. +; +; MessageFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n" +; MessageFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n" +; MessageFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormatBreakLine = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F Line: %L\n" +; MessageFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" + +; Error File - alternate file for storing error messages +; ErrorFile = error.log + +; Simulation Breakpoint messages +; This flag controls the display of function names when reporting the location +; where the simulator stops because of a breakpoint or fatal error. +; Example with function name: # Break in Process ctr at counter.vhd line 44 +; Example without function name: # Break at counter.vhd line 44 +; Default value is 1. +ShowFunctions = 1 + +; Default radix for all windows and commands. +; Radix may be one of: symbolic, ascii, binary, octal, decimal, hex, unsigned +; Flags may be one of: enumnumeric, showbase, wreal +DefaultRadix = hexadecimal +DefaultRadixFlags = showbase +; Set to 1 for make the signal_force VHDL and Verilog functions use the +; default radix when processing the force value. Prior to 10.2 signal_force +; used the default radix, now it always uses symbolic unless value explicitly indicates base +;SignalForceFunctionUseDefaultRadix = 0 + +; VSIM Startup command +; Startup = do startup.do + +; VSIM Shutdown file +; Filename to save u/i formats and configurations. +; ShutdownFile = restart.do +; To explicitly disable auto save: +; ShutdownFile = --disable-auto-save + +; Run simulator in batch mode as if -batch were specified on the command line if none of -c, -gui, or -i specified. +; Simulator runs in interactive mode as if -i were specified if this option is 0. Default is 0. +; BatchMode = 1 + +; File for saving command transcript when -batch option used +; This option is ignored when -c, -gui, or -i options are used or if BatchMode above is zero +; default is unset so command transcript only goes to stdout for better performance +; BatchTranscriptFile = transcript + +; File for saving command transcript, this option is ignored when -batch option is used +TranscriptFile = transcript + +; Transcript file long line wrapping mode(s) +; mode == 0 :: no wrapping, line recorded as is +; mode == 1 :: wrap at first whitespace after WSColumn +; or at Column. +; mode == 2 :: wrap as above, but add continuation +; character ('\') at end of each wrapped line +; +; WrapMode = 0 +; WrapColumn = 30000 +; WrapWSColumn = 27000 + +; File for saving command history +; CommandHistory = cmdhist.log + +; Specify whether paths in simulator commands should be described +; in VHDL or Verilog format. +; For VHDL, PathSeparator = / +; For Verilog, PathSeparator = . +; Must not be the same character as DatasetSeparator. +PathSeparator = / + +; Specify the dataset separator for fully rooted contexts. +; The default is ':'. For example: sim:/top +; Must not be the same character as PathSeparator. +DatasetSeparator = : + +; Specify a unique path separator for the Signal Spy set of functions. +; The default will be to use the PathSeparator variable. +; Must not be the same character as DatasetSeparator. +; SignalSpyPathSeparator = / + +; Used to control parsing of HDL identifiers input to the tool. +; This includes CLI commands, vsim/vopt/vlog/vcom options, +; string arguments to FLI/VPI/DPI calls, etc. +; If set to 1, accept either Verilog escaped Id syntax or +; VHDL extended id syntax, regardless of source language. +; If set to 0, the syntax of the source language must be used. +; Each identifier in a hierarchical name may need different syntax, +; e.g. "/top/\vhdl*ext*id\/middle/\vlog*ext*id /bottom" or +; "top.\vhdl*ext*id\.middle.\vlog*ext*id .bottom" +; GenerousIdentifierParsing = 1 + +; Disable VHDL assertion messages +; IgnoreNote = 1 +; IgnoreWarning = 1 +; IgnoreError = 1 +; IgnoreFailure = 1 + +; Disable SystemVerilog assertion messages +; IgnoreSVAInfo = 1 +; IgnoreSVAWarning = 1 +; IgnoreSVAError = 1 +; IgnoreSVAFatal = 1 + +; Do not print any additional information from Severity System tasks. +; Only the message provided by the user is printed along with severity +; information. +; SVAPrintOnlyUserMessage = 1; + +; Default force kind. May be freeze, drive, deposit, or default +; or in other terms, fixed, wired, or charged. +; A value of "default" will use the signal kind to determine the +; force kind, drive for resolved signals, freeze for unresolved signals +; DefaultForceKind = freeze + +; Control the iteration of events when a VHDL signal is forced to a value +; This flag can be set to honour the signal update event in next iteration, +; the default is to update and propagate in the same iteration. +; ForceSigNextIter = 1 + +; Enable simulation statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list,kb,eor] +; Add '-' to disable specific statistics. Default is [time,cmd,msg]. +; Stats = time,cmd,msg + +; If zero, open files when elaborated; otherwise, open files on +; first read or write. Default is 0. +; DelayFileOpen = 1 + +; Control VHDL files opened for write. +; 0 = Buffered, 1 = Unbuffered +UnbufferedOutput = 0 + +; Control the number of VHDL files open concurrently. +; This number should always be less than the current ulimit +; setting for max file descriptors. +; 0 = unlimited +ConcurrentFileLimit = 40 + +; If nonzero, close files as soon as there is either an explicit call to +; file_close, or when the file variable's scope is closed. When zero, a +; file opened in append mode is not closed in case it is immediately +; reopened in append mode; otherwise, the file will be closed at the +; point it is reopened. +; AppendClose = 1 + +; Control the number of hierarchical regions displayed as +; part of a signal name shown in the Wave window. +; A value of zero tells VSIM to display the full name. +; The default is 0. +; WaveSignalNameWidth = 0 + +; Turn off warnings when changing VHDL constants and generics +; Default is 1 to generate warning messages +; WarnConstantChange = 0 + +; Turn off warnings from accelerated versions of the std_logic_arith, +; std_logic_unsigned, and std_logic_signed packages. +; StdArithNoWarnings = 1 + +; Turn off warnings from accelerated versions of the IEEE numeric_std +; and numeric_bit packages. +; NumericStdNoWarnings = 1 + +; Use old-style (pre-6.6) VHDL FOR GENERATE statement iteration names +; in the design hierarchy. +; This style is controlled by the value of the GenerateFormat +; value described next. Default is to use new-style names, which +; comprise the generate statement label, '(', the value of the generate +; parameter, and a closing ')'. +; Set this to 1 to use old-style names. +; OldVhdlForGenNames = 1 + +; Control the format of the old-style VHDL FOR generate statement region +; name for each iteration. Do not quote the value. +; The format string here must contain the conversion codes %s and %d, +; in that order, and no other conversion codes. The %s represents +; the generate statement label; the %d represents the generate parameter value +; at a particular iteration (this is the position number if the generate parameter +; is of an enumeration type). Embedded whitespace is allowed (but discouraged); +; leading and trailing whitespace is ignored. +; Application of the format must result in a unique region name over all +; loop iterations for a particular immediately enclosing scope so that name +; lookup can function properly. The default is %s__%d. +; GenerateFormat = %s__%d + +; Enable more efficient logging of VHDL Variables. +; Logging VHDL variables without this enabled, while possible, is very +; inefficient. Enabling this will provide a more efficient logging methodology +; at the expense of more memory usage. By default this feature is disabled (0). +; To enabled this feature, set this variable to 1. +; VhdlVariableLogging = 1 + +; Enable logging of VHDL access type variables and their designated objects. +; This setting will allow both variables of an access type ("access variables") +; and their designated objects ("access objects") to be logged. Logging a +; variable of an access type will automatically also cause the designated +; object(s) of that variable to be logged as the simulation progresses. +; Further, enabling this allows access objects to be logged by name. By default +; this feature is disabled (0). To enable this feature, set this variable to 1. +; Enabling this will automatically enable the VhdlVariableLogging feature also. +; AccessObjDebug = 1 + +; Make each VHDL package in a PDU has its own separate copy of the package instead +; of sharing the package between PDUs. The default is to share packages. +; To ensure that each PDU has its own set of packages, set this variable to 1. +; VhdlSeparatePduPackage = 1 + +; Specify whether checkpoint files should be compressed. +; The default is 1 (compressed). +; CheckpointCompressMode = 0 + +; Specify gcc compiler used in the compilation of automatically generated DPI exportwrapper. +; Use custom gcc compiler located at this path rather than the default path. +; The path should point directly at a compiler executable. +; DpiCppPath = <your-gcc-installation>/bin/gcc +; +; Specify the compiler version from the list of support GNU compilers. +; examples 4.7.4, 5.3.0, 7.4.0 +; DpiCppInstall = 7.4.0 + +; Specify whether to enable SystemVerilog DPI "out-of-the-blue" calls. +; The term "out-of-the-blue" refers to SystemVerilog export function calls +; made from C functions that don't have the proper context setup +; (as is the case when running under "DPI-C" import functions). +; When this is enabled, one can call a DPI export function +; (but not task) from any C code. +; the setting of this variable can be one of the following values: +; 0 : dpioutoftheblue call is disabled (default) +; 1 : dpioutoftheblue call is enabled, but export call debug support is not available. +; 2 : dpioutoftheblue call is enabled, and limited export call debug support is available. +; DpiOutOfTheBlue = 1 + +; Specify whether continuous assignments are run before other normal priority +; processes scheduled in the same iteration. This event ordering minimizes race +; differences between optimized and non-optimized designs, and is the default +; behavior beginning with the 6.5 release. For pre-6.5 event ordering, set +; ImmediateContinuousAssign to 0. +; The default is 1 (enabled). +; ImmediateContinuousAssign = 0 + +; List of dynamically loaded objects for Verilog PLI applications +; Veriuser = veriuser.sl + +; Which default VPI object model should the tool conform to? +; The 1364 modes are Verilog-only, for backwards compatibility with older +; libraries, and SystemVerilog objects are not available in these modes. +; +; In the absence of a user-specified default, the tool default is the +; latest available LRM behavior. +; Options for PliCompatDefault are: +; VPI_COMPATIBILITY_VERSION_1364v1995 +; VPI_COMPATIBILITY_VERSION_1364v2001 +; VPI_COMPATIBILITY_VERSION_1364v2005 +; VPI_COMPATIBILITY_VERSION_1800v2005 +; VPI_COMPATIBILITY_VERSION_1800v2008 +; +; Synonyms for each string are also recognized: +; VPI_COMPATIBILITY_VERSION_1364v1995 (1995, 95, 1364v1995, 1364V1995, VL1995) +; VPI_COMPATIBILITY_VERSION_1364v2001 (2001, 01, 1364v2001, 1364V2001, VL2001) +; VPI_COMPATIBILITY_VERSION_1364v2005 (1364v2005, 1364V2005, VL2005) +; VPI_COMPATIBILITY_VERSION_1800v2005 (2005, 05, 1800v2005, 1800V2005, SV2005) +; VPI_COMPATIBILITY_VERSION_1800v2008 (2008, 08, 1800v2008, 1800V2008, SV2008) + + +; PliCompatDefault = VPI_COMPATIBILITY_VERSION_1800v2005 + +; Specify whether the Verilog system task $fopen or vpi_mcd_open() +; will create directories that do not exist when opening the file +; in "a" or "w" mode. +; The default is 0 (do not create non-existent directories) +; CreateDirForFileAccess = 1 + +; Specify default options for the restart command. Options can be one +; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions +; DefaultRestartOptions = -force + + +; Specify default UVM-aware debug options if the vsim -uvmcontrol switch is not used. +; Valid options include: all, none, verbose, disable, struct, reseed, msglog, trlog, certe. +; Options can be enabled by just adding the name, or disabled by prefixing the option with a "-". +; The list of options must be delimited by commas, without spaces or tabs. +; +; Some examples +; To turn on all available UVM-aware debug features: +; UVMControl = all +; To turn on the struct window, mesage logging, and transaction logging: +; UVMControl = struct,msglog,trlog +; To turn on all options except certe: +; UVMControl = all,-certe +; To completely disable all UVM-aware debug functionality: +; UVMControl = disable + +; Specify the WildcardFilter setting. +; A space separated list of object types to be excluded when performing +; wildcard matches with log, wave, etc commands. The default value for this variable is: +; "Variable Constant Generic Parameter SpecParam Memory Assertion Cover Endpoint ScVariable CellInternal ImmediateAssert VHDLFile" +; See "Using the WildcardFilter Preference Variable" in the documentation for +; details on how to use this variable and for descriptions of the filter types. +WildcardFilter = Variable Constant Generic Parameter SpecParam Memory Assertion Cover Endpoint ScVariable CellInternal ImmediateAssert VHDLFile + +; Specify the WildcardSizeThreshold setting. +; This integer setting specifies the size at which objects will be excluded when +; performing wildcard matches with log, wave, etc commands. Objects of size equal +; to or greater than the WildcardSizeThreshold will be filtered out from the wildcard +; matches. The size is a simple calculation of number of bits or items in the object. +; The default value is 8k (8192). Setting this value to 0 will disable the checking +; of object size against this threshold and allow all objects of any size to be logged. +WildcardSizeThreshold = 8192 + +; Specify whether warning messages are output when objects are filtered out due to the +; WildcardSizeThreshold. The default is 0 (no messages generated). +WildcardSizeThresholdVerbose = 0 + +; Turn on (1) or off (0) WLF file compression. +; The default is 1 (compress WLF file). +; WLFCompress = 0 + +; Specify whether to save all design hierarchy (1) in the WLF file +; or only regions containing logged signals (0). +; The default is 0 (save only regions with logged signals). +; WLFSaveAllRegions = 1 + +; WLF file time limit. Limit WLF file by time, as closely as possible, +; to the specified amount of simulation time. When the limit is exceeded +; the earliest times get truncated from the file. +; If both time and size limits are specified the most restrictive is used. +; UserTimeUnits are used if time units are not specified. +; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} +; WLFTimeLimit = 0 + +; WLF file size limit. Limit WLF file size, as closely as possible, +; to the specified number of megabytes. If both time and size limits +; are specified then the most restrictive is used. +; The default is 0 (no limit). +; WLFSizeLimit = 1000 + +; Specify whether or not a WLF file should be deleted when the +; simulation ends. A value of 1 will cause the WLF file to be deleted. +; The default is 0 (do not delete WLF file when simulation ends). +; WLFDeleteOnQuit = 1 + +; Specify whether or not a WLF file should be optimized during +; simulation. If set to 0, the WLF file will not be optimized. +; The default is 1, optimize the WLF file. +; WLFOptimize = 0 + +; Specify the name of the WLF file. +; The default is vsim.wlf +; WLFFilename = vsim.wlf + +; Specify whether to lock the WLF file. +; Locking the file prevents other invocations of ModelSim/Questa tools from +; inadvertently overwriting the WLF file. +; The default is 1, lock the WLF file. +; WLFFileLock = 0 + +; Specify the update interval for the WLF file in live simulation. +; The interval is given in seconds. +; The value is the smallest interval between WLF file updates. The WLF file +; will be flushed (updated) after (at least) the interval has elapsed, ensuring +; that the data is correct when viewed from a separate viewer. +; A value of 0 means that no updating will occur. +; The default value is 10 seconds. +; WLFUpdateInterval = 10 + +; Specify the WLF cache size limit for WLF files. +; The value is given in megabytes. A value of 0 turns off the cache. +; On non-Windows platforms the default WLFCacheSize setting is 2000 (megabytes). +; On Windows, the default value is 1000 (megabytes) to help to avoid filling +; process memory. +; WLFSimCacheSize allows a different cache size to be set for a live simulation +; WLF file, independent of post-simulation WLF file viewing. If WLFSimCacheSize +; is not set, it defaults to the WLFCacheSize value. +; WLFCacheSize = 2000 +; WLFSimCacheSize = 500 + +; Specify the WLF file event collapse mode. +; 0 = Preserve all events and event order. (same as -wlfnocollapse) +; 1 = Only record values of logged objects at the end of a simulator iteration. +; (same as -wlfcollapsedelta) +; 2 = Only record values of logged objects at the end of a simulator time step. +; (same as -wlfcollapsetime) +; The default is 1. +; WLFCollapseMode = 0 + +; Specify whether WLF file logging can use threads on multi-processor machines. +; If 0, no threads will be used; if 1, threads will be used if the system has +; more than one processor. +; WLFUseThreads = 1 + +; Specify the size of objects that will trigger "large object" messages +; at log/wave/list time. The size calculation of the object is the same as that +; used by the WildcardSizeThreshold. The default LargeObjectSize size is 500,000. +; Setting LargeObjectSize to 0 will disable these messages. +; LargeObjectSize = 500000 + +; Specify the depth of stack frames returned by $stacktrace([level]). +; This depth will be picked up when the optional 'level' argument +; is not specified or its value is not a positive integer. +; StackTraceDepth = 100 + +; Turn on/off undebuggable SystemC type warnings. Default is on. +; ShowUndebuggableScTypeWarning = 0 + +; Turn on/off unassociated SystemC name warnings. Default is off. +; ShowUnassociatedScNameWarning = 1 + +; Turn on/off SystemC IEEE 1666 deprecation warnings. Default is off. +; ScShowIeeeDeprecationWarnings = 1 + +; Turn on/off the check for multiple drivers on a SystemC sc_signal. Default is off. +; For SystemC-2.3.2 the valid values are 0,1 and 2 +; 0 = SC_SIGNAL_WRITE_CHECK_DISABLE_ +; 1 = SC_SIGNAL_WRITE_CHECK_DEFAULT_ +; 2 = SC_SIGNAL_WRITE_CHECK_CONFLICT_ +; For SystemC-2.2 the valid values are 0 and 1 +; 0 = DISABLE +; 1 = ENABLE +; ScEnableScSignalWriteCheck = 1 + +; Set SystemC default time unit. +; Set to fs, ps, ns, us, ms, or sec with optional +; prefix of 1, 10, or 100. The default is 1 ns. +; The ScTimeUnit value is honored if it is coarser than Resolution. +; If ScTimeUnit is finer than Resolution, it is set to the value +; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns, +; then the default time unit will be 1 ns. However if Resolution +; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns. +ScTimeUnit = ns + +; Set SystemC sc_main stack size. The stack size is set as an integer +; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or +; Gb(Giga-byte). Default is 10 Mb. The stack size for sc_main depends +; on the amount of data on the sc_main() stack and the memory required +; to succesfully execute the longest function call chain of sc_main(). +ScMainStackSize = 10 Mb + +; Set SystemC thread stack size. The stack size is set as an integer +; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or +; Gb(Giga-byte). The stack size for sc_thread depends +; on the amount of data on the sc_thread stack and the memory required +; to succesfully execute the thread. +; ScStackSize = 1 Mb + +; Turn on/off execution of remainder of sc_main upon quitting the current +; simulation session. If the cumulative length of sc_main() in terms of +; simulation time units is less than the length of the current simulation +; run upon quit or restart, sc_main() will be in the middle of execution. +; This switch gives the option to execute the remainder of sc_main upon +; quitting simulation. The drawback of not running sc_main till the end +; is memory leaks for objects created by sc_main. If on, the remainder of +; sc_main will be executed ignoring all delays. This may cause the simulator +; to crash if the code in sc_main is dependent on some simulation state. +; Default is on. +ScMainFinishOnQuit = 1 + +; Enable calling of the DPI export taks/functions from the +; SystemC start_of_simulation() callback. +; The default is off. +; EnableDpiSosCb = 1 + + +; Set the SCV relationship name that will be used to identify phase +; relations. If the name given to a transactor relation matches this +; name, the transactions involved will be treated as phase transactions +ScvPhaseRelationName = mti_phase + +; Customize the vsim kernel shutdown behavior at the end of the simulation. +; Some common causes of the end of simulation are $finish (implicit or explicit), +; sc_stop(), tf_dofinish(), and assertion failures. +; This should be set to "ask", "exit", or "stop". The default is "ask". +; "ask" -- In batch mode, the vsim kernel will abruptly exit. +; In GUI mode, a dialog box will pop up and ask for user confirmation +; whether or not to quit the simulation. +; "stop" -- Cause the simulation to stay loaded in memory. This can make some +; post-simulation tasks easier. +; "exit" -- The simulation will abruptly exit without asking for any confirmation. +; "final" -- Run SystemVerilog final blocks then behave as "stop". +; Note: This variable can be overridden with the vsim "-onfinish" command line switch. +OnFinish = ask + +; Print pending deferred assertion messages. +; Deferred assertion messages may be scheduled after the $finish in the same +; time step. Deferred assertions scheduled to print after the $finish are +; printed before exiting with severity level NOTE since it's not known whether +; the assertion is still valid due to being printed in the active region +; instead of the reactive region where they are normally printed. +; OnFinishPendingAssert = 1; + +; Print "simstats" result. Default is 0. +; 0 == do not print simstats +; 1 == print at end of simulation +; 2 == print at end of each run command and end of simulation +; PrintSimStats = 1 + +; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages +; AssertFile = assert.log + +; Enable assertion counts. Default is off. +; AssertionCounts = 1 + +; Run simulator in assertion debug mode. Default is off. +; AssertionDebug = 1 + +; Turn on/off PSL/SVA/VHDL assertion enable. Default is on. +; AssertionEnable = 0 + +; Set PSL/SVA/VHDL concurrent assertion fail limit. Default is -1. +; Any positive integer, -1 for infinity. +; AssertionLimit = 1 + +; Turn on/off concurrent assertion pass log. Default is off. +; Assertion pass logging is only enabled when assertion is browseable +; and assertion debug is enabled. +; AssertionPassLog = 1 + +; Turn on/off PSL concurrent assertion fail log. Default is on. +; The flag does not affect SVA +; AssertionFailLog = 0 + +; Turn on/off SVA concurrent assertion local var printing in -assertdebug mode. Default is on. +; AssertionFailLocalVarLog = 0 + +; Set action type for PSL/SVA concurrent assertion fail action. Default is continue. +; 0 = Continue 1 = Break 2 = Exit +; AssertionFailAction = 1 + +; Enable the active thread monitor in the waveform display when assertion debug is enabled. +; AssertionActiveThreadMonitor = 1 + +; Control how many waveform rows will be used for displaying the active threads. Default is 5. +; AssertionActiveThreadMonitorLimit = 5 + +; Assertion thread limit after which assertion would be killed/switched off. +; The default is -1 (unlimited). If the number of threads for an assertion go +; beyond this limit, the assertion would be either switched off or killed. This +; limit applies to only assert directives. +;AssertionThreadLimit = -1 + +; Action to be taken once the assertion thread limit is reached. Default +; is kill. It can have a value of off,kill or killon. In case of kill, all the existing +; threads are terminated and no new attempts are started. In case of off, the +; existing attempts keep on evaluating but no new attempts are started. In case of killon, +; all the existing threads are terminated but new attempts are started. This +; variable applies to only assert directives. +;AssertionThreadLimitAction = kill + +; Cover thread limit after which cover would be killed/switched off. +; The default is -1 (unlimited). If the number of threads for a cover go +; beyond this limit, the cover would be either switched off or killed. This +; limit applies to only cover directives. +;CoverThreadLimit = -1 + +; Action to be taken once the cover thread limit is reached. Default +; is kill. It can have a value of off, kill or killon. In case of kill, all the existing +; threads are terminated and no new attempts are started. In case of off, the +; existing attempts keep on evaluating but no new attempts are started. In case of killon, +; all the existing threads are terminated but new attempts are started. This +; variable applies to only cover directives. +;CoverThreadLimitAction = kill + + +; By default immediate assertions do not participate in Assertion Coverage calculations +; unless they are executed. This switch causes all immediate assertions in the design +; to participate in Assertion Coverage calculations, whether attempted or not. +; UnattemptedImmediateAssertions = 0 + +; By default immediate covers participate in Coverage calculations +; whether they are attempted or not. This switch causes all unattempted +; immediate covers in the design to stop participating in Coverage +; calculations. +; UnattemptedImmediateCovers = 0 + +; By default pass action block is not executed for assertions on vacuous +; success. The following variable is provided to enable execution of +; pass action block on vacuous success. The following variable is only effective +; if the user does not disable pass action block execution by using either +; system tasks or CLI. Also there is a performance penalty for enabling +; the following variable. +;AssertionEnableVacuousPassActionBlock = 1 + +; As per strict 1850-2005 PSL LRM, an always property can either pass +; or fail. However, by default, Questa reports multiple passes and +; multiple fails on top always/never property (always/never operator +; is the top operator under Verification Directive). The reason +; being that Questa reports passes and fails on per attempt of the +; top always/never property. Use the following flag to instruct +; Questa to strictly follow LRM. With this flag, all assert/never +; directives will start an attempt once at start of simulation. +; The attempt can either fail, match or match vacuously. +; For e.g. if always is the top operator under assert, the always will +; keep on checking the property at every clock. If the property under +; always fails, the directive will be considered failed and no more +; checking will be done for that directive. A top always property, +; if it does not fail, will show a pass at end of simulation. +; The default value is '0' (i.e. zero is off). For example: +; PslOneAttempt = 1 + +; Specify the number of clock ticks to represent infinite clock ticks. +; This affects eventually!, until! and until_!. If at End of Simulation +; (EOS) an active strong-property has not clocked this number of +; clock ticks then neither pass or fail (vacuous match) is returned +; else respective fail/pass is returned. The default value is '0' (zero) +; which effectively does not check for clock tick condition. For example: +; PslInfinityThreshold = 5000 + +; Control how many thread start times will be preserved for ATV viewing for a given assertion +; instance. Default is -1 (ALL). +; ATVStartTimeKeepCount = -1 + +; Turn on/off code coverage +; CodeCoverage = 0 + +; This option applies to condition and expression coverage UDP tables. It +; has no effect unless UDP is enabled for coverage with vcom/vlog/vopt -coverudp. +; If this option is used and a match occurs in more than one row in the UDP table, +; none of the counts for all matching rows is incremented. By default, counts are +; incremented for all matching rows. +; CoverCountAll = 1 + +; Turn off automatic inclusion of VHDL integers in toggle coverage. Default +; is to include them. +; ToggleNoIntegers = 1 + +; Set the maximum number of values that are collected for toggle coverage of +; VHDL integers. Default is 100; +; ToggleMaxIntValues = 100 + +; Set the maximum number of values that are collected for toggle coverage of +; Verilog real. Default is 100; +; ToggleMaxRealValues = 100 + +; Turn on automatic inclusion of Verilog integers in toggle coverage, except +; for enumeration types. Default is to include them. +; ToggleVlogIntegers = 0 + +; Turn on automatic inclusion of Verilog real type in toggle coverage, except +; for shortreal types. Default is to not include them. +; ToggleVlogReal = 1 + +; Turn on automatic inclusion of Verilog fixed-size unpacked arrays, VHDL multi-d arrays +; and VHDL arrays-of-arrays in toggle coverage. +; Default is to not include them. +; ToggleFixedSizeArray = 1 + +; Increase or decrease the maximum size of Verilog unpacked fixed-size arrays, +; VHDL multi-d arrays and VHDL arrays-of-arrays that are included for toggle coverage. +; This leads to a longer simulation time with bigger arrays covered with toggle coverage. +; Default is 1024. +; ToggleMaxFixedSizeArray = 1024 + +; Treat Verilog multi-dimensional packed vectors and packed structures as equivalently sized +; one-dimensional packed vectors for toggle coverage. Default is 0. +; TogglePackedAsVec = 0 + +; Treat Verilog enumerated types as equivalently sized one-dimensional packed vectors for +; toggle coverage. Default is 0. +; ToggleVlogEnumBits = 0 + +; Turn off automatic inclusion of VHDL records in toggle coverage. +; Default is to include them. +; ToggleVHDLRecords = 0 + +; Limit the widths of registers automatically tracked for toggle coverage. Default is 128. +; For unlimited width, set to 0. +; ToggleWidthLimit = 128 + +; Limit the counts that are tracked for toggle coverage. When all edges for a bit have +; reached this count, further activity on the bit is ignored. Default is 1. +; For unlimited counts, set to 0. +; ToggleCountLimit = 1 + +; Change the mode of extended toggle coverage. Default is 3. Valid modes are 1, 2 and 3. +; Following is the toggle coverage calculation criteria based on extended toggle mode: +; Mode 1: 0L->1H & 1H->0L & any one 'Z' transition (to/from 'Z'). +; Mode 2: 0L->1H & 1H->0L & one transition to 'Z' & one transition from 'Z'. +; Mode 3: 0L->1H & 1H->0L & all 'Z' transitions. +; ExtendedToggleMode = 3 + +; Enable toggle statistics collection only for ports. Default is 0. +; TogglePortsOnly = 1 + +; Limit the counts that are tracked for Focussed Expression Coverage. When a bin has +; reached this count, further tracking of the input patterns linked to it is ignored. +; Default is 1. For unlimited counts, set to 0. +; NOTE: Changing this value from its default value may affect simulation performance. +; FecCountLimit = 1 + +; Limit the counts that are tracked for UDP Coverage. When a bin has +; reached this count, further tracking of the input patterns linked to it is ignored. +; Default is 1. For unlimited counts, set to 0. +; NOTE: Changing this value from its default value may affect simulation performance. +; UdpCountLimit = 1 + +; Control toggle coverage deglitching period. A period of 0, eliminates delta +; cycle glitches. This is the default. The value of ToggleDeglitchPeriod needs to be either +; 0 or a time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". +; ToggleDeglitchPeriod = 10.0ps + +; Turn on/off all PSL/SVA cover directive enables. Default is on. +; CoverEnable = 0 + +; Turn on/off PSL/SVA cover log. Default is off "0". +; CoverLog = 1 + +; Set "at_least" value for all PSL/SVA cover directives. Default is 1. +; CoverAtLeast = 2 + +; Set "limit" value for all PSL/SVA cover directives. Default is -1. +; Any positive integer, -1 for infinity. +; CoverLimit = 1 + +; Specify the coverage database filename. +; Default is "" (i.e. database is NOT automatically saved on close). +; UCDBFilename = vsim.ucdb + +; Specify the maximum limit for the number of Cross (bin) products reported +; in XML and UCDB report against a Cross. A warning is issued if the limit +; is crossed. Default is zero. vsim switch -cvgmaxrptrhscross can override this +; setting. +; MaxReportRhsSVCrossProducts = 1000 + +; Specify the override for the "auto_bin_max" option for the Covergroups. +; If not specified then value from Covergroup "option" is used. +; SVCoverpointAutoBinMax = 64 + +; Specify the override for the value of "cross_num_print_missing" +; option for the Cross in Covergroups. If not specified then value +; specified in the "option.cross_num_print_missing" is used. This +; is a runtime option. NOTE: This overrides any "cross_num_print_missing" +; value specified by user in source file and any SVCrossNumPrintMissingDefault +; specified in modelsim.ini. +; SVCrossNumPrintMissing = 0 + +; Specify whether to use the value of "cross_num_print_missing" +; option in report and GUI for the Cross in Covergroups. If not specified then +; cross_num_print_missing is ignored for creating reports and displaying +; covergroups in GUI. Default is 0, which means ignore "cross_num_print_missing". +; UseSVCrossNumPrintMissing = 0 + +; Specify the threshold of Coverpoint wildcard bin value range size, above which +; a warning will be triggered. The default is 4K -- 12 wildcard bits. +; SVCoverpointWildCardBinValueSizeWarn = 4096 + +; Specify the override for the value of "strobe" option for the +; Covergroup Type. If not specified then value in "type_option.strobe" +; will be used. This is runtime option which forces "strobe" to +; user specified value and supersedes user specified values in the +; SystemVerilog Code. NOTE: This also overrides the compile time +; default value override specified using "SVCovergroupStrobeDefault" +; SVCovergroupStrobe = 0 + +; Override for explicit assignments in source code to "option.goal" of +; SystemVerilog covergroup, coverpoint, and cross. It also overrides the +; default value of "option.goal" (defined to be 100 in the SystemVerilog +; LRM) and the value of modelsim.ini variable "SVCovergroupGoalDefault". +; SVCovergroupGoal = 100 + +; Override for explicit assignments in source code to "type_option.goal" of +; SystemVerilog covergroup, coverpoint, and cross. It also overrides the +; default value of "type_option.goal" (defined to be 100 in the SystemVerilog +; LRM) and the value of modelsim.ini variable "SVCovergroupTypeGoalDefault". +; SVCovergroupTypeGoal = 100 + +; Enforce the 6.3 behavior of covergroup get_coverage() and get_inst_coverage() +; builtin functions, and report. This setting changes the default values of +; option.get_inst_coverage and type_option.merge_instances to ensure the 6.3 +; behavior if explicit assignments are not made on option.get_inst_coverage and +; type_option.merge_instances by the user. There are two vsim command line +; options, -cvg63 and -nocvg63 to override this setting from vsim command line. +; The default value of this variable from release 6.6 onwards is 0. This default +; drives compliance with the clarified behavior in the IEEE 1800-2009 standard. +; SVCovergroup63Compatibility = 0 + +; Enforce the default behavior of covergroup get_coverage() builtin function, GUI +; and report. This variable sets the default value of type_option.merge_instances. +; There are two vsim command line options, -cvgmergeinstances and +; -nocvgmergeinstances to override this setting from vsim command line. +; The default value of this variable, -1 (don't care), allows the tool to determine +; the effective value, based on factors related to capacity and optimization. +; The type_option.merge_instances appears in the GUI and coverage reports as either +; auto(1) or auto(0), depending on whether the effective value was determined to +; be a 1 or a 0. +; SVCovergroupMergeInstancesDefault = -1 + +; Enable or disable generation of more detailed information about the sampling +; of covergroup, cross, and coverpoints. It provides the details of the number +; of times the covergroup instance and type were sampled, as well as details +; about why covergroup, cross and coverpoint were not covered. A non-zero value +; is to enable this feature. 0 is to disable this feature. Default is 0 +; SVCovergroupSampleInfo = 0 + +; Specify the maximum number of Coverpoint bins in whole design for +; all Covergroups. +; MaxSVCoverpointBinsDesign = 2147483648 + +; Specify maximum number of Coverpoint bins in any instance of a Covergroup, default is 2^10 bins +; MaxSVCoverpointBinsInst = 1048576 + +; Specify the maximum number of Cross bins in whole design for +; all Covergroups. +; MaxSVCrossBinsDesign = 2147483648 + +; Specify maximum number of Cross bins in any instance of a Covergroup, default is 2^16 bins +; MaxSVCrossBinsInst = 67108864 + +; Specify whether vsim will collect the coverage data of zero-weight coverage items or not. +; By default, this variable is set 0, in which case option.no_collect setting will take effect. +; If this variable is set to 1, all zero-weight coverage items will not be saved. +; Note that the usage of vsim switch -cvgzwnocollect, if present, will override the setting +; of this variable. +; CvgZWNoCollect = 1 + +; Specify a space delimited list of double quoted TCL style +; regular expressions which will be matched against the text of all messages. +; If any regular expression is found to be contained within any message, the +; status for that message will not be propagated to the UCDB TESTSTATUS. +; If no match is detected, then the status will be propagated to the +; UCDB TESTSTATUS. More than one such regular expression text is allowed, +; and each message text is compared for each regular expression in the list. +; UCDBTestStatusMessageFilter = "Done with Test Bench" "Ignore .* message" + +; Set weight for all PSL/SVA cover directives. Default is 1. +; CoverWeight = 2 + +; Check vsim plusargs. Default is 0 (off). +; The command line equivalent is -check_plusargs <number>. +; 0 = Don't check plusargs (this is the default) +; 1 = Warning on unrecognized plusarg +; 2 = Error and exit on unrecognized plusarg +; CheckPlusargs = 1 + +; Load the specified shared objects with the RTLD_GLOBAL flag. +; This gives global visibility to all symbols in the shared objects, +; meaning that subsequently loaded shared objects can bind to symbols +; in the global shared objects. The list of shared objects should +; be whitespace delimited. This option is not supported on the +; Windows or AIX platforms. +; GlobalSharedObjectList = example1.so example2.so example3.so + +; Generate the stub definitions for the undefined symbols in the shared libraries being +; loaded in the simulation. When this flow is turned on, the undefined symbols will not +; prevent vsim from loading. Calling undefined symbols at runtime will cause fatal error. +; The valid arguments are: on, off, verbose. +; on : turn on the automatic generation of stub definitions. +; off: turn off the flow. The undefined symbols will trigger an immediate load failure. +; verbose: Turn on the flow and report the undefined symbols for each shared library. +; NOTE: This variable can be overriden with vsim switch "-undefsyms". +; The default is on. +; +; UndefSyms = off + +; Enable the support for automatically checkpointing foreign C/C++ libraries. +; The valid arguments are: 0, 1, 2 +; 0: off (default) +; 1: on (manually save/restore user shared library data) +; 2: auto (automatically save/restore user shared library data) +; This option is not supported on the Windows platforms. +; +; AllowCheckpointCpp = 2 + +; Initial seed for the random number generator of the root thread (SystemVerilog). +; NOTE: This variable can be overridden with the vsim "-sv_seed" command line switch. +; The default value is 0. +; Sv_Seed = 0 + +; Specify the solver "engine" that vsim will select for constrained random +; generation. +; Valid values are: +; "auto" - automatically select the best engine for the current +; constraint scenario +; "bdd" - evaluate all constraint scenarios using the BDD solver engine +; "act" - evaluate all constraint scenarios using the ACT solver engine +; While the BDD solver engine is generally efficient with constraint scenarios +; involving bitwise logical relationships, the ACT solver engine can exhibit +; superior performance with constraint scenarios involving large numbers of +; random variables related via arithmetic operators (+, *, etc). +; NOTE: This variable can be overridden with the vsim "-solveengine" command +; line switch. +; The default value is "auto". +; SolveEngine = auto + +; Specify the maximum size that a random dynamic array or queue may be resized +; to by the solver. If the solver attempts to resize a dynamic array or queue +; to a size greater than the specified limit, an error will be issued and +; randomize() will fail. The default value is 65535. A value of 0 disables the +; resize check (i.e. no error will be issued regardless of size). +; SolveArrayResizeMax = 65535 + +; Specify the maximum size that a random dynamic array or queue may be resized +; to by the solver without a warning. If the solver attempts to resize a dynamic +; array or queue to a size greater than the specified limit, a warning will be +; issued. The default value is 65535. A value of 0 disables the resize check +; (i.e. no warning will be issued regardless of size). +; SolveArrayResizeWarn = 65535 + +; Specify error message severity when randomize() and randomize(null) failures +; are detected. +; +; Integer value up to two digits are allowed with each digit having the following legal values: +; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal +; +; 1) When a value with two digits is used, the digit at tenth place (leftmost digit) represents +; the severtity setting for normal randomize() calls. The digit at ones place (rightmost digit) +; represents the setting for randomize(null) calls. +; +; 2) When a single digit value is used, the setting is applied to both normal randomize() call +; and randomize(null) call. +; +; Example: Fatal error for randomize() failures and NO error for randomize(null) failures +; -solvefailseverity=40 +; +; NOTE: SolveFailSeverity can affect the behavior of SolveFailDebug. When SolveFailDebug is +; enabled, a constraint contradiction report will be displayed for randomize() calls that +; have a message severity >= warning (i.e. constraint contradiction reports will not be +; generated for randomize() calls having a "no error" severity level) +; +; NOTE: This variable can be overridden with the vsim "-solvefailseverity" command +; line switch. +; +; The default is 1 (warning). +; SolveFailSeverity = 1 + +; Error message severity for suppressible errors that are detected in a +; solve/before constraint. +; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal +; NOTE: This variable can be overridden with the vsim "-solvebeforeerrorseverity" +; command line switch. +; The default is 2 (error). +; SolveBeforeErrorSeverity = 2 + +; Error message severity for suppressible errors that are related to +; solve engine capacity limits +; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal +; NOTE: This variable can be overridden with the vsim "-solveengineerrorseverity" +; command line switch. +; The default is 2 (error). +; SolveEngineErrorSeverity = 2 + +; Enable/disable constraint conflicts on randomize() failure +; Valid values: +; 0 - disable solvefaildebug +; 1 - basic debug (no performance penalty) +; 2 - enhanced debug (runtime performance penalty) +; +; NOTE: SolveFailSeverity can affect the behavior of SolveFailDebug. When SolveFailDebug is +; enabled, a constraint contradiction report will be displayed for randomize() calls that +; have a message severity >= warning (i.e. constraint contradiction reports will not be +; generated for randomize() calls having a "no error" severity level) +; +; NOTE: This variable can be overridden with the vsim "-solvefaildebug" command +; line switch. +; +; The default is 1 (basic debug). +; SolveFailDebug = 1 + +; Upon encountering a randomize() failure, generate a simplified testcase that +; will reproduce the failure. Optionally output the testcase to a file. +; Testcases for 'no-solution' failures will only be produced if SolveFailDebug +; is enabled (see above). +; NOTE: This variable can be overridden with the vsim "-solvefailtestcase" +; command line switch. +; The default is OFF (do not generate a testcase). To enable testcase +; generation, uncomment this variable. To redirect testcase generation to a +; file, specify the name of the output file. +; SolveFailTestcase = + +; Specify solver timeout threshold (in seconds). randomize() will fail if the +; CPU time required to evaluate the call exceeds the specified timeout. +; The default value is 1000. A value of 0 will disable timeout failures. +; SolveTimeout = 1000 + +; Specify the alternative behavior during solver replay. Must be used when combined with -solvereplay switch. +; Valid <opt> settings: +; validate : toggle the checking of value changes of non-random variables involved in randomize(). (default is off)" +; SolveReplayOpt=[+|-]<option>[,[+|-]<option>]* + +; Switch to specify options that control the behavior of the solver profiler. +; Valid options are: +; cputime - use CPU time instead of elapsed time (wall time) to measure performance data (default is off) +; randsets - enable detailed profiling of randsets (default is off) +; testgen - generate randset testcases (only when 'randsets' option is enabled, default is off) +; SolverFProf = [+|-]<option>[,[+|-]<option>]* + +; Specify the maximum size of the solution graph generated by the BDD solver. +; This value can be used to force the BDD solver to abort the evaluation of a +; complex constraint scenario that cannot be evaluated with finite memory. +; This value is specified in 1000s of nodes. +; The default value is 10000. A value of 0 indicates no limit. +; SolveGraphMaxSize = 10000 + +; Specify the maximum number of evaluations that may be performed on the +; solution graph by the BDD solver. This value can be used to force the BDD +; solver to abort the evaluation of a complex constraint scenario that cannot +; be evaluated in finite time. This value is specified in 10000s of evaluations. +; The default value is 10000. A value of 0 indicates no limit. +; SolveGraphMaxEval = 10000 + +; Specify random sequence compatiblity with a prior release. This +; option is used to get the same random sequences during simulation as +; as a prior release. Only prior releases with the same major version +; as the current release are allowed. +; NOTE: This variable can be overridden with the vsim "-solverev" command +; line switch. +; Default value set to "" (no compatibility). +; SolveRev = + +; Environment variable expansion of command line arguments has been deprecated +; in favor shell level expansion. Universal environment variable expansion +; inside -f files is support and continued support for MGC Location Maps provide +; alternative methods for handling flexible pathnames. +; The following line may be uncommented and the value set to 1 to re-enable this +; deprecated behavior. The default value is 0. +; DeprecatedEnvironmentVariableExpansion = 0 + +; Specify the memory threshold for the System Verilog garbage collector. +; The value is the number of megabytes of class objects that must accumulate +; before the garbage collector is run. +; The GCThreshold setting is used when class debug mode is disabled to allow +; less frequent garbage collection and better simulation performance. +; The GCThresholdClassDebug setting is used when class debug mode is enabled +; to allow for more frequent garbage collection. +; GCThreshold = 100 +; GCThresholdClassDebug = 5 + +; Turn on/off collapsing of bus ports in VCD dumpports output +DumpportsCollapse = 1 + +; Location of Multi-Level Verification Component (MVC) installation. +; The default location is the product installation directory. +MvcHome = $QUESTA_MVC_HOME + +; Location of InFact installation. The default is $MODEL_TECH/../../infact +; +; InFactHome = $MODEL_TECH/../../infact + +; Initialize SystemVerilog enums using the base type's default value +; instead of the leftmost value. +; EnumBaseInit = 1 + +; Suppress file type registration. +; SuppressFileTypeReg = 1 + +; Controls SystemVerilog Language Extensions. These options enable +; some non-LRM compliant behavior. +; SvExtensions = [+|-]<extension>[,[+|-]<extension>]* + +; Enable/disable non-LRM compliant SystemVerilog constrained-random language extensions. +; Valid extensions are: +; arraymode - consider rand_mode of unpacked array field independently from its elements +; deepcheck - allow randomize(null) to recursively consider constraints from member rand class handles (Default) +; dynext - enhanced evaluation for constraints involving random dynamic arrays that are resized during randomize() +; funcback - enable function backtracking (ACT only) +; nodist - interpret 'dist' constraint as 'inside' (ACT only) +; noorder - ignore solve/before ordering constraints (ACT only) +; oobidx - allow out-of-bounds value for an indexed-expression with random indices if indexed-expression yields a 2-state packed type +; prerandfirst - execute all pre_randomize() functions before evaluating any constraints (Default) +; promotedist - promote priority of 'dist' constraint if LHS has no solve/before +; purecheck - suppress pre_randomize() and post_randomize() calls for randomize(null) +; randcext - allow 'randc' and other 'rand' variables to be solved in the same randset (Default) +; randindex - allow random index in constraint (Default) +; randstruct - consider all fields of unpacked structs as 'rand' +; skew - skew randomize results (ACT only) +; srandom - interpret $srandom(seed) system task calls as equivalent process::self().srandom(seed) calls (Default) +; strictstab - strict random stability +; SvRandExtensions = [+|-]<extension>[,[+|-]<extension>]* + +; Controls the formatting of '%p' and '%P' conversion specification, used in $display +; and similar system tasks. +; 1. SVPrettyPrintFlags=I<n><S|T> use <n> spaces(S) or tabs(T) per indentation level. +; The 'I' flag when present causes relevant data types to be expanded and indented into +; a more readable format. +; (e.g. SVPrettyPrintFlags=I4S will cause 4 spaces to be used per indentation level). +; 2. SVPrettyPrintFlags=L<numLines> limits the output to <numLines> lines. +; (e.g. SVPrettyPrintFlags=L20 will limit the output to 20 lines). +; 3. SVPrettyPrintFlags=C<numChars> limits the output to <numChars> characters. +; (e.g. SVPrettyPrintFlags=C256 will limit the output to 256 characters). +; 4. SVPrettyPrintFlags=F<numFields> limits the output to <numFields> of relevant datatypes +; (e.g. SVPrettyPrintFlags=F4 will limit the output to 4 fields of a structure). +; 5. SVPrettyPrintFlags=E<numElements> limits the output to <numElements> of relevant datatypes +; (e.g. SVPrettyPrintFlags=E50 will limit the output to 50 elements of an array). +; 6. SVPrettyPrintFlags=D<depth> suppresses the output of sub-elements below <depth>. +; (e.g. SVPrettyPrintFlags=D5 will suppresses the output of sub elements below a depth of 5). +; 7. SVPrettyPrintFlags=R<specifier> shows the output of specifier %p as per the specifed radix. +; It changes the output in $display and similar systasks. It does not affect formatted output functions ($displayh etc)). +; (e.g. SVPrettyPrintFlags=Rb will show the output of %p specifier in binary format. +; 8. Items 1-7 above can be combined as a comma separated list. +; (e.g. SVPrettyPrintFlags=I4S,L20,C256,F4,E50,D5,Rb) +; SVPrettyPrintFlags=I4S + +[lmc] +; The simulator's interface to Logic Modeling's SmartModel SWIFT software +libsm = $MODEL_TECH/libsm.sl +; The simulator's interface to Logic Modeling's SmartModel SWIFT software (Windows NT) +; libsm = $MODEL_TECH/libsm.dll +; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700) +; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl +; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000) +; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o +; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris) +; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so +; Logic Modeling's SmartModel SWIFT software (Windows NT) +; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll +; Logic Modeling's SmartModel SWIFT software (non-Enterprise versions of Linux) +; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so +; Logic Modeling's SmartModel SWIFT software (Enterprise versions of Linux) +; libswift = $LMC_HOME/lib/linux.lib/libswift.so + +; The simulator's interface to Logic Modeling's hardware modeler SFI software +libhm = $MODEL_TECH/libhm.sl +; The simulator's interface to Logic Modeling's hardware modeler SFI software (Windows NT) +; libhm = $MODEL_TECH/libhm.dll +; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700) +; libsfi = <sfi_dir>/lib/hp700/libsfi.sl +; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000) +; libsfi = <sfi_dir>/lib/rs6000/libsfi.a +; Logic Modeling's hardware modeler SFI software (Sun4 Solaris) +; libsfi = <sfi_dir>/lib/sun4.solaris/libsfi.so +; Logic Modeling's hardware modeler SFI software (Windows NT) +; libsfi = <sfi_dir>/lib/pcnt/lm_sfi.dll +; Logic Modeling's hardware modeler SFI software (Linux) +; libsfi = <sfi_dir>/lib/linux/libsfi.so + +[msg_system] +; Change a message severity or suppress a message. +; The format is: <msg directive> = <msg number>[,<msg number>...] +; suppress can be used to achieve +nowarn<CODE> functionality +; The format is: suppress = <CODE>,<msg number>,[<CODE>,<msg number>,...] +; Examples: +suppress = 8780 ;an explanation can be had by running: verror 8780 +; note = 3009 +; warning = 3033 +; error = 3010,3016 +; fatal = 3016,3033 +; suppress = 3009,3016,3601 +; suppress = 3009,CNNODP,3601,TFMPC +; suppress = 8683,8684 +; The command verror <msg number> can be used to get the complete +; description of a message. + +; Control transcripting of Verilog display system task messages and +; PLI/FLI print function call messages. The system tasks include +; $display[bho], $strobe[bho], $monitor[bho], and $write[bho]. They +; also include the analogous file I/O tasks that write to STDOUT +; (i.e. $fwrite or $fdisplay). The PLI/FLI calls include io_printf, +; vpi_printf, mti_PrintMessage, and mti_PrintFormatted. The default +; is to have messages appear only in the transcript. The other +; settings are to send messages to the wlf file only (messages that +; are recorded in the wlf file can be viewed in the MsgViewer) or +; to both the transcript and the wlf file. The valid values are +; tran {transcript only (default)} +; wlf {wlf file only} +; both {transcript and wlf file} +; displaymsgmode = tran + +; Control transcripting of elaboration/runtime messages not +; addressed by the displaymsgmode setting. The default is to +; have messages appear only in the transcript. The other settings +; are to send messages to the wlf file only (messages that are +; recorded in the wlf file can be viewed in the MsgViewer) or to both +; the transcript and the wlf file. The valid values are +; tran {transcript only (default)} +; wlf {wlf file only} +; both {transcript and wlf file} +; msgmode = tran + +; Controls number of displays of a particluar message +; default value is 5 +; MsgLimitCount = 5 + +[utils] +; Default Library Type (while creating a library with "vlib") +; 0 - legacy library using subdirectories for design units +; 2 - flat library +; DefaultLibType = 2 + +; Flat Library Page Size (while creating a library with "vlib") +; Set the size in bytes for flat library file pages. Libraries containing +; very large files may benefit from a larger value. +; FlatLibPageSize = 8192 + +; Flat Library Page Cleanup Percentage (while creating a library with "vlib") +; Set the percentage of total pages deleted before library cleanup can occur. +; This setting is applied together with FlatLibPageDeleteThreshold. +; FlatLibPageDeletePercentage = 50 + +; Flat Library Page Cleanup Threshold (while creating a library with "vlib") +; Set the number of pages deleted before library cleanup can occur. +; This setting is applied together with FlatLibPageDeletePercentage. +; FlatLibPageDeleteThreshold = 1000 + diff --git a/sim/win/sim.do b/sim/win/sim.do new file mode 100644 index 0000000..5277b81 --- /dev/null +++ b/sim/win/sim.do @@ -0,0 +1,2 @@ +# assumes the work libraries are already built. +vsim -voptargs="+acc" -L work -L work_lib -L lpm_ver -L sgate_ver -L altera_ver -L altera_mf_ver -L altera_lnsim_ver -L tennm_ver -L tennm_sm_hps_ver -L tennm_sm4_hssi_ver -L tennm_revb_hvio_ver -L tennm_revb_io96_ver -L altera_iopll_2110 -L pll_io -L altera_gpio_core10_ph2_2210 -L altera_gpio_2300 -L ddr_o -L ddr_i tb
\ No newline at end of file diff --git a/src/ml_module_agilex.v b/src/ml_module_agilex.v new file mode 100644 index 0000000..ad25cf6 --- /dev/null +++ b/src/ml_module_agilex.v @@ -0,0 +1,96 @@ + +/* + * ml_module_agilex.v + * + * Copyright (C) 2026 Private Island Networks Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * function: top module for Machine Learning Module using Agilex 3 + * + * + */ + +module ml_module_agilex ( + input rstn, + input clk_i, // 25Mhz input + +`ifdef SIMULATION + output pll_locked_o, + output pclk, // primary clock +`endif + + // RGMII PHY Emulation, Module GigE Interface + input rgmii_rx_clk, + input rgmii_rx_ctl, + input [3:0] rgmii_rx_d, + + output rgmii_tx_clk, + output rgmii_tx_ctl, + output [3:0] rgmii_tx_d, + + input rgmii_mdc, + inout rgmii_mdio, + + output rgmii_intn, + output [1:0] rgmii_gpio, + + // Alternate High Speed LVDS Interface + + // Configuration ROM / FLASH (Xccela) Interface + output flash_clk, + input flash_dqs, + output flash_seln, + inout [7:0] flash_d, + + // Optional LPDDR4 Exernal DDR Memory + + // Optional LVDS SMA Interface + + // Optional GPIO External Connector for Expansion + + // Debug + output [2:0] fpga_led +); + +wire [1:0] tx_ctl, rx_ctl; +wire [7:0] tx_d, rx_d; + +pll_io pll_0( + .refclk(clk_i), // refclk.clk, The reference clock source that drives the I/O PLL. + .locked(pll_locked_o), // locked.export, The IOPLL IP core drives this port high when the PLL acquires lock. The port remains high as long as the I/O PLL is locked. The I/O PLL asserts the locked port when the phases and frequencies of the reference clock and feedback clock are the same or within the lock circuit tolerance. When the difference between the two clock signals exceeds the lock circuit tolerance, the I/O PLL loses lock. + .rst(~rstn), // reset.reset, The asynchronous reset port for the output clocks. Drive this port high to reset all output clocks to the value of 0. + .outclk_0(clk_25), // outclk0.clk, Output clock Channel 0 from I/O PLL. + .outclk_1(clk_125) // outclk1.clk, Output clock Channel 1 from I/O PLL. +); + +ddr_i rgmii_i ( + .ck(rgmii_rx_clk), + .dout({{rx_ctl[1],rx_d[7:4]},{rx_ctl[0],rx_d[3:0]}}), + .pad_in({rgmii_rx_ctl, rgmii_rx_d}) +); + +// Simple loopback +assign tx_ctl = rx_ctl; +assign tx_d = rx_d; + +ddr_o rgmii_o( + .ck(clk_125), + .din({{1'b0, tx_ctl[1], tx_d[7:4]},{1'b1, tx_ctl[0], tx_d[3:0]}}), + .pad_out({rgmii_tx_clk, rgmii_tx_ctl, rgmii_tx_d}) +); + +assign fpga_led = 3'b101; + + +endmodule |
