aboutsummaryrefslogtreecommitdiffhomepage
path: root/sim/win/sim.do
blob: 5277b81af43deafaa1c0c159443fa7de748b6bc1 (plain)
1
2
# assumes the work libraries are already built.
vsim -voptargs="+acc" -L work -L work_lib -L lpm_ver -L sgate_ver -L altera_ver -L altera_mf_ver -L altera_lnsim_ver -L tennm_ver -L tennm_sm_hps_ver -L tennm_sm4_hssi_ver -L tennm_revb_hvio_ver -L tennm_revb_io96_ver -L altera_iopll_2110 -L pll_io -L altera_gpio_core10_ph2_2210 -L altera_gpio_2300 -L ddr_o -L ddr_i tb 

Highly Recommended Verilog Books