privateisland - FPGA network processor

summary refs log tree commit diff homepage

path: root/boards/darsena/labs.trc

Age	Commit message (Expand)	Author
2019-07-08	ldf: update project file to include reveal files for lab exercises	mindchasers
2019-07-08	reveal: add labs reveal files to support lab exercises	mindchasers

Highly Recommended Verilog Books

Digital VLSI Design with Verilog: A Textbook from Silicon Valley Polytechnic Institute

The Verilog Hardware Description Language

Verilog HDL A Guide to Digital Design and Synthesis