gpio: first pass changes to support new GPIO daughter boardgpio

1 files changed, 52 insertions, 9 deletions

diff --git a/src/controller.v b/src/controller.v
index e30d461..b0e7689 100644
--- a/src/controller.v
+++ b/src/controller.v
@@ -77,7 +77,17 @@ module controller	#(parameter MDIO_ADDR_SZ = 7, parameter NUM_PHYS=3)
 	output reg [NUM_PHYS-1:0] mac_reset,
 	
 	// Debug
-	output [7:0] gpio	
+// ===========================
+// GPIO INTERFACE
+// ===========================
+`ifdef GPIO_PRESENT
+	input [19:0] gpio_in,
+	output [19:0] gpio_out,
+	output [19:0] gpio_out_en
+`else
+	output [7:0] gpio
+`endif
+
 );
 
 `define INCLUDED
@@ -125,6 +135,13 @@ module controller	#(parameter MDIO_ADDR_SZ = 7, parameter NUM_PHYS=3)
 	reg [3:0] mi_state; // mdio init state 
 	reg [7:0] mdio_init_cnt;
 	reg [1:0] mdio_init_mux_sel;
+// ============================
+// GPIO REGISTERS
+// ============================
+`ifdef GPIO_PRESENT 
+	reg [19:0] gpio_direction; //1 = output, 0 = input
+	reg [19:0] gpio_value;
+`endif
 	
 	// metastability synchronizer regs
 	reg rx_fifo_int_m1, rx_fifo_int_m2;
@@ -323,8 +340,8 @@ module controller	#(parameter MDIO_ADDR_SZ = 7, parameter NUM_PHYS=3)
 		else if (mem_state == MEM_ST_RD_FIFO && rx_cnt == 5'd11)
 			msg_data[7:0] <= mem_d_i[7:0];
 		
-	// msg_response
-	always @(posedge clk, negedge rstn)
+		// msg_response
+	always @(posedge clk or negedge rstn)
 		if (!rstn)
 			msg_response <= 16'heeee;
 		else if (mem_state == MEM_ST_IDLE)
@@ -341,9 +358,14 @@ module controller	#(parameter MDIO_ADDR_SZ = 7, parameter NUM_PHYS=3)
 				{MSG_MAC_ADDR[15:8],8'h??}: msg_response <= mem_d_i;
 				{MSG_MDIO_ADDR[15:8],8'h??}: msg_response <= mdio_d;
 				{MSG_MLE_ADDR[15:8],8'h??}: msg_response <= mem_d_i;
+`ifdef GPIO_PRESENT
+    16'h0030: msg_response <= gpio_direction;
+    16'h0034: msg_response <= gpio_value;
+    16'h0038: msg_response <= gpio_in;
+`endif
 				default: msg_response <= mem_d_i[15:0];
-			endcase	
-
+			endcase
+  
 
 /***********************************************************************
  * 
@@ -388,7 +410,16 @@ module controller	#(parameter MDIO_ADDR_SZ = 7, parameter NUM_PHYS=3)
 		
 	// set mdio_phy_addr
 	assign mdio_phy_addr = 5'h00;		// Set phy_addr[3:2]
-		
+	
+// =================================================
+// GPIO OUTPUT CONNECTIONS
+// Connect controller registers to GPIO interface
+// =================================================
+`ifdef GPIO_PRESENT
+	assign gpio_out = gpio_value;
+	assign gpio_out_en = gpio_direction;
+`endif
+
 	// set mdio_reg_addr
     always @(posedge clk or negedge rstn) 
 		begin 
@@ -422,7 +453,8 @@ module controller	#(parameter MDIO_ADDR_SZ = 7, parameter NUM_PHYS=3)
 			mdio_d <= 16'h0000;
 		else if (mdio_we)
 			mdio_d <= mdio_d_i;
-	end	
+	end
+
 		
 	// PHY Reset
 	always @(posedge clk, negedge rstn)	
@@ -704,6 +736,10 @@ module controller	#(parameter MDIO_ADDR_SZ = 7, parameter NUM_PHYS=3)
 			mac_addr <= 2'd0;
 			mdio_mux_sel <= 2'b00;
 			pkt_filter_addr <= 16'd0;
+	`ifdef GPIO_PRESENT
+		gpio_direction <= 20'd0;
+		gpio_value <= 20'd0;
+	`endif
 		end
 		else if (rx_msg_captured && !msg_error && msg_type == MSG_TYPE_WRITE) begin
 			if (msg_addr==MAC_ADDR)
@@ -712,8 +748,15 @@ module controller	#(parameter MDIO_ADDR_SZ = 7, parameter NUM_PHYS=3)
 				mdio_mux_sel <= msg_data[1:0];
 			else if (msg_addr==PKT_FILT_ADDR)
 				pkt_filter_addr <= msg_data[15:0];
+	`ifdef GPIO_PRESENT
+		else if (msg_addr == 16'h0030)
+			gpio_direction <= msg_data[19:0];
+		else if (msg_addr == 16'h0034)
+			gpio_value <= msg_data[19:0];
+	`endif
 		end
 		
+		
 	/***********************************************************************
 	 * 
 	 * 	MDIO Initialization
@@ -793,7 +836,7 @@ module controller	#(parameter MDIO_ADDR_SZ = 7, parameter NUM_PHYS=3)
 	/* 
 	 * 	Debug
 	 */
-	assign gpio = 8'h00;
+
 
 			
-endmodule
+endmodule
\ No newline at end of file