summaryrefslogtreecommitdiffhomepage
path: root/source
diff options
context:
space:
mode:
authormindchasers <privateisland@mindchasers.com>2021-06-30 20:15:41 -0400
committermindchasers <privateisland@mindchasers.com>2021-06-30 20:15:41 -0400
commit55bb92f3d547aafb15926639a11b4038097eedf0 (patch)
tree21041d1cc75d2f4ca713b254d469b7b7feb0648b /source
parenteb791420392e21f011c37c7e78e4259189f39906 (diff)
controller: rm i2c_fifo_priority because it is no longer used
Diffstat (limited to 'source')
-rw-r--r--source/controller.v2
1 files changed, 0 insertions, 2 deletions
diff --git a/source/controller.v b/source/controller.v
index c695938..2b95d1e 100644
--- a/source/controller.v
+++ b/source/controller.v
@@ -74,7 +74,6 @@ module controller #(parameter ADDR_SZ = 7)
output [3:0] rx_pcs_rst,
output reg [1:0] mdio_mux_sel,
- output i2c_fifo_priority,
// TX custom packet
output reg tx_custom
@@ -130,7 +129,6 @@ module controller #(parameter ADDR_SZ = 7)
reg cont_start, cont_busy, cont_done;
- assign i2c_fifo_priority = 1'b1;
assign pcs_s = { pll_lol, pcs_rx_error };
assign link_s = port_up;

Highly Recommended Verilog Books