summaryrefslogtreecommitdiffhomepage
path: root/manufacturer/altera/cyclone10_lp/ip/pll/pll_inst.v
diff options
context:
space:
mode:
authorPrivate Island Networks Inc <opensource@privateisland.tech>2025-12-21 20:51:04 -0500
committerPrivate Island Networks Inc <opensource@privateisland.tech>2025-12-21 20:51:04 -0500
commit7b1b5e7eb712d41888398934834cae730e0aa5a0 (patch)
tree8b8aba85e19a079fbbd4962c57ff89ca701c6e4d /manufacturer/altera/cyclone10_lp/ip/pll/pll_inst.v
parentf4bdc9f4365d3a3ce3f906e68cd018cb57561e56 (diff)
betsy: preliminary beta snapshot
Diffstat (limited to 'manufacturer/altera/cyclone10_lp/ip/pll/pll_inst.v')
-rw-r--r--manufacturer/altera/cyclone10_lp/ip/pll/pll_inst.v7
1 files changed, 7 insertions, 0 deletions
diff --git a/manufacturer/altera/cyclone10_lp/ip/pll/pll_inst.v b/manufacturer/altera/cyclone10_lp/ip/pll/pll_inst.v
new file mode 100644
index 0000000..6da79e5
--- /dev/null
+++ b/manufacturer/altera/cyclone10_lp/ip/pll/pll_inst.v
@@ -0,0 +1,7 @@
+pll pll_inst (
+ .areset ( areset_sig ),
+ .inclk0 ( inclk0_sig ),
+ .c0 ( c0_sig ),
+ .c1 ( c1_sig ),
+ .locked ( locked_sig )
+ );

Highly Recommended Verilog Books