summaryrefslogtreecommitdiffhomepage
path: root/FOOTPRINTS.pretty/TP25_VIA.kicad_mod
blob: 519f8bc1ce3cf18501140ea268b7e368fbd695bb (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
(footprint "TP25_VIA"
	(version 20241229)
	(generator "pcbnew")
	(generator_version "9.0")
	(layer "F.Cu")
	(descr "25 MIL ROUND TP")
	(property "Reference" "REF**"
		(at 0 -1.0175 0)
		(layer "F.SilkS")
		(uuid "9c60904a-6559-4543-b295-e9d589d20daa")
		(effects
			(font
				(size 1 1)
				(thickness 0.15)
			)
		)
	)
	(property "Value" "TP25_VIA"
		(at 0 1.0175 0)
		(layer "F.Fab")
		(uuid "313cdccf-688c-463e-a0f0-a2fc3c858563")
		(effects
			(font
				(size 1 1)
				(thickness 0.15)
			)
		)
	)
	(property "Datasheet" ""
		(at 0 0 0)
		(layer "F.Fab")
		(hide yes)
		(uuid "5554d677-0640-4620-8b42-40ef24d542a3")
		(effects
			(font
				(size 1 1)
				(thickness 0.15)
			)
		)
	)
	(property "Description" ""
		(at 0 0 0)
		(layer "F.Fab")
		(hide yes)
		(uuid "c1595a9c-6539-41ee-95a1-c173c1a779f9")
		(effects
			(font
				(size 1 1)
				(thickness 0.15)
			)
		)
	)
	(pad "1" thru_hole circle
		(at 0 0)
		(size 0.635 0.635)
		(drill 0.2)
		(layers "*.Cu" "*.Mask")
		(remove_unused_layers no)
		(solder_paste_margin -2147.48364)
		(thermal_bridge_angle 90)
		(uuid "553ad029-b712-4b13-9aaa-b04d23555447")
	)
	(embedded_fonts no)
)

Highly Recommended Verilog Books