ml_module_agilex3 - ML Module using Agilex 3 for Betsy

summary refs log tree commit diff homepage

path: root/FOOTPRINTS.pretty/CAPC3216X120.kicad_mod

Age	Commit message (Collapse)	Author
16 hours	initial commit of design template + starting local librariesHEAD master	Private Island Networks Inc.

Highly Recommended Verilog Books

Digital VLSI Design with Verilog: A Textbook from Silicon Valley Polytechnic Institute

The Verilog Hardware Description Language

Verilog HDL A Guide to Digital Design and Synthesis