diff options
Diffstat (limited to 'ml_module_agilex3.kicad_pro')
| -rw-r--r-- | ml_module_agilex3.kicad_pro | 96 |
1 files changed, 92 insertions, 4 deletions
diff --git a/ml_module_agilex3.kicad_pro b/ml_module_agilex3.kicad_pro index 3ff92aa..095a30e 100644 --- a/ml_module_agilex3.kicad_pro +++ b/ml_module_agilex3.kicad_pro @@ -50,7 +50,23 @@ "silk_text_thickness": 0.1, "silk_text_upright": false, "zones": { - "min_clearance": 0.5 + "border_display_style": 2, + "border_hatch_pitch": 0.5, + "corner_radius": 0.0, + "corner_smoothing": 0, + "fill_mode": 0, + "hatch_gap": 1.5, + "hatch_orientation": 0.0, + "hatch_smoothing_level": 0, + "hatch_smoothing_value": 0.1, + "hatch_thickness": 1.0, + "min_clearance": 0.5, + "min_island_area": 10.0, + "min_thickness": 0.25, + "pad_connection": 1, + "remove_islands": 0, + "thermal_relief_gap": 0.5, + "thermal_relief_spoke_width": 0.5 } }, "diff_pair_dimensions": [], @@ -628,17 +644,89 @@ "top_level_sheets": [ { "filename": "ml_module_agilex3.kicad_sch", - "name": "ml_module_agilex3", + "name": "Top, DB Connectors", "uuid": "b2fc4a0c-e3ab-4107-afc6-0319a0f50aee" + }, + { + "filename": "configuration.kicad_sch", + "name": "FPGA Configuration, SDM", + "uuid": "efae9cb8-b844-4f1b-9f4c-398c6a5fce03" + }, + { + "filename": "fpga_power.kicad_sch", + "name": "FPGA Power", + "uuid": "fe5e4fe6-83a2-4226-981c-6795c0ea8ea6" + }, + { + "filename": "power.kicad_sch", + "name": "System Power", + "uuid": "40f68d6b-1137-4ac8-b168-b5b95c774b2e" + }, + { + "filename": "fpga_banks_3a_6a.kicad_sch", + "name": "FPGA Banks 3A and 6A", + "uuid": "3c0900d6-fd44-4d2a-8ed4-61ac6016b344" + }, + { + "filename": "fpga_banks_6b_6c.kicad_sch", + "name": "FPGA Banks 6B and 6C", + "uuid": "0e7c7e5f-82cf-4601-92b9-defcfbaad9a6" + }, + { + "filename": "fpga_banks_6d_6e.kicad_sch", + "name": "FPGA Banks 6D and 6E", + "uuid": "1c3aedd9-9d83-472c-a6eb-08aa4aa51563" + }, + { + "filename": "fpga_banks_6f_6g_6h.kicad_sch", + "name": "FPGA Banks 6F, 6G and 6H", + "uuid": "40dd6d9b-cedf-466e-93c7-0250310dbdfa" + }, + { + "filename": "lpddr4.kicad_sch", + "name": "LPDDR4", + "uuid": "47d203e8-6013-4021-be29-15e7a1672177" } ], - "used_designators": "U1-3,R1,C1-2,D1,FD1-9,J1-3", + "used_designators": "U4", "variants": [] }, "sheets": [ [ "b2fc4a0c-e3ab-4107-afc6-0319a0f50aee", - "ml_module_agilex3" + "Top, DB Connectors" + ], + [ + "efae9cb8-b844-4f1b-9f4c-398c6a5fce03", + "FPGA Configuration, SDM" + ], + [ + "fe5e4fe6-83a2-4226-981c-6795c0ea8ea6", + "FPGA Power" + ], + [ + "40f68d6b-1137-4ac8-b168-b5b95c774b2e", + "System Power" + ], + [ + "3c0900d6-fd44-4d2a-8ed4-61ac6016b344", + "FPGA Banks 3A and 6A" + ], + [ + "0e7c7e5f-82cf-4601-92b9-defcfbaad9a6", + "FPGA Banks 6B and 6C" + ], + [ + "1c3aedd9-9d83-472c-a6eb-08aa4aa51563", + "FPGA Banks 6D and 6E" + ], + [ + "40dd6d9b-cedf-466e-93c7-0250310dbdfa", + "FPGA Banks 6F, 6G and 6H" + ], + [ + "47d203e8-6013-4021-be29-15e7a1672177", + "LPDDR4" ] ], "text_variables": {}, |
