aboutsummaryrefslogtreecommitdiffhomepage
path: root/sim/win/common
ModeNameSize
-rw-r--r--modelsim_files.tcl4059logplain
generated by cgit v1.2.3-8-gadcc (git 2.29.0) at 2026-05-24 16:32:31 +0000

Highly Recommended Verilog Books

Digital VLSI Design with Verilog: A Textbook from Silicon Valley Polytechnic Institute
The Verilog Hardware Description Language
Verilog HDL A Guide to Digital Design and Synthesis