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AgeCommit message (Expand)Author
8 dayspcb: remove HLE alignment pins, realign layers, move power snippet into placePrivate Island Networks Inc.
10 daysinitial v02 commit with inclusion of ftdi and power snippetsPrivate Island Networks Inc.
2026-07-08pcb: further clean up and order some test boardsHEADv01Private Island Networks Inc.
2026-07-06design files: DRC clean up of 400+ errors and warnings. Remaining errors and...Private Island Networks Inc.
2026-06-23add CERN license and update files to reference itPrivate Island Networks Inc.
2026-06-23start cleaning up split power plane, remove mounting holes from RJ45 symbolPrivate Island Networks Inc.
2026-06-22add globals for FLASH nets, so they connect between sheetsPrivate Island Networks Inc.
2026-06-22finish manual anotation of reference designators to align with Altium BetsyPrivate Island Networks Inc.
2026-06-21labels: Start using global labels and combining pagesPrivate Island Networks Inc.
2026-06-21initial commit after restarting project using schematic imports and manual sy...mainPrivate Island Networks Inc.
generated by cgit v1.2.3-8-gadcc (git 2.29.0) at 2026-07-23 23:31:46 +0000

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Digital VLSI Design with Verilog: A Textbook from Silicon Valley Polytechnic Institute
The Verilog Hardware Description Language
Verilog HDL A Guide to Digital Design and Synthesis