Adding GPIO Bit Banging to FPGA Open Source Project

Overview

This article reviews the steps taken to add a GPIO bit banging capability to the Betsy™ maker board. This requires various changes to the Private Island ^® open source FPGA project. Once complete, the 20 I/O header pins on the Betsy expansion header (see pic below) can be configured as either inputs or outputs and set and queried via the LAN. This work is being accomplished to support a new GPIO expansion daughter card that is currently under development.

The source code can be found on this website under open source. The Verilog and project modifications will be made inside a gpio branch from the 6e0b5af5 commit. The changes will ultimately be merged back into the master branch to give users the option to either work with the GigE daughter board or the GPIO expansion board.

Overview of Required Changes

The changes to be made assume that the project will be built for a particular configuration. At this point, we are not requiring the FPGA logic to detect which daughter board is inserted and have dynamic logic to support both boards. This simplification will result in less overall logic utilization.

Listed below are the required changes (in loose order):

1. Create a new Quartus project revision for GPIO.
2. Define a new Verilog directive in the top betsy.v module: GPIO_PRESENT.
3. Modify the top level port definition to redefine the current PHY2 RGMII interface (e.g., phy2_rstn) to gpio[19:0] when GPIO_PRESENT is defined.
4. Make other top level changes to map the gpio I/O to the controller module.
5. Create three new top level 20-bit wire vectors: gpio_in, gpio_out, and gpio_out_en.
6. Define a 3-state enable variable mapped to the controller that drives 3-state logic using the Verilog conditional operator at the top level.
7. Inside controller, define two new 20-bit registers: gpio_direction and gpio_value. The latter register sets the pin state when configured as an output. This register (address) can always be read to query the current pin value.
8. Modify the controller logic to support writing and reading these new registers. The gpio_direction register will drive the aforementioned 3-state logic at the top level. Refer to the controller design documentation for guidance.
9. Create new controller logic and assignments that connect the gpio_value register to the top level gpio input and output buses.

Detailed Change Description

To Be Added...