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/*
* dpram_inf.v
*
* Copyright (C) 2024-2025 Private Island Networks Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* Inferred DPRAM
*
*/
module dpram_inf
#(parameter DATA_WIDTH=9, parameter ADDR_WIDTH=11, parameter DPRAM_INIT="zero.txt")
(
input rstn,
// PORT A
input a_clk,
input a_clk_e,
input a_we,
input a_oe,
input [(ADDR_WIDTH-1):0] a_addr,
input [(DATA_WIDTH-1):0] a_din,
output reg [(DATA_WIDTH-1):0] a_dout,
// PORT A
input b_clk,
input b_clk_e,
input b_we,
input b_oe,
input [(ADDR_WIDTH-1):0] b_addr,
input [(DATA_WIDTH-1):0] b_din,
output reg [(DATA_WIDTH-1):0] b_dout
);
`ifdef SIMULATION
localparam DPRAM_FILE = {"../../",DPRAM_INIT};
`else
localparam DPRAM_FILE = DPRAM_INIT;
`endif
// Declare the RAM variable
reg [11:0] ram[2**ADDR_WIDTH-1:0];
initial begin
$readmemh(DPRAM_FILE, ram);
end
always @ (posedge a_clk)
begin
// Port A
if (a_clk_e && a_we)
begin
ram[a_addr] <= a_din;
a_dout <= a_din;
end
else
begin
a_dout <= ram[a_addr][(DATA_WIDTH-1):0];
end
end
always @ (posedge b_clk)
begin
// Port B
if (b_clk_e && b_we)
begin
ram[b_addr] <= b_din;
b_dout <= b_din;
end
else
begin
b_dout <= ram[b_addr][(DATA_WIDTH-1):0];
end
end
endmodule
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