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/*
* cam.v
*
* Copyright (C) 2025 Private Island Networks Inc.
* Copyright (C) 2018-2022 Mind Chasers Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* function: single cycle, parameterized CAM
*
*/
module cam #(parameter DEPTH = 8, DATAW = 32)
(
input rstn,
input clk,
// input for programming
input prgclk,
input sel,
input we,
input [$clog2(DEPTH)-1:0] addr, // include two lsbits for the byte selects
input [DATAW-1:0] d_i,
output [DATAW-1:0] d_o,
input search,
input [DATAW-1:0] search_address,
// output
output reg match
);
reg [DATAW-1:0] content[0:DEPTH-1];
reg valid[0:DEPTH-1];
integer i,j;
// Program the CAM
always @(posedge prgclk, negedge rstn)
if( !rstn ) begin
for (i=0; i < DEPTH; i=i+1) begin
content[i] <= 'd0;
valid[i] <= 1'b0;
end
end
else if ( we && sel )
begin
content[addr] <= d_i;
valid[addr] <= 1'b1;
end
assign d_o = valid[addr] ? content[addr] : 'd0;
// search the CAM
always @(posedge clk) begin
match <= 1'b0;
for (j=0; j < DEPTH; j=j+1) begin
if (search && valid[j] && search_address == content[j])
match <= 1'b1;
end
end
endmodule
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