1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
|
/*
* mdio_data_ti.v ( TI DP83867 PHY )
*
* Copyright (C) 2018, 2019 Mind Chasers Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* function: MDIO ROM for TI DP83867 PHY
*
*/
`timescale 1ns /10ps
module mdio_data_ti #(parameter ADDR_SZ = 7)
(
// params that alter the data returned
input [4:0] page,
input [4:0] reg_addr,
input [7:0] data_in_h,
input [7:0] data_in_l,
// ROM interface
input oe,
input [ADDR_SZ-1:0]ad,
output [7:0]d
);
localparam R = 8'h20;
localparam W = 8'h00;
localparam EOP = 8'h80;
localparam REGCR = 5'h0d;
localparam ADDAR = 5'h0e;
reg [7:0]data;
assign d = oe ? data : 8'hzz;
// register 22 is page
always @ (*)
begin
case (ad)
/*
Subroutine: SGMII Init ( i ) Not Needed for TI PHY, but read PHY Control Register (PHYCR), Address 0x0010
*/
// read the PHYCR register, SGMII Enable is bill 11
0: data = R|8'h10; // pg 18, reg 20
/*
Subroutine: Read Live Status ( s )
*/
// read the live copper status PHYSTS (0x17)
20 : data = R|8'h11; // read addr[17]
/*
Subroutine: Dump Registers 0:3
*/
25: data = R|8'd0;
26 : data = R|8'd1;
27 : data = R|8'd2;
28 : data = R|8'd3;
/*
Subroutine: : Loopback ( 0_0.14 )
*/
40 : data = W|8'd0; // write addr[0]
44 : data = 8'b01000000; // collision, speed select, reserved
45 : data = 8'b01010001; // reset, loopback, speed, AN enable, power down, isolate, restart AN, duplex;
// read it back
46: data = R|8'd0;
/*
Subroutine: : Read a register.
*/
48: data = { 3'b001, reg_addr };
/*
Subroutine: : Write a register.
*/
50: data = { 3'b000, reg_addr };
51: data = data_in_l;
52: data = data_in_h;
// read it back
// 53: data = { 3'b001, reg_addr };
// y: extended read
60: data = {3'b000 , REGCR };
61: data = 8'h1f;
62: data = 8'h00;
// Write the extended address to 0xe
63: data = { 3'b000, ADDAR };
64: data = data_in_l;
65: data = data_in_h;
// Write 0x401f to 0xd
66: data = { 3'b000, REGCR };
67: data = 8'h1f;
68: data = 8'h40;
// Read value in extended register: read 0x0E
69: data = { 3'b001, ADDAR };
// z: extended write
// Write value in extended register: 0x0E
80: data = { 3'b000, ADDAR };
81: data = data_in_l;
82: data = data_in_h;
// read it back
83: data = { 3'b001, ADDAR };
default: data = R|EOP;
endcase
end
endmodule
|