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/*
* link_timer.v
*
* Copyright 2020 Mind Chasers Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* function: Generate link timer pulse (1.6 and 10 ms) per SGMII and IEEE 802.3
*
*/
module link_timer(
input rstn,
input clk, // 125 MHz data clock
output pulse_1_6ms,
output pulse_10ms
);
reg [13:0] cnt; // 0.1 ms counter
reg [3:0] cnt_1_6ms;
reg [6:0] cnt_10ms;
// 0.1 ms counter
always @ (posedge clk or negedge rstn)
if ( !rstn )
cnt <= 'd0;
else if (cnt == 'd12500)
cnt <= 'd0;
else
cnt <= cnt + 1;
// 1.6 ms counter
always @ (posedge clk or negedge rstn)
if ( !rstn )
cnt_1_6ms <= 'd0;
else if (cnt == 'd12500)
if (cnt_1_6ms == 'd16)
cnt_1_6ms <= 'd0;
else
cnt_1_6ms <= cnt_1_6ms + 1;
assign pulse_1_6ms = (cnt == 'd12500 && cnt_1_6ms == 'd15);
// 10 ms counter
always @ (posedge clk or negedge rstn)
if ( !rstn )
cnt_10ms <= 'd0;
else if (cnt == 'd12500)
if (cnt_10ms == 'd99)
cnt_10ms <= 'd0;
else
cnt_10ms <= cnt_10ms + 1;
assign pulse_10ms = (cnt == 'd12500 && cnt_10ms == 'd99);
endmodule
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