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/* synthesis translate_off*/
`define SBP_SIMULATION
/* synthesis translate_on*/
`ifndef SBP_SIMULATION
`define SBP_SYNTHESIS
`endif
//
// Verific Verilog Description of module pcs
//
module pcs (sgmii0_rx_cv_err, sgmii0_rx_disp_err, sgmii0_rx_k, sgmii0_rxdata,
sgmii0_sci_addr, sgmii0_sci_rddata, sgmii0_sci_wrdata, sgmii0_tx_disp_correct,
sgmii0_tx_k, sgmii0_txdata, sgmii0_xmit, sgmii1_rx_cv_err,
sgmii1_rx_disp_err, sgmii1_rx_k, sgmii1_rxdata, sgmii1_tx_disp_correct,
sgmii1_tx_k, sgmii1_txdata, sgmii1_xmit, sgmii2_rx_cv_err,
sgmii2_rx_disp_err, sgmii2_rx_k, sgmii2_rxdata, sgmii2_sci_addr,
sgmii2_sci_rddata, sgmii2_sci_wrdata, sgmii2_tx_disp_correct,
sgmii2_tx_k, sgmii2_txdata, sgmii2_xmit, sgmii3_rx_cv_err,
sgmii3_rx_disp_err, sgmii3_rx_k, sgmii3_rxdata, sgmii3_tx_disp_correct,
sgmii3_tx_k, sgmii3_txdata, sgmii3_xmit, refclk0_refclkn,
refclk0_refclkp, sgmii0_ctc_del_s, sgmii0_ctc_ins_s, sgmii0_ctc_orun_s,
sgmii0_ctc_urun_s, sgmii0_cyawstn, sgmii0_hdinn, sgmii0_hdinp,
sgmii0_hdoutn, sgmii0_hdoutp, sgmii0_lsm_status_s, sgmii0_pll_lol,
sgmii0_rst_dual_c, sgmii0_rx_cdr_lol_s, sgmii0_rx_los_low_s,
sgmii0_rx_pcs_rst_c, sgmii0_rx_pwrup_c, sgmii0_rx_serdes_rst_c,
sgmii0_sci_en, sgmii0_sci_en_dual, sgmii0_sci_int, sgmii0_sci_rd,
sgmii0_sci_sel, sgmii0_sci_sel_dual, sgmii0_sci_wrn, sgmii0_serdes_rst_dual_c,
sgmii0_signal_detect_c, sgmii0_tx_pclk, sgmii0_tx_pcs_rst_c,
sgmii0_tx_pwrup_c, sgmii0_tx_serdes_rst_c, sgmii0_txi_clk,
sgmii1_ctc_del_s, sgmii1_ctc_ins_s, sgmii1_ctc_orun_s, sgmii1_ctc_urun_s,
sgmii1_hdinn, sgmii1_hdinp, sgmii1_hdoutn, sgmii1_hdoutp,
sgmii1_lsm_status_s, sgmii1_rst_dual_c, sgmii1_rx_cdr_lol_s,
sgmii1_rx_los_low_s, sgmii1_rx_pcs_rst_c, sgmii1_rx_pwrup_c,
sgmii1_rx_serdes_rst_c, sgmii1_sci_en, sgmii1_sci_sel, sgmii1_serdes_pdb,
sgmii1_serdes_rst_dual_c, sgmii1_signal_detect_c, sgmii1_tx_pclk,
sgmii1_tx_pcs_rst_c, sgmii1_tx_pwrup_c, sgmii1_tx_serdes_rst_c,
sgmii1_txi_clk, sgmii2_ctc_del_s, sgmii2_ctc_ins_s, sgmii2_ctc_orun_s,
sgmii2_ctc_urun_s, sgmii2_cyawstn, sgmii2_hdinn, sgmii2_hdinp,
sgmii2_hdoutn, sgmii2_hdoutp, sgmii2_lsm_status_s, sgmii2_pll_lol,
sgmii2_rst_dual_c, sgmii2_rx_cdr_lol_s, sgmii2_rx_los_low_s,
sgmii2_rx_pcs_rst_c, sgmii2_rx_pwrup_c, sgmii2_rx_serdes_rst_c,
sgmii2_sci_en, sgmii2_sci_en_dual, sgmii2_sci_int, sgmii2_sci_rd,
sgmii2_sci_sel, sgmii2_sci_sel_dual, sgmii2_sci_wrn, sgmii2_serdes_pdb,
sgmii2_serdes_rst_dual_c, sgmii2_signal_detect_c, sgmii2_tx_pclk,
sgmii2_tx_pcs_rst_c, sgmii2_tx_pwrup_c, sgmii2_tx_serdes_rst_c,
sgmii2_txi_clk, sgmii3_ctc_del_s, sgmii3_ctc_ins_s, sgmii3_ctc_orun_s,
sgmii3_ctc_urun_s, sgmii3_hdinn, sgmii3_hdinp, sgmii3_hdoutn,
sgmii3_hdoutp, sgmii3_lsm_status_s, sgmii3_rst_dual_c,
sgmii3_rx_cdr_lol_s, sgmii3_rx_los_low_s, sgmii3_rx_pcs_rst_c,
sgmii3_rx_pwrup_c, sgmii3_rx_serdes_rst_c,
sgmii3_sci_sel, sgmii3_serdes_rst_dual_c, sgmii3_signal_detect_c,
sgmii3_tx_pclk, sgmii3_tx_pcs_rst_c, sgmii3_tx_pwrup_c, sgmii3_tx_serdes_rst_c,
sgmii3_txi_clk, refclk0_refclko) /* synthesis sbp_module=true */ ;
output [0:0]sgmii0_rx_cv_err;
output [0:0]sgmii0_rx_disp_err;
output [0:0]sgmii0_rx_k;
output [7:0]sgmii0_rxdata;
input [5:0]sgmii0_sci_addr;
output [7:0]sgmii0_sci_rddata;
input [7:0]sgmii0_sci_wrdata;
input [0:0]sgmii0_tx_disp_correct;
input [0:0]sgmii0_tx_k;
input [7:0]sgmii0_txdata;
input [0:0]sgmii0_xmit;
output [0:0]sgmii1_rx_cv_err;
output [0:0]sgmii1_rx_disp_err;
output [0:0]sgmii1_rx_k;
output [7:0]sgmii1_rxdata;
input [0:0]sgmii1_tx_disp_correct;
input [0:0]sgmii1_tx_k;
input [7:0]sgmii1_txdata;
input [0:0]sgmii1_xmit;
output [0:0]sgmii2_rx_cv_err;
output [0:0]sgmii2_rx_disp_err;
output [0:0]sgmii2_rx_k;
output [7:0]sgmii2_rxdata;
input [5:0]sgmii2_sci_addr;
output [7:0]sgmii2_sci_rddata;
input [7:0]sgmii2_sci_wrdata;
input [0:0]sgmii2_tx_disp_correct;
input [0:0]sgmii2_tx_k;
input [7:0]sgmii2_txdata;
input [0:0]sgmii2_xmit;
output [0:0]sgmii3_rx_cv_err;
output [0:0]sgmii3_rx_disp_err;
output [0:0]sgmii3_rx_k;
output [7:0]sgmii3_rxdata;
input [0:0]sgmii3_tx_disp_correct;
input [0:0]sgmii3_tx_k;
input [7:0]sgmii3_txdata;
input [0:0]sgmii3_xmit;
input refclk0_refclkn;
input refclk0_refclkp;
output sgmii0_ctc_del_s;
output sgmii0_ctc_ins_s;
output sgmii0_ctc_orun_s;
output sgmii0_ctc_urun_s;
input sgmii0_cyawstn;
input sgmii0_hdinn;
input sgmii0_hdinp;
output sgmii0_hdoutn;
output sgmii0_hdoutp;
output sgmii0_lsm_status_s;
output sgmii0_pll_lol;
input sgmii0_rst_dual_c;
output sgmii0_rx_cdr_lol_s;
output sgmii0_rx_los_low_s;
input sgmii0_rx_pcs_rst_c;
input sgmii0_rx_pwrup_c;
input sgmii0_rx_serdes_rst_c;
input sgmii0_sci_en;
input sgmii0_sci_en_dual;
output sgmii0_sci_int;
input sgmii0_sci_rd;
input sgmii0_sci_sel;
input sgmii0_sci_sel_dual;
input sgmii0_sci_wrn;
input sgmii0_serdes_rst_dual_c;
input sgmii0_signal_detect_c;
output sgmii0_tx_pclk;
input sgmii0_tx_pcs_rst_c;
input sgmii0_tx_pwrup_c;
input sgmii0_tx_serdes_rst_c;
input sgmii0_txi_clk;
output sgmii1_ctc_del_s;
output sgmii1_ctc_ins_s;
output sgmii1_ctc_orun_s;
output sgmii1_ctc_urun_s;
input sgmii1_hdinn;
input sgmii1_hdinp;
output sgmii1_hdoutn;
output sgmii1_hdoutp;
output sgmii1_lsm_status_s;
input sgmii1_rst_dual_c;
output sgmii1_rx_cdr_lol_s;
output sgmii1_rx_los_low_s;
input sgmii1_rx_pcs_rst_c;
input sgmii1_rx_pwrup_c;
input sgmii1_rx_serdes_rst_c;
input sgmii1_sci_en;
input sgmii1_sci_sel;
input sgmii1_serdes_pdb;
input sgmii1_serdes_rst_dual_c;
input sgmii1_signal_detect_c;
output sgmii1_tx_pclk;
input sgmii1_tx_pcs_rst_c;
input sgmii1_tx_pwrup_c;
input sgmii1_tx_serdes_rst_c;
input sgmii1_txi_clk;
output sgmii2_ctc_del_s;
output sgmii2_ctc_ins_s;
output sgmii2_ctc_orun_s;
output sgmii2_ctc_urun_s;
input sgmii2_cyawstn;
input sgmii2_hdinn;
input sgmii2_hdinp;
output sgmii2_hdoutn;
output sgmii2_hdoutp;
output sgmii2_lsm_status_s;
output sgmii2_pll_lol;
input sgmii2_rst_dual_c;
output sgmii2_rx_cdr_lol_s;
output sgmii2_rx_los_low_s;
input sgmii2_rx_pcs_rst_c;
input sgmii2_rx_pwrup_c;
input sgmii2_rx_serdes_rst_c;
input sgmii2_sci_en;
input sgmii2_sci_en_dual;
output sgmii2_sci_int;
input sgmii2_sci_rd;
input sgmii2_sci_sel;
input sgmii2_sci_sel_dual;
input sgmii2_sci_wrn;
input sgmii2_serdes_pdb;
input sgmii2_serdes_rst_dual_c;
input sgmii2_signal_detect_c;
output sgmii2_tx_pclk;
input sgmii2_tx_pcs_rst_c;
input sgmii2_tx_pwrup_c;
input sgmii2_tx_serdes_rst_c;
input sgmii2_txi_clk;
output sgmii3_ctc_del_s;
output sgmii3_ctc_ins_s;
output sgmii3_ctc_orun_s;
output sgmii3_ctc_urun_s;
input sgmii3_hdinn;
input sgmii3_hdinp;
output sgmii3_hdoutn;
output sgmii3_hdoutp;
output sgmii3_lsm_status_s;
input sgmii3_rst_dual_c;
output sgmii3_rx_cdr_lol_s;
output sgmii3_rx_los_low_s;
input sgmii3_rx_pcs_rst_c;
input sgmii3_rx_pwrup_c;
input sgmii3_rx_serdes_rst_c;
input sgmii3_sci_sel;
input sgmii3_serdes_rst_dual_c;
input sgmii3_signal_detect_c;
output sgmii3_tx_pclk;
input sgmii3_tx_pcs_rst_c;
input sgmii3_tx_pwrup_c;
input sgmii3_tx_serdes_rst_c;
input sgmii3_txi_clk;
output refclk0_refclko;
wire [7:0]i_sgmii0_sci_rddata;
wire [7:0]i_sgmii1_sci_rddata;
wire [7:0]o_sgmii1_sci_rddata;
wire [7:0]i_sgmii2_sci_rddata;
wire [7:0]o_sgmii2_sci_rddata;
wire [7:0]i_sgmii3_sci_rddata;
wire i_sgmii0_sci_int, i_sgmii1_sci_int, o_sgmii1_sci_int, i_sgmii2_sci_int,
o_sgmii2_sci_int, i_sgmii3_sci_int, sli_rst_wire0, sli_rst_wire2;
assign sli_rst_wire0 = sgmii0_serdes_rst_dual_c || sgmii0_tx_serdes_rst_c || (!sgmii1_serdes_pdb) || (!sgmii0_tx_pwrup_c) || (!sgmii1_tx_pwrup_c);
assign sli_rst_wire2 = sgmii2_serdes_rst_dual_c || sgmii2_tx_serdes_rst_c || (!sgmii2_serdes_pdb) || (!sgmii2_tx_pwrup_c) || (!sgmii3_tx_pwrup_c);
/* synthesis translate_off*/
`define sbx_mux
/* synthesis translate_on*/
`ifdef sbx_mux
assign o_sgmii1_sci_rddata = sgmii1_sci_sel ? i_sgmii1_sci_rddata : 8'b0;
assign sgmii0_sci_rddata = sgmii0_sci_sel ? i_sgmii0_sci_rddata : o_sgmii1_sci_rddata;
assign o_sgmii2_sci_rddata = sgmii2_sci_sel ? i_sgmii2_sci_rddata : 8'b0;
assign sgmii2_sci_rddata = sgmii3_sci_sel ? i_sgmii3_sci_rddata : o_sgmii2_sci_rddata;
assign o_sgmii1_sci_int = sgmii1_sci_sel ? i_sgmii1_sci_int : 0;
assign sgmii0_sci_int = sgmii0_sci_sel ? i_sgmii0_sci_int : o_sgmii1_sci_int;
assign o_sgmii2_sci_int = sgmii2_sci_sel ? i_sgmii2_sci_int : 0;
assign sgmii2_sci_int = sgmii3_sci_sel ? i_sgmii3_sci_int : o_sgmii2_sci_int;
`else
assign sgmii0_sci_rddata = i_sgmii0_sci_rddata;
assign sgmii2_sci_rddata = i_sgmii3_sci_rddata;
assign sgmii0_sci_int = i_sgmii0_sci_int;
assign sgmii2_sci_int = i_sgmii3_sci_int;
`endif
refclk0 refclk0_inst (.refclkn(refclk0_refclkn), .refclko(refclk0_refclko),
.refclkp(refclk0_refclkp));
sgmii0 sgmii0_inst (.rx_cv_err({sgmii0_rx_cv_err}), .rx_disp_err({sgmii0_rx_disp_err}),
.rx_k({sgmii0_rx_k}), .rxdata({sgmii0_rxdata}), .sci_addr({sgmii0_sci_addr}),
.sci_rddata({i_sgmii0_sci_rddata}), .sci_wrdata({sgmii0_sci_wrdata}),
.tx_disp_correct({sgmii0_tx_disp_correct}), .tx_k({sgmii0_tx_k}),
.txdata({sgmii0_txdata}), .xmit({sgmii0_xmit}), .ctc_del_s(sgmii0_ctc_del_s),
.ctc_ins_s(sgmii0_ctc_ins_s), .ctc_orun_s(sgmii0_ctc_orun_s),
.ctc_urun_s(sgmii0_ctc_urun_s), .cyawstn(sgmii0_cyawstn), .hdinn(sgmii0_hdinn),
.hdinp(sgmii0_hdinp), .hdoutn(sgmii0_hdoutn), .hdoutp(sgmii0_hdoutp),
.lsm_status_s(sgmii0_lsm_status_s), .pll_lol(sgmii0_pll_lol),
.pll_refclki(refclk0_refclko), .rst_dual_c(sgmii0_rst_dual_c),
.rx_cdr_lol_s(sgmii0_rx_cdr_lol_s), .rx_los_low_s(sgmii0_rx_los_low_s),
.rx_pcs_rst_c(sgmii0_rx_pcs_rst_c), .rx_pwrup_c(sgmii0_rx_pwrup_c),
.rx_serdes_rst_c(sgmii0_rx_serdes_rst_c), .rxrefclk(refclk0_refclko),
.sci_en(sgmii0_sci_en), .sci_en_dual(sgmii0_sci_en_dual), .sci_int(i_sgmii0_sci_int),
.sci_rd(sgmii0_sci_rd), .sci_sel(sgmii0_sci_sel), .sci_sel_dual(sgmii0_sci_sel_dual),
.sci_wrn(sgmii0_sci_wrn), .serdes_pdb(sgmii1_serdes_pdb), .serdes_rst_dual_c(sgmii0_serdes_rst_dual_c),
.signal_detect_c(sgmii0_signal_detect_c), .sli_rst(sli_rst_wire0),
.tx_pclk(sgmii0_tx_pclk), .tx_pcs_rst_c(sgmii0_tx_pcs_rst_c),
.tx_pwrup_c(sgmii0_tx_pwrup_c), .tx_serdes_rst_c(sgmii0_tx_serdes_rst_c),
.txi_clk(sgmii0_txi_clk), .tx_full_clk());
sgmii1 sgmii1_inst (.rx_cv_err({sgmii1_rx_cv_err}), .rx_disp_err({sgmii1_rx_disp_err}),
.rx_k({sgmii1_rx_k}), .rxdata({sgmii1_rxdata}), .sci_addr({sgmii0_sci_addr}),
.sci_rddata({i_sgmii1_sci_rddata}), .sci_wrdata({sgmii0_sci_wrdata}),
.tx_disp_correct({sgmii1_tx_disp_correct}), .tx_k({sgmii1_tx_k}),
.txdata({sgmii1_txdata}), .xmit({sgmii1_xmit}), .ctc_del_s(sgmii1_ctc_del_s),
.ctc_ins_s(sgmii1_ctc_ins_s), .ctc_orun_s(sgmii1_ctc_orun_s),
.ctc_urun_s(sgmii1_ctc_urun_s), .cyawstn(sgmii0_cyawstn), .hdinn(sgmii1_hdinn),
.hdinp(sgmii1_hdinp), .hdoutn(sgmii1_hdoutn), .hdoutp(sgmii1_hdoutp),
.lsm_status_s(sgmii1_lsm_status_s), .pll_refclki(refclk0_refclko),
.rst_dual_c(sgmii1_rst_dual_c), .rx_cdr_lol_s(sgmii1_rx_cdr_lol_s),
.rx_los_low_s(sgmii1_rx_los_low_s), .rx_pcs_rst_c(sgmii1_rx_pcs_rst_c),
.rx_pwrup_c(sgmii1_rx_pwrup_c), .rx_serdes_rst_c(sgmii1_rx_serdes_rst_c),
.rxrefclk(refclk0_refclko), .sci_en(sgmii1_sci_en), .sci_en_dual(sgmii0_sci_en_dual),
.sci_int(i_sgmii1_sci_int), .sci_rd(sgmii0_sci_rd), .sci_sel(sgmii1_sci_sel),
.sci_sel_dual(sgmii0_sci_sel_dual), .sci_wrn(sgmii0_sci_wrn),
.serdes_pdb(sgmii1_serdes_pdb), .serdes_rst_dual_c(sgmii1_serdes_rst_dual_c),
.signal_detect_c(sgmii1_signal_detect_c), .tx_pclk(sgmii1_tx_pclk),
.tx_pcs_rst_c(sgmii1_tx_pcs_rst_c), .tx_pwrup_c(sgmii1_tx_pwrup_c),
.tx_serdes_rst_c(sgmii1_tx_serdes_rst_c), .txi_clk(sgmii1_txi_clk),.tx_full_clk());
sgmii2 sgmii2_inst (.rx_cv_err({sgmii2_rx_cv_err}), .rx_disp_err({sgmii2_rx_disp_err}),
.rx_k({sgmii2_rx_k}), .rxdata({sgmii2_rxdata}), .sci_addr({sgmii2_sci_addr}),
.sci_rddata({i_sgmii2_sci_rddata}), .sci_wrdata({sgmii2_sci_wrdata}),
.tx_disp_correct({sgmii2_tx_disp_correct}), .tx_k({sgmii2_tx_k}),
.txdata({sgmii2_txdata}), .xmit({sgmii2_xmit}), .ctc_del_s(sgmii2_ctc_del_s),
.ctc_ins_s(sgmii2_ctc_ins_s), .ctc_orun_s(sgmii2_ctc_orun_s),
.ctc_urun_s(sgmii2_ctc_urun_s), .cyawstn(sgmii2_cyawstn), .hdinn(sgmii2_hdinn),
.hdinp(sgmii2_hdinp), .hdoutn(sgmii2_hdoutn), .hdoutp(sgmii2_hdoutp),
.lsm_status_s(sgmii2_lsm_status_s), .pll_lol(sgmii2_pll_lol),
.pll_refclki(refclk0_refclko), .rst_dual_c(sgmii2_rst_dual_c),
.rx_cdr_lol_s(sgmii2_rx_cdr_lol_s), .rx_los_low_s(sgmii2_rx_los_low_s),
.rx_pcs_rst_c(sgmii2_rx_pcs_rst_c), .rx_pwrup_c(sgmii2_rx_pwrup_c),
.rx_serdes_rst_c(sgmii2_rx_serdes_rst_c), .rxrefclk(refclk0_refclko),
.sci_en(sgmii2_sci_en), .sci_en_dual(sgmii2_sci_en_dual), .sci_int(i_sgmii2_sci_int),
.sci_rd(sgmii2_sci_rd), .sci_sel(sgmii2_sci_sel), .sci_sel_dual(sgmii2_sci_sel_dual),
.sci_wrn(sgmii2_sci_wrn), .serdes_pdb(sgmii2_serdes_pdb), .serdes_rst_dual_c(sgmii2_serdes_rst_dual_c),
.signal_detect_c(sgmii2_signal_detect_c), .sli_rst(sli_rst_wire2),
.tx_pclk(sgmii2_tx_pclk), .tx_pcs_rst_c(sgmii2_tx_pcs_rst_c),
.tx_pwrup_c(sgmii2_tx_pwrup_c), .tx_serdes_rst_c(sgmii2_tx_serdes_rst_c),
.txi_clk(sgmii2_txi_clk),.tx_full_clk());
sgmii3 sgmii3_inst (.rx_cv_err({sgmii3_rx_cv_err}), .rx_disp_err({sgmii3_rx_disp_err}),
.rx_k({sgmii3_rx_k}), .rxdata({sgmii3_rxdata}), .sci_addr({sgmii2_sci_addr}),
.sci_rddata({i_sgmii3_sci_rddata}), .sci_wrdata({sgmii2_sci_wrdata}),
.tx_disp_correct({sgmii3_tx_disp_correct}), .tx_k({sgmii3_tx_k}),
.txdata({sgmii3_txdata}), .xmit({sgmii3_xmit}), .ctc_del_s(sgmii3_ctc_del_s),
.ctc_ins_s(sgmii3_ctc_ins_s), .ctc_orun_s(sgmii3_ctc_orun_s),
.ctc_urun_s(sgmii3_ctc_urun_s), .cyawstn(sgmii2_cyawstn), .hdinn(sgmii3_hdinn),
.hdinp(sgmii3_hdinp), .hdoutn(sgmii3_hdoutn), .hdoutp(sgmii3_hdoutp),
.lsm_status_s(sgmii3_lsm_status_s), .pll_refclki(refclk0_refclko),
.rst_dual_c(sgmii3_rst_dual_c), .rx_cdr_lol_s(sgmii3_rx_cdr_lol_s),
.rx_los_low_s(sgmii3_rx_los_low_s), .rx_pcs_rst_c(sgmii3_rx_pcs_rst_c),
.rx_pwrup_c(sgmii3_rx_pwrup_c), .rx_serdes_rst_c(sgmii3_rx_serdes_rst_c),
.rxrefclk(refclk0_refclko), .sci_en(sgmii2_sci_en), .sci_en_dual(sgmii2_sci_en_dual),
.sci_int(i_sgmii3_sci_int), .sci_rd(sgmii2_sci_rd), .sci_sel(sgmii3_sci_sel),
.sci_sel_dual(sgmii2_sci_sel_dual), .sci_wrn(sgmii2_sci_wrn),
.serdes_pdb(sgmii2_serdes_pdb), .serdes_rst_dual_c(sgmii3_serdes_rst_dual_c),
.signal_detect_c(sgmii3_signal_detect_c), .tx_pclk(sgmii3_tx_pclk),
.tx_pcs_rst_c(sgmii3_tx_pcs_rst_c), .tx_pwrup_c(sgmii3_tx_pwrup_c),
.tx_serdes_rst_c(sgmii3_tx_serdes_rst_c), .txi_clk(sgmii3_txi_clk),.tx_full_clk());
endmodule
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