ddro_inst.v « rgmii_txd « ip « cyclone10_lp « altera « manufacturer - privateisland - FPGA network processor

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path: root/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro_inst.v

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ddro	ddro_inst (
	.aclr ( aclr_sig ),
	.datain_h ( datain_h_sig ),
	.datain_l ( datain_l_sig ),
	.oe ( oe_sig ),
	.outclock ( outclock_sig ),
	.dataout ( dataout_sig )
	);

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