privateisland - FPGA network processor

summary refs log tree commit diff homepage

path: root/testbenches/README

Age	Commit message (Expand)	Author
2020-11-16	project: rename sim folder, update README	mindchasers
2019-05-01	initial commit, all basic functions work on Darsena V02	mindchasers

Highly Recommended Verilog Books

Digital VLSI Design with Verilog: A Textbook from Silicon Valley Polytechnic Institute

The Verilog Hardware Description Language

Verilog HDL A Guide to Digital Design and Synthesis