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2020-11-16directives: rename file and update for new optionsmindchasers
2020-11-15ecp5um project: restructure so we can add more devicesmindchasers
2020-10-01link_timer: Generate link timer pulse (1.6 and 10 ms) per SGMII and IEEE 802.3mindchasers
2019-07-08top: fix typo for debug defines: DEBUG_I2Cmindchasers
2019-05-01initial commit, all basic functions work on Darsena V02mindchasers
generated by cgit v1.2.3-8-gadcc (git 2.29.0) at 2024-11-10 05:22:39 +0000

Highly Recommended Verilog Books

Digital VLSI Design with Verilog: A Textbook from Silicon Valley Polytechnic Institute
The Verilog Hardware Description Language
Verilog HDL A Guide to Digital Design and Synthesis