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2020-11-15ecp5um project: restructure so we can add more devicesmindchasers
2019-07-08ldf: update project file to include reveal files for lab exercisesmindchasers
2019-07-08reveal: add labs reveal files to support lab exercisesmindchasers
2019-07-08lpf: increase PAR Adjust on pcs_pclk to ease meeting timingmindchasers
2019-05-01initial commit, all basic functions work on Darsena V02mindchasers
generated by cgit v1.2.3-8-gadcc (git 2.29.0) at 2024-11-12 22:37:36 +0000

Highly Recommended Verilog Books

Digital VLSI Design with Verilog: A Textbook from Silicon Valley Polytechnic Institute
The Verilog Hardware Description Language
Verilog HDL A Guide to Digital Design and Synthesis