summaryrefslogtreecommitdiffhomepage
AgeCommit message (Expand)Author
2020-10-01link_timer: Generate link timer pulse (1.6 and 10 ms) per SGMII and IEEE 802.3mindchasers
2020-09-27clarity: update SERDES/PCS block to be compatible with Diamond 3.11mindchasers
2019-07-08ldf: update project file to include reveal files for lab exercisesmindchasers
2019-07-08reveal: add labs reveal files to support lab exercisesmindchasers
2019-07-08top: fix typo for debug defines: DEBUG_I2Cmindchasers
2019-07-08lpf: increase PAR Adjust on pcs_pclk to ease meeting timingmindchasers
2019-05-01initial commit, all basic functions work on Darsena V02mindchasers
generated by cgit v1.2.3-8-gadcc (git 2.29.0) at 2024-11-10 05:00:42 +0000

Highly Recommended Verilog Books

Digital VLSI Design with Verilog: A Textbook from Silicon Valley Polytechnic Institute
The Verilog Hardware Description Language
Verilog HDL A Guide to Digital Design and Synthesis