diff options
Diffstat (limited to 'src/mdio_cont.v')
| -rw-r--r-- | src/mdio_cont.v | 93 |
1 files changed, 41 insertions, 52 deletions
diff --git a/src/mdio_cont.v b/src/mdio_cont.v index ad595fd..a31a30d 100644 --- a/src/mdio_cont.v +++ b/src/mdio_cont.v @@ -1,6 +1,7 @@ /* - * mdio_cont.v + * mdio_cont.v * + * Copyright (C) 2025 Private Island Networks Inc. * Copyright (C) 2018, 2019 Mind Chasers Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -19,9 +20,7 @@ * */ -`timescale 1ns /10ps - -module mdio_controller #(parameter ADDR_SZ = 6) +module mdio_cont #(parameter ADDR_SZ = 6) ( // system interface @@ -86,69 +85,59 @@ module mdio_controller #(parameter ADDR_SZ = 6) /* read the eop bit during S1 */ always @(posedge clk or negedge rstn) - begin - if ( !rstn ) - work_done <= 1'b0; - else if ( cont_state == S1 && di[7] == 1'b1 ) - work_done <= 1'b1; - else - work_done <= 1'b0; - end + if ( !rstn ) + work_done <= 1'b0; + else if ( cont_state == S1 && di[7] == 1'b1 ) + work_done <= 1'b1; + else + work_done <= 1'b0; /* work_run */ always @(posedge clk or negedge rstn) - begin - if ( !rstn ) - work_run <= 1'b0; - else if ( work_start == 1'b1 ) - work_run <= 1'b1; - else if ( work_done == 1'b1 ) - work_run <= 1'b0; - end + if ( !rstn ) + work_run <= 1'b0; + else if ( work_start == 1'b1 ) + work_run <= 1'b1; + else if ( work_done == 1'b1 ) + work_run <= 1'b0; /* set RWN for duration of cyle */ always @(posedge clk or negedge rstn) - begin - if ( rstn == 1'b0 || work_done ==1'b1 ) - begin - rwn <= 1'b1; - end - else if ( cont_state == S1 ) - begin - rwn <= di[5]; - end - end + if (!rstn) + rwn <= 1'b1; + else if (work_done) + rwn <= 1'b1; + else if ( cont_state == S1 ) + rwn <= di[5]; /* reg_addr is the mdio register address */ always @(posedge clk or negedge rstn) - begin - if ( rstn == 1'b0 || work_done ==1'b1 ) - reg_addr <= 5'h0; - else if ( cont_state == S1 ) - reg_addr <= di[4:0]; - end + if (!rstn) + reg_addr <= 5'h0; + else if (work_done) + reg_addr <= 5'h0; + else if ( cont_state == S1 ) + reg_addr <= di[4:0]; /* addr is the program address */ always @(posedge clk or negedge rstn) - begin - if (rstn == 1'b0 || work_done == 1'b1 ) - addr <= 0; - else if ( work_start == 1'b1 ) - addr <= routine_addr[ADDR_SZ-1:0]; - else if ( cont_state == S3 || cont_state == S4 || cont_state == S8 ) - addr <= addr + 1; - end + if (!rstn) + addr <= 0; + else if (work_done) + addr <= 0; + else if (work_start) + addr <= routine_addr[ADDR_SZ-1:0]; + else if ( cont_state == S3 || cont_state == S4 || cont_state == S8 ) + addr <= addr + 1'b1; // latch the write data to mdio always @(posedge clk or negedge rstn) - begin - if (rstn == 0) - dout <= 16'h0000; - else if ( ld_dl == 1'b1 ) - dout[7:0] <= di; - else if ( ld_dh == 1'b1 ) - dout[15:8] <= di; - end + if (rstn == 0) + dout <= 16'h0000; + else if ( ld_dl == 1'b1 ) + dout[7:0] <= di; + else if ( ld_dh == 1'b1 ) + dout[15:8] <= di; // combinatorial logic here assign ld_dl = ( cont_state == S4 ) ? 1'b1 : 1'b0; |
