diff options
Diffstat (limited to 'manufacturer/altera')
4 files changed, 249 insertions, 51 deletions
diff --git a/manufacturer/altera/cyclone10_lp/sim/data/cont_query.dat b/manufacturer/altera/cyclone10_lp/sim/data/cont_query.dat index 4590ab9..9f8719c 100644 --- a/manufacturer/altera/cyclone10_lp/sim/data/cont_query.dat +++ b/manufacturer/altera/cyclone10_lp/sim/data/cont_query.dat @@ -47,14 +47,14 @@ A8 // 168 0f AC // UDP Checksum E6 -02 // Msg Type +01 // Msg Type ed // Token -01 // Address MSByte -04 // Address LSByte +08 // Address MSByte, Pkt Gen +00 // Address LSByte 00 // Data MSbyte 00 00 -00 // Data LSbyte +01 // Data LSbyte 00 // PAD 00 00 @@ -69,7 +69,7 @@ ed // Token E3 // 95 184 -40 // Idle Clocks * 16 +20 // Idle Clocks * 16 55 // Preamble 55 55 @@ -121,8 +121,8 @@ AC // UDP Checksum E6 02 // Msg Type c3 // Token -00 // Address MSByte -10 // Address LSByte +08 // Address MSByte +00 // Address LSByte 01 // Data MSbyte 02 03 diff --git a/manufacturer/altera/cyclone10_lp/sim/src/tb.sv b/manufacturer/altera/cyclone10_lp/sim/src/tb.sv index 25fbe75..742a6b1 100644 --- a/manufacturer/altera/cyclone10_lp/sim/src/tb.sv +++ b/manufacturer/altera/cyclone10_lp/sim/src/tb.sv @@ -26,9 +26,9 @@ `timescale 1ns / 1ps -`define TEST_ETOE +//`define TEST_ETOE //`define ML_ENGINE -//`define TEST_CONTROLLER +`define TEST_CONTROLLER `define INCLUDED `include "../../../../../src/rgmii_params.v" diff --git a/manufacturer/altera/cyclone10_lp/sim/wav/wave_pkt_gen.do b/manufacturer/altera/cyclone10_lp/sim/wav/wave_pkt_gen.do new file mode 100644 index 0000000..fe83e32 --- /dev/null +++ b/manufacturer/altera/cyclone10_lp/sim/wav/wave_pkt_gen.do @@ -0,0 +1,196 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /tb/rstn +add wave -noupdate /tb/clk_125 +add wave -noupdate /tb/clk_25 +add wave -noupdate /tb/clk_phy +add wave -noupdate /tb/clk_phyx2 +add wave -noupdate /tb/pll_lock +add wave -noupdate /tb/phy_up +add wave -noupdate /tb/pclk +add wave -noupdate -radix unsigned /tb/rx0_data_cnt +add wave -noupdate /tb/rx0_idle_cnt +add wave -noupdate /tb/rx0_last_byte +add wave -noupdate -radix hexadecimal /tb/rx_clk_cnt +add wave -noupdate /tb/phy0_rx_clk +add wave -noupdate /tb/phy0_rx_ctl +add wave -noupdate /tb/phy0_rx_d +add wave -noupdate /tb/phy1_rx_clk +add wave -noupdate /tb/phy1_rx_ctl +add wave -noupdate /tb/phy1_rx_d +add wave -noupdate /tb/phy2_rx_clk +add wave -noupdate /tb/phy2_rx_ctl +add wave -noupdate /tb/phy2_rx_d +add wave -noupdate /tb/phy0_tx_clk +add wave -noupdate /tb/phy0_tx_ctl +add wave -noupdate /tb/phy0_tx_d +add wave -noupdate /tb/phy1_tx_clk +add wave -noupdate /tb/phy1_tx_ctl +add wave -noupdate /tb/phy1_tx_d +add wave -noupdate /tb/phy2_tx_clk +add wave -noupdate /tb/phy2_tx_ctl +add wave -noupdate /tb/phy2_tx_d +add wave -noupdate -divider Top +add wave -noupdate /tb/dut/rstn +add wave -noupdate /tb/dut/sys_rstn +add wave -noupdate /tb/dut/clk_i +add wave -noupdate /tb/dut/pll_locked +add wave -noupdate /tb/clk_25 +add wave -noupdate /tb/clk_125 +add wave -noupdate /tb/dut/phy0_clk +add wave -noupdate /tb/dut/phy1_clk +add wave -noupdate /tb/dut/cont_clk +add wave -noupdate /tb/dut/sys_rstn +add wave -noupdate /tb/dut/phy_resetn +add wave -noupdate /tb/dut/phy0_rstn +add wave -noupdate /tb/dut/phy1_rstn +add wave -noupdate /tb/clk_phy +add wave -noupdate /tb/clk_phyx2 +add wave -noupdate {/tb/dut/phy_up[0]} +add wave -noupdate /tb/phy0_rx_clk +add wave -noupdate /tb/dut/rgmi_rx_0/datain +add wave -noupdate /tb/dut/rgmi_rx_0/inclock +add wave -noupdate /tb/dut/rgmi_rx_0/dataout_h +add wave -noupdate /tb/dut/rgmi_rx_0/dataout_l +add wave -noupdate /tb/dut/rx0_ctl_m1 +add wave -noupdate /tb/dut/rx0_d_m1 +add wave -noupdate /tb/dut/rx0_ctl_m2 +add wave -noupdate /tb/dut/rx0_d_m2 +add wave -noupdate /tb/dut/tx0_ctl +add wave -noupdate /tb/dut/tx0_d +add wave -noupdate /tb/dut/tx1_ctl +add wave -noupdate /tb/dut/tx1_d +add wave -noupdate -divider {SWITCH 0} +add wave -noupdate /tb/dut/switch_0/clk +add wave -noupdate /tb/dut/switch_0/phy_up +add wave -noupdate /tb/dut/switch_0/rx_d_01 +add wave -noupdate /tb/dut/switch_0/rx_d_0u +add wave -noupdate /tb/dut/switch_0/rx0_byte_cnt +add wave -noupdate /tb/dut/switch_0/rx_fifo_empty_0u +add wave -noupdate /tb/dut/switch_0/rx_fifo_empty_01 +add wave -noupdate /tb/dut/switch_0/rx_fifo_empty_u0 +add wave -noupdate /tb/dut/switch_0/rx_fifo_re_01 +add wave -noupdate /tb/dut/switch_0/rx_fifo_re_0u +add wave -noupdate {/tb/dut/switch_0/tx_f[0]} +add wave -noupdate {/tb/dut/switch_0/tx_fifo_empty[0]} +add wave -noupdate {/tb/dut/switch_0/tx_f[1]} +add wave -noupdate {/tb/dut/switch_0/tx_fifo_empty[1]} +add wave -noupdate /tb/dut/switch_0/tx_mode0 +add wave -noupdate /tb/dut/switch_0/tx0_byte_cnt +add wave -noupdate /tb/dut/switch_0/tx0_src_sel +add wave -noupdate -divider {Half FIFO} +add wave -noupdate /tb/dut/micro_fifo_0/dpram_addr +add wave -noupdate /tb/dut/micro_fifo_0/dpram_din +add wave -noupdate /tb/dut/micro_fifo_0/dpram_dout +add wave -noupdate /tb/dut/micro_fifo_0/dpram_oe +add wave -noupdate /tb/dut/micro_fifo_0/dpram_ptrs_sel +add wave -noupdate /tb/dut/micro_fifo_0/dpram_rx_dout +add wave -noupdate /tb/dut/micro_fifo_0/dpram_rx_sel +add wave -noupdate /tb/dut/micro_fifo_0/dpram_tx_dout +add wave -noupdate /tb/dut/micro_fifo_0/dpram_tx_sel +add wave -noupdate /tb/dut/micro_fifo_0/dpram_we +add wave -noupdate /tb/dut/micro_fifo_0/fifo_clk +add wave -noupdate /tb/dut/micro_fifo_0/fifo_d_out +add wave -noupdate /tb/dut/micro_fifo_0/fifo_re +add wave -noupdate /tb/dut/micro_fifo_0/fifo_we +add wave -noupdate /tb/dut/micro_fifo_0/fifo_we_m1 +add wave -noupdate /tb/dut/micro_fifo_0/reset_ptrs +add wave -noupdate /tb/dut/micro_fifo_0/rx_wr_ptr +add wave -noupdate /tb/dut/micro_fifo_0/rx_wr_ptr_latched +add wave -noupdate /tb/dut/micro_fifo_0/fifo_d_in +add wave -noupdate /tb/dut/micro_fifo_0/tx_rd_ptr +add wave -noupdate /tb/dut/micro_fifo_0/tx_wr_ptr +add wave -noupdate /tb/dut/micro_fifo_0/tx_wr_ptr_latched +add wave -noupdate /tb/dut/micro_fifo_0/uc_clk +add wave -noupdate -divider Controller +add wave -noupdate /tb/dut/controller_0/clk +add wave -noupdate /tb/dut/controller_0/rx_fifo_int +add wave -noupdate /tb/dut/controller_0/rx_fifo_int_m1 +add wave -noupdate /tb/dut/controller_0/rx_fifo_int_m2 +add wave -noupdate /tb/dut/controller_0/rx_fifo_int_acked +add wave -noupdate /tb/dut/controller_0/tx_fifo_empty +add wave -noupdate /tb/dut/controller_0/mac_sel +add wave -noupdate /tb/dut/controller_0/mac_addr +add wave -noupdate /tb/dut/controller_0/pkt_filter_addr +add wave -noupdate /tb/dut/controller_0/pkt_filter_sel +add wave -noupdate /tb/dut/controller_0/hf_ptrs_sel +add wave -noupdate /tb/dut/controller_0/hf_rx_sel +add wave -noupdate /tb/dut/controller_0/hf_tx_sel +add wave -noupdate -color Yellow /tb/dut/controller_0/rx_msg_captured +add wave -noupdate /tb/dut/controller_0/rx_msg_cnt +add wave -noupdate /tb/dut/controller_0/rx_rd_active +add wave -noupdate /tb/dut/controller_0/rx_wr_ptr +add wave -noupdate /tb/dut/controller_0/rx_rd_ptr +add wave -noupdate /tb/dut/controller_0/mem_tgt_ready +add wave -noupdate /tb/dut/controller_0/mem_tgt_ready_m1 +add wave -noupdate /tb/dut/controller_0/mem_tgt_ready_m2 +add wave -noupdate -color gold /tb/dut/controller_0/cont_state +add wave -noupdate /tb/dut/controller_0/cont_msg +add wave -noupdate /tb/dut/controller_0/msg_type +add wave -noupdate /tb/dut/controller_0/msg_token +add wave -noupdate /tb/dut/controller_0/msg_addr +add wave -noupdate /tb/dut/controller_0/msg_addr_valid +add wave -noupdate /tb/dut/controller_0/msg_addr_ro +add wave -noupdate /tb/dut/controller_0/msg_data +add wave -noupdate /tb/dut/controller_0/msg_error +add wave -noupdate /tb/dut/controller_0/msg_response +add wave -noupdate /tb/dut/controller_0/clk +add wave -noupdate /tb/dut/controller_0/mem_cmd +add wave -noupdate /tb/dut/controller_0/mem_oe +add wave -noupdate -color Gold /tb/dut/controller_0/mem_state +add wave -noupdate /tb/dut/controller_0/mem_we +add wave -noupdate /tb/dut/controller_0/mem_addr +add wave -noupdate /tb/dut/controller_0/mem_d_o +add wave -noupdate /tb/dut/controller_0/mem_d_i +add wave -noupdate /tb/dut/controller_0/rx_cnt +add wave -noupdate /tb/dut/controller_0/tx_cnt +add wave -noupdate /tb/dut/controller_0/tx_wr_active +add wave -noupdate /tb/dut/controller_0/tx_wr_ptr +add wave -noupdate -divider {Top Data Mux} +add wave -noupdate /tb/dut/controller_0/hf_tx_sel +add wave -noupdate /tb/dut/controller_0/hf_rx_sel +add wave -noupdate /tb/dut/controller_0/hf_ptrs_sel +add wave -noupdate /tb/dut/controller_0/pkt_gen_sel +add wave -noupdate /tb/dut/controller_0/mle_sel +add wave -noupdate /tb/dut/controller_0/mac_sel +add wave -noupdate /tb/dut/controller_0/mac_addr +add wave -noupdate /tb/dut/controller_0/mem_d_i +add wave -noupdate -divider {PKT GEN} +add wave -noupdate /tb/dut/pkt_gen_0/rstn +add wave -noupdate /tb/dut/pkt_gen_0/pclk +add wave -noupdate /tb/dut/pkt_gen_0/cont_addr +add wave -noupdate /tb/dut/pkt_gen_0/cont_clk +add wave -noupdate /tb/dut/pkt_gen_0/cont_d_i +add wave -noupdate /tb/dut/pkt_gen_0/cont_d_o +add wave -noupdate /tb/dut/pkt_gen_0/cont_sel +add wave -noupdate /tb/dut/pkt_gen_0/cont_we +add wave -noupdate /tb/dut/pkt_gen_0/cont_tgt_ready +add wave -noupdate /tb/dut/pkt_gen_0/pkt_gen_en +add wave -noupdate /tb/dut/pkt_gen_0/fifo_d_o +add wave -noupdate /tb/dut/pkt_gen_0/byte_cnt +add wave -noupdate /tb/dut/pkt_gen_0/fifo_empty_o +add wave -noupdate /tb/dut/pkt_gen_0/fifo_re +add wave -noupdate -divider {MAC 0} +add wave -noupdate /tb/dut/mac_0/tx_state +add wave -noupdate /tb/dut/mac_0/tx_sop +add wave -noupdate /tb/dut/mac_0/tx_eop +add wave -noupdate /tb/dut/mac_0/tx_ctl +add wave -noupdate /tb/dut/mac_0/tx_d +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {6579034 ps} 0} +quietly wave cursor active 1 +configure wave -namecolwidth 257 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ps +update +WaveRestoreZoom {6253959 ps} {6727162 ps} diff --git a/manufacturer/altera/cyclone10_lp/sim/win/betsy.mpf b/manufacturer/altera/cyclone10_lp/sim/win/betsy.mpf index 241cb09..1d64834 100644 --- a/manufacturer/altera/cyclone10_lp/sim/win/betsy.mpf +++ b/manufacturer/altera/cyclone10_lp/sim/win/betsy.mpf @@ -921,7 +921,7 @@ Resolution = ns UserTimeUnit = default ; Default run length -RunLength = 20 us +RunLength = 10 us ; Maximum iterations that can be run without advancing simulation time IterationLimit = 10000000 @@ -2236,67 +2236,69 @@ suppress = 8780 ;an explanation can be had by running: verror 8780 Project_Version = 6 Project_DefaultLib = work Project_SortMethod = unused -Project_Files_Count = 30 +Project_Files_Count = 31 Project_File_0 = C:/Projects/PrivateIsland/privateisland/src/mdio_data_ti.v -Project_File_P_0 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1782576101 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 11 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_P_0 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1782576101 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 11 cover_expr 0 dont_compile 0 cover_stmt 0 Project_File_1 = C:/Projects/PrivateIsland/privateisland/src/half_fifo.v -Project_File_P_1 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1782576101 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 6 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_P_1 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1782576101 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 6 cover_expr 0 dont_compile 0 cover_stmt 0 Project_File_2 = C:/Projects/PrivateIsland/privateisland/src/ipv4_rx_c.v -Project_File_P_2 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1782576101 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 8 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_P_2 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1782576101 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 8 cover_expr 0 dont_compile 0 cover_stmt 0 Project_File_3 = C:/Projects/PrivateIsland/privateisland/src/cont_params.v -Project_File_P_3 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 last_compile 1782576101 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 19 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_P_3 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1782831444 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 19 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_4 = C:/Projects/PrivateIsland/privateisland/src/ipv4_tx_c.v -Project_File_P_4 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1782576101 cover_fsm 0 cover_branch 0 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 28 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_P_4 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1782576101 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 28 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_5 = C:/Projects/PrivateIsland/privateisland/src/drop_fifo.v -Project_File_P_5 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1782576101 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 3 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_P_5 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1782576101 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 3 cover_expr 0 dont_compile 0 cover_stmt 0 Project_File_6 = C:/Projects/PrivateIsland/privateisland/src/mac_rgmii.v -Project_File_P_6 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 last_compile 1782576101 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 20 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_P_6 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1782576101 cover_fsm 0 cover_branch 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 20 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_7 = C:/Projects/PrivateIsland/privateisland/src/cam.v -Project_File_P_7 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1782736853 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_P_7 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1782736853 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0 Project_File_8 = C:/Projects/PrivateIsland/privateisland/src/mle_params.v -Project_File_P_8 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1782576101 cover_fsm 0 cover_branch 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 27 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_P_8 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1782576101 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 27 cover_expr 0 dont_compile 0 cover_stmt 0 Project_File_9 = C:/Projects/PrivateIsland/privateisland/src/mdio.v -Project_File_P_9 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1782576101 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 9 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_P_9 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1782576101 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 9 cover_expr 0 dont_compile 0 cover_stmt 0 Project_File_10 = C:/Projects/PrivateIsland/privateisland/src/switch.v -Project_File_P_10 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1782576101 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +define+PHY2_PRESENT=1 compile_order 13 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_P_10 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1782576101 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +define+PHY2_PRESENT=1 compile_to work vlog_upper 0 cover_noshort 0 compile_order 13 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_11 = C:/Projects/PrivateIsland/privateisland/src/udp_rx.v -Project_File_P_11 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1782576101 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 15 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_P_11 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1782576101 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 15 cover_expr 0 dont_compile 0 cover_stmt 0 Project_File_12 = C:/Projects/PrivateIsland/privateisland/manufacturer/altera/cyclone10_lp/src/betsy.v -Project_File_P_12 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1782576101 cover_fsm 0 cover_branch 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +define+SIMULATION=1 compile_to work vlog_upper 0 cover_noshort 0 compile_order 17 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_P_12 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1782843186 cover_fsm 0 cover_branch 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +define+SIMULATION=1 compile_order 17 cover_expr 0 dont_compile 0 cover_stmt 0 Project_File_13 = C:/Projects/PrivateIsland/privateisland/src/mdio_cont.v -Project_File_P_13 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1782576101 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 10 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_P_13 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1782576101 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 10 cover_expr 0 dont_compile 0 cover_stmt 0 Project_File_14 = C:/Projects/PrivateIsland/privateisland/src/ipv4_rx.v -Project_File_P_14 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1782576101 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 7 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_P_14 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1782576101 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 7 cover_expr 0 dont_compile 0 cover_stmt 0 Project_File_15 = C:/Projects/PrivateIsland/privateisland/manufacturer/altera/cyclone10_lp/ip/pll/pll.v -Project_File_P_15 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1782576101 cover_fsm 0 cover_branch 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 22 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_P_15 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1782576101 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 22 cover_expr 0 dont_compile 0 cover_stmt 0 Project_File_16 = C:/Projects/PrivateIsland/privateisland/manufacturer/altera/cyclone10_lp/ip/rgmii_txd/ddro.v -Project_File_P_16 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1782576101 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 24 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_P_16 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 last_compile 1782576101 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 24 cover_expr 0 dont_compile 0 cover_stmt 0 Project_File_17 = C:/Projects/PrivateIsland/privateisland/src/pkt_filter.v -Project_File_P_17 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1782576101 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 12 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_P_17 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1782576101 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 12 cover_expr 0 dont_compile 0 cover_stmt 0 Project_File_18 = C:/Projects/PrivateIsland/privateisland/manufacturer/altera/cyclone10_lp/sim/src/tb.sv -Project_File_P_18 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1782578131 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 18 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_P_18 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1782842321 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 18 cover_expr 0 dont_compile 0 cover_stmt 0 Project_File_19 = C:/Projects/PrivateIsland/privateisland/src/ml_engine.v -Project_File_P_19 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1782576101 cover_fsm 0 cover_branch 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 26 dont_compile 0 cover_expr 0 cover_stmt 0 -Project_File_20 = C:/Projects/PrivateIsland/privateisland/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio.v -Project_File_P_20 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1782576101 cover_fsm 0 cover_branch 0 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 23 cover_expr 0 dont_compile 0 cover_stmt 0 -Project_File_21 = C:/Projects/PrivateIsland/privateisland/src/sync_fifo.v -Project_File_P_21 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1782576101 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 14 dont_compile 0 cover_expr 0 cover_stmt 0 -Project_File_22 = C:/Projects/PrivateIsland/privateisland/src/dpram_inf.v -Project_File_P_22 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1782576101 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +define+SIMULATION=1 compile_order 2 cover_expr 0 dont_compile 0 cover_stmt 0 -Project_File_23 = C:/Projects/PrivateIsland/privateisland/src/ethernet_params.v -Project_File_P_23 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1782576101 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 4 dont_compile 0 cover_expr 0 cover_stmt 0 -Project_File_24 = C:/Projects/PrivateIsland/privateisland/src/ipv4_tx_mle.v -Project_File_P_24 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1782576101 cover_fsm 0 cover_branch 0 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 29 cover_expr 0 dont_compile 0 cover_stmt 0 -Project_File_25 = C:/Projects/PrivateIsland/privateisland/src/rgmii_params.v -Project_File_P_25 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1782576101 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 21 dont_compile 0 cover_expr 0 cover_stmt 0 -Project_File_26 = C:/Projects/PrivateIsland/privateisland/src/controller.v -Project_File_P_26 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1782576101 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0 -Project_File_27 = C:/Projects/PrivateIsland/privateisland/src/udp_rx_c.v -Project_File_P_27 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1782576101 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 16 dont_compile 0 cover_expr 0 cover_stmt 0 -Project_File_28 = C:/Projects/PrivateIsland/privateisland/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.v -Project_File_P_28 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1782576101 cover_fsm 0 cover_branch 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 25 cover_expr 0 dont_compile 0 cover_stmt 0 -Project_File_29 = C:/Projects/PrivateIsland/privateisland/src/fcs.v -Project_File_P_29 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1782576101 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 5 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_P_19 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1782576101 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 26 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_20 = C:/Projects/PrivateIsland/privateisland/src/pkt_gen.v +Project_File_P_20 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1782842814 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 30 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_21 = C:/Projects/PrivateIsland/privateisland/manufacturer/altera/cyclone10_lp/ip/ddrio/ddrio.v +Project_File_P_21 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1782576101 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 23 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_22 = C:/Projects/PrivateIsland/privateisland/src/sync_fifo.v +Project_File_P_22 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1782576101 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 14 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_23 = C:/Projects/PrivateIsland/privateisland/src/dpram_inf.v +Project_File_P_23 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1782576101 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +define+SIMULATION=1 compile_to work vlog_upper 0 cover_noshort 0 compile_order 2 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_24 = C:/Projects/PrivateIsland/privateisland/src/ethernet_params.v +Project_File_P_24 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1782576101 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 4 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_25 = C:/Projects/PrivateIsland/privateisland/src/ipv4_tx_mle.v +Project_File_P_25 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1782576101 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 29 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_26 = C:/Projects/PrivateIsland/privateisland/src/rgmii_params.v +Project_File_P_26 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1782576101 cover_fsm 0 cover_branch 0 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 21 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_27 = C:/Projects/PrivateIsland/privateisland/src/controller.v +Project_File_P_27 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 last_compile 1782843370 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 1 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_28 = C:/Projects/PrivateIsland/privateisland/src/udp_rx_c.v +Project_File_P_28 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1782576101 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 16 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_29 = C:/Projects/PrivateIsland/privateisland/manufacturer/altera/cyclone10_lp/ip/rgmii_rxd/ddri.v +Project_File_P_29 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1782576101 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 25 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_30 = C:/Projects/PrivateIsland/privateisland/src/fcs.v +Project_File_P_30 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1782576101 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 5 cover_expr 0 dont_compile 0 cover_stmt 0 Project_Sim_Count = 0 Project_Folder_Count = 0 Echo_Compile_Output = 0 |
