diff options
author | mindchasers <privateisland@mindchasers.com> | 2021-03-02 13:04:51 -0500 |
---|---|---|
committer | mindchasers <privateisland@mindchasers.com> | 2021-03-02 13:04:51 -0500 |
commit | 1f36e77c8aea1373a21b71955fff2e34e4e1bd9f (patch) | |
tree | 4a4b4a2b8b94bc3b73d1d0a6f9fb8f4088a5172f /source | |
parent | 05366eaac0ece9c7b4312721c4d4e1dba75efc7b (diff) |
controller: clean up, tx_metrics becomes tx_custom
Diffstat (limited to 'source')
-rw-r--r-- | source/controller.v | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/source/controller.v b/source/controller.v index 6ede860..c695938 100644 --- a/source/controller.v +++ b/source/controller.v @@ -1,7 +1,7 @@ /* * controller.v * - * Copyright (C) 2018, 2109 Mind Chasers Inc. + * Copyright (C) 2018, 2109, 2020, 2021 Mind Chasers Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -15,7 +15,7 @@ * See the License for the specific language governing permissions and * limitations under the License. * - * function: FPGA internal controller + * function: FPGA internal state machine controller * */ @@ -77,7 +77,7 @@ module controller #(parameter ADDR_SZ = 7) output i2c_fifo_priority, // TX custom packet - output reg tx_metrics + output reg tx_custom ); @@ -247,7 +247,7 @@ module controller #(parameter ADDR_SZ = 7) mdio_routine_addr <= 'd80; end - // mdio_cont_busy and mux self + // mdio_cont_busy always @(posedge clk or negedge rstn) begin if ( !rstn ) @@ -397,15 +397,15 @@ module controller #(parameter ADDR_SZ = 7) mdio_mux_sel <= buffer[1][1:0]; end - /* transmit test packet */ + /* transmit custom packet */ always @(posedge clk or negedge rstn) begin if ( !rstn ) - tx_metrics <= 1'b0; + tx_custom <= 1'b0; else if ( rx_cmd && cmd == ASCIIt ) - tx_metrics <= 1'b1; + tx_custom <= 1'b1; else - tx_metrics <= 1'b0; + tx_custom <= 1'b0; end /* FIFO logic */ @@ -425,7 +425,7 @@ module controller #(parameter ADDR_SZ = 7) if ( !rstn ) read_fifo_d_o <= 0; else if ( cont_state == S2 && cmd == ASCIIp ) // pcs status - read_fifo_d_o <= { 2'b00, pcs_s }; + read_fifo_d_o <= { 1'b0, pcs_s }; else if ( cont_state == S2 && cmd == ASCIIl ) // link status read_fifo_d_o <= { 3'b000, link_s }; end |