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author | mindchasers <privateisland@mindchasers.com> | 2020-11-16 13:59:15 -0500 |
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committer | mindchasers <privateisland@mindchasers.com> | 2020-11-16 13:59:15 -0500 |
commit | da76ee103bf89c28c7d6027371e4a420ada41932 (patch) | |
tree | aea0c2c1cdd61cbeebf028170943d0a08132b05a /simulation/README.txt | |
parent | 3e6999c467908663d2539483de82057f587ffbb2 (diff) |
project: rename sim folder, update README
Diffstat (limited to 'simulation/README.txt')
-rw-r--r-- | simulation/README.txt | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/simulation/README.txt b/simulation/README.txt new file mode 100644 index 0000000..0c38a5f --- /dev/null +++ b/simulation/README.txt @@ -0,0 +1,3 @@ +System Verilog Test Benches + +Will be added soon |