diff options
| author | mindchasers <privateisland@mindchasers.com> | 2020-11-16 17:10:41 -0500 |
|---|---|---|
| committer | mindchasers <privateisland@mindchasers.com> | 2020-11-16 17:10:41 -0500 |
| commit | 6e969b02b4f6266bb9af926bfba6698468c74c28 (patch) | |
| tree | d14b41cd45508e52f04b1c8003dcecdbd76f46d9 /manufacturer/lattice/ecp5um/clarity/pcs/refclk0 | |
| parent | 3fa59667468487b7931bafc30e8ec290db899ec8 (diff) | |
project: rename device to lattice to include specific manufacturers
Diffstat (limited to 'manufacturer/lattice/ecp5um/clarity/pcs/refclk0')
3 files changed, 53 insertions, 0 deletions
diff --git a/manufacturer/lattice/ecp5um/clarity/pcs/refclk0/refclk0.fdc b/manufacturer/lattice/ecp5um/clarity/pcs/refclk0/refclk0.fdc new file mode 100644 index 0000000..6fbcac9 --- /dev/null +++ b/manufacturer/lattice/ecp5um/clarity/pcs/refclk0/refclk0.fdc @@ -0,0 +1,2 @@ +###==== Start Configuration + diff --git a/manufacturer/lattice/ecp5um/clarity/pcs/refclk0/refclk0.lpc b/manufacturer/lattice/ecp5um/clarity/pcs/refclk0/refclk0.lpc new file mode 100644 index 0000000..1894b2d --- /dev/null +++ b/manufacturer/lattice/ecp5um/clarity/pcs/refclk0/refclk0.lpc @@ -0,0 +1,31 @@ +[Device] +Family=ecp5um +OperatingCondition=COM +Package=CABGA381 +PartName=LFE5UM-45F-8BG381C +PartType=LFE5UM-45F +SpeedGrade=8 +Status=P +[IP] +CoreName=EXTREF +CoreRevision=1.1 +CoreStatus=Demo +CoreType=LPM +Date=03/06/2020 +ModuleName=refclk0 +ParameterFileVersion=1.0 +SourceFormat=verilog +Time=20:20:44 +VendorName=Lattice Semiconductor Corporation +[Parameters] +Destination=Synplicity +EDIF=1 +EXTREFDCBIAS=Disabled +EXTREFTERMRES=50 ohms +Expression=BusA(0 to 7) +IO=0 +Order=Big Endian [MSB:LSB] +VHDL=0 +Verilog=1 +[SYSTEMPNR] +EXTREF=DCU0 diff --git a/manufacturer/lattice/ecp5um/clarity/pcs/refclk0/refclk0.v b/manufacturer/lattice/ecp5um/clarity/pcs/refclk0/refclk0.v new file mode 100644 index 0000000..edeb81f --- /dev/null +++ b/manufacturer/lattice/ecp5um/clarity/pcs/refclk0/refclk0.v @@ -0,0 +1,20 @@ +// Verilog netlist produced by program ASBGen: Ports rev. 2.30, Attr. rev. 2.65 +// Netlist written on Fri Mar 06 20:20:57 2020 +// +// Verilog Description of module refclk0 +// + +`timescale 1ns/1ps +module refclk0 (refclkp, refclkn, refclko); + input refclkp; + input refclkn; + output refclko; + + + EXTREFB EXTREF0_inst (.REFCLKP(refclkp), .REFCLKN(refclkn), .REFCLKO(refclko)) /* synthesis LOC=EXTREF0 */ ; + defparam EXTREF0_inst.REFCK_PWDNB = "0b1"; + defparam EXTREF0_inst.REFCK_RTERM = "0b1"; + defparam EXTREF0_inst.REFCK_DCBIAS_EN = "0b0"; + +endmodule + |
