diff options
author | mindchasers <privateisland@mindchasers.com> | 2020-11-16 17:10:41 -0500 |
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committer | mindchasers <privateisland@mindchasers.com> | 2020-11-16 17:10:41 -0500 |
commit | 6e969b02b4f6266bb9af926bfba6698468c74c28 (patch) | |
tree | d14b41cd45508e52f04b1c8003dcecdbd76f46d9 /manufacturer/lattice/ecp5um/boards/darsena/labs.rvs | |
parent | 3fa59667468487b7931bafc30e8ec290db899ec8 (diff) |
project: rename device to lattice to include specific manufacturers
Diffstat (limited to 'manufacturer/lattice/ecp5um/boards/darsena/labs.rvs')
-rw-r--r-- | manufacturer/lattice/ecp5um/boards/darsena/labs.rvs | 102 |
1 files changed, 102 insertions, 0 deletions
diff --git a/manufacturer/lattice/ecp5um/boards/darsena/labs.rvs b/manufacturer/lattice/ecp5um/boards/darsena/labs.rvs new file mode 100644 index 0000000..67553e6 --- /dev/null +++ b/manufacturer/lattice/ecp5um/boards/darsena/labs.rvs @@ -0,0 +1,102 @@ +<Project ModBy="Analyzer" Name="C:/projects/lattice/privateisland/boards/darsena/labs.rvs" Date="2019-07-08"> + <Core Name="lab_1_i2c"> + <Setting> + <Capture SamplesPerTrig="2048" NumTrigsCap="1"/> + <Event EventCnt="0" CntEnableRun="0"/> + <TrigSetting PreTrgSamples="" AND_ALL="0" PostTrgSamples="" TURadix="0"/> + </Setting> + <Dataset Name="Base"> + <Trace> + <Sig Name="i2c_0/scl_i"/> + <Sig Name="i2c_0/scl_i_m1"/> + <Sig Name="i2c_0/scl_i_m2"/> + <Sig Name="i2c_0/scl_high"/> + <Sig Name="i2c_0/scl_low"/> + <Sig Name="i2c_0/sda_i"/> + <Sig Name="i2c_0/sda_i_m1"/> + <Sig Name="i2c_0/start"/> + <Sig Name="i2c_0/stop"/> + <Sig Name="i2c_0/run"/> + <Bus Name="i2c_0/bit_cnt" Radix="0"> + <Sig Name="i2c_0/bit_cnt:0"/> + <Sig Name="i2c_0/bit_cnt:1"/> + <Sig Name="i2c_0/bit_cnt:2"/> + <Sig Name="i2c_0/bit_cnt:3"/> + <Sig Name="i2c_0/bit_cnt:4"/> + </Bus> + <Bus Name="i2c_0/dev_ad" Radix="0"> + <Sig Name="i2c_0/dev_ad:0"/> + <Sig Name="i2c_0/dev_ad:1"/> + <Sig Name="i2c_0/dev_ad:2"/> + <Sig Name="i2c_0/dev_ad:3"/> + <Sig Name="i2c_0/dev_ad:4"/> + <Sig Name="i2c_0/dev_ad:5"/> + <Sig Name="i2c_0/dev_ad:6"/> + </Bus> + <Bus Name="i2c_0/addr" Radix="0"> + <Sig Name="i2c_0/addr:0"/> + <Sig Name="i2c_0/addr:1"/> + <Sig Name="i2c_0/addr:2"/> + <Sig Name="i2c_0/addr:3"/> + <Sig Name="i2c_0/addr:4"/> + <Sig Name="i2c_0/addr:5"/> + <Sig Name="i2c_0/addr:6"/> + <Sig Name="i2c_0/addr:7"/> + </Bus> + <Bus Name="i2c_0/d" Radix="0"> + <Sig Name="i2c_0/d:0"/> + <Sig Name="i2c_0/d:1"/> + <Sig Name="i2c_0/d:2"/> + <Sig Name="i2c_0/d:3"/> + <Sig Name="i2c_0/d:4"/> + <Sig Name="i2c_0/d:5"/> + <Sig Name="i2c_0/d:6"/> + <Sig Name="i2c_0/d:7"/> + </Bus> + <Sig Name="i2c_0/ack"/> + <Sig Name="i2c_0/rwn"/> + <Sig Name="i2c_0/cont_sel"/> + <Sig Name="i2c_0/cont_done"/> + <Bus Name="i2c_0/fifo_di" Radix="0"> + <Sig Name="i2c_0/fifo_di:0"/> + <Sig Name="i2c_0/fifo_di:1"/> + <Sig Name="i2c_0/fifo_di:2"/> + <Sig Name="i2c_0/fifo_di:3"/> + <Sig Name="i2c_0/fifo_di:4"/> + <Sig Name="i2c_0/fifo_di:5"/> + <Sig Name="i2c_0/fifo_di:6"/> + </Bus> + <Sig Name="i2c_0/mem_we"/> + <Sig Name="i2c_0/cont_we"/> + <Bus Name="i2c_0/mem_do" Radix="0"> + <Sig Name="i2c_0/mem_do:0"/> + <Sig Name="i2c_0/mem_do:1"/> + <Sig Name="i2c_0/mem_do:2"/> + <Sig Name="i2c_0/mem_do:3"/> + <Sig Name="i2c_0/mem_do:4"/> + <Sig Name="i2c_0/mem_do:5"/> + <Sig Name="i2c_0/mem_do:6"/> + <Sig Name="i2c_0/mem_do:7"/> + </Bus> + <Sig Name="i2c_0/fifo_re"/> + <Bus Name="i2c_0/i_di" Radix="0"> + <Sig Name="i2c_0/i_di:0"/> + <Sig Name="i2c_0/i_di:1"/> + <Sig Name="i2c_0/i_di:2"/> + <Sig Name="i2c_0/i_di:3"/> + <Sig Name="i2c_0/i_di:4"/> + <Sig Name="i2c_0/i_di:5"/> + <Sig Name="i2c_0/i_di:6"/> + <Sig Name="i2c_0/i_di:7"/> + </Bus> + <Sig Name="i2c_0/sda_o"/> + <Sig Name="i2c_0/sda_oe"/> + <Sig Name="i2c_0/tx_fifo_empty"/> + </Trace> + <Trigger> + <TU Operator="0" Name="TU1" ID="1" Value="1" Radix="0"/> + <TE Enable="1" Expression="TU1" Name="TE1" ID="1"/> + </Trigger> + </Dataset> + </Core> +</Project> |