diff options
author | mindchasers <privateisland@mindchasers.com> | 2020-11-15 23:42:42 -0500 |
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committer | mindchasers <privateisland@mindchasers.com> | 2020-11-15 23:42:42 -0500 |
commit | 3e6999c467908663d2539483de82057f587ffbb2 (patch) | |
tree | ec10f61e27b36eee8a37f46feb45601243174fc4 /manufacturer/device/ecp5um/boards/darsena/labs.rvl | |
parent | 8e8ce59d8f74e1d3de89e5b2b720039ed32a9768 (diff) |
ecp5um project: restructure so we can add more devices
Diffstat (limited to 'manufacturer/device/ecp5um/boards/darsena/labs.rvl')
-rw-r--r-- | manufacturer/device/ecp5um/boards/darsena/labs.rvl | 107 |
1 files changed, 107 insertions, 0 deletions
diff --git a/manufacturer/device/ecp5um/boards/darsena/labs.rvl b/manufacturer/device/ecp5um/boards/darsena/labs.rvl new file mode 100644 index 0000000..ad00f8e --- /dev/null +++ b/manufacturer/device/ecp5um/boards/darsena/labs.rvl @@ -0,0 +1,107 @@ +<Project ModBy="Inserter" SigType="0" Name="C:/projects/lattice/privateisland/boards/darsena/labs.rvl" Date="2019-07-08"> + <IP Version="1_6_042617"/> + <Design DesignEntry="Schematic/Verilog HDL" Synthesis="synplify" DeviceFamily="ECP5UM" DesignName="privateisland"/> + <Core InsertDataset="0" Insert="1" Reveal_sig="231808093" Name="lab_1_i2c" ID="0"> + <Setting> + <Clock SampleClk="clk_10" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/> + <TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="1" BufferDepth="2048"/> + <Capture Mode="0" MinSamplesPerTrig="8"/> + <Event CntEnable="0" MaxEventCnt="8"/> + <TrigOut Polarity="0" MinPulseWidth="0" TrigOutNetType="1" EnableTrigOut="0" TrigOutNet="reveal_debug_top_LA0_net"/> + <DistRAM Disable="0"/> + </Setting> + <Dataset Name="Base"> + <Trace> + <Sig Type="SIG" Name="i2c_0/scl_i"/> + <Sig Type="SIG" Name="i2c_0/scl_i_m1"/> + <Sig Type="SIG" Name="i2c_0/scl_i_m2"/> + <Sig Type="SIG" Name="i2c_0/scl_high"/> + <Sig Type="SIG" Name="i2c_0/scl_low"/> + <Sig Type="SIG" Name="i2c_0/sda_i"/> + <Sig Type="SIG" Name="i2c_0/sda_i_m1"/> + <Sig Type="SIG" Name="i2c_0/start"/> + <Sig Type="SIG" Name="i2c_0/stop"/> + <Sig Type="SIG" Name="i2c_0/run"/> + <Bus Name="i2c_0/bit_cnt"> + <Sig Type="SIG" Name="i2c_0/bit_cnt:0"/> + <Sig Type="SIG" Name="i2c_0/bit_cnt:1"/> + <Sig Type="SIG" Name="i2c_0/bit_cnt:2"/> + <Sig Type="SIG" Name="i2c_0/bit_cnt:3"/> + <Sig Type="SIG" Name="i2c_0/bit_cnt:4"/> + </Bus> + <Bus Name="i2c_0/dev_ad"> + <Sig Type="SIG" Name="i2c_0/dev_ad:0"/> + <Sig Type="SIG" Name="i2c_0/dev_ad:1"/> + <Sig Type="SIG" Name="i2c_0/dev_ad:2"/> + <Sig Type="SIG" Name="i2c_0/dev_ad:3"/> + <Sig Type="SIG" Name="i2c_0/dev_ad:4"/> + <Sig Type="SIG" Name="i2c_0/dev_ad:5"/> + <Sig Type="SIG" Name="i2c_0/dev_ad:6"/> + </Bus> + <Bus Name="i2c_0/addr"> + <Sig Type="SIG" Name="i2c_0/addr:0"/> + <Sig Type="SIG" Name="i2c_0/addr:1"/> + <Sig Type="SIG" Name="i2c_0/addr:2"/> + <Sig Type="SIG" Name="i2c_0/addr:3"/> + <Sig Type="SIG" Name="i2c_0/addr:4"/> + <Sig Type="SIG" Name="i2c_0/addr:5"/> + <Sig Type="SIG" Name="i2c_0/addr:6"/> + <Sig Type="SIG" Name="i2c_0/addr:7"/> + </Bus> + <Bus Name="i2c_0/d"> + <Sig Type="SIG" Name="i2c_0/d:0"/> + <Sig Type="SIG" Name="i2c_0/d:1"/> + <Sig Type="SIG" Name="i2c_0/d:2"/> + <Sig Type="SIG" Name="i2c_0/d:3"/> + <Sig Type="SIG" Name="i2c_0/d:4"/> + <Sig Type="SIG" Name="i2c_0/d:5"/> + <Sig Type="SIG" Name="i2c_0/d:6"/> + <Sig Type="SIG" Name="i2c_0/d:7"/> + </Bus> + <Sig Type="SIG" Name="i2c_0/ack"/> + <Sig Type="SIG" Name="i2c_0/rwn"/> + <Sig Type="SIG" Name="i2c_0/cont_sel"/> + <Sig Type="SIG" Name="i2c_0/cont_done"/> + <Bus Name="i2c_0/fifo_di"> + <Sig Type="SIG" Name="i2c_0/fifo_di:0"/> + <Sig Type="SIG" Name="i2c_0/fifo_di:1"/> + <Sig Type="SIG" Name="i2c_0/fifo_di:2"/> + <Sig Type="SIG" Name="i2c_0/fifo_di:3"/> + <Sig Type="SIG" Name="i2c_0/fifo_di:4"/> + <Sig Type="SIG" Name="i2c_0/fifo_di:5"/> + <Sig Type="SIG" Name="i2c_0/fifo_di:6"/> + </Bus> + <Sig Type="SIG" Name="i2c_0/mem_we"/> + <Sig Type="SIG" Name="i2c_0/cont_we"/> + <Bus Name="i2c_0/mem_do"> + <Sig Type="SIG" Name="i2c_0/mem_do:0"/> + <Sig Type="SIG" Name="i2c_0/mem_do:1"/> + <Sig Type="SIG" Name="i2c_0/mem_do:2"/> + <Sig Type="SIG" Name="i2c_0/mem_do:3"/> + <Sig Type="SIG" Name="i2c_0/mem_do:4"/> + <Sig Type="SIG" Name="i2c_0/mem_do:5"/> + <Sig Type="SIG" Name="i2c_0/mem_do:6"/> + <Sig Type="SIG" Name="i2c_0/mem_do:7"/> + </Bus> + <Sig Type="SIG" Name="i2c_0/fifo_re"/> + <Bus Name="i2c_0/i_di"> + <Sig Type="SIG" Name="i2c_0/i_di:0"/> + <Sig Type="SIG" Name="i2c_0/i_di:1"/> + <Sig Type="SIG" Name="i2c_0/i_di:2"/> + <Sig Type="SIG" Name="i2c_0/i_di:3"/> + <Sig Type="SIG" Name="i2c_0/i_di:4"/> + <Sig Type="SIG" Name="i2c_0/i_di:5"/> + <Sig Type="SIG" Name="i2c_0/i_di:6"/> + <Sig Type="SIG" Name="i2c_0/i_di:7"/> + </Bus> + <Sig Type="SIG" Name="i2c_0/sda_o"/> + <Sig Type="SIG" Name="i2c_0/sda_oe"/> + <Sig Type="SIG" Name="i2c_0/tx_fifo_empty"/> + </Trace> + <Trigger> + <TU Serialbits="0" Type="0" ID="1" Sig="i2c_0/start,"/> + <TE MaxSequence="1" MaxEvnCnt="1" ID="1" Resource="1"/> + </Trigger> + </Dataset> + </Core> +</Project> |